Unified Coverage Report :: Module :: otp_ctrl

Module : otp_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.50	92.95	86.96	87.31		93.10	97.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	96.19	94.16	96.15	97.04		96.43	97.18

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.19	94.16	96.15	97.04		96.43	97.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.28	93.78	96.70	96.00	91.65	97.24	96.34

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
core_tlul_assert_device	100.00	100.00				100.00	100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
gen_alert_tx[3].u_prim_alert_sender	100.00			100.00
gen_alert_tx[4].u_prim_alert_sender	100.00			100.00
gen_bufs[0].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[0].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[10].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[10].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[8].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[8].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[9].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[9].u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_partitions[0].gen_unbuffered.u_part_unbuf	96.73	100.00	100.00	100.00	85.00	98.15	97.22
gen_partitions[10].gen_lifecycle.u_part_buf	91.25	90.44	100.00	75.74	95.24	100.00	86.05
gen_partitions[1].gen_unbuffered.u_part_unbuf	98.32	100.00	100.00	100.00	91.67	98.25	100.00
gen_partitions[2].gen_unbuffered.u_part_unbuf	97.83	100.00	97.06	100.00	91.67	98.25	100.00
gen_partitions[3].gen_unbuffered.u_part_unbuf	98.32	100.00	100.00	100.00	91.67	98.25	100.00
gen_partitions[4].gen_unbuffered.u_part_unbuf	98.32	100.00	100.00	100.00	91.67	98.25	100.00
gen_partitions[5].gen_buffered.u_part_buf	96.47	100.00	97.62	100.00	96.00	98.53	86.67
gen_partitions[6].gen_buffered.u_part_buf	93.40	96.65	92.86	100.00	91.67	92.54	86.67
gen_partitions[7].gen_buffered.u_part_buf	96.45	98.54	93.75	100.00	94.44	96.25	95.74
gen_partitions[8].gen_buffered.u_part_buf	95.99	98.54	93.75	100.00	91.67	96.25	95.74
gen_partitions[9].gen_buffered.u_part_buf	95.99	98.54	93.75	100.00	91.67	96.25	95.74
otp_ctrl_core_csr_assert	100.00						100.00
prim_tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_arb	93.35	92.31	87.76			100.00	93.33
u_intr_error	100.00	100.00	100.00			100.00	100.00
u_intr_operation_done	100.00	100.00	100.00			100.00	100.00
u_keygmr_key_valid	100.00	100.00				100.00
u_otp	98.91	93.68	99.80	100.00	100.00	100.00	100.00
u_otp_arb	97.29	98.07	97.35			100.00	93.75
u_otp_ctrl_dai	90.67	85.64	91.96	100.00	89.47	89.73	87.23
u_otp_ctrl_kdi	96.45	99.63	99.64	100.00	86.36	95.70	97.37
u_otp_ctrl_lci	100.00	100.00	100.00	100.00	100.00	100.00	100.00
u_otp_ctrl_lfsr_timer	97.65	100.00	97.47	88.46	100.00	100.00	100.00
u_otp_ctrl_scrmbl	96.92	81.50	100.00	100.00	100.00	100.00	100.00
u_otp_init_sync	100.00	100.00				100.00
u_otp_rsp_fifo	96.83	100.00	92.31			95.00	100.00
u_part_sel_idx	74.55	65.65	89.83			88.89	53.85
u_prim_edn_req	92.19	100.00	93.75			100.00	75.00
u_prim_lc_sender_otp_broadcast_valid	100.00	100.00				100.00
u_prim_lc_sender_rma_token_valid	100.00	100.00				100.00
u_prim_lc_sender_secrets_valid	100.00	100.00				100.00
u_prim_lc_sender_test_tokens_valid	100.00	100.00				100.00
u_prim_lc_sync_check_byp_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_creator_seed_sw_rw_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_escalate_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_owner_seed_sw_rw_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_seed_hw_rd_en	100.00	100.00				100.00	100.00
u_reg_core	99.17	99.65	96.20	100.00		100.00	100.00
u_scrmbl_mtx	79.55	75.00	99.45			100.00	43.75
u_tlul_adapter_sram	93.06	89.80	92.65			89.77	100.00
u_tlul_lc_gate	85.26	95.28	92.86		57.14	93.55	87.50

Line Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
TOTAL		156	145	92.95
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
ALWAYS	284	14	13	92.86
ALWAYS	308	3	3	100.00
ALWAYS	324	11	10	90.91
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
ALWAYS	407	5	5	100.00
ALWAYS	434	19	19	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
ALWAYS	499	9	9	100.00
ALWAYS	521	10	10	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	593	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	765	1	1	100.00
CONT_ASSIGN	766	1	1	100.00
CONT_ASSIGN	767	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
ALWAYS	876	2	2	100.00
ALWAYS	934	2	2	100.00
ALWAYS	961	4	4	100.00
CONT_ASSIGN	988	1	1	100.00
ALWAYS	991	3	3	100.00
CONT_ASSIGN	1043	1	1	100.00
CONT_ASSIGN	1045	1	1	100.00
CONT_ASSIGN	1079	1	0	0.00
CONT_ASSIGN	1130	1	0	0.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1300	1	0	0.00
CONT_ASSIGN	1312	1	0	0.00
CONT_ASSIGN	1336	1	1	100.00
ALWAYS	1348	2	2	100.00
CONT_ASSIGN	1362	1	1	100.00
ALWAYS	1390	9	9	100.00
CONT_ASSIGN	1421	1	1	100.00
CONT_ASSIGN	1422	1	1	100.00
CONT_ASSIGN	1424	1	1	100.00
CONT_ASSIGN	1426	1	1	100.00
CONT_ASSIGN	1430	1	1	100.00
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1441	1	1	100.00
CONT_ASSIGN	1443	1	1	100.00
CONT_ASSIGN	1475	1	1	100.00
CONT_ASSIGN	1477	1	1	100.00
CONT_ASSIGN	1481	1	1	100.00
CONT_ASSIGN	1485	1	1	100.00
CONT_ASSIGN	1489	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
251	1	1
253	10	10
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
292	0	1
			MISSING_ELSE
297	1	1
298	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
308	1	1
309	1	1
311	1	1
324	1	1
329	1	1
330	1	1
334	1	1
335	1	1
336	1	1
337	1	1
			MISSING_ELSE
			MISSING_ELSE
341	1	1
342	1	1
343	1	1
344	0	1
			MISSING_ELSE
			MISSING_ELSE
382	1	1
386	1	1
390	1	1
394	1	1
395	1	1
403	1	1
404	1	1
407	1	1
408	1	1
410	1	1
412	1	1
413	1	1
434	1	1
435	1	1
436	1	1
438	1	1
440	1	1
443	1	1
445	1	1
448	1	1
449	1	1
			MISSING_ELSE
453	1	1
455	1	1
459	1	1
462	1	1
464	1	1
469	1	1
470	1	1
			MISSING_ELSE
472	1	1
473	1	1
			MISSING_ELSE
478	1	1
488	1	1
496	1	1
499	1	1
500	1	1
501	1	1
502	1	1
503	1	1
505	1	1
506	1	1
507	1	1
508	1	1
521	1	1
523	1	1
525	1	1
527	1	1
529	1	1
538	1	1
540	1	1
541	1	1
542	1	1
543	1	1
585	1	1
593	1	1
640	1	1
642	1	1
765	1	1
766	1	1
767	1	1
797	1	1
799	1	1
876	1	1
877	1	1
934	1	1
935	1	1
961	1	1
962	1	1
963	1	1
964	1	1
988	1	1
991	1	1
992	1	1
994	1	1
1043	1	1
1045	1	1
1079	0	1
1130	0	1
1185	5	5
1240	0	5
1300	0	1
1312	0	1
1336	1	1
1348	1	1
1349	1	1
1362	1	1
1390	1	1
1391	1	1
1392	1	1
1393	1	1
1395	1	1
1396	1	1
1397	1	1
1398	1	1
1399	1	1
1421	1	1
1422	1	1
1424	1	1
1426	1	1
1430	1	1
1432	1	1
1434	1	1
1439	1	1
1441	1	1
1443	1	1
1475	1	1
1477	1	1
1481	1	1
1485	1	1
1489	1	1

---

Cond Coverage for Module : otp_ctrl

	Total	Covered	Percent
Conditions	115	100	86.96
Logical	115	100	86.96
Non-Logical	0	0
Event	0	0

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00110110000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b10001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[8].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[9].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd))
             -------------------1------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

 LINE       288
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       297
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       298
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       382
 EXPRESSION ((reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q))) ? 1'b0 : direct_access_regwen_q)
             -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       382
 SUB-EXPRESSION (reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q)))
                 ---------------1--------------    -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       386
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       403
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       436
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Not Covered

 LINE       445
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       449
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T14,T58

 LINE       469
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T4
1	0	Covered	T2,T14,T17

 LINE       478
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T14,T15
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Covered	T10,T11,T12
1	0	0	0	Covered	T1,T4,T8

 LINE       527
 EXPRESSION (direct_access_regwen_q & dai_idle)
             -----------1----------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T183,T195,T196
1	0	Covered	T1,T2,T3
1	1	Covered	T183,T195,T196

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T183,T195,T196
1	0	Covered	T1,T2,T3
1	1	Covered	T183,T195,T196

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T183,T195,T196
1	0	Covered	T1,T2,T3
1	1	Covered	T183,T195,T196

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T183,T195,T196
1	0	Covered	T1,T2,T3
1	1	Covered	T183,T195,T196

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T183,T195,T196
1	0	Covered	T1,T2,T3
1	1	Covered	T183,T195,T196

 LINE       640
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T4

 LINE       642
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       765
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       766
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       767
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       877
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1421
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T15,T24

 LINE       1439
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       1439
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       1441
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T15

 LINE       1441
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T15

 LINE       1443
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T15

 LINE       1443
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T15

---

Toggle Coverage for Module : otp_ctrl

	Total	Covered	Percent
Totals	156	142	91.03
Total Bits	11096	9688	87.31
Total Bits 0->1	5548	4844	87.31
Total Bits 1->0	5548	4844	87.31

Ports	156	142	91.03
Port Bits	11096	9688	87.31
Port Bits 0->1	5548	4844	87.31
Port Bits 1->0	5548	4844	87.31

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o.edn_req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
edn_i.edn_fips	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
edn_i.edn_ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
core_tl_i.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_error	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T6,T13	Yes	T1,T6,T13	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T1,T6,T13	Yes	T1,T6,T13	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T1,T6,T13	Yes	T1,T6,T13	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T1,T6,T13	Yes	T1,T6,T13	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_i.a_valid	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_o.a_ready	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
prim_tl_o.d_error	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
prim_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T3,*T5	Yes	T1,T3,T5	OUTPUT
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T5	Yes	T1,T3,T5	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
intr_otp_error_o	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T14,T17	Yes	T2,T14,T17	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T183,T195,T196	Yes	T183,T195,T196	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T183,T195,T196	Yes	T183,T195,T196	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T183,T195,T196	Yes	T183,T195,T196	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T14,T17	Yes	T2,T14,T17	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T183,T195,T196	Yes	T183,T195,T196	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T183,T195,T196	Yes	T183,T195,T196	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T183,T195,T196	Yes	T183,T195,T196	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	No	No		No		OUTPUT
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T1,T4,T14	Yes	T1,T4,T6	INPUT
pwr_otp_i.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	No	No		No		OUTPUT
lc_otp_program_i.count[383:0]	Yes	Yes	T8,T34,T9	Yes	T18,T8,T34	INPUT
lc_otp_program_i.state[319:0]	Yes	Yes	T8,T32,T34	Yes	T8,T32,T34	INPUT
lc_otp_program_i.req	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
lc_otp_program_o.ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
lc_otp_program_o.err	Yes	Yes	T18,T32,T34	Yes	T18,T32,T34	OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T4	INPUT
lc_owner_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T3,T4	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T5,T13,T16	Yes	T5,T13,T16	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T5,T116,T96	Yes	T116,T96,T241	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T4,T15,T24	Yes	T4,T6,T15	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T34,T20,T94	Yes	T106,T87,T34	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T4,T6,T15	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T4,T15,T24	Yes	T4,T6,T15	OUTPUT
otp_lc_data_o.count[0]	No	No		No		OUTPUT
otp_lc_data_o.count[14:1]	Yes	Yes	T3,T4,T6	Yes	T3,T5,T4	OUTPUT
otp_lc_data_o.count[16:15]	No	No		No		OUTPUT
otp_lc_data_o.count[27:17]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[29:28]	No	No		No		OUTPUT
otp_lc_data_o.count[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[32:31]	No	No		No		OUTPUT
otp_lc_data_o.count[41:33]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[42]	No	No		No		OUTPUT
otp_lc_data_o.count[51:43]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[52]	No	No		No		OUTPUT
otp_lc_data_o.count[63:53]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[64]	No	No		No		OUTPUT
otp_lc_data_o.count[78:65]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[79]	No	No		No		OUTPUT
otp_lc_data_o.count[84:80]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[86:85]	No	No		No		OUTPUT
otp_lc_data_o.count[101:87]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[102]	No	No		No		OUTPUT
otp_lc_data_o.count[104:103]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[105]	No	No		No		OUTPUT
otp_lc_data_o.count[115:106]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[116]	No	No		No		OUTPUT
otp_lc_data_o.count[118:117]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[119]	No	No		No		OUTPUT
otp_lc_data_o.count[121:120]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[122]	No	No		No		OUTPUT
otp_lc_data_o.count[124:123]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[125]	No	No		No		OUTPUT
otp_lc_data_o.count[134:126]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[135]	No	No		No		OUTPUT
otp_lc_data_o.count[142:136]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[143]	No	No		No		OUTPUT
otp_lc_data_o.count[151:144]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[152]	No	No		No		OUTPUT
otp_lc_data_o.count[155:153]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[156]	No	No		No		OUTPUT
otp_lc_data_o.count[164:157]	Yes	Yes	*T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[165]	No	No		No		OUTPUT
otp_lc_data_o.count[174:166]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[175]	No	No		No		OUTPUT
otp_lc_data_o.count[185:176]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[187:186]	No	No		No		OUTPUT
otp_lc_data_o.count[193:188]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[194]	No	No		No		OUTPUT
otp_lc_data_o.count[196:195]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[197]	No	No		No		OUTPUT
otp_lc_data_o.count[217:198]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[218]	No	No		No		OUTPUT
otp_lc_data_o.count[228:219]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[229]	No	No		No		OUTPUT
otp_lc_data_o.count[240:230]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[241]	No	No		No		OUTPUT
otp_lc_data_o.count[243:242]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[244]	No	No		No		OUTPUT
otp_lc_data_o.count[254:245]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[255]	No	No		No		OUTPUT
otp_lc_data_o.count[265:256]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[266]	No	No		No		OUTPUT
otp_lc_data_o.count[269:267]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[270]	No	No		No		OUTPUT
otp_lc_data_o.count[274:271]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[275]	No	No		No		OUTPUT
otp_lc_data_o.count[312:276]	Yes	Yes	*T3,T4,*T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[313]	No	No		No		OUTPUT
otp_lc_data_o.count[324:314]	Yes	Yes	*T3,T4,*T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[325]	No	No		No		OUTPUT
otp_lc_data_o.count[336:326]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[337]	No	No		No		OUTPUT
otp_lc_data_o.count[338]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[339]	No	No		No		OUTPUT
otp_lc_data_o.count[345:340]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[346]	No	No		No		OUTPUT
otp_lc_data_o.count[357:347]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[358]	No	No		No		OUTPUT
otp_lc_data_o.count[364:359]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[367:365]	No	No		No		OUTPUT
otp_lc_data_o.count[379:368]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[381:380]	No	No		No		OUTPUT
otp_lc_data_o.count[383:382]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[6]	No	No		No		OUTPUT
otp_lc_data_o.state[9:7]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[10]	No	No		No		OUTPUT
otp_lc_data_o.state[12:11]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[15:14]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[16]	No	No		No		OUTPUT
otp_lc_data_o.state[18:17]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[19]	No	No		No		OUTPUT
otp_lc_data_o.state[31:20]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[32]	No	No		No		OUTPUT
otp_lc_data_o.state[34:33]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[35]	No	No		No		OUTPUT
otp_lc_data_o.state[46:36]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[47]	No	No		No		OUTPUT
otp_lc_data_o.state[52:48]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[53]	No	No		No		OUTPUT
otp_lc_data_o.state[59:54]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[60]	No	No		No		OUTPUT
otp_lc_data_o.state[65:61]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[66]	No	No		No		OUTPUT
otp_lc_data_o.state[68:67]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[69]	No	No		No		OUTPUT
otp_lc_data_o.state[75:70]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[76]	No	No		No		OUTPUT
otp_lc_data_o.state[79:77]	Yes	Yes	T4,T6,*T24	Yes	T4,T6,T24	OUTPUT
otp_lc_data_o.state[80]	No	No		No		OUTPUT
otp_lc_data_o.state[84:81]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[85]	No	No		No		OUTPUT
otp_lc_data_o.state[87:86]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[88]	No	No		No		OUTPUT
otp_lc_data_o.state[95:89]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[96]	No	No		No		OUTPUT
otp_lc_data_o.state[103:97]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[106:105]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[107]	No	No		No		OUTPUT
otp_lc_data_o.state[110:108]	Yes	Yes	T4,T6,T24	Yes	T4,T6,T24	OUTPUT
otp_lc_data_o.state[111]	No	No		No		OUTPUT
otp_lc_data_o.state[123:112]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[124]	No	No		No		OUTPUT
otp_lc_data_o.state[131:125]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[133:132]	No	No		No		OUTPUT
otp_lc_data_o.state[134]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[135]	No	No		No		OUTPUT
otp_lc_data_o.state[146:136]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[147]	No	No		No		OUTPUT
otp_lc_data_o.state[149:148]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[150]	No	No		No		OUTPUT
otp_lc_data_o.state[151]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[154:152]	No	No		No		OUTPUT
otp_lc_data_o.state[156:155]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[157]	No	No		No		OUTPUT
otp_lc_data_o.state[160:158]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[161]	No	No		No		OUTPUT
otp_lc_data_o.state[180:162]	Yes	Yes	*T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[181]	No	No		No		OUTPUT
otp_lc_data_o.state[182]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[184:183]	No	No		No		OUTPUT
otp_lc_data_o.state[187:185]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[188]	No	No		No		OUTPUT
otp_lc_data_o.state[199:189]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[200]	No	No		No		OUTPUT
otp_lc_data_o.state[210:201]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[211]	No	No		No		OUTPUT
otp_lc_data_o.state[214:212]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[215]	No	No		No		OUTPUT
otp_lc_data_o.state[220:216]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[221]	No	No		No		OUTPUT
otp_lc_data_o.state[226:222]	Yes	Yes	*T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[227]	No	No		No		OUTPUT
otp_lc_data_o.state[234:228]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[237:235]	No	No		No		OUTPUT
otp_lc_data_o.state[241:238]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[242]	No	No		No		OUTPUT
otp_lc_data_o.state[243]	Yes	Yes	*T3,*T4,*T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[244]	No	No		No		OUTPUT
otp_lc_data_o.state[246:245]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[247]	No	No		No		OUTPUT
otp_lc_data_o.state[256:248]	Yes	Yes	T4,T6,*T109	Yes	T4,T6,T109	OUTPUT
otp_lc_data_o.state[257]	No	No		No		OUTPUT
otp_lc_data_o.state[260:258]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[261]	No	No		No		OUTPUT
otp_lc_data_o.state[268:262]	Yes	Yes	*T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[269]	No	No		No		OUTPUT
otp_lc_data_o.state[273:270]	Yes	Yes	T4,T6,*T109	Yes	T4,T6,T109	OUTPUT
otp_lc_data_o.state[274]	No	No		No		OUTPUT
otp_lc_data_o.state[277:275]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[279:278]	No	No		No		OUTPUT
otp_lc_data_o.state[284:280]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[286:285]	No	No		No		OUTPUT
otp_lc_data_o.state[301:287]	Yes	Yes	*T3,T4,*T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[302]	No	No		No		OUTPUT
otp_lc_data_o.state[319:303]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.error	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.owner_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.owner_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_root_key_share1_valid	Yes	Yes	T4,T15,T24	Yes	T4,T6,T15	OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:0]	Yes	Yes	T34,T96,T117	Yes	T34,T96,T242	OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid	Yes	Yes	T4,T15,T24	Yes	T4,T6,T15	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
flash_otp_key_i.data_req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T4,T24,T25	Yes	T4,T24,T25	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i[1].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i[2].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i[3].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T4,T24,T25	Yes	T4,T24,T25	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T4,T24,T25	Yes	T4,T24,T25	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T4,T24,T25	Yes	T4,T24,T25	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[3].seed_valid	Yes	Yes	T4,T24,T25	Yes	T4,T24,T25	OUTPUT
sram_otp_key_o[3].nonce[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[3].key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[3].ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T4,T24,T25	Yes	T4,T24,T25	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.dis_rv_dm_late_debug[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.unallocated[39:0]	Yes	Yes	T6,T37,T34	Yes	T6,T37,T110	OUTPUT
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0]	Yes	Yes	T4,T15,T24	Yes	T4,T15,T24	OUTPUT
otp_broadcast_o.valid[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T4,T13	INPUT
scan_rst_ni	Yes	Yes	T5,T4,T6	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T24	INPUT
cio_test_o[7:0]	No	No		No		OUTPUT
cio_test_en_o[7:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
Branches		29	27	93.10
TERNARY	382	2	1	50.00
TERNARY	1439	2	2	100.00
TERNARY	1441	2	2	100.00
TERNARY	1443	2	2	100.00
IF	287	3	2	66.67
IF	308	2	2	100.00
IF	334	2	2	100.00
IF	341	2	2	100.00
IF	407	2	2	100.00
IF	448	2	2	100.00
IF	469	2	2	100.00
IF	472	2	2	100.00
IF	499	2	2	100.00
IF	991	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	382	((reg2hw.direct_access_regwen.qe && (!reg2hw.direct_access_regwen.q))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1439	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1441	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1443	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	287	if (tlul_req)
-2-:	288	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	308	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	341	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	407	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	448	if (otp_ctrl_part_pkg::PartInfo[k].integrity)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	469	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	472	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	499	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	991	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	71	71	100.00	69	97.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	71	71	100.00	69	97.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	469360011	468476094	0	0
CoreTlOutKnown_A	469360011	468476094	0	0
CreatorRootKeyShare0Size_A	1151	1151	0	0
CreatorRootKeyShare1Size_A	1151	1151	0	0
ErrorCodeWidth_A	1151	1151	0	0
FlashAddrKeySeedSize_A	1151	1151	0	0
FlashDataKeySeedSize_A	1151	1151	0	0
FlashOtpKeyRspKnown_A	469360011	468476094	0	0
FpvSecCmCntCnstyCheck_A	469360011	50	0	0
FpvSecCmCntDaiCheck_A	469360011	50	0	0
FpvSecCmCntIntegCheck_A	469360011	50	0	0
FpvSecCmCntKdiEntropyCheck_A	469360011	50	0	0
FpvSecCmCntKdiSeedCheck_A	469360011	50	0	0
FpvSecCmCntLciCheck_A	469360011	50	0	0
FpvSecCmCntScrmblCheck_A	469360011	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	469360011	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	469360011	50	0	0
FpvSecCmCtrlLciFsmCheck_A	469360011	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	469360011	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	469360011	50	0	0
FpvSecCmDoubleLfsrCheck_A	469360011	50	0	0
FpvSecCmRegWeOnehotCheck_A	469360011	50	0	0
FpvSecCmTlLcGateFsm_A	469360011	50	0	0
IntrOtpErrorKnown_A	469360011	468476094	0	0
IntrOtpOperationDoneKnown_A	469360011	468476094	0	0
LcOtpProgramRspKnown_A	469360011	468476094	0	0
LcSeedHwRdEnStable0_A	469360011	2376	0	0
LcSeedHwRdEnStable1_A	469360011	2376	0	0
LcSeedHwRdEnStable2_A	469360011	0	0	0
LcSeedHwRdEnStable3_A	469360011	0	0	0
LcStateSize_A	1151	1151	0	0
LcTransitionCntSize_A	1151	1151	0	0
OtpAstPwrSeqKnown_A	469360011	468476094	0	0
OtpBroadcastKnown_A	469360011	468476094	0	0
OtpErrorCode0_A	1151	1151	0	0
OtpErrorCode1_A	1151	1151	0	0
OtpErrorCode2_A	1151	1151	0	0
OtpErrorCode3_A	1151	1151	0	0
OtpErrorCode4_A	1151	1151	0	0
OtpIfWidth_A	1151	1151	0	0
OtpKeymgrKeyKnown_A	469360011	468476094	0	0
OtpLcDataKnown_A	469360011	468476094	0	0
OtpOtgnKeyKnown_A	469360011	468476094	0	0
OtpRespFifoUnderflow_A	469360011	1502213	0	0
OtpSramKeyKnown_A	469360011	468476094	0	0
PartSelMustBeOnehot_A	469360011	468476094	0	0
PrimTlOutKnown_A	469360011	468476094	0	0
PwrOtpInitRspKnown_A	469360011	468476094	0	0
RmaTokenSize_A	1151	1151	0	0
SramDataKeySeedSize_A	1151	1151	0	0
TestExitTokenSize_A	1151	1151	0	0
TestUnlockTokenSize_A	1151	1151	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	469360011	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A	469360011	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	469360011	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	469360011	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	469360011	50	0	0
gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	469360011	50	0	0
gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	469360011	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	469360011	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	469360011	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	469360011	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	469360011	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A	469360011	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	469360011	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A	469360011	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	469360011	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A	469360011	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	469360011	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	469360011	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	469360011	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

LcSeedHwRdEnStable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	2376	0	0
T4	48462	4	0	0
T6	16025	1	0	0
T13	43153	0	0	0
T14	10053	0	0	0
T15	15270	1	0	0
T16	27925	0	0	0
T17	136533	0	0	0
T24	63421	12	0	0
T25	0	7	0	0
T37	0	1	0	0
T89	0	4	0	0
T100	34520	0	0	0
T101	11479	0	0	0
T106	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

LcSeedHwRdEnStable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	2376	0	0
T4	48462	4	0	0
T6	16025	1	0	0
T13	43153	0	0	0
T14	10053	0	0	0
T15	15270	1	0	0
T16	27925	0	0	0
T17	136533	0	0	0
T24	63421	12	0	0
T25	0	7	0	0
T37	0	1	0	0
T89	0	4	0	0
T100	34520	0	0	0
T101	11479	0	0	0
T106	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

LcSeedHwRdEnStable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	0	0	0

LcSeedHwRdEnStable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	0	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpBroadcastKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	1502213	0	0
T1	794146	1176	0	0
T2	10971	217	0	0
T3	16710	260	0	0
T4	48462	1043	0	0
T5	25453	151	0	0
T6	16025	271	0	0
T13	43153	213	0	0
T14	10053	136	0	0
T15	15270	241	0	0
T16	27925	197	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		154	145	94.16
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
ALWAYS	284	13	13	100.00
ALWAYS	308	3	3	100.00
ALWAYS	324	10	10	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
ALWAYS	407	5	5	100.00
ALWAYS	434	19	19	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
ALWAYS	499	9	9	100.00
ALWAYS	521	10	10	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	593	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	765	1	1	100.00
CONT_ASSIGN	766	1	1	100.00
CONT_ASSIGN	767	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
ALWAYS	876	2	2	100.00
ALWAYS	934	2	2	100.00
ALWAYS	961	4	4	100.00
CONT_ASSIGN	988	1	1	100.00
ALWAYS	991	3	3	100.00
CONT_ASSIGN	1043	1	1	100.00
CONT_ASSIGN	1045	1	1	100.00
CONT_ASSIGN	1079	1	0	0.00
CONT_ASSIGN	1130	1	0	0.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1300	1	0	0.00
CONT_ASSIGN	1312	1	0	0.00
CONT_ASSIGN	1336	1	1	100.00
ALWAYS	1348	2	2	100.00
CONT_ASSIGN	1362	1	1	100.00
ALWAYS	1390	9	9	100.00
CONT_ASSIGN	1421	1	1	100.00
CONT_ASSIGN	1422	1	1	100.00
CONT_ASSIGN	1424	1	1	100.00
CONT_ASSIGN	1426	1	1	100.00
CONT_ASSIGN	1430	1	1	100.00
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1441	1	1	100.00
CONT_ASSIGN	1443	1	1	100.00
CONT_ASSIGN	1475	1	1	100.00
CONT_ASSIGN	1477	1	1	100.00
CONT_ASSIGN	1481	1	1	100.00
CONT_ASSIGN	1485	1	1	100.00
CONT_ASSIGN	1489	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
251	1	1
253	10	10
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
292		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
297	1	1
298	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
308	1	1
309	1	1
311	1	1
324	1	1
329	1	1
330	1	1
334	1	1
335	1	1
336	1	1
337	1	1
			MISSING_ELSE
			MISSING_ELSE
341	1	1
342	1	1
343	1	1
344		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
			MISSING_ELSE
382	1	1
386	1	1
390	1	1
394	1	1
395	1	1
403	1	1
404	1	1
407	1	1
408	1	1
410	1	1
412	1	1
413	1	1
434	1	1
435	1	1
436	1	1
438	1	1
440	1	1
443	1	1
445	1	1
448	1	1
449	1	1
			MISSING_ELSE
453	1	1
455	1	1
459	1	1
462	1	1
464	1	1
469	1	1
470	1	1
			MISSING_ELSE
472	1	1
473	1	1
			MISSING_ELSE
478	1	1
488	1	1
496	1	1
499	1	1
500	1	1
501	1	1
502	1	1
503	1	1
505	1	1
506	1	1
507	1	1
508	1	1
521	1	1
523	1	1
525	1	1
527	1	1
529	1	1
538	1	1
540	1	1
541	1	1
542	1	1
543	1	1
585	1	1
593	1	1
640	1	1
642	1	1
765	1	1
766	1	1
767	1	1
797	1	1
799	1	1
876	1	1
877	1	1
934	1	1
935	1	1
961	1	1
962	1	1
963	1	1
964	1	1
988	1	1
991	1	1
992	1	1
994	1	1
1043	1	1
1045	1	1
1079	0	1
1130	0	1
1185	5	5
1240	0	5
1300	0	1
1312	0	1
1336	1	1
1348	1	1
1349	1	1
1362	1	1
1390	1	1
1391	1	1
1392	1	1
1393	1	1
1395	1	1
1396	1	1
1397	1	1
1398	1	1
1399	1	1
1421	1	1
1422	1	1
1424	1	1
1426	1	1
1430	1	1
1432	1	1
1434	1	1
1439	1	1
1441	1	1
1443	1	1
1475	1	1
1477	1	1
1481	1	1
1485	1	1
1489	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	104	100	96.15
Logical	104	100	96.15
Non-Logical	0	0
Event	0	0

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00110110000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b10001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[8].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[9].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd))
             -------------------1------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		vcs_gen_start:k=10:vcs_gen_end:VC_COV_UNR
1	1	Covered	T1,T7,T8

 LINE       288
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       297
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3

 LINE       298
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3

 LINE       382
 EXPRESSION ((reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q))) ? 1'b0 : direct_access_regwen_q)
             -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       382
 SUB-EXPRESSION (reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q)))
                 ---------------1--------------    -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       386
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Excluded		VC_COV_UNR
0	1	0	Excluded		VC_COV_UNR
1	0	0	Excluded		VC_COV_UNR

 LINE       403
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       436
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Excluded		VC_COV_UNR

 LINE       445
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       449
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T14,T58

 LINE       469
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T4
1	0	Covered	T2,T14,T17

 LINE       478
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T14,T15
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Covered	T10,T11,T12
1	0	0	0	Covered	T1,T4,T8

 LINE       527
 EXPRESSION (direct_access_regwen_q & dai_idle)
             -----------1----------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T183,T195,T196
1	0	Covered	T1,T2,T3
1	1	Covered	T183,T195,T196

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T183,T195,T196
1	0	Covered	T1,T2,T3
1	1	Covered	T183,T195,T196

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T183,T195,T196
1	0	Covered	T1,T2,T3
1	1	Covered	T183,T195,T196

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T183,T195,T196
1	0	Covered	T1,T2,T3
1	1	Covered	T183,T195,T196

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T183,T195,T196
1	0	Covered	T1,T2,T3
1	1	Covered	T183,T195,T196

 LINE       640
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T4

 LINE       642
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       765
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       766
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       767
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       877
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       1421
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T15,T24

 LINE       1439
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       1439
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       1441
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T15

 LINE       1441
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T15

 LINE       1443
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T15

 LINE       1443
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T15

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	149	142	95.30
Total Bits	9984	9688	97.04
Total Bits 0->1	4992	4844	97.04
Total Bits 1->0	4992	4844	97.04

Ports	149	142	95.30
Port Bits	9984	9688	97.04
Port Bits 0->1	4992	4844	97.04
Port Bits 1->0	4992	4844	97.04

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o.edn_req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
edn_i.edn_fips	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
edn_i.edn_ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
core_tl_i.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_error	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T6,T13	Yes	T1,T6,T13	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T1,T6,T13	Yes	T1,T6,T13	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T1,T6,T13	Yes	T1,T6,T13	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T1,T6,T13	Yes	T1,T6,T13	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_i.a_valid	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_o.a_ready	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
prim_tl_o.d_error	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
prim_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T3,*T5	Yes	T1,T3,T5	OUTPUT
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T5	Yes	T1,T3,T5	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
intr_otp_error_o	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T14,T17	Yes	T2,T14,T17	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T183,T195,T196	Yes	T183,T195,T196	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T183,T195,T196	Yes	T183,T195,T196	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T183,T195,T196	Yes	T183,T195,T196	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T14,T17	Yes	T2,T14,T17	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T183,T195,T196	Yes	T183,T195,T196	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T183,T195,T196	Yes	T183,T195,T196	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T183,T195,T196	Yes	T183,T195,T196	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T1,T4,T14	Yes	T1,T4,T6	INPUT
pwr_otp_i.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
lc_otp_program_i.count[383:0]	Yes	Yes	T8,T34,T9	Yes	T18,T8,T34	INPUT
lc_otp_program_i.state[319:0]	Yes	Yes	T8,T32,T34	Yes	T8,T32,T34	INPUT
lc_otp_program_i.req	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
lc_otp_program_o.ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
lc_otp_program_o.err	Yes	Yes	T18,T32,T34	Yes	T18,T32,T34	OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T4	INPUT
lc_owner_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T3,T4	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T5,T13,T16	Yes	T5,T13,T16	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T5,T116,T96	Yes	T116,T96,T241	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T4,T15,T24	Yes	T4,T6,T15	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T34,T20,T94	Yes	T106,T87,T34	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T4,T6,T15	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T4,T15,T24	Yes	T4,T6,T15	OUTPUT
otp_lc_data_o.count[0]	No	No		No		OUTPUT
otp_lc_data_o.count[14:1]	Yes	Yes	T3,T4,T6	Yes	T3,T5,T4	OUTPUT
otp_lc_data_o.count[16:15]	No	No		No		OUTPUT
otp_lc_data_o.count[27:17]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[29:28]	No	No		No		OUTPUT
otp_lc_data_o.count[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[32:31]	No	No		No		OUTPUT
otp_lc_data_o.count[41:33]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[42]	No	No		No		OUTPUT
otp_lc_data_o.count[51:43]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[52]	No	No		No		OUTPUT
otp_lc_data_o.count[63:53]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[64]	No	No		No		OUTPUT
otp_lc_data_o.count[78:65]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[79]	No	No		No		OUTPUT
otp_lc_data_o.count[84:80]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[86:85]	No	No		No		OUTPUT
otp_lc_data_o.count[101:87]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[102]	No	No		No		OUTPUT
otp_lc_data_o.count[104:103]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[105]	No	No		No		OUTPUT
otp_lc_data_o.count[115:106]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[116]	No	No		No		OUTPUT
otp_lc_data_o.count[118:117]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[119]	No	No		No		OUTPUT
otp_lc_data_o.count[121:120]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[122]	No	No		No		OUTPUT
otp_lc_data_o.count[124:123]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[125]	No	No		No		OUTPUT
otp_lc_data_o.count[134:126]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[135]	No	No		No		OUTPUT
otp_lc_data_o.count[142:136]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[143]	No	No		No		OUTPUT
otp_lc_data_o.count[151:144]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[152]	No	No		No		OUTPUT
otp_lc_data_o.count[155:153]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[156]	No	No		No		OUTPUT
otp_lc_data_o.count[164:157]	Yes	Yes	*T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[165]	No	No		No		OUTPUT
otp_lc_data_o.count[174:166]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[175]	No	No		No		OUTPUT
otp_lc_data_o.count[185:176]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[187:186]	No	No		No		OUTPUT
otp_lc_data_o.count[193:188]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[194]	No	No		No		OUTPUT
otp_lc_data_o.count[196:195]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[197]	No	No		No		OUTPUT
otp_lc_data_o.count[217:198]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[218]	No	No		No		OUTPUT
otp_lc_data_o.count[228:219]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[229]	No	No		No		OUTPUT
otp_lc_data_o.count[240:230]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[241]	No	No		No		OUTPUT
otp_lc_data_o.count[243:242]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[244]	No	No		No		OUTPUT
otp_lc_data_o.count[254:245]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[255]	No	No		No		OUTPUT
otp_lc_data_o.count[265:256]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[266]	No	No		No		OUTPUT
otp_lc_data_o.count[269:267]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[270]	No	No		No		OUTPUT
otp_lc_data_o.count[274:271]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[275]	No	No		No		OUTPUT
otp_lc_data_o.count[312:276]	Yes	Yes	*T3,T4,*T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[313]	No	No		No		OUTPUT
otp_lc_data_o.count[324:314]	Yes	Yes	*T3,T4,*T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[325]	No	No		No		OUTPUT
otp_lc_data_o.count[336:326]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[337]	No	No		No		OUTPUT
otp_lc_data_o.count[338]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[339]	No	No		No		OUTPUT
otp_lc_data_o.count[345:340]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[346]	No	No		No		OUTPUT
otp_lc_data_o.count[357:347]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.count[358]	No	No		No		OUTPUT
otp_lc_data_o.count[364:359]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[367:365]	No	No		No		OUTPUT
otp_lc_data_o.count[379:368]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[381:380]	No	No		No		OUTPUT
otp_lc_data_o.count[383:382]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[6]	No	No		No		OUTPUT
otp_lc_data_o.state[9:7]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[10]	No	No		No		OUTPUT
otp_lc_data_o.state[12:11]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[15:14]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[16]	No	No		No		OUTPUT
otp_lc_data_o.state[18:17]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[19]	No	No		No		OUTPUT
otp_lc_data_o.state[31:20]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[32]	No	No		No		OUTPUT
otp_lc_data_o.state[34:33]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[35]	No	No		No		OUTPUT
otp_lc_data_o.state[46:36]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[47]	No	No		No		OUTPUT
otp_lc_data_o.state[52:48]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[53]	No	No		No		OUTPUT
otp_lc_data_o.state[59:54]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[60]	No	No		No		OUTPUT
otp_lc_data_o.state[65:61]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[66]	No	No		No		OUTPUT
otp_lc_data_o.state[68:67]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[69]	No	No		No		OUTPUT
otp_lc_data_o.state[75:70]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[76]	No	No		No		OUTPUT
otp_lc_data_o.state[79:77]	Yes	Yes	T4,T6,*T24	Yes	T4,T6,T24	OUTPUT
otp_lc_data_o.state[80]	No	No		No		OUTPUT
otp_lc_data_o.state[84:81]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[85]	No	No		No		OUTPUT
otp_lc_data_o.state[87:86]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[88]	No	No		No		OUTPUT
otp_lc_data_o.state[95:89]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[96]	No	No		No		OUTPUT
otp_lc_data_o.state[103:97]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[106:105]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[107]	No	No		No		OUTPUT
otp_lc_data_o.state[110:108]	Yes	Yes	T4,T6,T24	Yes	T4,T6,T24	OUTPUT
otp_lc_data_o.state[111]	No	No		No		OUTPUT
otp_lc_data_o.state[123:112]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[124]	No	No		No		OUTPUT
otp_lc_data_o.state[131:125]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[133:132]	No	No		No		OUTPUT
otp_lc_data_o.state[134]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[135]	No	No		No		OUTPUT
otp_lc_data_o.state[146:136]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[147]	No	No		No		OUTPUT
otp_lc_data_o.state[149:148]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[150]	No	No		No		OUTPUT
otp_lc_data_o.state[151]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[154:152]	No	No		No		OUTPUT
otp_lc_data_o.state[156:155]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[157]	No	No		No		OUTPUT
otp_lc_data_o.state[160:158]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[161]	No	No		No		OUTPUT
otp_lc_data_o.state[180:162]	Yes	Yes	*T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[181]	No	No		No		OUTPUT
otp_lc_data_o.state[182]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[184:183]	No	No		No		OUTPUT
otp_lc_data_o.state[187:185]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[188]	No	No		No		OUTPUT
otp_lc_data_o.state[199:189]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[200]	No	No		No		OUTPUT
otp_lc_data_o.state[210:201]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[211]	No	No		No		OUTPUT
otp_lc_data_o.state[214:212]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[215]	No	No		No		OUTPUT
otp_lc_data_o.state[220:216]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[221]	No	No		No		OUTPUT
otp_lc_data_o.state[226:222]	Yes	Yes	*T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[227]	No	No		No		OUTPUT
otp_lc_data_o.state[234:228]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[237:235]	No	No		No		OUTPUT
otp_lc_data_o.state[241:238]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[242]	No	No		No		OUTPUT
otp_lc_data_o.state[243]	Yes	Yes	*T3,*T4,*T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[244]	No	No		No		OUTPUT
otp_lc_data_o.state[246:245]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[247]	No	No		No		OUTPUT
otp_lc_data_o.state[256:248]	Yes	Yes	T4,T6,*T109	Yes	T4,T6,T109	OUTPUT
otp_lc_data_o.state[257]	No	No		No		OUTPUT
otp_lc_data_o.state[260:258]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[261]	No	No		No		OUTPUT
otp_lc_data_o.state[268:262]	Yes	Yes	*T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[269]	No	No		No		OUTPUT
otp_lc_data_o.state[273:270]	Yes	Yes	T4,T6,*T109	Yes	T4,T6,T109	OUTPUT
otp_lc_data_o.state[274]	No	No		No		OUTPUT
otp_lc_data_o.state[277:275]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[279:278]	No	No		No		OUTPUT
otp_lc_data_o.state[284:280]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[286:285]	No	No		No		OUTPUT
otp_lc_data_o.state[301:287]	Yes	Yes	*T3,T4,*T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.state[302]	No	No		No		OUTPUT
otp_lc_data_o.state[319:303]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
otp_lc_data_o.error	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.owner_seed_valid	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.owner_seed[255:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_seed_valid	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_seed[255:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_root_key_share1_valid	Yes	Yes	T4,T15,T24	Yes	T4,T6,T15	OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:0]	Yes	Yes	T34,T96,T117	Yes	T34,T96,T242	OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid	Yes	Yes	T4,T15,T24	Yes	T4,T6,T15	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
flash_otp_key_i.data_req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T4,T24,T25	Yes	T4,T24,T25	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i[1].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i[2].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_i[3].req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T4,T24,T25	Yes	T4,T24,T25	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T4,T24,T25	Yes	T4,T24,T25	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T4,T24,T25	Yes	T4,T24,T25	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[3].seed_valid	Yes	Yes	T4,T24,T25	Yes	T4,T24,T25	OUTPUT
sram_otp_key_o[3].nonce[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[3].key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_o[3].ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T4,T24,T25	Yes	T4,T24,T25	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.dis_rv_dm_late_debug[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg1_data.unallocated[39:0]	Yes	Yes	T6,T37,T34	Yes	T6,T37,T110	OUTPUT
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0]	Yes	Yes	T4,T15,T24	Yes	T4,T15,T24	OUTPUT
otp_broadcast_o.valid[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T4,T13	INPUT
scan_rst_ni	Yes	Yes	T5,T4,T6	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T24	INPUT
cio_test_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
cio_test_en_o[7:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		28	27	96.43
TERNARY	382	2	1	50.00
TERNARY	1439	2	2	100.00
TERNARY	1441	2	2	100.00
TERNARY	1443	2	2	100.00
IF	287	2	2	100.00
IF	308	2	2	100.00
IF	334	2	2	100.00
IF	341	2	2	100.00
IF	407	2	2	100.00
IF	448	2	2	100.00
IF	469	2	2	100.00
IF	472	2	2	100.00
IF	499	2	2	100.00
IF	991	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	382	((reg2hw.direct_access_regwen.qe && (!reg2hw.direct_access_regwen.q))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1439	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1441	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1443	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	287	if (tlul_req)
-2-:	288	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	308	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	341	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	407	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	448	if (otp_ctrl_part_pkg::PartInfo[k].integrity)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	469	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	472	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	499	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	991	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	71	71	100.00	69	97.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	71	71	100.00	69	97.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	469360011	468476094	0	0
CoreTlOutKnown_A	469360011	468476094	0	0
CreatorRootKeyShare0Size_A	1151	1151	0	0
CreatorRootKeyShare1Size_A	1151	1151	0	0
ErrorCodeWidth_A	1151	1151	0	0
FlashAddrKeySeedSize_A	1151	1151	0	0
FlashDataKeySeedSize_A	1151	1151	0	0
FlashOtpKeyRspKnown_A	469360011	468476094	0	0
FpvSecCmCntCnstyCheck_A	469360011	50	0	0
FpvSecCmCntDaiCheck_A	469360011	50	0	0
FpvSecCmCntIntegCheck_A	469360011	50	0	0
FpvSecCmCntKdiEntropyCheck_A	469360011	50	0	0
FpvSecCmCntKdiSeedCheck_A	469360011	50	0	0
FpvSecCmCntLciCheck_A	469360011	50	0	0
FpvSecCmCntScrmblCheck_A	469360011	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	469360011	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	469360011	50	0	0
FpvSecCmCtrlLciFsmCheck_A	469360011	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	469360011	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	469360011	50	0	0
FpvSecCmDoubleLfsrCheck_A	469360011	50	0	0
FpvSecCmRegWeOnehotCheck_A	469360011	50	0	0
FpvSecCmTlLcGateFsm_A	469360011	50	0	0
IntrOtpErrorKnown_A	469360011	468476094	0	0
IntrOtpOperationDoneKnown_A	469360011	468476094	0	0
LcOtpProgramRspKnown_A	469360011	468476094	0	0
LcSeedHwRdEnStable0_A	469360011	2376	0	0
LcSeedHwRdEnStable1_A	469360011	2376	0	0
LcSeedHwRdEnStable2_A	469360011	0	0	0
LcSeedHwRdEnStable3_A	469360011	0	0	0
LcStateSize_A	1151	1151	0	0
LcTransitionCntSize_A	1151	1151	0	0
OtpAstPwrSeqKnown_A	469360011	468476094	0	0
OtpBroadcastKnown_A	469360011	468476094	0	0
OtpErrorCode0_A	1151	1151	0	0
OtpErrorCode1_A	1151	1151	0	0
OtpErrorCode2_A	1151	1151	0	0
OtpErrorCode3_A	1151	1151	0	0
OtpErrorCode4_A	1151	1151	0	0
OtpIfWidth_A	1151	1151	0	0
OtpKeymgrKeyKnown_A	469360011	468476094	0	0
OtpLcDataKnown_A	469360011	468476094	0	0
OtpOtgnKeyKnown_A	469360011	468476094	0	0
OtpRespFifoUnderflow_A	469360011	1502213	0	0
OtpSramKeyKnown_A	469360011	468476094	0	0
PartSelMustBeOnehot_A	469360011	468476094	0	0
PrimTlOutKnown_A	469360011	468476094	0	0
PwrOtpInitRspKnown_A	469360011	468476094	0	0
RmaTokenSize_A	1151	1151	0	0
SramDataKeySeedSize_A	1151	1151	0	0
TestExitTokenSize_A	1151	1151	0	0
TestUnlockTokenSize_A	1151	1151	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	469360011	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A	469360011	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	469360011	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	469360011	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	469360011	50	0	0
gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	469360011	50	0	0
gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	469360011	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	469360011	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	469360011	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	469360011	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	469360011	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A	469360011	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	469360011	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A	469360011	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	469360011	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A	469360011	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	469360011	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	469360011	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	469360011	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

LcSeedHwRdEnStable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	2376	0	0
T4	48462	4	0	0
T6	16025	1	0	0
T13	43153	0	0	0
T14	10053	0	0	0
T15	15270	1	0	0
T16	27925	0	0	0
T17	136533	0	0	0
T24	63421	12	0	0
T25	0	7	0	0
T37	0	1	0	0
T89	0	4	0	0
T100	34520	0	0	0
T101	11479	0	0	0
T106	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

LcSeedHwRdEnStable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	2376	0	0
T4	48462	4	0	0
T6	16025	1	0	0
T13	43153	0	0	0
T14	10053	0	0	0
T15	15270	1	0	0
T16	27925	0	0	0
T17	136533	0	0	0
T24	63421	12	0	0
T25	0	7	0	0
T37	0	1	0	0
T89	0	4	0	0
T100	34520	0	0	0
T101	11479	0	0	0
T106	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

LcSeedHwRdEnStable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	0	0	0

LcSeedHwRdEnStable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	0	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpBroadcastKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	1502213	0	0
T1	794146	1176	0	0
T2	10971	217	0	0
T3	16710	260	0	0
T4	48462	1043	0	0
T5	25453	151	0	0
T6	16025	271	0	0
T13	43153	213	0	0
T14	10053	136	0	0
T15	15270	241	0	0
T16	27925	197	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	50	0	0
T10	103843	10	0	0
T11	0	10	0	0
T12	0	10	0	0
T33	267660	0	0	0
T45	19250	0	0	0
T71	39614	0	0	0
T95	151466	0	0	0
T103	61601	0	0	0
T186	18129	0	0	0
T191	182255	0	0	0
T225	31762	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	21305	0	0	0