Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T21,T22

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T136,T62,T102

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T10,T11,T12

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T66,T137,T138
1	Covered	T66,T137,T138

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T2,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T13,T16

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T13,T16

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T5
ReadWaitSt	252	Covered	T1,T2,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T5,T4
IdleSt->ReadSt	236	Covered	T1,T2,T5
InitSt->ErrorSt	315	Covered	T2,T145,T165
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T14,T58,T88
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T5,T4
ReadSt->ReadWaitSt	252	Covered	T1,T2,T6
ReadWaitSt->ErrorSt	276	Covered	T141,T146,T187
ReadWaitSt->IdleSt	270	Covered	T1,T2,T6
ResetSt->ErrorSt	315	Covered	T65,T66,T67
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T5,T4
CheckFailError	317	Covered	T66,T137,T138
FsmStateError	289	Covered	T1,T2,T5
MacroEccCorrError	221	Covered	T136,T20,T62
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T1,T5,T17
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T4,T24
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T66,T137,T138
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T136,T20,T141
MacroEccCorrError->NoError	235	Covered	T62,T102,T117
NoError->AccessError	256	Covered	T1,T5,T4
NoError->CheckFailError	317	Covered	T66,T137,T138
NoError->FsmStateError	289	Covered	T2,T4,T13
NoError->MacroEccCorrError	221	Covered	T136,T20,T62

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T58,T142,T197
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T32,T34,T94
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T5,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T136,T62,T102
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T141,T146,T187
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T10,T11,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T13,T16
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T13,T16
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T66,T137,T138
1	0	Covered	T66,T137,T138
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	469360011	468476094	0	0
DigestKnown_A	469360011	468476094	0	0
DigestOffsetMustBeRepresentable_A	1151	1151	0	0
EccErrorState_A	469360011	15717	0	0
ErrorKnown_A	469360011	468476094	0	0
FsmStateKnown_A	469360011	468476094	0	0
InitDoneKnown_A	469360011	468476094	0	0
InitReadLocksPartition_A	469360011	95933517	0	0
InitWriteLocksPartition_A	469360011	95933517	0	0
OffsetMustBeBlockAligned_A	1151	1151	0	0
OtpAddrKnown_A	469360011	468476094	0	0
OtpCmdKnown_A	469360011	468476094	0	0
OtpErrorState_A	469360011	44	0	0
OtpReqKnown_A	469360011	468476094	0	0
OtpSizeKnown_A	469360011	468476094	0	0
OtpWdataKnown_A	469360011	468476094	0	0
ReadLockPropagation_A	469360011	202684382	0	0
SizeMustBeBlockAligned_A	1151	1151	0	0
TlulGntKnown_A	469360011	468476094	0	0
TlulRdataKnown_A	469360011	468476094	0	0
TlulReadOnReadLock_A	469360011	8364	0	0
TlulRerrorKnown_A	469360011	468476094	0	0
TlulRvalidKnown_A	469360011	468476094	0	0
WriteLockPropagation_A	469360011	2664732	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	469360011	28645712	0	0
u_state_regs_A	469360011	468476094	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	15717	0	0
T66	9325	2899	0	0
T75	56367	0	0	0
T137	0	3650	0	0
T138	0	2903	0	0
T143	0	3409	0	0
T144	0	2856	0	0
T147	107996	0	0	0
T158	89067	0	0	0
T159	8817	0	0	0
T160	26616	0	0	0
T161	32516	0	0	0
T162	14031	0	0	0
T163	57245	0	0	0
T164	12648	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	95933517	0	0
T1	794146	15407	0	0
T2	10971	3403	0	0
T3	16710	455	0	0
T4	48462	2313	0	0
T5	25453	10218	0	0
T6	16025	298	0	0
T13	43153	25705	0	0
T14	10053	4843	0	0
T15	15270	4297	0	0
T16	27925	11755	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	95933517	0	0
T1	794146	15407	0	0
T2	10971	3403	0	0
T3	16710	455	0	0
T4	48462	2313	0	0
T5	25453	10218	0	0
T6	16025	298	0	0
T13	43153	25705	0	0
T14	10053	4843	0	0
T15	15270	4297	0	0
T16	27925	11755	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	44	0	0
T23	470699	0	0	0
T32	255152	0	0	0
T43	14558	0	0	0
T58	9941	1	0	0
T107	14349	0	0	0
T108	21112	0	0	0
T110	21137	0	0	0
T136	109365	0	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T145	15194	0	0	0
T146	0	1	0	0
T165	14019	0	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	202684382	0	0
T1	794146	271483	0	0
T2	10971	0	0	0
T3	16710	5374	0	0
T4	48462	3047	0	0
T5	25453	17485	0	0
T6	16025	0	0	0
T7	0	492711	0	0
T13	43153	25891	0	0
T14	10053	0	0	0
T15	15270	0	0	0
T16	27925	18163	0	0
T17	0	121549	0	0
T24	0	1649	0	0
T101	0	1652	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	8364	0	0
T1	794146	7	0	0
T2	10971	0	0	0
T3	16710	0	0	0
T4	48462	1	0	0
T5	25453	11	0	0
T6	16025	0	0	0
T13	43153	7	0	0
T14	10053	0	0	0
T15	15270	0	0	0
T16	27925	2	0	0
T17	0	24	0	0
T18	0	12	0	0
T24	0	1	0	0
T100	0	4	0	0
T101	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	2664732	0	0
T7	541625	0	0	0
T8	642853	0	0	0
T17	136533	0	0	0
T18	45597	0	0	0
T24	63421	3673	0	0
T25	57361	2945	0	0
T29	14747	0	0	0
T34	0	51653	0	0
T57	0	2047	0	0
T62	0	52546	0	0
T89	0	7299	0	0
T92	0	14871	0	0
T94	0	35528	0	0
T96	0	33045	0	0
T100	34520	0	0	0
T101	11479	0	0	0
T103	0	2863	0	0
T105	22078	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	28645712	0	0
T4	48462	25172	0	0
T6	16025	0	0	0
T13	43153	4725	0	0
T14	10053	0	0	0
T15	15270	0	0	0
T16	27925	2444	0	0
T17	136533	0	0	0
T24	63421	50537	0	0
T25	0	46025	0	0
T34	0	475584	0	0
T57	0	23545	0	0
T58	0	2296	0	0
T89	0	59325	0	0
T92	0	49562	0	0
T100	34520	0	0	0
T101	11479	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T80,T81,T74

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T4,T62,T102

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T10,T11,T12

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T65,T144
1	Covered	T65,T144

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T4,T24

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T4,T24

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T5,T4
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T2,T14,T145
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T58,T142,T197
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T3,T16
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Covered	T202,T203,T187
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T65,T66,T67
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T3,T16
CheckFailError	317	Covered	T65,T144
FsmStateError	289	Covered	T1,T2,T5
MacroEccCorrError	221	Covered	T4,T62,T102
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T1,T16,T17
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T3,T16
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T65,T144
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T141,T80,T81
MacroEccCorrError->NoError	235	Covered	T4,T62,T102
NoError->AccessError	256	Covered	T1,T3,T16
NoError->CheckFailError	317	Covered	T65,T144
NoError->FsmStateError	289	Covered	T2,T5,T4
NoError->MacroEccCorrError	221	Covered	T4,T62,T102

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T80,T81,T74
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T204,T205,T206
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T34,T94,T191
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T16
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T4,T62,T102
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T202,T203,T187
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T10,T11,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T13,T17
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T13,T17
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T65,T144
1	0	Covered	T65,T144
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	469360011	468476094	0	0
DigestKnown_A	469360011	468476094	0	0
DigestOffsetMustBeRepresentable_A	1151	1151	0	0
EccErrorState_A	469360011	6353	0	0
ErrorKnown_A	469360011	468476094	0	0
FsmStateKnown_A	469360011	468476094	0	0
InitDoneKnown_A	469360011	468476094	0	0
InitReadLocksPartition_A	469360011	96118888	0	0
InitWriteLocksPartition_A	469360011	96118888	0	0
OffsetMustBeBlockAligned_A	1151	1151	0	0
OtpAddrKnown_A	469360011	468476094	0	0
OtpCmdKnown_A	469360011	468476094	0	0
OtpErrorState_A	469360011	29	0	0
OtpReqKnown_A	469360011	468476094	0	0
OtpSizeKnown_A	469360011	468476094	0	0
OtpWdataKnown_A	469360011	468476094	0	0
ReadLockPropagation_A	469360011	208130119	0	0
SizeMustBeBlockAligned_A	1151	1151	0	0
TlulGntKnown_A	469360011	468476094	0	0
TlulRdataKnown_A	469360011	468476094	0	0
TlulReadOnReadLock_A	469360011	7781	0	0
TlulRerrorKnown_A	469360011	468476094	0	0
TlulRvalidKnown_A	469360011	468476094	0	0
WriteLockPropagation_A	469360011	911035	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	469360011	11828047	0	0
u_state_regs_A	469360011	468476094	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	6353	0	0
T65	11099	3497	0	0
T144	0	2856	0	0
T149	12719	0	0	0
T150	217978	0	0	0
T151	25204	0	0	0
T152	11266	0	0	0
T153	161125	0	0	0
T154	5583	0	0	0
T155	70843	0	0	0
T156	5032	0	0	0
T157	15035	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	96118888	0	0
T1	794146	15509	0	0
T2	10971	3437	0	0
T3	16710	523	0	0
T4	48462	2517	0	0
T5	25453	10252	0	0
T6	16025	349	0	0
T13	43153	25756	0	0
T14	10053	4860	0	0
T15	15270	4331	0	0
T16	27925	11806	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	96118888	0	0
T1	794146	15509	0	0
T2	10971	3437	0	0
T3	16710	523	0	0
T4	48462	2517	0	0
T5	25453	10252	0	0
T6	16025	349	0	0
T13	43153	25756	0	0
T14	10053	4860	0	0
T15	15270	4331	0	0
T16	27925	11806	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	29	0	0
T72	72504	0	0	0
T140	10234	0	0	0
T174	9673	0	0	0
T175	13630	0	0	0
T187	0	1	0	0
T188	0	1	0	0
T193	65623	0	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	11695	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0
T210	16052	0	0	0
T211	298279	0	0	0
T212	25947	0	0	0
T213	32232	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	208130119	0	0
T1	794146	271903	0	0
T2	10971	0	0	0
T3	16710	6361	0	0
T4	48462	2548	0	0
T5	25453	13499	0	0
T6	16025	0	0	0
T7	0	534269	0	0
T8	0	378507	0	0
T13	43153	0	0	0
T14	10053	0	0	0
T15	15270	0	0	0
T16	27925	17532	0	0
T17	0	122608	0	0
T24	0	853	0	0
T101	0	2376	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	7781	0	0
T1	794146	10	0	0
T2	10971	0	0	0
T3	16710	1	0	0
T4	48462	0	0	0
T5	25453	9	0	0
T6	16025	0	0	0
T7	0	47	0	0
T8	0	40	0	0
T13	43153	9	0	0
T14	10053	0	0	0
T15	15270	0	0	0
T16	27925	2	0	0
T17	0	17	0	0
T18	0	4	0	0
T100	0	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	911035	0	0
T7	541625	0	0	0
T8	642853	0	0	0
T17	136533	0	0	0
T18	45597	0	0	0
T24	63421	2062	0	0
T25	57361	4171	0	0
T29	14747	0	0	0
T34	0	8927	0	0
T89	0	9892	0	0
T94	0	17614	0	0
T95	0	7972	0	0
T96	0	8824	0	0
T100	34520	0	0	0
T101	11479	0	0	0
T105	22078	0	0	0
T128	0	11277	0	0
T179	0	7116	0	0
T182	0	3926	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	11828047	0	0
T4	48462	38950	0	0
T5	25453	2628	0	0
T6	16025	0	0	0
T13	43153	0	0	0
T14	10053	0	0	0
T15	15270	0	0	0
T16	27925	0	0	0
T17	136533	0	0	0
T24	63421	50316	0	0
T25	0	45855	0	0
T34	0	225388	0	0
T89	0	59087	0	0
T92	0	49477	0	0
T94	0	207291	0	0
T100	34520	0	0	0
T129	0	11041	0	0
T214	0	4672	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469360011	468476094	0	0
T1	794146	794059	0	0
T2	10971	10653	0	0
T3	16710	16382	0	0
T4	48462	47426	0	0
T5	25453	25282	0	0
T6	16025	15739	0	0
T13	43153	42873	0	0
T14	10053	9790	0	0
T15	15270	15048	0	0
T16	27925	27633	0	0