Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T3,T10
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T140,T145,T146
1	Covered	T140,T145,T146

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T10

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T3,T10

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T12

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T12

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T3,T10
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T10
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T16,T190
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T191,T192,T193
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T3,T6
ReadSt->ReadWaitSt	252	Covered	T1,T3,T10
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T3,T10
ResetSt->ErrorSt	315	Covered	T65,T73,T15
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T2,T3,T6
CheckFailError	317	Covered	T140,T145,T146
FsmStateError	289	Covered	T1,T2,T10
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T2,T16,T96
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T3,T6,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T140,T145,T146
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T2,T10
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T2,T3,T6
NoError->CheckFailError	317	Covered	T140,T145,T146
NoError->FsmStateError	289	Covered	T1,T10,T4
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T10
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T65,T98
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T9,T16
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T8,T9,T16
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T140,T145,T146
1	0	Covered	T140,T145,T146
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	485267964	484436711	0	0
DigestKnown_A	485267964	484436711	0	0
DigestOffsetMustBeRepresentable_A	1157	1157	0	0
EccErrorState_A	485267964	22360	0	0
ErrorKnown_A	485267964	484436711	0	0
FsmStateKnown_A	485267964	484436711	0	0
InitDoneKnown_A	485267964	484436711	0	0
InitReadLocksPartition_A	485267964	87192719	0	0
InitWriteLocksPartition_A	485267964	87192719	0	0
OffsetMustBeBlockAligned_A	1157	1157	0	0
OtpAddrKnown_A	485267964	484436711	0	0
OtpCmdKnown_A	485267964	484436711	0	0
OtpErrorState_A	485267964	0	0	0
OtpReqKnown_A	485267964	484436711	0	0
OtpSizeKnown_A	485267964	484436711	0	0
OtpWdataKnown_A	485267964	484436711	0	0
ReadLockPropagation_A	485267964	245725402	0	0
SizeMustBeBlockAligned_A	1157	1157	0	0
TlulGntKnown_A	485267964	484436711	0	0
TlulRdataKnown_A	485267964	484436711	0	0
TlulReadOnReadLock_A	485267964	7900	0	0
TlulRerrorKnown_A	485267964	484436711	0	0
TlulRvalidKnown_A	485267964	484436711	0	0
WriteLockPropagation_A	485267964	2536694	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	485267964	30262814	0	0
u_state_regs_A	485267964	484436711	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	22360	0	0
T131	18115	0	0	0
T140	13788	3788	0	0
T143	88647	0	0	0
T145	0	2398	0	0
T146	0	2382	0	0
T148	0	2636	0	0
T149	0	2284	0	0
T154	0	2350	0	0
T155	0	2649	0	0
T156	0	3873	0	0
T158	21424	0	0	0
T159	15661	0	0	0
T160	14754	0	0	0
T161	12430	0	0	0
T162	69372	0	0	0
T163	12224	0	0	0
T164	11942	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	87192719	0	0
T1	15720	3878	0	0
T2	32382	6344	0	0
T3	77057	2346	0	0
T4	11406	5132	0	0
T5	4679	52	0	0
T6	65643	1379	0	0
T10	10040	3947	0	0
T11	6040	77	0	0
T12	10914	3192	0	0
T13	9832	1283	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	87192719	0	0
T1	15720	3878	0	0
T2	32382	6344	0	0
T3	77057	2346	0	0
T4	11406	5132	0	0
T5	4679	52	0	0
T6	65643	1379	0	0
T10	10040	3947	0	0
T11	6040	77	0	0
T12	10914	3192	0	0
T13	9832	1283	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	245725402	0	0
T2	32382	24318	0	0
T3	77057	8261	0	0
T4	11406	0	0	0
T5	4679	0	0	0
T6	65643	21559	0	0
T7	0	33274	0	0
T9	0	197538	0	0
T10	10040	0	0	0
T11	6040	0	0	0
T12	10914	0	0	0
T13	9832	0	0	0
T16	0	86653	0	0
T59	0	18330	0	0
T65	0	73838	0	0
T95	11060	0	0	0
T96	0	58824	0	0
T97	0	5656	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	7900	0	0
T2	32382	1	0	0
T3	77057	10	0	0
T4	11406	0	0	0
T5	4679	0	0	0
T6	65643	6	0	0
T7	0	7	0	0
T8	0	1	0	0
T9	0	85	0	0
T10	10040	0	0	0
T11	6040	0	0	0
T12	10914	0	0	0
T13	9832	0	0	0
T16	0	123	0	0
T59	0	2	0	0
T95	11060	0	0	0
T96	0	16	0	0
T97	0	8	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	2536694	0	0
T3	77057	2475	0	0
T4	11406	0	0	0
T5	4679	0	0	0
T6	65643	6119	0	0
T7	0	9196	0	0
T10	10040	0	0	0
T11	6040	0	0	0
T12	10914	0	0	0
T13	9832	0	0	0
T16	0	18653	0	0
T33	0	11167	0	0
T46	15566	0	0	0
T59	0	9023	0	0
T65	0	5777	0	0
T70	0	4253	0	0
T91	0	4131	0	0
T93	0	9001	0	0
T95	11060	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	30262814	0	0
T3	77057	65847	0	0
T4	11406	0	0	0
T5	4679	0	0	0
T6	65643	40724	0	0
T7	0	124071	0	0
T10	10040	0	0	0
T11	6040	0	0	0
T12	10914	2487	0	0
T13	9832	0	0	0
T16	0	168900	0	0
T46	15566	0	0	0
T50	0	38601	0	0
T59	0	79515	0	0
T65	0	269491	0	0
T95	11060	3731	0	0
T116	0	2677	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T95,T67,T147

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T97,T50,T116

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T146,T148,T149
1	Covered	T146,T148,T149

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T10

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T3,T10

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T6

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T6

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T3,T10
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T4
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T16,T191,T192
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T10,T152,T175
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T3,T6
ReadSt->ReadWaitSt	252	Covered	T1,T3,T10
ReadWaitSt->ErrorSt	276	Covered	T116,T194,T195
ReadWaitSt->IdleSt	270	Covered	T1,T3,T10
ResetSt->ErrorSt	315	Covered	T65,T73,T15
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T3,T6
CheckFailError	317	Covered	T146,T148,T149
FsmStateError	289	Covered	T1,T2,T4
MacroEccCorrError	221	Covered	T95,T97,T50
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T2,T9,T16
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T3,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T146,T148,T149
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T95,T97,T116
MacroEccCorrError->NoError	235	Covered	T50,T33,T70
NoError->AccessError	256	Covered	T2,T3,T6
NoError->CheckFailError	317	Covered	T146,T148,T149
NoError->FsmStateError	289	Covered	T1,T4,T6
NoError->MacroEccCorrError	221	Covered	T95,T97,T50

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T95,T67,T147
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T10,T152,T175
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T10
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T98,T196
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T97,T50,T116
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T116,T194,T195
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T13,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T13,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T146,T148,T149
1	0	Covered	T146,T148,T149
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	485267964	484436711	0	0
DigestKnown_A	485267964	484436711	0	0
DigestOffsetMustBeRepresentable_A	1157	1157	0	0
EccErrorState_A	485267964	13305	0	0
ErrorKnown_A	485267964	484436711	0	0
FsmStateKnown_A	485267964	484436711	0	0
InitDoneKnown_A	485267964	484436711	0	0
InitReadLocksPartition_A	485267964	87371086	0	0
InitWriteLocksPartition_A	485267964	87371086	0	0
OffsetMustBeBlockAligned_A	1157	1157	0	0
OtpAddrKnown_A	485267964	484436711	0	0
OtpCmdKnown_A	485267964	484436711	0	0
OtpErrorState_A	485267964	80	0	0
OtpReqKnown_A	485267964	484436711	0	0
OtpSizeKnown_A	485267964	484436711	0	0
OtpWdataKnown_A	485267964	484436711	0	0
ReadLockPropagation_A	485267964	238912354	0	0
SizeMustBeBlockAligned_A	1157	1157	0	0
TlulGntKnown_A	485267964	484436711	0	0
TlulRdataKnown_A	485267964	484436711	0	0
TlulReadOnReadLock_A	485267964	8211	0	0
TlulRerrorKnown_A	485267964	484436711	0	0
TlulRvalidKnown_A	485267964	484436711	0	0
WriteLockPropagation_A	485267964	2601039	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	485267964	29999388	0	0
u_state_regs_A	485267964	484436711	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	13305	0	0
T60	64740	0	0	0
T146	14650	2382	0	0
T148	0	2636	0	0
T149	0	2284	0	0
T156	0	3873	0	0
T157	0	2130	0	0
T165	9098	0	0	0
T166	12880	0	0	0
T167	53627	0	0	0
T168	5826	0	0	0
T169	11377	0	0	0
T170	21447	0	0	0
T171	9955	0	0	0
T172	23173	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	87371086	0	0
T1	15720	3929	0	0
T2	32382	6378	0	0
T3	77057	2652	0	0
T4	11406	5166	0	0
T5	4679	69	0	0
T6	65643	1549	0	0
T10	10040	3988	0	0
T11	6040	94	0	0
T12	10914	3226	0	0
T13	9832	1334	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	87371086	0	0
T1	15720	3929	0	0
T2	32382	6378	0	0
T3	77057	2652	0	0
T4	11406	5166	0	0
T5	4679	69	0	0
T6	65643	1549	0	0
T10	10040	3988	0	0
T11	6040	94	0	0
T12	10914	3226	0	0
T13	9832	1334	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	80	0	0
T4	11406	0	0	0
T5	4679	0	0	0
T6	65643	0	0	0
T7	143329	0	0	0
T10	10040	1	0	0
T11	6040	0	0	0
T12	10914	0	0	0
T13	9832	0	0	0
T46	15566	0	0	0
T95	11060	0	0	0
T116	0	1	0	0
T152	0	1	0	0
T175	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	238912354	0	0
T2	32382	24312	0	0
T3	77057	6238	0	0
T4	11406	0	0	0
T5	4679	0	0	0
T6	65643	17355	0	0
T7	0	32324	0	0
T9	0	138295	0	0
T10	10040	0	0	0
T11	6040	0	0	0
T12	10914	0	0	0
T13	9832	0	0	0
T16	0	81521	0	0
T50	0	23701	0	0
T59	0	10521	0	0
T65	0	93294	0	0
T95	11060	0	0	0
T96	0	58811	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	8211	0	0
T2	32382	8	0	0
T3	77057	4	0	0
T4	11406	0	0	0
T5	4679	0	0	0
T6	65643	5	0	0
T7	0	4	0	0
T8	0	5	0	0
T9	0	88	0	0
T10	10040	0	0	0
T11	6040	0	0	0
T12	10914	0	0	0
T13	9832	1	0	0
T16	0	111	0	0
T59	0	2	0	0
T95	11060	0	0	0
T96	0	6	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	2601039	0	0
T3	77057	1427	0	0
T4	11406	0	0	0
T5	4679	0	0	0
T6	65643	6119	0	0
T7	0	15172	0	0
T10	10040	0	0	0
T11	6040	0	0	0
T12	10914	0	0	0
T13	9832	0	0	0
T16	0	7834	0	0
T33	0	19765	0	0
T46	15566	0	0	0
T65	0	33898	0	0
T71	0	12131	0	0
T91	0	6254	0	0
T92	0	5346	0	0
T93	0	5950	0	0
T95	11060	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	29999388	0	0
T3	77057	65558	0	0
T4	11406	0	0	0
T5	4679	0	0	0
T6	65643	51867	0	0
T7	0	123816	0	0
T10	10040	2743	0	0
T11	6040	0	0	0
T12	10914	0	0	0
T13	9832	0	0	0
T16	0	177571	0	0
T46	15566	0	0	0
T50	0	38550	0	0
T59	0	47099	0	0
T65	0	268794	0	0
T91	0	76094	0	0
T95	11060	0	0	0
T116	0	2643	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T150,T74,T151

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T50,T33,T70

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T140,T146,T148
1	Covered	T140,T146,T148

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T2,T10,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T10

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T3,T10

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T3,T10
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T6,T12
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T16,T191,T192
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T1,T10,T4
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T3,T6
ReadSt->ReadWaitSt	252	Covered	T1,T3,T10
ReadWaitSt->ErrorSt	276	Covered	T97,T142,T197
ReadWaitSt->IdleSt	270	Covered	T1,T3,T10
ResetSt->ErrorSt	315	Covered	T65,T73,T15
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T3,T6
CheckFailError	317	Covered	T140,T146,T148
FsmStateError	289	Covered	T2,T10,T6
MacroEccCorrError	221	Covered	T50,T33,T70
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T2,T16,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T3,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T140,T146,T148
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T10,T6
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T198,T199,T142
MacroEccCorrError->NoError	235	Covered	T50,T33,T70
NoError->AccessError	256	Covered	T2,T3,T6
NoError->CheckFailError	317	Covered	T140,T146,T148
NoError->FsmStateError	289	Covered	T10,T6,T12
NoError->MacroEccCorrError	221	Covered	T50,T33,T70

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T150,T74,T151
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T95
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T10
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T65,T98
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T50,T33,T70
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T97,T142,T197
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T140,T146,T148
1	0	Covered	T140,T146,T148
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T10,T6
1	0	Covered	T1,T2,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	485267964	484436711	0	0
DigestKnown_A	485267964	484436711	0	0
DigestOffsetMustBeRepresentable_A	1157	1157	0	0
EccErrorState_A	485267964	19443	0	0
ErrorKnown_A	485267964	484436711	0	0
FsmStateKnown_A	485267964	484436711	0	0
InitDoneKnown_A	485267964	484436711	0	0
InitReadLocksPartition_A	485267964	87548156	0	0
InitWriteLocksPartition_A	485267964	87548156	0	0
OffsetMustBeBlockAligned_A	1157	1157	0	0
OtpAddrKnown_A	485267964	484436711	0	0
OtpCmdKnown_A	485267964	484436711	0	0
OtpErrorState_A	485267964	69	0	0
OtpReqKnown_A	485267964	484436711	0	0
OtpSizeKnown_A	485267964	484436711	0	0
OtpWdataKnown_A	485267964	484436711	0	0
ReadLockPropagation_A	485267964	235090495	0	0
SizeMustBeBlockAligned_A	1157	1157	0	0
TlulGntKnown_A	485267964	484436711	0	0
TlulRdataKnown_A	485267964	484436711	0	0
TlulReadOnReadLock_A	485267964	8448	0	0
TlulRerrorKnown_A	485267964	484436711	0	0
TlulRvalidKnown_A	485267964	484436711	0	0
WriteLockPropagation_A	485267964	1947459	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	485267964	21028787	0	0
u_state_regs_A	485267964	484436711	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	19443	0	0
T131	18115	0	0	0
T140	13788	3788	0	0
T143	88647	0	0	0
T146	0	2382	0	0
T148	0	2636	0	0
T149	0	2284	0	0
T154	0	2350	0	0
T156	0	3873	0	0
T157	0	2130	0	0
T158	21424	0	0	0
T159	15661	0	0	0
T160	14754	0	0	0
T161	12430	0	0	0
T162	69372	0	0	0
T163	12224	0	0	0
T164	11942	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	87548156	0	0
T1	15720	3970	0	0
T2	32382	6412	0	0
T3	77057	2952	0	0
T4	11406	5190	0	0
T5	4679	86	0	0
T6	65643	1719	0	0
T10	10040	4022	0	0
T11	6040	111	0	0
T12	10914	3260	0	0
T13	9832	1385	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	87548156	0	0
T1	15720	3970	0	0
T2	32382	6412	0	0
T3	77057	2952	0	0
T4	11406	5190	0	0
T5	4679	86	0	0
T6	65643	1719	0	0
T10	10040	4022	0	0
T11	6040	111	0	0
T12	10914	3260	0	0
T13	9832	1385	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	69	0	0
T1	15720	1	0	0
T2	32382	0	0	0
T3	77057	0	0	0
T4	11406	1	0	0
T5	4679	0	0	0
T6	65643	0	0	0
T10	10040	0	0	0
T11	6040	0	0	0
T12	10914	0	0	0
T13	9832	0	0	0
T95	0	1	0	0
T97	0	1	0	0
T142	0	1	0	0
T147	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	235090495	0	0
T2	32382	24305	0	0
T3	77057	7550	0	0
T4	11406	0	0	0
T5	4679	0	0	0
T6	65643	26314	0	0
T7	0	39813	0	0
T9	0	176522	0	0
T10	10040	0	0	0
T11	6040	0	0	0
T12	10914	0	0	0
T13	9832	0	0	0
T16	0	57016	0	0
T50	0	14883	0	0
T59	0	8503	0	0
T65	0	84291	0	0
T95	11060	0	0	0
T97	0	6812	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	8448	0	0
T2	32382	9	0	0
T3	77057	6	0	0
T4	11406	0	0	0
T5	4679	0	0	0
T6	65643	2	0	0
T7	0	5	0	0
T8	0	2	0	0
T9	0	62	0	0
T10	10040	0	0	0
T11	6040	0	0	0
T12	10914	0	0	0
T13	9832	0	0	0
T16	0	98	0	0
T59	0	1	0	0
T95	11060	0	0	0
T96	0	8	0	0
T97	0	6	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	1947459	0	0
T6	65643	6513	0	0
T7	143329	18015	0	0
T8	31729	0	0	0
T9	740502	0	0	0
T12	10914	0	0	0
T13	9832	0	0	0
T16	457596	7542	0	0
T46	15566	0	0	0
T59	95816	3834	0	0
T65	0	9912	0	0
T71	0	24121	0	0
T93	0	5400	0	0
T94	0	6148	0	0
T95	11060	0	0	0
T98	0	4932	0	0
T107	0	2529	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	21028787	0	0
T1	15720	3054	0	0
T2	32382	0	0	0
T3	77057	65275	0	0
T4	11406	3867	0	0
T5	4679	0	0	0
T6	65643	51731	0	0
T7	0	123561	0	0
T10	10040	0	0	0
T11	6040	0	0	0
T12	10914	0	0	0
T13	9832	0	0	0
T16	0	86318	0	0
T59	0	79209	0	0
T65	0	184075	0	0
T95	0	3709	0	0
T116	0	2609	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0