Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 7368026 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 7080585 1 T1 106 T2 708 T3 989



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 8603367 1 T1 1810 T2 2517 T3 3488
values[0x0] 2240464 1 T1 33 T2 125 T3 134
values[0x1] 3604780 1 T1 31 T2 116 T3 136



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4826556 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 9622055 1 T1 675 T2 1291 T3 1772



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 50477 1 T1 5 T2 16 T3 16
valid_sources[0x01] 55783 1 T1 11 T2 7 T3 25
valid_sources[0x02] 134941 1 T1 111 T2 13 T3 20
valid_sources[0x03] 51059 1 T2 7 T3 6 T5 38
valid_sources[0x04] 48649 1 T1 68 T2 1 T3 31
valid_sources[0x05] 59854 1 T2 23 T3 8 T5 32
valid_sources[0x06] 87435 1 T2 11 T3 13 T5 33
valid_sources[0x07] 54134 1 T1 2 T2 5 T3 11
valid_sources[0x08] 57561 1 T2 9 T3 19 T5 24
valid_sources[0x09] 49923 1 T2 9 T3 20 T5 37
valid_sources[0x0a] 56721 1 T1 35 T2 3 T3 9
valid_sources[0x0b] 57420 1 T1 25 T2 30 T3 20
valid_sources[0x0c] 57509 1 T2 15 T3 22 T5 37
valid_sources[0x0d] 54899 1 T1 10 T2 10 T3 11
valid_sources[0x0e] 48727 1 T2 2 T3 15 T5 41
valid_sources[0x0f] 50044 1 T1 20 T2 11 T3 28
valid_sources[0x10] 52814 1 T2 3 T3 16 T5 46
valid_sources[0x11] 50567 1 T1 6 T2 17 T3 20
valid_sources[0x12] 52767 1 T1 10 T2 4 T3 11
valid_sources[0x13] 46980 1 T2 10 T3 25 T5 30
valid_sources[0x14] 54668 1 T2 15 T3 17 T5 30
valid_sources[0x15] 62588 1 T1 5 T2 3 T3 13
valid_sources[0x16] 57727 1 T2 13 T3 25 T5 32
valid_sources[0x17] 48569 1 T1 14 T2 12 T3 9
valid_sources[0x18] 57461 1 T2 30 T3 24 T5 18
valid_sources[0x19] 51515 1 T2 10 T3 20 T5 35
valid_sources[0x1a] 50610 1 T2 7 T3 7 T5 41
valid_sources[0x1b] 53048 1 T2 4 T3 10 T5 26
valid_sources[0x1c] 51213 1 T2 14 T3 22 T5 26
valid_sources[0x1d] 52592 1 T1 6 T2 15 T3 14
valid_sources[0x1e] 49984 1 T2 13 T3 17 T5 28
valid_sources[0x1f] 52443 1 T2 22 T3 15 T5 26
valid_sources[0x20] 50256 1 T2 8 T3 31 T5 38
valid_sources[0x21] 49560 1 T1 17 T2 3 T3 8
valid_sources[0x22] 54256 1 T2 12 T3 11 T5 41
valid_sources[0x23] 50528 1 T1 33 T2 17 T3 11
valid_sources[0x24] 57200 1 T1 3 T2 21 T3 6
valid_sources[0x25] 61489 1 T2 13 T3 13 T5 45
valid_sources[0x26] 54038 1 T1 43 T2 22 T3 10
valid_sources[0x27] 162411 1 T2 11 T3 11 T5 38
valid_sources[0x28] 56205 1 T2 25 T3 19 T5 29
valid_sources[0x29] 56269 1 T1 3 T2 7 T3 13
valid_sources[0x2a] 48842 1 T2 31 T3 10 T5 21
valid_sources[0x2b] 63987 1 T2 4 T3 9 T5 27
valid_sources[0x2c] 49464 1 T1 4 T2 9 T3 7
valid_sources[0x2d] 52151 1 T1 13 T2 25 T3 22
valid_sources[0x2e] 76815 1 T2 14 T3 17 T5 52
valid_sources[0x2f] 52699 1 T1 3 T2 22 T3 10
valid_sources[0x30] 50306 1 T2 11 T3 13 T5 27
valid_sources[0x31] 53897 1 T1 37 T2 6 T3 13
valid_sources[0x32] 60352 1 T1 45 T2 3 T3 24
valid_sources[0x33] 59920 1 T1 9 T2 18 T3 14
valid_sources[0x34] 49722 1 T1 9 T2 10 T3 11
valid_sources[0x35] 56945 1 T1 8 T3 14 T5 33
valid_sources[0x36] 65756 1 T2 13 T3 15 T5 36
valid_sources[0x37] 66252 1 T2 27 T3 25 T5 52
valid_sources[0x38] 47374 1 T2 1 T3 11 T5 29
valid_sources[0x39] 50348 1 T2 10 T3 17 T5 32
valid_sources[0x3a] 52927 1 T1 2 T2 1 T3 11
valid_sources[0x3b] 116137 1 T1 21 T2 3 T3 11
valid_sources[0x3c] 48351 1 T1 5 T2 16 T3 29
valid_sources[0x3d] 53053 1 T1 2 T2 5 T3 20
valid_sources[0x3e] 53881 1 T2 12 T3 13 T5 41
valid_sources[0x3f] 51132 1 T2 21 T3 7 T5 47
valid_sources[0x40] 49404 1 T2 14 T3 17 T5 20
valid_sources[0x41] 61589 1 T1 2 T2 23 T3 19
valid_sources[0x42] 50908 1 T3 14 T5 48 T9 15
valid_sources[0x43] 52054 1 T2 11 T3 25 T5 64
valid_sources[0x44] 50705 1 T2 14 T3 17 T5 35
valid_sources[0x45] 68897 1 T1 2 T2 17 T3 15
valid_sources[0x46] 51550 1 T1 9 T2 4 T3 20
valid_sources[0x47] 58805 1 T2 16 T3 5 T5 40
valid_sources[0x48] 51984 1 T1 2 T2 1 T3 9
valid_sources[0x49] 48923 1 T3 13 T5 60 T9 13
valid_sources[0x4a] 52088 1 T1 43 T2 9 T3 11
valid_sources[0x4b] 51295 1 T2 3 T3 15 T5 33
valid_sources[0x4c] 55609 1 T2 5 T3 7 T5 16
valid_sources[0x4d] 64521 1 T2 6 T3 30 T5 49
valid_sources[0x4e] 49684 1 T1 10 T2 9 T3 14
valid_sources[0x4f] 48476 1 T1 10 T2 8 T3 21
valid_sources[0x50] 61187 1 T2 2 T3 16 T5 29
valid_sources[0x51] 46443 1 T1 11 T2 13 T3 9
valid_sources[0x52] 58042 1 T1 10 T2 14 T3 13
valid_sources[0x53] 66781 1 T1 14 T2 9 T3 11
valid_sources[0x54] 49762 1 T2 17 T3 9 T5 32
valid_sources[0x55] 52512 1 T1 10 T2 26 T3 15
valid_sources[0x56] 60231 1 T1 16 T2 19 T3 10
valid_sources[0x57] 62944 1 T1 9 T2 9 T3 19
valid_sources[0x58] 51554 1 T2 17 T3 15 T5 30
valid_sources[0x59] 77829 1 T2 19 T3 10 T5 40
valid_sources[0x5a] 53798 1 T2 4 T3 15 T5 30
valid_sources[0x5b] 50552 1 T1 14 T2 14 T3 6
valid_sources[0x5c] 52849 1 T2 13 T3 21 T5 41
valid_sources[0x5d] 50297 1 T2 4 T3 13 T5 57
valid_sources[0x5e] 55974 1 T1 35 T2 12 T3 12
valid_sources[0x5f] 55117 1 T1 17 T2 10 T3 16
valid_sources[0x60] 56324 1 T1 13 T2 5 T3 19
valid_sources[0x61] 61489 1 T2 9 T3 13 T5 83
valid_sources[0x62] 49239 1 T1 11 T2 1 T3 9
valid_sources[0x63] 151620 1 T1 28 T2 20 T3 17
valid_sources[0x64] 50052 1 T1 28 T2 4 T3 12
valid_sources[0x65] 54443 1 T2 16 T3 6 T5 22
valid_sources[0x66] 56234 1 T2 3 T3 20 T5 40
valid_sources[0x67] 54116 1 T2 2 T3 14 T5 27
valid_sources[0x68] 56936 1 T2 10 T3 13 T5 21
valid_sources[0x69] 53159 1 T2 4 T3 12 T5 35
valid_sources[0x6a] 51442 1 T2 19 T3 21 T5 43
valid_sources[0x6b] 53476 1 T1 6 T2 7 T3 19
valid_sources[0x6c] 51219 1 T2 7 T3 18 T5 27
valid_sources[0x6d] 53575 1 T2 10 T3 32 T5 30
valid_sources[0x6e] 68877 1 T2 20 T3 13 T5 46
valid_sources[0x6f] 47726 1 T2 7 T3 25 T5 40
valid_sources[0x70] 52736 1 T2 6 T3 14 T5 36
valid_sources[0x71] 49571 1 T1 20 T2 15 T3 5
valid_sources[0x72] 52523 1 T2 5 T3 3 T5 32
valid_sources[0x73] 49561 1 T2 1 T3 9 T5 38
valid_sources[0x74] 49333 1 T2 2 T3 16 T5 36
valid_sources[0x75] 51554 1 T2 9 T3 10 T5 42
valid_sources[0x76] 48144 1 T1 47 T2 10 T3 7
valid_sources[0x77] 51970 1 T2 11 T3 16 T5 41
valid_sources[0x78] 49053 1 T2 8 T3 8 T5 21
valid_sources[0x79] 62005 1 T1 2 T2 10 T3 24
valid_sources[0x7a] 53254 1 T2 10 T3 13 T5 38
valid_sources[0x7b] 60662 1 T2 11 T3 27 T5 35
valid_sources[0x7c] 61229 1 T2 7 T3 7 T5 27
valid_sources[0x7d] 48471 1 T2 7 T3 12 T5 29
valid_sources[0x7e] 48575 1 T2 2 T3 13 T5 33
valid_sources[0x7f] 57383 1 T2 5 T3 15 T5 52
valid_sources[0x80] 53384 1 T1 21 T2 15 T3 13



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 3478485 1 T1 83 T2 615 T3 879
values[0x0] all_enables biggest_size 1841411 1 T1 11 T2 56 T3 59
values[0x1] all_enables biggest_size 1760689 1 T1 12 T2 37 T3 51


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 235861 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 8556261 1 T1 60 T2 160 T3 40



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 2189315 1 T1 30 T2 80 T3 20
values[0x0] 3207583 1 T1 14 T2 39 T3 8
values[0x1] 3395224 1 T1 16 T2 41 T3 12



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 85256 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 8706866 1 T1 60 T2 160 T3 40



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 35448 1 T10 1 T6 576 T141 2
valid_sources[0x01] 35817 1 T16 1 T6 542 T97 1
valid_sources[0x02] 35448 1 T6 446 T197 4 T7 369
valid_sources[0x03] 34793 1 T16 1 T95 1 T6 573
valid_sources[0x04] 34984 1 T13 9 T16 2 T6 504
valid_sources[0x05] 33954 1 T5 2 T6 489 T18 4
valid_sources[0x06] 33795 1 T8 11 T6 492 T18 1
valid_sources[0x07] 33722 1 T10 1 T6 547 T18 1
valid_sources[0x08] 34261 1 T12 1 T16 1 T95 2
valid_sources[0x09] 36651 1 T5 2 T12 1 T16 2
valid_sources[0x0a] 35480 1 T5 1 T12 1 T16 3
valid_sources[0x0b] 33983 1 T16 1 T6 572 T197 1
valid_sources[0x0c] 34233 1 T3 1 T12 2 T16 1
valid_sources[0x0d] 33601 1 T6 580 T96 5 T97 3
valid_sources[0x0e] 33556 1 T10 1 T6 606 T18 3
valid_sources[0x0f] 34323 1 T6 512 T18 2 T7 403
valid_sources[0x10] 34352 1 T16 1 T6 529 T130 1
valid_sources[0x11] 34649 1 T95 1 T6 553 T130 2
valid_sources[0x12] 35348 1 T16 1 T6 538 T130 1
valid_sources[0x13] 33553 1 T12 3 T16 2 T6 598
valid_sources[0x14] 37122 1 T3 1 T6 530 T96 1
valid_sources[0x15] 33008 1 T9 1 T16 2 T95 3
valid_sources[0x16] 35237 1 T5 1 T12 1 T16 1
valid_sources[0x17] 35087 1 T12 2 T16 2 T6 524
valid_sources[0x18] 34385 1 T12 1 T16 1 T6 533
valid_sources[0x19] 34611 1 T5 1 T16 1 T95 5
valid_sources[0x1a] 34251 1 T3 1 T10 2 T16 1
valid_sources[0x1b] 34533 1 T6 559 T130 2 T7 405
valid_sources[0x1c] 34283 1 T12 4 T16 1 T6 491
valid_sources[0x1d] 33865 1 T16 1 T6 532 T130 4
valid_sources[0x1e] 34600 1 T16 1 T6 506 T130 2
valid_sources[0x1f] 35659 1 T95 1 T6 550 T130 2
valid_sources[0x20] 33396 1 T13 4 T6 481 T130 2
valid_sources[0x21] 33228 1 T3 2 T16 1 T6 523
valid_sources[0x22] 33436 1 T16 2 T6 619 T18 1
valid_sources[0x23] 33906 1 T16 3 T6 511 T130 1
valid_sources[0x24] 34472 1 T3 1 T6 541 T130 1
valid_sources[0x25] 33325 1 T6 610 T130 1 T18 1
valid_sources[0x26] 37266 1 T3 1 T12 2 T13 4
valid_sources[0x27] 35371 1 T16 1 T6 609 T18 1
valid_sources[0x28] 33886 1 T13 6 T95 4 T6 532
valid_sources[0x29] 34178 1 T95 1 T6 552 T18 2
valid_sources[0x2a] 33344 1 T8 3 T16 1 T6 597
valid_sources[0x2b] 34894 1 T6 512 T141 2 T7 405
valid_sources[0x2c] 34199 1 T6 543 T130 2 T97 1
valid_sources[0x2d] 33296 1 T12 1 T16 3 T6 507
valid_sources[0x2e] 34685 1 T16 1 T6 538 T97 1
valid_sources[0x2f] 32859 1 T16 1 T95 3 T6 482
valid_sources[0x30] 33090 1 T6 518 T130 1 T97 2
valid_sources[0x31] 35706 1 T95 3 T6 538 T18 2
valid_sources[0x32] 32965 1 T16 2 T95 1 T6 533
valid_sources[0x33] 34285 1 T12 1 T6 598 T130 1
valid_sources[0x34] 34345 1 T13 1 T6 534 T130 1
valid_sources[0x35] 36768 1 T12 3 T6 627 T18 1
valid_sources[0x36] 33886 1 T3 1 T6 494 T18 3
valid_sources[0x37] 33297 1 T12 3 T16 1 T95 1
valid_sources[0x38] 34854 1 T3 1 T12 1 T6 523
valid_sources[0x39] 34070 1 T6 534 T130 1 T97 1
valid_sources[0x3a] 35361 1 T3 1 T9 2 T10 1
valid_sources[0x3b] 34595 1 T12 2 T16 2 T95 2
valid_sources[0x3c] 33424 1 T10 1 T16 3 T6 574
valid_sources[0x3d] 35944 1 T8 11 T6 584 T130 1
valid_sources[0x3e] 34140 1 T16 1 T6 423 T130 1
valid_sources[0x3f] 34048 1 T16 1 T6 629 T130 1
valid_sources[0x40] 34863 1 T12 1 T16 2 T6 602
valid_sources[0x41] 34665 1 T12 1 T16 1 T6 532
valid_sources[0x42] 34288 1 T95 1 T6 523 T130 3
valid_sources[0x43] 34250 1 T6 544 T97 1 T141 1
valid_sources[0x44] 34271 1 T6 491 T18 3 T7 400
valid_sources[0x45] 34923 1 T16 1 T6 513 T97 1
valid_sources[0x46] 34206 1 T95 4 T6 515 T7 417
valid_sources[0x47] 33423 1 T95 2 T6 506 T130 1
valid_sources[0x48] 34056 1 T16 1 T6 503 T18 1
valid_sources[0x49] 34766 1 T16 1 T6 545 T130 2
valid_sources[0x4a] 35096 1 T13 10 T16 1 T6 559
valid_sources[0x4b] 33987 1 T16 1 T6 485 T130 1
valid_sources[0x4c] 34957 1 T95 2 T6 501 T96 3
valid_sources[0x4d] 34885 1 T12 1 T6 475 T130 2
valid_sources[0x4e] 33678 1 T95 3 T6 480 T18 2
valid_sources[0x4f] 36789 1 T3 1 T13 5 T16 1
valid_sources[0x50] 35497 1 T8 27 T6 498 T130 1
valid_sources[0x51] 33629 1 T6 512 T130 1 T18 2
valid_sources[0x52] 35140 1 T12 1 T6 620 T141 1
valid_sources[0x53] 34466 1 T3 1 T13 1 T16 2
valid_sources[0x54] 36448 1 T16 1 T6 581 T130 5
valid_sources[0x55] 33639 1 T16 1 T95 1 T6 509
valid_sources[0x56] 36456 1 T3 1 T13 3 T6 571
valid_sources[0x57] 32207 1 T6 541 T18 4 T97 1
valid_sources[0x58] 35346 1 T5 1 T10 1 T16 2
valid_sources[0x59] 34604 1 T5 1 T12 2 T16 5
valid_sources[0x5a] 35137 1 T6 578 T97 3 T7 415
valid_sources[0x5b] 34337 1 T6 574 T7 446 T90 2
valid_sources[0x5c] 34051 1 T16 4 T6 508 T97 1
valid_sources[0x5d] 34206 1 T16 1 T6 499 T97 1
valid_sources[0x5e] 34514 1 T9 1 T16 2 T6 560
valid_sources[0x5f] 34209 1 T8 2 T16 2 T6 561
valid_sources[0x60] 34432 1 T16 2 T6 553 T141 1
valid_sources[0x61] 32850 1 T6 571 T96 1 T141 1
valid_sources[0x62] 35390 1 T8 1 T6 531 T130 1
valid_sources[0x63] 34665 1 T3 1 T16 1 T6 500
valid_sources[0x64] 35153 1 T11 200 T16 1 T6 533
valid_sources[0x65] 34645 1 T3 1 T12 2 T6 493
valid_sources[0x66] 33884 1 T5 2 T10 1 T16 1
valid_sources[0x67] 33110 1 T1 60 T16 1 T6 533
valid_sources[0x68] 34549 1 T16 1 T6 593 T130 1
valid_sources[0x69] 32661 1 T12 3 T6 602 T7 386
valid_sources[0x6a] 35253 1 T16 1 T6 568 T130 1
valid_sources[0x6b] 33617 1 T10 1 T12 1 T16 1
valid_sources[0x6c] 33480 1 T6 542 T130 2 T18 5
valid_sources[0x6d] 34599 1 T16 2 T6 570 T130 1
valid_sources[0x6e] 35256 1 T12 1 T6 515 T130 2
valid_sources[0x6f] 35641 1 T13 2 T16 1 T6 541
valid_sources[0x70] 33250 1 T16 1 T95 1 T6 548
valid_sources[0x71] 32818 1 T6 513 T130 1 T97 1
valid_sources[0x72] 34214 1 T12 4 T16 1 T6 535
valid_sources[0x73] 33999 1 T95 1 T6 628 T97 1
valid_sources[0x74] 33790 1 T10 1 T16 1 T6 521
valid_sources[0x75] 33172 1 T3 1 T6 589 T97 1
valid_sources[0x76] 34994 1 T3 1 T10 1 T6 583
valid_sources[0x77] 35233 1 T16 1 T6 631 T130 1
valid_sources[0x78] 34290 1 T6 511 T130 2 T97 1
valid_sources[0x79] 33615 1 T3 1 T12 1 T6 623
valid_sources[0x7a] 35821 1 T6 590 T97 2 T7 412
valid_sources[0x7b] 33317 1 T16 2 T6 482 T96 2
valid_sources[0x7c] 34631 1 T6 589 T7 415 T98 2
valid_sources[0x7d] 33158 1 T6 565 T18 2 T97 3
valid_sources[0x7e] 33599 1 T95 1 T6 510 T7 388
valid_sources[0x7f] 36334 1 T10 1 T95 1 T6 507
valid_sources[0x80] 35598 1 T12 2 T95 1 T6 569



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 2175532 1 T1 30 T2 80 T3 20
values[0x0] all_enables biggest_size 3191332 1 T1 14 T2 39 T3 8
values[0x1] all_enables biggest_size 3189397 1 T1 16 T2 41 T3 12

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%