Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24422452

1

T1

1768

T2

2050

T3

2769

full_word

8113266

1

T1

106

T2

708

T3

989

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32535418	1			T1	1874		T2	2758		T3	3758
auto[TlIntgErrCmd]	89	1			T275	7		T276	9		T277	1
auto[TlIntgErrData]	99	1			T275	6		T276	6		T277	4
auto[TlIntgErrBoth]	112	1			T275	7		T276	5		T277	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9851617

1

T1

1810

T2

2517

T3

3488

auto[1]

22684101

1

T1

64

T2

241

T3

270

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6246094	1			T1	1727		T2	1902		T3	2609
auto[TlIntgErrNone]	partial	auto[1]	18176082	1			T1	41		T2	148		T3	160
auto[TlIntgErrNone]	full_word	auto[0]	3605387	1			T1	83		T2	615		T3	879
auto[TlIntgErrNone]	full_word	auto[1]	4507855	1			T1	23		T2	93		T3	110
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T275	3		T276	5		T282	4
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T275	3		T276	4		T277	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T282	1		T362	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T275	1		T363	1		T364	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T275	3		T276	4		T277	1
auto[TlIntgErrData]	partial	auto[1]	38	1			T276	2		T277	2		T358	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T275	1		T282	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1			T275	2		T277	1		T282	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T275	2		T276	2		T277	3
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T275	5		T276	3		T277	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T282	1		T361	3		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T277	1		T360	1		T281	1