Unified Coverage Report :: Module :: prim_lfsr

Module Definition

dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_lfsr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.08			71.08

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr	71.08			71.08
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr	71.08			71.08

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.08			71.08

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.08			71.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.08			71.08

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.08			71.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	118	71.08
Total Bits 0->1	83	59	71.08
Total Bits 1->0	83	59	71.08


Ports	5	4	80.00
Port Bits	166	118	71.08
Port Bits 0->1	83	59	71.08
Port Bits 1->0	83	59	71.08

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[0]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[4:1]	No	No		No		INPUT
entropy_i[5]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[7:6]	No	No		No		INPUT
entropy_i[9:8]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[10]	No	No		No		INPUT
entropy_i[11]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[13:12]	No	No		No		INPUT
entropy_i[14]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[19:15]	No	No		No		INPUT
entropy_i[20]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[21]	No	No		No		INPUT
entropy_i[22]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[24:23]	No	No		No		INPUT
entropy_i[25]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[27:26]	No	No		No		INPUT
entropy_i[28]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[29]	No	No		No		INPUT
entropy_i[31:30]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[32]	No	No		No		INPUT
entropy_i[33]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[35:34]	No	No		No		INPUT
entropy_i[38:36]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[39]	No	No		No		INPUT
state_o[39:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	118	71.08
Total Bits 0->1	83	59	71.08
Total Bits 1->0	83	59	71.08


Ports	5	4	80.00
Port Bits	166	118	71.08
Port Bits 0->1	83	59	71.08
Port Bits 1->0	83	59	71.08

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[0]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[4:1]	No	No		No		INPUT
entropy_i[5]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[7:6]	No	No		No		INPUT
entropy_i[9:8]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[10]	No	No		No		INPUT
entropy_i[11]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[13:12]	No	No		No		INPUT
entropy_i[14]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[19:15]	No	No		No		INPUT
entropy_i[20]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[21]	No	No		No		INPUT
entropy_i[22]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[24:23]	No	No		No		INPUT
entropy_i[25]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[27:26]	No	No		No		INPUT
entropy_i[28]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[29]	No	No		No		INPUT
entropy_i[31:30]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[32]	No	No		No		INPUT
entropy_i[33]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[35:34]	No	No		No		INPUT
entropy_i[38:36]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[39]	No	No		No		INPUT
state_o[39:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	118	71.08
Total Bits 0->1	83	59	71.08
Total Bits 1->0	83	59	71.08


Ports	5	4	80.00
Port Bits	166	118	71.08
Port Bits 0->1	83	59	71.08
Port Bits 1->0	83	59	71.08

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[0]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[4:1]	No	No		No		INPUT
entropy_i[5]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[7:6]	No	No		No		INPUT
entropy_i[9:8]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[10]	No	No		No		INPUT
entropy_i[11]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[13:12]	No	No		No		INPUT
entropy_i[14]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[19:15]	No	No		No		INPUT
entropy_i[20]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[21]	No	No		No		INPUT
entropy_i[22]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[24:23]	No	No		No		INPUT
entropy_i[25]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[27:26]	No	No		No		INPUT
entropy_i[28]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[29]	No	No		No		INPUT
entropy_i[31:30]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[32]	No	No		No		INPUT
entropy_i[33]	Yes	Yes	*T4	Yes	T4	INPUT
entropy_i[35:34]	No	No		No		INPUT
entropy_i[38:36]	Yes	Yes	T4	Yes	T4	INPUT
entropy_i[39]	No	No		No		INPUT
state_o[39:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%