Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.98		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	459058100	7671671	0	0
check_regwen_rd_A	459058100	3296	0	0
check_timeout_rd_A	459058100	3082	0	0
check_trigger_regwen_rd_A	459058100	3259	0	0
consistency_check_period_rd_A	459058100	3381	0	0
creator_sw_cfg_read_lock_rd_A	459058100	2910	0	0
direct_access_address_rd_A	459058100	1762	0	0
direct_access_wdata_0_rd_A	459058100	1255	0	0
direct_access_wdata_1_rd_A	459058100	1381	0	0
integrity_check_period_rd_A	459058100	3206	0	0
intr_enable_rd_A	459058100	4196	0	0
owner_sw_cfg_read_lock_rd_A	459058100	2639	0	0
rot_creator_auth_codesign_read_lock_rd_A	459058100	3035	0	0
rot_creator_auth_state_read_lock_rd_A	459058100	2792	0	0
vendor_test_read_lock_rd_A	459058100	2620	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	7671671	0	0
T6	513787	119381	0	0
T7	0	90933	0	0
T14	0	222754	0	0
T18	181251	0	0	0
T19	0	190837	0	0
T36	0	51768	0	0
T96	55474	0	0	0
T97	140995	0	0	0
T103	15092	0	0	0
T128	0	82446	0	0
T130	115923	0	0	0
T141	18354	0	0	0
T165	15517	0	0	0
T169	0	197158	0	0
T197	39647	0	0	0
T198	8367	0	0	0
T206	0	48302	0	0
T250	0	13950	0	0
T283	0	77103	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	3296	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	98	0	0
T242	0	27	0	0
T251	178839	57	0	0
T252	343821	33	0	0
T262	993476	0	0	0
T263	0	97	0	0
T264	62811	0	0	0
T338	0	52	0	0
T339	0	62	0	0
T340	0	40	0	0
T341	0	46	0	0
T342	0	118	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	3082	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	113	0	0
T242	0	18	0	0
T251	178839	54	0	0
T252	343821	87	0	0
T262	993476	0	0	0
T263	0	149	0	0
T264	62811	0	0	0
T338	0	86	0	0
T339	0	77	0	0
T340	0	46	0	0
T341	0	15	0	0
T342	0	132	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	3259	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	120	0	0
T242	0	20	0	0
T251	178839	50	0	0
T252	343821	82	0	0
T262	993476	0	0	0
T263	0	100	0	0
T264	62811	0	0	0
T338	0	94	0	0
T339	0	31	0	0
T340	0	44	0	0
T341	0	80	0	0
T342	0	77	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	3381	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	92	0	0
T242	0	26	0	0
T251	178839	35	0	0
T252	343821	51	0	0
T262	993476	0	0	0
T263	0	161	0	0
T264	62811	0	0	0
T338	0	104	0	0
T339	0	79	0	0
T340	0	32	0	0
T341	0	21	0	0
T342	0	135	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	2910	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	132	0	0
T242	0	35	0	0
T251	178839	48	0	0
T252	343821	64	0	0
T262	993476	0	0	0
T263	0	103	0	0
T264	62811	0	0	0
T338	0	116	0	0
T339	0	90	0	0
T340	0	41	0	0
T341	0	52	0	0
T342	0	159	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	1762	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	101	0	0
T242	0	32	0	0
T251	178839	78	0	0
T252	343821	59	0	0
T262	993476	0	0	0
T263	0	152	0	0
T264	62811	0	0	0
T338	0	65	0	0
T339	0	57	0	0
T340	0	44	0	0
T341	0	13	0	0
T342	0	162	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	1255	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	76	0	0
T242	0	21	0	0
T251	178839	26	0	0
T252	343821	29	0	0
T262	993476	0	0	0
T263	0	93	0	0
T264	62811	0	0	0
T338	0	34	0	0
T339	0	65	0	0
T340	0	9	0	0
T341	0	17	0	0
T342	0	105	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	1381	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	99	0	0
T242	0	17	0	0
T251	178839	37	0	0
T252	343821	23	0	0
T262	993476	0	0	0
T263	0	54	0	0
T264	62811	0	0	0
T338	0	27	0	0
T339	0	76	0	0
T340	0	20	0	0
T341	0	38	0	0
T342	0	129	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	3206	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	65	0	0
T242	0	14	0	0
T251	178839	53	0	0
T252	343821	46	0	0
T262	993476	0	0	0
T263	0	108	0	0
T264	62811	0	0	0
T338	0	60	0	0
T339	0	93	0	0
T340	0	27	0	0
T341	0	23	0	0
T342	0	133	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	4196	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	151	0	0
T242	0	43	0	0
T251	178839	53	0	0
T252	343821	68	0	0
T262	993476	0	0	0
T263	0	108	0	0
T264	62811	0	0	0
T269	0	13	0	0
T338	0	92	0	0
T339	0	52	0	0
T340	0	37	0	0
T341	0	47	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	2639	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	80	0	0
T242	0	15	0	0
T251	178839	44	0	0
T252	343821	23	0	0
T262	993476	0	0	0
T263	0	131	0	0
T264	62811	0	0	0
T338	0	61	0	0
T339	0	53	0	0
T340	0	35	0	0
T341	0	38	0	0
T342	0	115	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	3035	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	115	0	0
T242	0	41	0	0
T251	178839	54	0	0
T252	343821	29	0	0
T262	993476	0	0	0
T263	0	112	0	0
T264	62811	0	0	0
T338	0	78	0	0
T339	0	69	0	0
T340	0	42	0	0
T341	0	53	0	0
T342	0	132	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	2792	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	100	0	0
T242	0	40	0	0
T251	178839	84	0	0
T252	343821	57	0	0
T262	993476	0	0	0
T263	0	90	0	0
T264	62811	0	0	0
T338	0	65	0	0
T339	0	65	0	0
T340	0	34	0	0
T341	0	43	0	0
T342	0	161	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459058100	2620	0	0
T42	11492	0	0	0
T43	14453	0	0	0
T131	710917	0	0	0
T134	0	116	0	0
T242	0	27	0	0
T251	178839	44	0	0
T252	343821	39	0	0
T262	993476	0	0	0
T263	0	102	0	0
T264	62811	0	0	0
T338	0	86	0	0
T339	0	67	0	0
T340	0	38	0	0
T341	0	54	0	0
T342	0	138	0	0
T343	48987	0	0	0
T344	19117	0	0	0
T345	41143	0	0	0