Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	100.00	100.00		85.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.73	100.00	100.00	100.00	85.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.98		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.98		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.98		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T3,T8
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T9,T12
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T75,T163,T164
1	Covered	T75,T163,T164

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T9,T12
1	Covered	T5,T9,T12

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T5,T9
1	1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T5,T9,T12
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T8
ReadWaitSt	252	Covered	T2,T3,T8
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T5,T9,T12
IdleSt->ReadSt	236	Covered	T2,T3,T8
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T203,T172,T204
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T8,T9,T11
ReadSt->ReadWaitSt	252	Covered	T2,T3,T8
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T2,T3,T8
ResetSt->ErrorSt	315	Covered	T73,T74,T75
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T8,T9,T11
CheckFailError	317	Covered	T75,T163,T164
FsmStateError	289	Covered	T5,T9,T12
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T6,T141,T14
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T8,T9,T11
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T75,T163,T164
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T5,T9,T12
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T8,T9,T11
NoError->CheckFailError	317	Covered	T75,T163,T164
NoError->FsmStateError	289	Covered	T5,T9,T12
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T8
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T8
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T95,T155,T169
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8,T9,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T5,T9,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T75,T163,T164
1	0	Covered	T75,T163,T164
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T5,T9,T12
1	0	Covered	T5,T9,T12
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T65
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	455722203	454852145	0	0
DigestKnown_A	455722203	454852145	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	455722203	11875	0	0
ErrorKnown_A	455722203	454852145	0	0
FsmStateKnown_A	455722203	454852145	0	0
InitDoneKnown_A	455722203	454852145	0	0
InitReadLocksPartition_A	455722203	70538526	0	0
InitWriteLocksPartition_A	455722203	70538526	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	455722203	454852145	0	0
OtpCmdKnown_A	455722203	454852145	0	0
OtpErrorState_A	455722203	0	0	0
OtpReqKnown_A	455722203	454852145	0	0
OtpSizeKnown_A	455722203	454852145	0	0
OtpWdataKnown_A	455722203	454852145	0	0
ReadLockPropagation_A	455722203	166463056	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	455722203	454852145	0	0
TlulRdataKnown_A	455722203	454852145	0	0
TlulReadOnReadLock_A	455722203	8228	0	0
TlulRerrorKnown_A	455722203	454852145	0	0
TlulRvalidKnown_A	455722203	454852145	0	0
WriteLockPropagation_A	455722203	2659398	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	455722203	32101648	0	0
u_state_regs_A	455722203	454852145	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	11875	0	0
T75	10932	3659	0	0
T136	11754	0	0	0
T162	0	2588	0	0
T163	0	3433	0	0
T164	0	2195	0	0
T177	13105	0	0	0
T178	11035	0	0	0
T179	49724	0	0	0
T180	16884	0	0	0
T181	24331	0	0	0
T182	12027	0	0	0
T183	337531	0	0	0
T184	13763	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	70538526	0	0
T1	30508	356	0	0
T2	63077	693	0	0
T3	51786	7168	0	0
T5	28014	17790	0	0
T8	94381	981	0	0
T9	58562	10472	0	0
T10	14541	119	0	0
T11	93972	3818	0	0
T12	8684	2722	0	0
T13	37929	1124	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	70538526	0	0
T1	30508	356	0	0
T2	63077	693	0	0
T3	51786	7168	0	0
T5	28014	17790	0	0
T8	94381	981	0	0
T9	58562	10472	0	0
T10	14541	119	0	0
T11	93972	3818	0	0
T12	8684	2722	0	0
T13	37929	1124	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	166463056	0	0
T2	63077	6507	0	0
T3	51786	0	0	0
T5	28014	0	0	0
T6	0	181401	0	0
T8	94381	6741	0	0
T9	58562	10015	0	0
T10	14541	0	0	0
T11	93972	9644	0	0
T12	8684	0	0	0
T13	37929	5943	0	0
T16	77161	318	0	0
T18	0	35674	0	0
T95	0	3553	0	0
T130	0	6848	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	8228	0	0
T5	28014	14	0	0
T6	0	57	0	0
T8	94381	3	0	0
T9	58562	3	0	0
T10	14541	0	0	0
T11	93972	8	0	0
T12	8684	3	0	0
T13	37929	0	0	0
T16	77161	0	0	0
T18	0	15	0	0
T65	13066	0	0	0
T66	10748	0	0	0
T95	0	1	0	0
T96	0	3	0	0
T130	0	8	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	2659398	0	0
T5	28014	0	0	0
T8	94381	15367	0	0
T9	58562	10311	0	0
T10	14541	0	0	0
T11	93972	4137	0	0
T12	8684	0	0	0
T13	37929	2440	0	0
T16	77161	2616	0	0
T18	0	28168	0	0
T65	13066	0	0	0
T66	10748	0	0	0
T95	0	712	0	0
T96	0	8955	0	0
T97	0	11407	0	0
T98	0	2033	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	32101648	0	0
T1	30508	25884	0	0
T2	63077	24820	0	0
T3	51786	0	0	0
T5	28014	0	0	0
T8	94381	82704	0	0
T9	58562	37906	0	0
T10	14541	0	0	0
T11	93972	69425	0	0
T12	8684	0	0	0
T13	37929	31660	0	0
T16	0	48410	0	0
T65	0	3884	0	0
T66	0	3834	0	0
T95	0	42805	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T165,T68,T159

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T9,T130,T57

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T9,T12
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T73,T163,T164
1	Covered	T73,T163,T164

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T9,T12
1	Covered	T5,T9,T12

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T5,T9
1	1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T8

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T5,T9,T12
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T8
ReadWaitSt	252	Covered	T2,T3,T8
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T5,T9,T12
IdleSt->ReadSt	236	Covered	T2,T3,T8
InitSt->ErrorSt	315	Covered	T203,T172,T204
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T65,T67,T103
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T8,T9,T11
ReadSt->ReadWaitSt	252	Covered	T2,T3,T8
ReadWaitSt->ErrorSt	276	Covered	T152,T167,T205
ReadWaitSt->IdleSt	270	Covered	T2,T3,T8
ResetSt->ErrorSt	315	Covered	T73,T74,T75
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T8,T9,T11
CheckFailError	317	Covered	T73,T163,T164
FsmStateError	289	Covered	T5,T9,T12
MacroEccCorrError	221	Covered	T9,T130,T165
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T141,T168
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T8,T9,T11
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T73,T163,T164
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T5,T9,T12
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T130,T165,T68
MacroEccCorrError->NoError	235	Covered	T9,T57,T201
NoError->AccessError	256	Covered	T8,T9,T11
NoError->CheckFailError	317	Covered	T73,T163,T164
NoError->FsmStateError	289	Covered	T5,T9,T12
NoError->MacroEccCorrError	221	Covered	T9,T130,T165

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T165,T68,T159
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T65,T67,T103
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T8
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T8
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T95,T14,T206
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8,T9,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T9,T130,T57
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T152,T167,T205
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T5,T9,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T73,T163,T164
1	0	Covered	T73,T163,T164
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T5,T9,T12
1	0	Covered	T5,T9,T12
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	455722203	454852145	0	0
DigestKnown_A	455722203	454852145	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	455722203	10323	0	0
ErrorKnown_A	455722203	454852145	0	0
FsmStateKnown_A	455722203	454852145	0	0
InitDoneKnown_A	455722203	454852145	0	0
InitReadLocksPartition_A	455722203	70721777	0	0
InitWriteLocksPartition_A	455722203	70721777	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	455722203	454852145	0	0
OtpCmdKnown_A	455722203	454852145	0	0
OtpErrorState_A	455722203	69	0	0
OtpReqKnown_A	455722203	454852145	0	0
OtpSizeKnown_A	455722203	454852145	0	0
OtpWdataKnown_A	455722203	454852145	0	0
ReadLockPropagation_A	455722203	173270485	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	455722203	454852145	0	0
TlulRdataKnown_A	455722203	454852145	0	0
TlulReadOnReadLock_A	455722203	8317	0	0
TlulRerrorKnown_A	455722203	454852145	0	0
TlulRvalidKnown_A	455722203	454852145	0	0
WriteLockPropagation_A	455722203	2964974	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	455722203	31534469	0	0
u_state_regs_A	455722203	454852145	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	10323	0	0
T36	177858	0	0	0
T73	12402	2107	0	0
T162	0	2588	0	0
T163	0	3433	0	0
T164	0	2195	0	0
T167	71027	0	0	0
T169	710059	0	0	0
T171	60727	0	0	0
T172	15870	0	0	0
T173	12520	0	0	0
T174	15383	0	0	0
T175	29461	0	0	0
T176	89124	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	70721777	0	0
T1	30508	492	0	0
T2	63077	931	0	0
T3	51786	7270	0	0
T5	28014	17841	0	0
T8	94381	1219	0	0
T9	58562	10575	0	0
T10	14541	153	0	0
T11	93972	4107	0	0
T12	8684	2756	0	0
T13	37929	1277	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	70721777	0	0
T1	30508	492	0	0
T2	63077	931	0	0
T3	51786	7270	0	0
T5	28014	17841	0	0
T8	94381	1219	0	0
T9	58562	10575	0	0
T10	14541	153	0	0
T11	93972	4107	0	0
T12	8684	2756	0	0
T13	37929	1277	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	69	0	0
T6	513787	0	0	0
T17	6610	0	0	0
T18	181251	0	0	0
T60	14341	0	0	0
T65	13066	1	0	0
T66	10748	0	0	0
T67	10525	1	0	0
T95	50079	0	0	0
T103	15092	1	0	0
T130	115923	0	0	0
T152	0	1	0	0
T167	0	1	0	0
T185	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T191	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	173270485	0	0
T1	30508	1112	0	0
T2	63077	6315	0	0
T3	51786	0	0	0
T5	28014	0	0	0
T6	0	181958	0	0
T8	94381	14675	0	0
T9	58562	15661	0	0
T10	14541	0	0	0
T11	93972	11456	0	0
T12	8684	0	0	0
T13	37929	4932	0	0
T16	0	314	0	0
T95	0	5358	0	0
T130	0	6713	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	8317	0	0
T5	28014	15	0	0
T6	0	42	0	0
T8	94381	2	0	0
T9	58562	4	0	0
T10	14541	0	0	0
T11	93972	9	0	0
T12	8684	3	0	0
T13	37929	0	0	0
T16	77161	0	0	0
T18	0	9	0	0
T65	13066	0	0	0
T66	10748	0	0	0
T95	0	11	0	0
T96	0	1	0	0
T130	0	6	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	2964974	0	0
T2	63077	2657	0	0
T3	51786	0	0	0
T5	28014	0	0	0
T8	94381	0	0	0
T9	58562	0	0	0
T10	14541	0	0	0
T11	93972	13321	0	0
T12	8684	0	0	0
T13	37929	1326	0	0
T16	77161	0	0	0
T18	0	18717	0	0
T57	0	5986	0	0
T90	0	26101	0	0
T95	0	2973	0	0
T96	0	12672	0	0
T99	0	3080	0	0
T101	0	26215	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	31534469	0	0
T2	63077	24735	0	0
T3	51786	0	0	0
T5	28014	0	0	0
T8	94381	82483	0	0
T9	58562	37837	0	0
T10	14541	0	0	0
T11	93972	78739	0	0
T12	8684	0	0	0
T13	37929	31524	0	0
T16	77161	0	0	0
T18	0	154673	0	0
T65	0	3879	0	0
T67	0	3334	0	0
T95	0	42635	0	0
T103	0	3527	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T66,T91,T33

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T130,T57,T63

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T9,T12
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T75,T164,T162
1	Covered	T75,T164,T162

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T9,T12
1	Covered	T5,T9,T12

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T5,T9
1	1	Covered	T1,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T18

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T18

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T5,T9,T12
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T8
ReadWaitSt	252	Covered	T1,T3,T8
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T5,T9,T12
IdleSt->ReadSt	236	Covered	T1,T3,T8
InitSt->ErrorSt	315	Covered	T203,T172,T204
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T65,T67,T103
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T8,T9,T11
ReadSt->ReadWaitSt	252	Covered	T1,T3,T8
ReadWaitSt->ErrorSt	276	Covered	T176,T196,T207
ReadWaitSt->IdleSt	270	Covered	T1,T3,T8
ResetSt->ErrorSt	315	Covered	T73,T74,T75
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T8,T9,T11
CheckFailError	317	Covered	T75,T164,T162
FsmStateError	289	Covered	T5,T9,T12
MacroEccCorrError	221	Covered	T66,T130,T57
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T14,T158
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T8,T9,T11
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T75,T164,T162
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T5,T9,T12
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T66,T130,T91
MacroEccCorrError->NoError	235	Covered	T57,T63,T72
NoError->AccessError	256	Covered	T8,T9,T11
NoError->CheckFailError	317	Covered	T75,T164,T162
NoError->FsmStateError	289	Covered	T5,T9,T12
NoError->MacroEccCorrError	221	Covered	T66,T130,T57

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T66,T91,T33
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T165,T93,T186
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T8
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T8
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T95,T155,T14
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8,T9,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T130,T57,T63
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T176,T196,T207
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T5,T9,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T75,T164,T162
1	0	Covered	T75,T164,T162
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T5,T9,T12
1	0	Covered	T5,T9,T12
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	455722203	454852145	0	0
DigestKnown_A	455722203	454852145	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	455722203	8442	0	0
ErrorKnown_A	455722203	454852145	0	0
FsmStateKnown_A	455722203	454852145	0	0
InitDoneKnown_A	455722203	454852145	0	0
InitReadLocksPartition_A	455722203	70903840	0	0
InitWriteLocksPartition_A	455722203	70903840	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	455722203	454852145	0	0
OtpCmdKnown_A	455722203	454852145	0	0
OtpErrorState_A	455722203	43	0	0
OtpReqKnown_A	455722203	454852145	0	0
OtpSizeKnown_A	455722203	454852145	0	0
OtpWdataKnown_A	455722203	454852145	0	0
ReadLockPropagation_A	455722203	173666608	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	455722203	454852145	0	0
TlulRdataKnown_A	455722203	454852145	0	0
TlulReadOnReadLock_A	455722203	8676	0	0
TlulRerrorKnown_A	455722203	454852145	0	0
TlulRvalidKnown_A	455722203	454852145	0	0
WriteLockPropagation_A	455722203	1969909	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	455722203	21449062	0	0
u_state_regs_A	455722203	454852145	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	8442	0	0
T75	10932	3659	0	0
T136	11754	0	0	0
T162	0	2588	0	0
T164	0	2195	0	0
T177	13105	0	0	0
T178	11035	0	0	0
T179	49724	0	0	0
T180	16884	0	0	0
T181	24331	0	0	0
T182	12027	0	0	0
T183	337531	0	0	0
T184	13763	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	70903840	0	0
T1	30508	628	0	0
T2	63077	1169	0	0
T3	51786	7372	0	0
T5	28014	17892	0	0
T8	94381	1457	0	0
T9	58562	10677	0	0
T10	14541	187	0	0
T11	93972	4380	0	0
T12	8684	2790	0	0
T13	37929	1430	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	70903840	0	0
T1	30508	628	0	0
T2	63077	1169	0	0
T3	51786	7372	0	0
T5	28014	17892	0	0
T8	94381	1457	0	0
T9	58562	10677	0	0
T10	14541	187	0	0
T11	93972	4380	0	0
T12	8684	2790	0	0
T13	37929	1430	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	43	0	0
T7	100583	0	0	0
T57	61616	0	0	0
T62	76208	0	0	0
T89	22408	0	0	0
T93	0	1	0	0
T98	44748	0	0	0
T141	18354	0	0	0
T165	15517	1	0	0
T176	0	1	0	0
T185	11129	0	0	0
T186	0	1	0	0
T190	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	39647	0	0	0
T198	8367	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	173666608	0	0
T2	63077	7540	0	0
T3	51786	0	0	0
T5	28014	16966	0	0
T6	0	181969	0	0
T8	94381	13850	0	0
T9	58562	25838	0	0
T10	14541	0	0	0
T11	93972	10744	0	0
T12	8684	0	0	0
T13	37929	3626	0	0
T16	77161	343	0	0
T18	0	25056	0	0
T95	0	5366	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	8676	0	0
T5	28014	12	0	0
T6	0	35	0	0
T8	94381	5	0	0
T9	58562	10	0	0
T10	14541	0	0	0
T11	93972	5	0	0
T12	8684	6	0	0
T13	37929	2	0	0
T16	77161	0	0	0
T18	0	8	0	0
T65	13066	0	0	0
T66	10748	0	0	0
T95	0	10	0	0
T130	0	9	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	1969909	0	0
T5	28014	0	0	0
T8	94381	9765	0	0
T9	58562	10311	0	0
T10	14541	0	0	0
T11	93972	0	0	0
T12	8684	0	0	0
T13	37929	0	0	0
T16	77161	0	0	0
T65	13066	0	0	0
T66	10748	0	0	0
T72	0	6713	0	0
T90	0	44702	0	0
T97	0	10961	0	0
T100	0	6030	0	0
T199	0	1166	0	0
T200	0	27701	0	0
T201	0	5378	0	0
T202	0	2417	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	21449062	0	0
T5	28014	0	0	0
T8	94381	82262	0	0
T9	58562	37769	0	0
T10	14541	0	0	0
T11	93972	0	0	0
T12	8684	0	0	0
T13	37929	0	0	0
T16	77161	0	0	0
T18	0	154469	0	0
T65	13066	0	0	0
T66	10748	0	0	0
T90	0	304560	0	0
T93	0	3660	0	0
T96	0	40863	0	0
T97	0	118440	0	0
T99	0	69044	0	0
T141	0	4199	0	0
T165	0	3177	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0