Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.98		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.98		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T159,T160,T25

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T57,T161

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T9,T12
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T73,T75,T162
1	Covered	T73,T75,T162

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T9,T12
1	Covered	T5,T9,T12

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T5,T9
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T5,T9,T12
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T5,T9,T12
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T65,T67,T103
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T165,T91,T92
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T8,T9,T11
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T166,T208,T209
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T73,T74,T75
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T8,T9,T11
CheckFailError	317	Covered	T73,T75,T162
FsmStateError	289	Covered	T5,T9,T12
MacroEccCorrError	221	Covered	T9,T57,T161
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T141,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T8,T9,T11
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T73,T75,T162
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T5,T9,T12
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T159,T152,T160
MacroEccCorrError->NoError	235	Covered	T9,T57,T161
NoError->AccessError	256	Covered	T8,T9,T11
NoError->CheckFailError	317	Covered	T73,T75,T162
NoError->FsmStateError	289	Covered	T5,T9,T12
NoError->MacroEccCorrError	221	Covered	T9,T57,T161

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T159,T160,T25
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T91,T92,T210
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T95,T155,T211
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8,T9,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T9,T57,T161
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T166,T208,T209
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T5,T9,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T73,T75,T162
1	0	Covered	T73,T75,T162
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T5,T9,T12
1	0	Covered	T5,T9,T12
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	455722203	454852145	0	0
DigestKnown_A	455722203	454852145	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	455722203	11064	0	0
ErrorKnown_A	455722203	454852145	0	0
FsmStateKnown_A	455722203	454852145	0	0
InitDoneKnown_A	455722203	454852145	0	0
InitReadLocksPartition_A	455722203	71084936	0	0
InitWriteLocksPartition_A	455722203	71084936	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	455722203	454852145	0	0
OtpCmdKnown_A	455722203	454852145	0	0
OtpErrorState_A	455722203	47	0	0
OtpReqKnown_A	455722203	454852145	0	0
OtpSizeKnown_A	455722203	454852145	0	0
OtpWdataKnown_A	455722203	454852145	0	0
ReadLockPropagation_A	455722203	175144545	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	455722203	454852145	0	0
TlulRdataKnown_A	455722203	454852145	0	0
TlulReadOnReadLock_A	455722203	8336	0	0
TlulRerrorKnown_A	455722203	454852145	0	0
TlulRvalidKnown_A	455722203	454852145	0	0
WriteLockPropagation_A	455722203	2739745	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	455722203	29204169	0	0
u_state_regs_A	455722203	454852145	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	11064	0	0
T36	177858	0	0	0
T73	12402	2107	0	0
T75	0	3659	0	0
T162	0	2588	0	0
T167	71027	0	0	0
T169	710059	0	0	0
T170	0	2710	0	0
T171	60727	0	0	0
T172	15870	0	0	0
T173	12520	0	0	0
T174	15383	0	0	0
T175	29461	0	0	0
T176	89124	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	71084936	0	0
T1	30508	764	0	0
T2	63077	1407	0	0
T3	51786	7474	0	0
T5	28014	17943	0	0
T8	94381	1692	0	0
T9	58562	10779	0	0
T10	14541	221	0	0
T11	93972	4652	0	0
T12	8684	2824	0	0
T13	37929	1583	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	71084936	0	0
T1	30508	764	0	0
T2	63077	1407	0	0
T3	51786	7474	0	0
T5	28014	17943	0	0
T8	94381	1692	0	0
T9	58562	10779	0	0
T10	14541	221	0	0
T11	93972	4652	0	0
T12	8684	2824	0	0
T13	37929	1583	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	47	0	0
T33	14934	0	0	0
T63	55099	0	0	0
T91	9588	1	0	0
T92	7902	1	0	0
T93	10222	0	0	0
T94	7964	0	0	0
T99	100877	0	0	0
T155	20918	0	0	0
T166	0	1	0	0
T203	12482	0	0	0
T208	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T212	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0
T216	12124	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	175144545	0	0
T2	63077	6894	0	0
T3	51786	0	0	0
T5	28014	16964	0	0
T6	0	180625	0	0
T8	94381	21791	0	0
T9	58562	9417	0	0
T10	14541	0	0	0
T11	93972	12044	0	0
T12	8684	0	0	0
T13	37929	3458	0	0
T16	77161	129	0	0
T95	0	2757	0	0
T130	0	22593	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	8336	0	0
T5	28014	14	0	0
T6	0	33	0	0
T8	94381	2	0	0
T9	58562	3	0	0
T10	14541	0	0	0
T11	93972	5	0	0
T12	8684	4	0	0
T13	37929	2	0	0
T16	77161	0	0	0
T18	0	8	0	0
T65	13066	0	0	0
T66	10748	0	0	0
T95	0	3	0	0
T130	0	8	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	2739745	0	0
T2	63077	4853	0	0
T3	51786	0	0	0
T5	28014	0	0	0
T8	94381	5883	0	0
T9	58562	0	0	0
T10	14541	0	0	0
T11	93972	9495	0	0
T12	8684	0	0	0
T13	37929	0	0	0
T16	77161	0	0	0
T18	0	27198	0	0
T57	0	2028	0	0
T90	0	51253	0	0
T95	0	1472	0	0
T97	0	22371	0	0
T100	0	5873	0	0
T101	0	12913	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	29204169	0	0
T2	63077	53659	0	0
T3	51786	0	0	0
T5	28014	0	0	0
T8	94381	82044	0	0
T9	58562	37701	0	0
T10	14541	0	0	0
T11	93972	68744	0	0
T12	8684	0	0	0
T13	37929	31252	0	0
T16	77161	0	0	0
T18	0	154265	0	0
T95	0	42295	0	0
T96	0	40752	0	0
T97	0	118236	0	0
T197	0	17264	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T78,T77

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T57,T63,T161

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T9,T12
1	Covered	T22,T23,T24

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T163
1	Covered	T163

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T9,T12
1	Covered	T5,T9,T12

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T5,T9
1	1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T8

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T5,T9,T12
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T8
ReadWaitSt	252	Covered	T2,T3,T8
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T5,T9,T12
IdleSt->ReadSt	236	Covered	T2,T3,T8
InitSt->ErrorSt	315	Covered	T65,T67,T103
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T66,T68,T91
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T8,T9,T11
ReadSt->ReadWaitSt	252	Covered	T2,T3,T8
ReadWaitSt->ErrorSt	276	Covered	T152,T166,T167
ReadWaitSt->IdleSt	270	Covered	T2,T3,T8
ResetSt->ErrorSt	315	Covered	T73,T74,T75
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T8,T9,T11
CheckFailError	317	Covered	T163
FsmStateError	289	Covered	T5,T9,T12
MacroEccCorrError	221	Covered	T57,T63,T33
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T168,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T8,T9,T11
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T163
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T5,T9,T12
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T33,T152,T166
MacroEccCorrError->NoError	235	Covered	T57,T63,T161
NoError->AccessError	256	Covered	T8,T9,T11
NoError->CheckFailError	317	Covered	T163
NoError->FsmStateError	289	Covered	T5,T9,T12
NoError->MacroEccCorrError	221	Covered	T57,T63,T33

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T33,T78,T77
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T66,T68,T159
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T8
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T8
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T155,T211,T129
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8,T9,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T57,T63,T161
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T152,T166,T167
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T23,T24
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T5,T9,T12
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T5,T9,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T163
1	0	Covered	T163
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T5,T9,T12
1	0	Covered	T5,T9,T12
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	455722203	454852145	0	0
DigestKnown_A	455722203	454852145	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	455722203	3433	0	0
ErrorKnown_A	455722203	454852145	0	0
FsmStateKnown_A	455722203	454852145	0	0
InitDoneKnown_A	455722203	454852145	0	0
InitReadLocksPartition_A	455722203	71265214	0	0
InitWriteLocksPartition_A	455722203	71265214	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	455722203	454852145	0	0
OtpCmdKnown_A	455722203	454852145	0	0
OtpErrorState_A	455722203	36	0	0
OtpReqKnown_A	455722203	454852145	0	0
OtpSizeKnown_A	455722203	454852145	0	0
OtpWdataKnown_A	455722203	454852145	0	0
ReadLockPropagation_A	455722203	173143482	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	455722203	454852145	0	0
TlulRdataKnown_A	455722203	454852145	0	0
TlulReadOnReadLock_A	455722203	8165	0	0
TlulRerrorKnown_A	455722203	454852145	0	0
TlulRvalidKnown_A	455722203	454852145	0	0
WriteLockPropagation_A	455722203	1029357	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	455722203	12637586	0	0
u_state_regs_A	455722203	454852145	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	3433	0	0
T27	11057	0	0	0
T163	12537	3433	0	0
T217	105426	0	0	0
T218	570251	0	0	0
T219	26816	0	0	0
T220	11908	0	0	0
T221	6803	0	0	0
T222	104424	0	0	0
T223	11916	0	0	0
T224	13173	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	71265214	0	0
T1	30508	900	0	0
T2	63077	1645	0	0
T3	51786	7576	0	0
T5	28014	17994	0	0
T8	94381	1913	0	0
T9	58562	10881	0	0
T10	14541	255	0	0
T11	93972	4923	0	0
T12	8684	2858	0	0
T13	37929	1736	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	71265214	0	0
T1	30508	900	0	0
T2	63077	1645	0	0
T3	51786	7576	0	0
T5	28014	17994	0	0
T8	94381	1913	0	0
T9	58562	10881	0	0
T10	14541	255	0	0
T11	93972	4923	0	0
T12	8684	2858	0	0
T13	37929	1736	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	36	0	0
T6	513787	0	0	0
T17	6610	0	0	0
T18	181251	0	0	0
T60	14341	0	0	0
T66	10748	1	0	0
T67	10525	0	0	0
T68	0	1	0	0
T95	50079	0	0	0
T96	55474	0	0	0
T103	15092	0	0	0
T130	115923	0	0	0
T152	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T225	0	1	0	0
T226	0	1	0	0
T227	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	173143482	0	0
T1	30508	1110	0	0
T2	63077	3050	0	0
T3	51786	0	0	0
T5	28014	16962	0	0
T6	0	181524	0	0
T8	94381	14289	0	0
T9	58562	25809	0	0
T10	14541	0	0	0
T11	93972	12745	0	0
T12	8684	0	0	0
T13	37929	4095	0	0
T16	0	179	0	0
T95	0	4721	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	8165	0	0
T5	28014	8	0	0
T6	0	53	0	0
T8	94381	1	0	0
T9	58562	7	0	0
T10	14541	0	0	0
T11	93972	5	0	0
T12	8684	3	0	0
T13	37929	0	0	0
T16	77161	0	0	0
T18	0	6	0	0
T65	13066	0	0	0
T66	10748	0	0	0
T95	0	1	0	0
T96	0	1	0	0
T130	0	11	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	1029357	0	0
T2	63077	1820	0	0
T3	51786	0	0	0
T5	28014	0	0	0
T8	94381	0	0	0
T9	58562	0	0	0
T10	14541	0	0	0
T11	93972	2942	0	0
T12	8684	0	0	0
T13	37929	0	0	0
T16	77161	376	0	0
T28	0	6210	0	0
T95	0	453	0	0
T98	0	736	0	0
T101	0	39333	0	0
T129	0	24334	0	0
T228	0	26284	0	0
T229	0	3096	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	12637586	0	0
T1	30508	25408	0	0
T2	63077	53438	0	0
T3	51786	0	0	0
T5	28014	0	0	0
T8	94381	0	0	0
T9	58562	0	0	0
T10	14541	0	0	0
T11	93972	77974	0	0
T12	8684	0	0	0
T13	37929	31116	0	0
T16	0	18605	0	0
T57	0	53617	0	0
T66	0	3778	0	0
T68	0	3990	0	0
T95	0	42125	0	0
T98	0	35038	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455722203	454852145	0	0
T1	30508	29879	0	0
T2	63077	62033	0	0
T3	51786	51452	0	0
T5	28014	27728	0	0
T8	94381	93354	0	0
T9	58562	58054	0	0
T10	14541	14318	0	0
T11	93972	92621	0	0
T12	8684	8502	0	0
T13	37929	37130	0	0