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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.96 93.79 96.72 95.91 91.65 97.19 96.34 93.14


Total test records in report: 1323
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T1257 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3918598734 Aug 03 04:40:31 PM PDT 24 Aug 03 04:40:33 PM PDT 24 84411955 ps
T1258 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3337631677 Aug 03 04:40:27 PM PDT 24 Aug 03 04:40:29 PM PDT 24 573842607 ps
T1259 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.592853954 Aug 03 04:40:36 PM PDT 24 Aug 03 04:40:38 PM PDT 24 136262992 ps
T1260 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.196939444 Aug 03 04:40:59 PM PDT 24 Aug 03 04:41:06 PM PDT 24 95955308 ps
T1261 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3096573917 Aug 03 04:40:41 PM PDT 24 Aug 03 04:40:51 PM PDT 24 301384055 ps
T1262 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.587496698 Aug 03 04:40:49 PM PDT 24 Aug 03 04:40:53 PM PDT 24 230513779 ps
T1263 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.140123640 Aug 03 04:40:43 PM PDT 24 Aug 03 04:40:45 PM PDT 24 50049628 ps
T1264 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.507180917 Aug 03 04:40:39 PM PDT 24 Aug 03 04:40:41 PM PDT 24 52951277 ps
T1265 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.440522674 Aug 03 04:40:50 PM PDT 24 Aug 03 04:40:53 PM PDT 24 310701679 ps
T1266 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.4014556041 Aug 03 04:40:38 PM PDT 24 Aug 03 04:40:40 PM PDT 24 547937831 ps
T1267 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2410766239 Aug 03 04:40:29 PM PDT 24 Aug 03 04:40:30 PM PDT 24 140086516 ps
T1268 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.974425579 Aug 03 04:40:24 PM PDT 24 Aug 03 04:40:27 PM PDT 24 199396895 ps
T1269 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3874078307 Aug 03 04:40:54 PM PDT 24 Aug 03 04:41:04 PM PDT 24 1214713340 ps
T1270 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2965302495 Aug 03 04:40:28 PM PDT 24 Aug 03 04:40:31 PM PDT 24 182652478 ps
T1271 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1713812354 Aug 03 04:40:33 PM PDT 24 Aug 03 04:40:35 PM PDT 24 133811482 ps
T1272 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.1609404662 Aug 03 04:40:53 PM PDT 24 Aug 03 04:40:58 PM PDT 24 288322859 ps
T1273 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.381541132 Aug 03 04:41:19 PM PDT 24 Aug 03 04:41:21 PM PDT 24 41054458 ps
T359 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.110228911 Aug 03 04:40:50 PM PDT 24 Aug 03 04:41:27 PM PDT 24 18877094417 ps
T1274 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3862006817 Aug 03 04:40:58 PM PDT 24 Aug 03 04:41:00 PM PDT 24 563067598 ps
T1275 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.89793370 Aug 03 04:40:40 PM PDT 24 Aug 03 04:40:41 PM PDT 24 623528845 ps
T1276 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.200950166 Aug 03 04:40:39 PM PDT 24 Aug 03 04:40:42 PM PDT 24 66832068 ps
T1277 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2421026722 Aug 03 04:40:55 PM PDT 24 Aug 03 04:40:57 PM PDT 24 154766644 ps
T1278 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.4278523894 Aug 03 04:40:36 PM PDT 24 Aug 03 04:40:37 PM PDT 24 37385441 ps
T1279 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1480028899 Aug 03 04:40:53 PM PDT 24 Aug 03 04:40:55 PM PDT 24 541214964 ps
T1280 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.4228956507 Aug 03 04:40:28 PM PDT 24 Aug 03 04:40:30 PM PDT 24 596372274 ps
T1281 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.4113909403 Aug 03 04:40:30 PM PDT 24 Aug 03 04:40:32 PM PDT 24 89514845 ps
T1282 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2971928511 Aug 03 04:41:11 PM PDT 24 Aug 03 04:41:12 PM PDT 24 68649813 ps
T1283 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.3221423825 Aug 03 04:40:55 PM PDT 24 Aug 03 04:40:57 PM PDT 24 517241673 ps
T1284 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.558434694 Aug 03 04:40:37 PM PDT 24 Aug 03 04:40:39 PM PDT 24 541223425 ps
T315 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3263532225 Aug 03 04:40:56 PM PDT 24 Aug 03 04:40:58 PM PDT 24 46392901 ps
T1285 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3064923600 Aug 03 04:40:44 PM PDT 24 Aug 03 04:40:48 PM PDT 24 140333813 ps
T1286 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.1907720909 Aug 03 04:40:44 PM PDT 24 Aug 03 04:40:46 PM PDT 24 71181708 ps
T1287 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1766745518 Aug 03 04:40:34 PM PDT 24 Aug 03 04:40:36 PM PDT 24 167858442 ps
T1288 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3952163038 Aug 03 04:40:30 PM PDT 24 Aug 03 04:40:34 PM PDT 24 161996297 ps
T1289 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.690464722 Aug 03 04:40:31 PM PDT 24 Aug 03 04:40:34 PM PDT 24 119128556 ps
T1290 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3687206511 Aug 03 04:40:39 PM PDT 24 Aug 03 04:40:45 PM PDT 24 149467835 ps
T1291 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.4077244153 Aug 03 04:40:45 PM PDT 24 Aug 03 04:40:46 PM PDT 24 74623269 ps
T1292 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1856671583 Aug 03 04:40:33 PM PDT 24 Aug 03 04:40:35 PM PDT 24 37437756 ps
T1293 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1300413274 Aug 03 04:40:30 PM PDT 24 Aug 03 04:40:31 PM PDT 24 73392540 ps
T363 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1163324005 Aug 03 04:40:50 PM PDT 24 Aug 03 04:41:01 PM PDT 24 670902412 ps
T1294 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.439020936 Aug 03 04:40:34 PM PDT 24 Aug 03 04:40:44 PM PDT 24 3732782113 ps
T1295 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1160077541 Aug 03 04:40:45 PM PDT 24 Aug 03 04:40:47 PM PDT 24 149455168 ps
T1296 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.463797576 Aug 03 04:41:02 PM PDT 24 Aug 03 04:41:04 PM PDT 24 76405517 ps
T1297 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2575211731 Aug 03 04:40:38 PM PDT 24 Aug 03 04:40:41 PM PDT 24 82760814 ps
T1298 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.420712542 Aug 03 04:40:33 PM PDT 24 Aug 03 04:40:38 PM PDT 24 156065664 ps
T1299 /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3238176155 Aug 03 04:41:00 PM PDT 24 Aug 03 04:41:01 PM PDT 24 51120915 ps
T1300 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2133829455 Aug 03 04:41:01 PM PDT 24 Aug 03 04:41:05 PM PDT 24 229009998 ps
T1301 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.432795305 Aug 03 04:40:33 PM PDT 24 Aug 03 04:40:35 PM PDT 24 75462797 ps
T1302 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.83210569 Aug 03 04:40:53 PM PDT 24 Aug 03 04:40:55 PM PDT 24 554327788 ps
T1303 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2549511729 Aug 03 04:40:53 PM PDT 24 Aug 03 04:40:54 PM PDT 24 46627545 ps
T1304 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1430039267 Aug 03 04:40:57 PM PDT 24 Aug 03 04:40:58 PM PDT 24 134440862 ps
T1305 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.835071155 Aug 03 04:40:43 PM PDT 24 Aug 03 04:40:49 PM PDT 24 309499755 ps
T1306 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1858256006 Aug 03 04:41:03 PM PDT 24 Aug 03 04:41:06 PM PDT 24 261648457 ps
T1307 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.4224622616 Aug 03 04:41:05 PM PDT 24 Aug 03 04:41:06 PM PDT 24 41061210 ps
T1308 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.4052087065 Aug 03 04:40:54 PM PDT 24 Aug 03 04:40:56 PM PDT 24 136090127 ps
T1309 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.2039286656 Aug 03 04:41:03 PM PDT 24 Aug 03 04:41:05 PM PDT 24 177182259 ps
T1310 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3922787951 Aug 03 04:40:28 PM PDT 24 Aug 03 04:40:30 PM PDT 24 67675889 ps
T316 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1931200704 Aug 03 04:40:30 PM PDT 24 Aug 03 04:40:39 PM PDT 24 832838264 ps
T1311 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1618211593 Aug 03 04:40:46 PM PDT 24 Aug 03 04:41:29 PM PDT 24 5928908600 ps
T1312 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3587772838 Aug 03 04:40:33 PM PDT 24 Aug 03 04:40:40 PM PDT 24 531878688 ps
T1313 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.4217748061 Aug 03 04:40:59 PM PDT 24 Aug 03 04:41:03 PM PDT 24 137755904 ps
T1314 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3947148707 Aug 03 04:40:53 PM PDT 24 Aug 03 04:40:56 PM PDT 24 76178258 ps
T1315 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3932660068 Aug 03 04:41:05 PM PDT 24 Aug 03 04:41:07 PM PDT 24 131576930 ps
T1316 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.627487881 Aug 03 04:40:29 PM PDT 24 Aug 03 04:40:32 PM PDT 24 83518173 ps
T1317 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3142397023 Aug 03 04:40:39 PM PDT 24 Aug 03 04:40:41 PM PDT 24 298798800 ps
T1318 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3909739244 Aug 03 04:40:53 PM PDT 24 Aug 03 04:40:57 PM PDT 24 224156451 ps
T1319 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1669019987 Aug 03 04:40:53 PM PDT 24 Aug 03 04:40:56 PM PDT 24 435467858 ps
T1320 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.1827516222 Aug 03 04:40:50 PM PDT 24 Aug 03 04:40:51 PM PDT 24 133267002 ps
T364 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.266036088 Aug 03 04:40:36 PM PDT 24 Aug 03 04:40:47 PM PDT 24 10284339823 ps
T362 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2942371707 Aug 03 04:40:32 PM PDT 24 Aug 03 04:40:52 PM PDT 24 1318454219 ps
T1321 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2055028849 Aug 03 04:40:48 PM PDT 24 Aug 03 04:40:49 PM PDT 24 141117890 ps
T1322 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1252103088 Aug 03 04:41:02 PM PDT 24 Aug 03 04:41:04 PM PDT 24 568894078 ps
T1323 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.4011099591 Aug 03 04:41:03 PM PDT 24 Aug 03 04:41:05 PM PDT 24 36291464 ps

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.1395310965
Short name T11
Test name
Test status
Simulation time 939747557 ps
CPU time 35.82 seconds
Started Aug 03 06:39:49 PM PDT 24
Finished Aug 03 06:40:25 PM PDT 24
Peak memory 242452 kb
Host smart-e7171ceb-10ef-4b75-8de3-36e354d2b25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395310965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.1395310965
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.4062317835
Short name T6
Test name
Test status
Simulation time 54772319146 ps
CPU time 1310.83 seconds
Started Aug 03 06:49:15 PM PDT 24
Finished Aug 03 07:11:07 PM PDT 24
Peak memory 377540 kb
Host smart-12b96d47-2ae4-43b4-9cd6-8c59e34bf00a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062317835 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.4062317835
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.1579497538
Short name T129
Test name
Test status
Simulation time 80330160873 ps
CPU time 217.85 seconds
Started Aug 03 06:38:56 PM PDT 24
Finished Aug 03 06:42:34 PM PDT 24
Peak memory 256820 kb
Host smart-96a1601b-6aa1-4c9e-8398-5687d0110814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579497538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.1579497538
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.3420312405
Short name T57
Test name
Test status
Simulation time 1432985622 ps
CPU time 21.18 seconds
Started Aug 03 06:37:37 PM PDT 24
Finished Aug 03 06:37:58 PM PDT 24
Peak memory 248692 kb
Host smart-6fa48db5-9a54-495f-9665-c304b39743fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420312405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.3420312405
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.822551842
Short name T7
Test name
Test status
Simulation time 1669569977122 ps
CPU time 1981.53 seconds
Started Aug 03 06:37:58 PM PDT 24
Finished Aug 03 07:10:59 PM PDT 24
Peak memory 273340 kb
Host smart-78292e44-0c81-4afc-a3d3-707aa106953b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822551842 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.822551842
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.2913321998
Short name T269
Test name
Test status
Simulation time 109940827854 ps
CPU time 981.93 seconds
Started Aug 03 06:35:47 PM PDT 24
Finished Aug 03 06:52:09 PM PDT 24
Peak memory 260820 kb
Host smart-e768f479-a831-457a-bfe2-bbf19a242421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913321998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
2913321998
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.4018671082
Short name T22
Test name
Test status
Simulation time 40525221962 ps
CPU time 206.31 seconds
Started Aug 03 06:35:18 PM PDT 24
Finished Aug 03 06:38:44 PM PDT 24
Peak memory 276128 kb
Host smart-b51431da-3373-48fa-a931-f717c82a1b1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018671082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.4018671082
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.1434777681
Short name T75
Test name
Test status
Simulation time 312362192 ps
CPU time 4.15 seconds
Started Aug 03 06:57:03 PM PDT 24
Finished Aug 03 06:57:07 PM PDT 24
Peak memory 242408 kb
Host smart-553eef4c-7df5-491c-9b15-57ed352006e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434777681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.1434777681
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.587177298
Short name T18
Test name
Test status
Simulation time 1888125165 ps
CPU time 34.14 seconds
Started Aug 03 06:40:54 PM PDT 24
Finished Aug 03 06:41:29 PM PDT 24
Peak memory 242452 kb
Host smart-6083c9d6-9822-431f-af96-f77734608420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587177298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.587177298
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.3692036888
Short name T33
Test name
Test status
Simulation time 150871233 ps
CPU time 3.85 seconds
Started Aug 03 06:58:44 PM PDT 24
Finished Aug 03 06:58:48 PM PDT 24
Peak memory 242224 kb
Host smart-51eb4d85-62e1-49ab-bd9e-67ea4d696f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692036888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3692036888
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.3751056606
Short name T67
Test name
Test status
Simulation time 107419218 ps
CPU time 4.29 seconds
Started Aug 03 06:57:15 PM PDT 24
Finished Aug 03 06:57:19 PM PDT 24
Peak memory 242208 kb
Host smart-52f03161-aef2-4dd9-8fd2-7159df9fb081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751056606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3751056606
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.2298617834
Short name T242
Test name
Test status
Simulation time 50184887297 ps
CPU time 386.77 seconds
Started Aug 03 06:51:26 PM PDT 24
Finished Aug 03 06:57:53 PM PDT 24
Peak memory 282548 kb
Host smart-4b3615fe-f07f-462f-846e-536cb7097f61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298617834 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.2298617834
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3755591525
Short name T282
Test name
Test status
Simulation time 4902589935 ps
CPU time 18.37 seconds
Started Aug 03 04:40:33 PM PDT 24
Finished Aug 03 04:40:51 PM PDT 24
Peak memory 238960 kb
Host smart-6149d08b-c01b-4cb4-9cd4-358dd3b8e93c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755591525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.3755591525
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.3011596693
Short name T25
Test name
Test status
Simulation time 221325541 ps
CPU time 4.39 seconds
Started Aug 03 06:58:43 PM PDT 24
Finished Aug 03 06:58:48 PM PDT 24
Peak memory 242056 kb
Host smart-44d6e638-8dab-4d4a-ad44-eff09a3c0c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011596693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3011596693
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.3387585698
Short name T14
Test name
Test status
Simulation time 624112408276 ps
CPU time 3568.59 seconds
Started Aug 03 06:40:38 PM PDT 24
Finished Aug 03 07:40:07 PM PDT 24
Peak memory 344948 kb
Host smart-2784ddc0-6d9d-476c-9a29-e20e7ed87d62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387585698 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.3387585698
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.4262188571
Short name T393
Test name
Test status
Simulation time 8614303952 ps
CPU time 146.67 seconds
Started Aug 03 06:34:29 PM PDT 24
Finished Aug 03 06:36:56 PM PDT 24
Peak memory 245920 kb
Host smart-5de71e79-4407-4d94-904e-19a8935c0b83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262188571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
4262188571
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.4284630134
Short name T132
Test name
Test status
Simulation time 19470943149 ps
CPU time 203.77 seconds
Started Aug 03 06:44:38 PM PDT 24
Finished Aug 03 06:48:02 PM PDT 24
Peak memory 273248 kb
Host smart-35be59b0-c1c1-4a8a-a12e-7acbf2a9fec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284630134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.4284630134
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.3850365928
Short name T163
Test name
Test status
Simulation time 2089664417 ps
CPU time 6.46 seconds
Started Aug 03 06:46:06 PM PDT 24
Finished Aug 03 06:46:13 PM PDT 24
Peak memory 241880 kb
Host smart-03279b3b-ead2-40b0-b5af-c66024fdc5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850365928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.3850365928
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.1151443683
Short name T13
Test name
Test status
Simulation time 379324873 ps
CPU time 14.41 seconds
Started Aug 03 06:44:12 PM PDT 24
Finished Aug 03 06:44:26 PM PDT 24
Peak memory 248544 kb
Host smart-e9378bfe-314d-47d8-9a44-182f46aeaf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151443683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.1151443683
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.2007229591
Short name T166
Test name
Test status
Simulation time 917100771 ps
CPU time 20.56 seconds
Started Aug 03 06:45:31 PM PDT 24
Finished Aug 03 06:45:51 PM PDT 24
Peak memory 244032 kb
Host smart-ad6db39d-33d7-4aba-878c-498d26fa6a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007229591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.2007229591
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.1969821816
Short name T53
Test name
Test status
Simulation time 310752892 ps
CPU time 4.54 seconds
Started Aug 03 06:59:12 PM PDT 24
Finished Aug 03 06:59:16 PM PDT 24
Peak memory 241992 kb
Host smart-44c4177a-92da-4610-a356-4ea561f3b02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969821816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.1969821816
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.447472485
Short name T42
Test name
Test status
Simulation time 459735646 ps
CPU time 3.42 seconds
Started Aug 03 06:58:03 PM PDT 24
Finished Aug 03 06:58:07 PM PDT 24
Peak memory 242300 kb
Host smart-b8950a41-3b90-4753-af3c-9e0bbc73830f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447472485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.447472485
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.1803308171
Short name T60
Test name
Test status
Simulation time 2390328048 ps
CPU time 5.11 seconds
Started Aug 03 06:57:01 PM PDT 24
Finished Aug 03 06:57:06 PM PDT 24
Peak memory 242180 kb
Host smart-f2e32806-b4ed-4a88-900b-54e9be5d3f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803308171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.1803308171
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.109975567
Short name T128
Test name
Test status
Simulation time 527320341561 ps
CPU time 1533.87 seconds
Started Aug 03 06:41:12 PM PDT 24
Finished Aug 03 07:06:46 PM PDT 24
Peak memory 394584 kb
Host smart-e0815250-d01d-4e2d-8599-77889510af4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109975567 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.109975567
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.493796019
Short name T30
Test name
Test status
Simulation time 2392895651 ps
CPU time 7.53 seconds
Started Aug 03 06:36:48 PM PDT 24
Finished Aug 03 06:36:55 PM PDT 24
Peak memory 242280 kb
Host smart-14166400-f682-4424-b739-3196590f47a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493796019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.493796019
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.3089663067
Short name T63
Test name
Test status
Simulation time 1059645856 ps
CPU time 19.06 seconds
Started Aug 03 06:37:58 PM PDT 24
Finished Aug 03 06:38:17 PM PDT 24
Peak memory 242304 kb
Host smart-a99a6f10-ae70-4c04-b799-bf0e19a36c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089663067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.3089663067
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.2717610840
Short name T4
Test name
Test status
Simulation time 125575128827 ps
CPU time 890.29 seconds
Started Aug 03 06:46:01 PM PDT 24
Finished Aug 03 07:00:51 PM PDT 24
Peak memory 265176 kb
Host smart-26ce57df-2c03-4c61-89aa-615e15f4466f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717610840 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.2717610840
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.1558820793
Short name T508
Test name
Test status
Simulation time 457315455 ps
CPU time 11.74 seconds
Started Aug 03 06:55:25 PM PDT 24
Finished Aug 03 06:55:37 PM PDT 24
Peak memory 242444 kb
Host smart-d3a2a07f-57e8-4dba-84c3-96414285f386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558820793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1558820793
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.863750470
Short name T50
Test name
Test status
Simulation time 218165328 ps
CPU time 4.07 seconds
Started Aug 03 06:59:15 PM PDT 24
Finished Aug 03 06:59:19 PM PDT 24
Peak memory 242308 kb
Host smart-2cc3fe13-a481-4a70-b8e9-e1c3e95a0d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863750470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.863750470
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.2616972700
Short name T49
Test name
Test status
Simulation time 7151881196 ps
CPU time 14.32 seconds
Started Aug 03 06:40:31 PM PDT 24
Finished Aug 03 06:40:45 PM PDT 24
Peak memory 248652 kb
Host smart-fcdd2868-2fb8-48c5-87e4-7c2b4c9baabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616972700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.2616972700
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.1772603653
Short name T138
Test name
Test status
Simulation time 492583744 ps
CPU time 15.12 seconds
Started Aug 03 06:38:48 PM PDT 24
Finished Aug 03 06:39:03 PM PDT 24
Peak memory 242276 kb
Host smart-e3b6c169-5baf-4463-bb4d-7cb2a322e184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772603653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.1772603653
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.1418534936
Short name T37
Test name
Test status
Simulation time 364786640 ps
CPU time 4.45 seconds
Started Aug 03 06:44:18 PM PDT 24
Finished Aug 03 06:44:23 PM PDT 24
Peak memory 241968 kb
Host smart-14b2dba2-f4f8-4555-a9cb-993ae1ed889b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418534936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.1418534936
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.2498516232
Short name T152
Test name
Test status
Simulation time 2527729999 ps
CPU time 23.39 seconds
Started Aug 03 06:39:00 PM PDT 24
Finished Aug 03 06:39:24 PM PDT 24
Peak memory 248660 kb
Host smart-e221bbb2-9a42-4a3e-b693-007031224767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498516232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.2498516232
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.3495622237
Short name T294
Test name
Test status
Simulation time 55403929248 ps
CPU time 804.75 seconds
Started Aug 03 06:43:55 PM PDT 24
Finished Aug 03 06:57:20 PM PDT 24
Peak memory 380272 kb
Host smart-bf474d65-fc33-422c-bdf1-0bd1b28269bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495622237 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.3495622237
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.3410770733
Short name T136
Test name
Test status
Simulation time 489811280 ps
CPU time 6.59 seconds
Started Aug 03 06:58:00 PM PDT 24
Finished Aug 03 06:58:06 PM PDT 24
Peak memory 241896 kb
Host smart-2063f20f-0a17-4c8a-9322-377429e9a513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410770733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3410770733
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.728399358
Short name T90
Test name
Test status
Simulation time 3242517307 ps
CPU time 56.59 seconds
Started Aug 03 06:37:59 PM PDT 24
Finished Aug 03 06:38:56 PM PDT 24
Peak memory 242680 kb
Host smart-92483e2c-5e86-40a6-a74c-6bbb6a2d51a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728399358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.728399358
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.2466647723
Short name T149
Test name
Test status
Simulation time 14547659522 ps
CPU time 204.94 seconds
Started Aug 03 06:45:37 PM PDT 24
Finished Aug 03 06:49:02 PM PDT 24
Peak memory 256960 kb
Host smart-cefc7889-804e-48fe-adf2-bc92c563fab6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466647723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.2466647723
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.185253557
Short name T212
Test name
Test status
Simulation time 231429675 ps
CPU time 3.62 seconds
Started Aug 03 06:58:59 PM PDT 24
Finished Aug 03 06:59:03 PM PDT 24
Peak memory 241988 kb
Host smart-9d2df5cb-004d-4088-9e62-378ac778dc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185253557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.185253557
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.40560594
Short name T176
Test name
Test status
Simulation time 3565018934 ps
CPU time 26.8 seconds
Started Aug 03 06:41:05 PM PDT 24
Finished Aug 03 06:41:32 PM PDT 24
Peak memory 246564 kb
Host smart-27beabdf-06fd-4dcd-9d01-97386f283842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40560594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.40560594
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.2635018679
Short name T113
Test name
Test status
Simulation time 66592180997 ps
CPU time 1833 seconds
Started Aug 03 06:45:36 PM PDT 24
Finished Aug 03 07:16:09 PM PDT 24
Peak memory 294284 kb
Host smart-4397ab21-b8c9-45b4-af15-419e3ee9e566
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635018679 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.2635018679
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.640434360
Short name T404
Test name
Test status
Simulation time 214634438 ps
CPU time 1.9 seconds
Started Aug 03 06:38:17 PM PDT 24
Finished Aug 03 06:38:19 PM PDT 24
Peak memory 240604 kb
Host smart-d9af2eb7-9d6b-472d-afee-b5142037132e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640434360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.640434360
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.1695931935
Short name T24
Test name
Test status
Simulation time 19333012282 ps
CPU time 186.65 seconds
Started Aug 03 06:34:55 PM PDT 24
Finished Aug 03 06:38:02 PM PDT 24
Peak memory 270316 kb
Host smart-eecade7a-91c5-41bd-9290-64c83b49f497
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695931935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.1695931935
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.2605352754
Short name T366
Test name
Test status
Simulation time 444258761 ps
CPU time 6.98 seconds
Started Aug 03 06:40:06 PM PDT 24
Finished Aug 03 06:40:13 PM PDT 24
Peak memory 241908 kb
Host smart-a219a5b2-c0d6-439e-9907-32d52cf0f2d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605352754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.2605352754
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.3635472382
Short name T1035
Test name
Test status
Simulation time 60739513359 ps
CPU time 98.55 seconds
Started Aug 03 06:34:35 PM PDT 24
Finished Aug 03 06:36:14 PM PDT 24
Peak memory 256912 kb
Host smart-16eaccc6-81e9-4fe5-826c-3e988f551b61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635472382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
3635472382
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.778310980
Short name T70
Test name
Test status
Simulation time 137229337 ps
CPU time 3.95 seconds
Started Aug 03 06:59:14 PM PDT 24
Finished Aug 03 06:59:18 PM PDT 24
Peak memory 242200 kb
Host smart-c92081d2-28c3-4a98-be98-6dbbaa1cbf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778310980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.778310980
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.782137471
Short name T258
Test name
Test status
Simulation time 135001515 ps
CPU time 4.41 seconds
Started Aug 03 06:59:21 PM PDT 24
Finished Aug 03 06:59:26 PM PDT 24
Peak memory 241884 kb
Host smart-82bc87cd-3bff-4ea0-8aa2-99fc1c4942cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782137471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.782137471
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.3666565234
Short name T34
Test name
Test status
Simulation time 337229518 ps
CPU time 5.05 seconds
Started Aug 03 06:58:49 PM PDT 24
Finished Aug 03 06:58:54 PM PDT 24
Peak memory 241924 kb
Host smart-b92caf1a-eee4-4c28-9545-9af3903f9e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666565234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.3666565234
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.61561959
Short name T78
Test name
Test status
Simulation time 95251251 ps
CPU time 3.35 seconds
Started Aug 03 06:56:13 PM PDT 24
Finished Aug 03 06:56:17 PM PDT 24
Peak memory 241988 kb
Host smart-ff5d528d-689e-4a55-b8c4-3c3b40f58fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61561959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.61561959
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.868689972
Short name T95
Test name
Test status
Simulation time 8346880458 ps
CPU time 20.56 seconds
Started Aug 03 06:35:44 PM PDT 24
Finished Aug 03 06:36:05 PM PDT 24
Peak memory 248720 kb
Host smart-ebeb01f3-1ead-47af-8764-50477aac0f1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868689972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.868689972
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2885350824
Short name T360
Test name
Test status
Simulation time 1412787359 ps
CPU time 19.68 seconds
Started Aug 03 04:40:38 PM PDT 24
Finished Aug 03 04:40:58 PM PDT 24
Peak memory 243836 kb
Host smart-02aa79a5-bef8-4293-b84c-a176f8323d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885350824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.2885350824
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.401209129
Short name T369
Test name
Test status
Simulation time 766566357 ps
CPU time 9.18 seconds
Started Aug 03 06:42:29 PM PDT 24
Finished Aug 03 06:42:39 PM PDT 24
Peak memory 242296 kb
Host smart-46a692e3-3e82-442e-99b7-aea032847e75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401209129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.401209129
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.2481746954
Short name T704
Test name
Test status
Simulation time 41512601341 ps
CPU time 325.39 seconds
Started Aug 03 06:34:55 PM PDT 24
Finished Aug 03 06:40:21 PM PDT 24
Peak memory 308296 kb
Host smart-7020c9f0-ee8c-42d4-b43a-980f2c6dd7df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481746954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
2481746954
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.1411031428
Short name T241
Test name
Test status
Simulation time 2326634002 ps
CPU time 26.66 seconds
Started Aug 03 06:56:13 PM PDT 24
Finished Aug 03 06:56:40 PM PDT 24
Peak memory 242216 kb
Host smart-84fb4b35-b1ea-4f27-8a65-af6a45c82fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411031428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1411031428
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3263313199
Short name T307
Test name
Test status
Simulation time 75066855 ps
CPU time 1.45 seconds
Started Aug 03 04:40:37 PM PDT 24
Finished Aug 03 04:40:39 PM PDT 24
Peak memory 240276 kb
Host smart-f8c0acbd-2dac-4eb9-882b-df3d62462b6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263313199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3263313199
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.79980454
Short name T111
Test name
Test status
Simulation time 404976655 ps
CPU time 3.47 seconds
Started Aug 03 06:59:00 PM PDT 24
Finished Aug 03 06:59:04 PM PDT 24
Peak memory 242044 kb
Host smart-760317f8-811f-46bb-bcce-5d9d967db2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79980454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.79980454
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.456186264
Short name T28
Test name
Test status
Simulation time 1297332910 ps
CPU time 16.2 seconds
Started Aug 03 06:38:44 PM PDT 24
Finished Aug 03 06:39:00 PM PDT 24
Peak memory 242444 kb
Host smart-4861863c-2df9-44a7-94b8-39f4fa72fcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456186264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.456186264
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.4057500870
Short name T35
Test name
Test status
Simulation time 636958274 ps
CPU time 4.65 seconds
Started Aug 03 06:59:18 PM PDT 24
Finished Aug 03 06:59:23 PM PDT 24
Peak memory 242156 kb
Host smart-ef2da9bc-f5a8-4a9f-86a0-33247a47753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057500870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.4057500870
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.452957480
Short name T151
Test name
Test status
Simulation time 106841053781 ps
CPU time 778.31 seconds
Started Aug 03 06:38:38 PM PDT 24
Finished Aug 03 06:51:37 PM PDT 24
Peak memory 288528 kb
Host smart-93369cd0-5329-4afe-8274-e65df82743b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452957480 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.452957480
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.3337400586
Short name T117
Test name
Test status
Simulation time 2987047790 ps
CPU time 10.27 seconds
Started Aug 03 06:42:00 PM PDT 24
Finished Aug 03 06:42:10 PM PDT 24
Peak memory 242444 kb
Host smart-fb505980-2572-42d1-b2cd-78cb56ae6846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337400586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.3337400586
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.3100606289
Short name T69
Test name
Test status
Simulation time 3884322017 ps
CPU time 15.45 seconds
Started Aug 03 06:48:22 PM PDT 24
Finished Aug 03 06:48:38 PM PDT 24
Peak memory 242424 kb
Host smart-0a859ab3-f6f1-4854-b1e1-01b11a309f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100606289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.3100606289
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.161331604
Short name T291
Test name
Test status
Simulation time 75649967118 ps
CPU time 2052.76 seconds
Started Aug 03 06:47:32 PM PDT 24
Finished Aug 03 07:21:46 PM PDT 24
Peak memory 361120 kb
Host smart-c4b382af-c2ee-4b68-8140-d357bfa07694
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161331604 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.161331604
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.2368104056
Short name T126
Test name
Test status
Simulation time 558378560 ps
CPU time 9.46 seconds
Started Aug 03 06:36:36 PM PDT 24
Finished Aug 03 06:36:46 PM PDT 24
Peak memory 248620 kb
Host smart-3c7505f6-c5f9-4bc3-85da-3e239973485d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368104056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.2368104056
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.590152507
Short name T41
Test name
Test status
Simulation time 520535909 ps
CPU time 10.06 seconds
Started Aug 03 06:44:45 PM PDT 24
Finished Aug 03 06:44:56 PM PDT 24
Peak memory 242012 kb
Host smart-e1913fa4-bf27-4de0-bf64-a66035fcf885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590152507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.590152507
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.2010205219
Short name T118
Test name
Test status
Simulation time 15229778020 ps
CPU time 134.27 seconds
Started Aug 03 06:39:06 PM PDT 24
Finished Aug 03 06:41:20 PM PDT 24
Peak memory 248636 kb
Host smart-779ceb83-611c-44e7-adf1-3eb1c0f79ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010205219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.2010205219
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.2717044884
Short name T964
Test name
Test status
Simulation time 4742097602 ps
CPU time 145.61 seconds
Started Aug 03 06:38:03 PM PDT 24
Finished Aug 03 06:40:28 PM PDT 24
Peak memory 259136 kb
Host smart-a62a2aba-c327-4ee3-86fa-94bf6dd93706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717044884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.2717044884
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.2301579855
Short name T141
Test name
Test status
Simulation time 183567814 ps
CPU time 8.84 seconds
Started Aug 03 06:37:42 PM PDT 24
Finished Aug 03 06:37:51 PM PDT 24
Peak memory 241864 kb
Host smart-b78cd84e-bca0-4f4f-b3de-c462ff44bdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301579855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.2301579855
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3248861089
Short name T275
Test name
Test status
Simulation time 21765358228 ps
CPU time 19.68 seconds
Started Aug 03 04:41:00 PM PDT 24
Finished Aug 03 04:41:20 PM PDT 24
Peak memory 238920 kb
Host smart-a38f12a9-e5c3-4578-96cb-d3974220942e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248861089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.3248861089
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.2146552031
Short name T255
Test name
Test status
Simulation time 75872818445 ps
CPU time 327.96 seconds
Started Aug 03 06:48:39 PM PDT 24
Finished Aug 03 06:54:08 PM PDT 24
Peak memory 257076 kb
Host smart-a5c543d8-8721-4307-b021-5fcd4c2edd67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146552031 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.2146552031
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.282508611
Short name T86
Test name
Test status
Simulation time 207193245 ps
CPU time 3.34 seconds
Started Aug 03 06:45:36 PM PDT 24
Finished Aug 03 06:45:40 PM PDT 24
Peak memory 241960 kb
Host smart-eef477c3-7993-4986-9da0-1f2f9c64e37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282508611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.282508611
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.807833642
Short name T253
Test name
Test status
Simulation time 446280648 ps
CPU time 14.8 seconds
Started Aug 03 06:41:31 PM PDT 24
Finished Aug 03 06:41:46 PM PDT 24
Peak memory 248536 kb
Host smart-84e15468-ea45-4bb2-838d-10849238daad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=807833642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.807833642
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.3089014697
Short name T80
Test name
Test status
Simulation time 472762114 ps
CPU time 17.22 seconds
Started Aug 03 06:34:41 PM PDT 24
Finished Aug 03 06:34:59 PM PDT 24
Peak memory 242684 kb
Host smart-ccb65105-ad99-4bce-8ca2-a27da00caf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089014697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.3089014697
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.1563693414
Short name T107
Test name
Test status
Simulation time 1502709299 ps
CPU time 19.38 seconds
Started Aug 03 06:44:28 PM PDT 24
Finished Aug 03 06:44:48 PM PDT 24
Peak memory 248676 kb
Host smart-70549cee-1741-4f7d-9beb-32cb6a6879df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563693414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.1563693414
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.3749281513
Short name T93
Test name
Test status
Simulation time 204485956 ps
CPU time 3.44 seconds
Started Aug 03 06:55:33 PM PDT 24
Finished Aug 03 06:55:37 PM PDT 24
Peak memory 242152 kb
Host smart-3afbadff-9378-4ceb-8da4-31113f2b96d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749281513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3749281513
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.2772738441
Short name T225
Test name
Test status
Simulation time 209867029 ps
CPU time 2.89 seconds
Started Aug 03 06:57:05 PM PDT 24
Finished Aug 03 06:57:08 PM PDT 24
Peak memory 241964 kb
Host smart-23b41dc9-7f68-4af9-b74a-ebdba37e5342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772738441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.2772738441
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.1784243253
Short name T220
Test name
Test status
Simulation time 120305784 ps
CPU time 3.38 seconds
Started Aug 03 06:57:26 PM PDT 24
Finished Aug 03 06:57:29 PM PDT 24
Peak memory 242168 kb
Host smart-06d3017f-ecf1-4c9e-b3d6-d95a308c900c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784243253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.1784243253
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.924554273
Short name T367
Test name
Test status
Simulation time 3751898771 ps
CPU time 10.35 seconds
Started Aug 03 06:41:56 PM PDT 24
Finished Aug 03 06:42:06 PM PDT 24
Peak memory 242180 kb
Host smart-87205ddc-b827-4899-b0bf-d16180e166fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=924554273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.924554273
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.110228911
Short name T359
Test name
Test status
Simulation time 18877094417 ps
CPU time 36.49 seconds
Started Aug 03 04:40:50 PM PDT 24
Finished Aug 03 04:41:27 PM PDT 24
Peak memory 244488 kb
Host smart-19e870f3-62c9-4da7-ba28-b1067df3bdba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110228911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_int
g_err.110228911
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.421734291
Short name T100
Test name
Test status
Simulation time 753067199 ps
CPU time 16.19 seconds
Started Aug 03 06:36:13 PM PDT 24
Finished Aug 03 06:36:29 PM PDT 24
Peak memory 241872 kb
Host smart-833fe25c-3a92-4752-8249-482ee4b25f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421734291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.421734291
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.145963822
Short name T156
Test name
Test status
Simulation time 131411232 ps
CPU time 1.88 seconds
Started Aug 03 06:34:14 PM PDT 24
Finished Aug 03 06:34:16 PM PDT 24
Peak memory 240696 kb
Host smart-150d2bff-f8b6-40ae-8b0b-f86f2749bd20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=145963822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.145963822
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.3880877636
Short name T231
Test name
Test status
Simulation time 689026713 ps
CPU time 10.8 seconds
Started Aug 03 06:38:55 PM PDT 24
Finished Aug 03 06:39:06 PM PDT 24
Peak memory 242020 kb
Host smart-178b4263-d850-4473-a017-4a4b1a5db122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880877636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.3880877636
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.410578590
Short name T204
Test name
Test status
Simulation time 1135337660 ps
CPU time 16.34 seconds
Started Aug 03 06:52:37 PM PDT 24
Finished Aug 03 06:52:53 PM PDT 24
Peak memory 241996 kb
Host smart-6e27aa88-7939-4fbb-9560-84a558fef6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410578590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.410578590
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.1733228708
Short name T257
Test name
Test status
Simulation time 739494690 ps
CPU time 17.88 seconds
Started Aug 03 06:45:27 PM PDT 24
Finished Aug 03 06:45:45 PM PDT 24
Peak memory 242232 kb
Host smart-be9c53d2-c467-4c89-86f2-6835153a07a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1733228708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.1733228708
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2624151289
Short name T281
Test name
Test status
Simulation time 2373848267 ps
CPU time 9.93 seconds
Started Aug 03 04:40:45 PM PDT 24
Finished Aug 03 04:40:55 PM PDT 24
Peak memory 244004 kb
Host smart-66a11000-1e7d-4e49-9c3e-ea9e4d058cbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624151289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.2624151289
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3913792947
Short name T276
Test name
Test status
Simulation time 1376306026 ps
CPU time 18.59 seconds
Started Aug 03 04:40:46 PM PDT 24
Finished Aug 03 04:41:05 PM PDT 24
Peak memory 244016 kb
Host smart-cef015a0-7182-484a-b6b1-8cb77d17ebab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913792947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.3913792947
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.599939549
Short name T389
Test name
Test status
Simulation time 7124609385 ps
CPU time 100.11 seconds
Started Aug 03 06:38:29 PM PDT 24
Finished Aug 03 06:40:10 PM PDT 24
Peak memory 249080 kb
Host smart-2affc434-6192-40ac-b201-589e6e4fae3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599939549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.
599939549
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.3130728034
Short name T267
Test name
Test status
Simulation time 412869120 ps
CPU time 4.1 seconds
Started Aug 03 06:55:41 PM PDT 24
Finished Aug 03 06:55:45 PM PDT 24
Peak memory 242372 kb
Host smart-ccd01166-bdc0-4f4d-a41b-3ec3e7a66f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130728034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.3130728034
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.1458510163
Short name T405
Test name
Test status
Simulation time 1171877012 ps
CPU time 10.15 seconds
Started Aug 03 06:36:56 PM PDT 24
Finished Aug 03 06:37:06 PM PDT 24
Peak memory 242368 kb
Host smart-307b77dc-4350-46cd-9f4a-098f947539db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458510163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1458510163
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.1925515343
Short name T83
Test name
Test status
Simulation time 2216230051 ps
CPU time 4.66 seconds
Started Aug 03 06:56:59 PM PDT 24
Finished Aug 03 06:57:04 PM PDT 24
Peak memory 242432 kb
Host smart-d190ad0d-7333-4441-9f61-7ee754aef1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925515343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.1925515343
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.391155402
Short name T82
Test name
Test status
Simulation time 622072878 ps
CPU time 4.32 seconds
Started Aug 03 06:57:58 PM PDT 24
Finished Aug 03 06:58:02 PM PDT 24
Peak memory 241920 kb
Host smart-1a5e8e7a-0fa4-4ff1-8a30-184f143680c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391155402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.391155402
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.2858038172
Short name T228
Test name
Test status
Simulation time 3144675653 ps
CPU time 45.1 seconds
Started Aug 03 06:46:12 PM PDT 24
Finished Aug 03 06:46:57 PM PDT 24
Peak memory 248660 kb
Host smart-56b205a6-4119-46be-9d23-5b8710b03a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858038172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.2858038172
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.2308104381
Short name T478
Test name
Test status
Simulation time 1308480577 ps
CPU time 11.8 seconds
Started Aug 03 06:40:46 PM PDT 24
Finished Aug 03 06:40:58 PM PDT 24
Peak memory 242400 kb
Host smart-1337b5e9-eb3b-4a6a-9f4a-383920233d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308104381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.2308104381
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.536132309
Short name T88
Test name
Test status
Simulation time 1710897763 ps
CPU time 4.29 seconds
Started Aug 03 06:54:19 PM PDT 24
Finished Aug 03 06:54:23 PM PDT 24
Peak memory 242184 kb
Host smart-1a409cdf-2bc4-44fe-8c45-ebc66828b223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536132309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.536132309
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.1906245501
Short name T469
Test name
Test status
Simulation time 229594683 ps
CPU time 8 seconds
Started Aug 03 06:36:22 PM PDT 24
Finished Aug 03 06:36:30 PM PDT 24
Peak memory 241944 kb
Host smart-088f3c30-2717-4d1c-a2c4-54e29bb0bd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906245501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.1906245501
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1346887051
Short name T304
Test name
Test status
Simulation time 3148842426 ps
CPU time 7.87 seconds
Started Aug 03 04:40:33 PM PDT 24
Finished Aug 03 04:40:41 PM PDT 24
Peak memory 238860 kb
Host smart-70193776-c07f-4404-ba44-78ddb50c6c55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346887051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.1346887051
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1931200704
Short name T316
Test name
Test status
Simulation time 832838264 ps
CPU time 8.8 seconds
Started Aug 03 04:40:30 PM PDT 24
Finished Aug 03 04:40:39 PM PDT 24
Peak memory 230532 kb
Host smart-7fc8e5ec-e130-4443-ac0a-f21eb2144a7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931200704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.1931200704
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.974425579
Short name T1268
Test name
Test status
Simulation time 199396895 ps
CPU time 2.45 seconds
Started Aug 03 04:40:24 PM PDT 24
Finished Aug 03 04:40:27 PM PDT 24
Peak memory 238824 kb
Host smart-3414823c-05fa-4f8e-b2e5-cfa2f782ee84
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974425579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_re
set.974425579
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.132799299
Short name T1199
Test name
Test status
Simulation time 212633232 ps
CPU time 3.14 seconds
Started Aug 03 04:40:46 PM PDT 24
Finished Aug 03 04:40:49 PM PDT 24
Peak memory 246324 kb
Host smart-319633b3-8e5a-44ef-bb66-952b0d00264c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132799299 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.132799299
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.420712542
Short name T1298
Test name
Test status
Simulation time 156065664 ps
CPU time 1.67 seconds
Started Aug 03 04:40:33 PM PDT 24
Finished Aug 03 04:40:38 PM PDT 24
Peak memory 240756 kb
Host smart-95ca2b50-12a7-4025-a05c-337f0fa65a4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420712542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.420712542
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2072369605
Short name T1225
Test name
Test status
Simulation time 78624104 ps
CPU time 1.39 seconds
Started Aug 03 04:40:38 PM PDT 24
Finished Aug 03 04:40:40 PM PDT 24
Peak memory 230092 kb
Host smart-6b05c8d1-49ee-42b6-982a-b249d5924cb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072369605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2072369605
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.4258064521
Short name T1219
Test name
Test status
Simulation time 74575949 ps
CPU time 1.39 seconds
Started Aug 03 04:40:37 PM PDT 24
Finished Aug 03 04:40:39 PM PDT 24
Peak memory 229600 kb
Host smart-8792ddc0-13b8-45cc-8775-23e4fc4fbd3d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258064521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.4258064521
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3922787951
Short name T1310
Test name
Test status
Simulation time 67675889 ps
CPU time 1.48 seconds
Started Aug 03 04:40:28 PM PDT 24
Finished Aug 03 04:40:30 PM PDT 24
Peak memory 230436 kb
Host smart-28e3a5a6-30e9-437f-bc98-535584e89810
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922787951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.3922787951
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.4135041514
Short name T329
Test name
Test status
Simulation time 813751482 ps
CPU time 2.65 seconds
Started Aug 03 04:40:23 PM PDT 24
Finished Aug 03 04:40:25 PM PDT 24
Peak memory 238736 kb
Host smart-035cc382-0bd0-49d1-9281-dcb4e8dc6493
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135041514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.4135041514
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.218667026
Short name T1234
Test name
Test status
Simulation time 175827879 ps
CPU time 6.14 seconds
Started Aug 03 04:40:31 PM PDT 24
Finished Aug 03 04:40:37 PM PDT 24
Peak memory 246124 kb
Host smart-be8415a0-f2f3-4cfc-a9f0-c73779ec4e88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218667026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.218667026
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2737860568
Short name T1216
Test name
Test status
Simulation time 10334451286 ps
CPU time 13.89 seconds
Started Aug 03 04:40:52 PM PDT 24
Finished Aug 03 04:41:06 PM PDT 24
Peak memory 244148 kb
Host smart-62352679-06bf-4d2c-ad46-3073008e0321
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737860568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.2737860568
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3765955710
Short name T309
Test name
Test status
Simulation time 180879839 ps
CPU time 3 seconds
Started Aug 03 04:40:22 PM PDT 24
Finished Aug 03 04:40:25 PM PDT 24
Peak memory 238772 kb
Host smart-184a5d40-9843-4776-a622-cf8eec630976
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765955710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.3765955710
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.439020936
Short name T1294
Test name
Test status
Simulation time 3732782113 ps
CPU time 10.39 seconds
Started Aug 03 04:40:34 PM PDT 24
Finished Aug 03 04:40:44 PM PDT 24
Peak memory 238764 kb
Host smart-5c15c442-4b6f-43e2-bf00-17463e62ccdc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439020936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_b
ash.439020936
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.4050470170
Short name T1217
Test name
Test status
Simulation time 1549988407 ps
CPU time 4.3 seconds
Started Aug 03 04:40:43 PM PDT 24
Finished Aug 03 04:40:48 PM PDT 24
Peak memory 238776 kb
Host smart-9ebef467-2529-4c9e-b60e-349dc1ef5228
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050470170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.4050470170
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.627487881
Short name T1316
Test name
Test status
Simulation time 83518173 ps
CPU time 2.21 seconds
Started Aug 03 04:40:29 PM PDT 24
Finished Aug 03 04:40:32 PM PDT 24
Peak memory 245348 kb
Host smart-140be375-4bb5-4548-976d-9d963aef0625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627487881 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.627487881
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.184624792
Short name T279
Test name
Test status
Simulation time 614079948 ps
CPU time 1.56 seconds
Started Aug 03 04:40:33 PM PDT 24
Finished Aug 03 04:40:34 PM PDT 24
Peak memory 240704 kb
Host smart-c93a506d-7bb4-43dd-afeb-0b620591375f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184624792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.184624792
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.492311263
Short name T1191
Test name
Test status
Simulation time 612991445 ps
CPU time 1.78 seconds
Started Aug 03 04:40:27 PM PDT 24
Finished Aug 03 04:40:29 PM PDT 24
Peak memory 230564 kb
Host smart-f0c593d2-df69-48c8-87b7-93563fe4018e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492311263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.492311263
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2410766239
Short name T1267
Test name
Test status
Simulation time 140086516 ps
CPU time 1.5 seconds
Started Aug 03 04:40:29 PM PDT 24
Finished Aug 03 04:40:30 PM PDT 24
Peak memory 229460 kb
Host smart-c2d6bb5c-7aa0-4b74-af8f-8e78c74f9743
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410766239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.2410766239
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1819921796
Short name T1215
Test name
Test status
Simulation time 133197960 ps
CPU time 1.45 seconds
Started Aug 03 04:40:33 PM PDT 24
Finished Aug 03 04:40:34 PM PDT 24
Peak memory 229944 kb
Host smart-a6e161af-f9c2-4cb0-b3a8-ac3d09760b73
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819921796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.1819921796
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2575211731
Short name T1297
Test name
Test status
Simulation time 82760814 ps
CPU time 2.77 seconds
Started Aug 03 04:40:38 PM PDT 24
Finished Aug 03 04:40:41 PM PDT 24
Peak memory 238784 kb
Host smart-3a1c299d-b6f0-4855-840a-08cb696cd293
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575211731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.2575211731
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.278557140
Short name T1203
Test name
Test status
Simulation time 1238676447 ps
CPU time 4.62 seconds
Started Aug 03 04:40:45 PM PDT 24
Finished Aug 03 04:40:50 PM PDT 24
Peak memory 238784 kb
Host smart-f9be0d8b-7cce-4ee7-bda2-0b88cabe268e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278557140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.278557140
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1163324005
Short name T363
Test name
Test status
Simulation time 670902412 ps
CPU time 10.8 seconds
Started Aug 03 04:40:50 PM PDT 24
Finished Aug 03 04:41:01 PM PDT 24
Peak memory 238792 kb
Host smart-89e59fcf-eb18-4199-b503-2fa735337b9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163324005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.1163324005
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1426768573
Short name T1247
Test name
Test status
Simulation time 79982526 ps
CPU time 2.24 seconds
Started Aug 03 04:40:38 PM PDT 24
Finished Aug 03 04:40:40 PM PDT 24
Peak memory 245688 kb
Host smart-93bf6520-c063-48e1-b667-d2c35a509ad1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426768573 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.1426768573
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1978485409
Short name T1229
Test name
Test status
Simulation time 77110948 ps
CPU time 1.47 seconds
Started Aug 03 04:40:43 PM PDT 24
Finished Aug 03 04:40:45 PM PDT 24
Peak memory 230580 kb
Host smart-fa059a89-62b5-4dea-b95a-ced3b7da4c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978485409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.1978485409
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2675304303
Short name T330
Test name
Test status
Simulation time 263617402 ps
CPU time 2.38 seconds
Started Aug 03 04:40:35 PM PDT 24
Finished Aug 03 04:40:37 PM PDT 24
Peak memory 238828 kb
Host smart-cccc0428-a8d3-4fd9-9200-475cc1822c30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675304303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.2675304303
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3096573917
Short name T1261
Test name
Test status
Simulation time 301384055 ps
CPU time 4.91 seconds
Started Aug 03 04:40:41 PM PDT 24
Finished Aug 03 04:40:51 PM PDT 24
Peak memory 246112 kb
Host smart-31abfeea-4bbc-45be-9543-6a0a00eed22e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096573917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3096573917
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3762546088
Short name T1223
Test name
Test status
Simulation time 895739359 ps
CPU time 10.18 seconds
Started Aug 03 04:40:48 PM PDT 24
Finished Aug 03 04:40:59 PM PDT 24
Peak memory 243624 kb
Host smart-b49e47bb-af3c-40eb-8b28-a69fef14aa22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762546088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.3762546088
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.2412091250
Short name T1231
Test name
Test status
Simulation time 147659563 ps
CPU time 2.15 seconds
Started Aug 03 04:40:34 PM PDT 24
Finished Aug 03 04:40:42 PM PDT 24
Peak memory 245172 kb
Host smart-3fa12959-5b8d-4b65-997f-b7ec9313b2af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412091250 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.2412091250
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.532472682
Short name T313
Test name
Test status
Simulation time 79765529 ps
CPU time 1.6 seconds
Started Aug 03 04:40:38 PM PDT 24
Finished Aug 03 04:40:39 PM PDT 24
Peak memory 240492 kb
Host smart-9f6de61c-b971-4914-89e9-fd8c1a689afa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532472682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.532472682
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.3085161579
Short name T1198
Test name
Test status
Simulation time 79072253 ps
CPU time 1.48 seconds
Started Aug 03 04:41:03 PM PDT 24
Finished Aug 03 04:41:05 PM PDT 24
Peak memory 229812 kb
Host smart-f78d8844-db92-41c3-be18-5ba7fad05af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085161579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.3085161579
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3909739244
Short name T1318
Test name
Test status
Simulation time 224156451 ps
CPU time 3.62 seconds
Started Aug 03 04:40:53 PM PDT 24
Finished Aug 03 04:40:57 PM PDT 24
Peak memory 238776 kb
Host smart-5f7bb202-56e5-4d34-89b1-f48d36878171
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909739244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.3909739244
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3403746388
Short name T1248
Test name
Test status
Simulation time 1502268980 ps
CPU time 4.7 seconds
Started Aug 03 04:40:34 PM PDT 24
Finished Aug 03 04:40:41 PM PDT 24
Peak memory 245800 kb
Host smart-13f32aa0-c0a7-425c-986f-1b6e4d2f18bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403746388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.3403746388
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2942371707
Short name T362
Test name
Test status
Simulation time 1318454219 ps
CPU time 19.42 seconds
Started Aug 03 04:40:32 PM PDT 24
Finished Aug 03 04:40:52 PM PDT 24
Peak memory 243932 kb
Host smart-3d8aa619-bb9f-4c30-9fea-7242d071ee26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942371707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.2942371707
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1109967488
Short name T1218
Test name
Test status
Simulation time 1678121003 ps
CPU time 4.98 seconds
Started Aug 03 04:40:50 PM PDT 24
Finished Aug 03 04:41:05 PM PDT 24
Peak memory 246620 kb
Host smart-c870f538-e5bb-4839-9f93-d7062433fb8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109967488 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.1109967488
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.369547226
Short name T323
Test name
Test status
Simulation time 74367549 ps
CPU time 1.6 seconds
Started Aug 03 04:40:36 PM PDT 24
Finished Aug 03 04:40:38 PM PDT 24
Peak memory 240964 kb
Host smart-e9e2243d-a162-4194-9d79-0248458fbb70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369547226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.369547226
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.1827516222
Short name T1320
Test name
Test status
Simulation time 133267002 ps
CPU time 1.37 seconds
Started Aug 03 04:40:50 PM PDT 24
Finished Aug 03 04:40:51 PM PDT 24
Peak memory 229876 kb
Host smart-4deb1963-a637-4239-b232-cc15c25fd297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827516222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.1827516222
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3127022665
Short name T327
Test name
Test status
Simulation time 82973225 ps
CPU time 2.35 seconds
Started Aug 03 04:40:44 PM PDT 24
Finished Aug 03 04:40:46 PM PDT 24
Peak memory 238712 kb
Host smart-722b5201-48e6-4fd5-a6e5-5d9914d0e126
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127022665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.3127022665
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.4126387418
Short name T1256
Test name
Test status
Simulation time 3381677064 ps
CPU time 9.78 seconds
Started Aug 03 04:40:50 PM PDT 24
Finished Aug 03 04:41:00 PM PDT 24
Peak memory 246676 kb
Host smart-591a551e-622c-4eb2-b805-44d076732e41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126387418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.4126387418
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.828893223
Short name T1194
Test name
Test status
Simulation time 1701458676 ps
CPU time 5.21 seconds
Started Aug 03 04:40:36 PM PDT 24
Finished Aug 03 04:40:41 PM PDT 24
Peak memory 247056 kb
Host smart-fc591479-b3a9-49b0-bdad-6d7e81891ea7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828893223 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.828893223
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.432500670
Short name T328
Test name
Test status
Simulation time 540068050 ps
CPU time 1.65 seconds
Started Aug 03 04:40:37 PM PDT 24
Finished Aug 03 04:40:39 PM PDT 24
Peak memory 240020 kb
Host smart-bdae192f-ef8e-49c5-840f-59a78a7cb84f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432500670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.432500670
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3371037990
Short name T1250
Test name
Test status
Simulation time 40015191 ps
CPU time 1.36 seconds
Started Aug 03 04:40:47 PM PDT 24
Finished Aug 03 04:40:48 PM PDT 24
Peak memory 229696 kb
Host smart-98e2b0e3-8ece-4bb5-8132-65ab1077dc8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371037990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.3371037990
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1898493791
Short name T1237
Test name
Test status
Simulation time 128931313 ps
CPU time 3.19 seconds
Started Aug 03 04:40:34 PM PDT 24
Finished Aug 03 04:40:40 PM PDT 24
Peak memory 241788 kb
Host smart-603489fa-c482-4c14-b4c3-7c4ebb37c627
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898493791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.1898493791
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.412503990
Short name T1212
Test name
Test status
Simulation time 290657961 ps
CPU time 5.24 seconds
Started Aug 03 04:40:54 PM PDT 24
Finished Aug 03 04:40:59 PM PDT 24
Peak memory 245964 kb
Host smart-34b8dafa-8ace-49f4-addd-371c0540fd25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412503990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.412503990
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.118077599
Short name T1222
Test name
Test status
Simulation time 1320782100 ps
CPU time 10.43 seconds
Started Aug 03 04:40:36 PM PDT 24
Finished Aug 03 04:40:47 PM PDT 24
Peak memory 243468 kb
Host smart-94af70a0-0026-4bd7-a2ba-15c0501161c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118077599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_in
tg_err.118077599
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1669019987
Short name T1319
Test name
Test status
Simulation time 435467858 ps
CPU time 2.75 seconds
Started Aug 03 04:40:53 PM PDT 24
Finished Aug 03 04:40:56 PM PDT 24
Peak memory 247032 kb
Host smart-2fe9a37b-a23a-47fd-8ecc-4359fa3bd53a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669019987 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.1669019987
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3816047819
Short name T1230
Test name
Test status
Simulation time 43546884 ps
CPU time 1.54 seconds
Started Aug 03 04:40:38 PM PDT 24
Finished Aug 03 04:40:39 PM PDT 24
Peak memory 240568 kb
Host smart-423134dc-ec9f-49da-b5cf-00b89031e925
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816047819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.3816047819
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.4223726654
Short name T1243
Test name
Test status
Simulation time 48092099 ps
CPU time 1.46 seconds
Started Aug 03 04:40:56 PM PDT 24
Finished Aug 03 04:40:58 PM PDT 24
Peak memory 230188 kb
Host smart-61cd239e-2069-43e6-a691-d41316329ec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223726654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.4223726654
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3565384565
Short name T1245
Test name
Test status
Simulation time 323602989 ps
CPU time 2.98 seconds
Started Aug 03 04:40:37 PM PDT 24
Finished Aug 03 04:40:40 PM PDT 24
Peak memory 238808 kb
Host smart-142b855a-9119-4ba6-84db-1f42af5c1813
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565384565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.3565384565
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3306461133
Short name T1211
Test name
Test status
Simulation time 614958192 ps
CPU time 6.03 seconds
Started Aug 03 04:40:59 PM PDT 24
Finished Aug 03 04:41:05 PM PDT 24
Peak memory 245956 kb
Host smart-e59ea015-bd4b-4279-97f1-21da19ba47ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306461133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3306461133
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.351938190
Short name T1224
Test name
Test status
Simulation time 9857304782 ps
CPU time 12 seconds
Started Aug 03 04:40:54 PM PDT 24
Finished Aug 03 04:41:06 PM PDT 24
Peak memory 244132 kb
Host smart-57956231-a130-4ad9-a4b5-00f54d28202f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351938190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_in
tg_err.351938190
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.600917239
Short name T1210
Test name
Test status
Simulation time 213046851 ps
CPU time 3.12 seconds
Started Aug 03 04:40:49 PM PDT 24
Finished Aug 03 04:40:52 PM PDT 24
Peak memory 247052 kb
Host smart-e7040407-2a78-484b-b66e-59cbeb71821a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600917239 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.600917239
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1720795050
Short name T333
Test name
Test status
Simulation time 135626482 ps
CPU time 1.57 seconds
Started Aug 03 04:40:38 PM PDT 24
Finished Aug 03 04:40:40 PM PDT 24
Peak memory 240456 kb
Host smart-ce746058-3125-4a22-9ac5-09976e64a7ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720795050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.1720795050
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3264068858
Short name T1232
Test name
Test status
Simulation time 146893913 ps
CPU time 1.38 seconds
Started Aug 03 04:40:38 PM PDT 24
Finished Aug 03 04:40:40 PM PDT 24
Peak memory 230576 kb
Host smart-ab7bf357-3a90-4f0c-a7ca-970ecb01cf0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264068858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.3264068858
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2421026722
Short name T1277
Test name
Test status
Simulation time 154766644 ps
CPU time 2.19 seconds
Started Aug 03 04:40:55 PM PDT 24
Finished Aug 03 04:40:57 PM PDT 24
Peak memory 238740 kb
Host smart-ebb18514-8d1c-4e19-8aa6-e5e51a049159
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421026722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.2421026722
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.4217748061
Short name T1313
Test name
Test status
Simulation time 137755904 ps
CPU time 4.07 seconds
Started Aug 03 04:40:59 PM PDT 24
Finished Aug 03 04:41:03 PM PDT 24
Peak memory 245624 kb
Host smart-904923ce-7dd8-488f-80b2-070330fed605
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217748061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.4217748061
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3874078307
Short name T1269
Test name
Test status
Simulation time 1214713340 ps
CPU time 9.55 seconds
Started Aug 03 04:40:54 PM PDT 24
Finished Aug 03 04:41:04 PM PDT 24
Peak memory 243580 kb
Host smart-3af70216-9908-4989-981c-ef85abe13055
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874078307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.3874078307
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1307844324
Short name T278
Test name
Test status
Simulation time 71104342 ps
CPU time 2.63 seconds
Started Aug 03 04:41:07 PM PDT 24
Finished Aug 03 04:41:10 PM PDT 24
Peak memory 247024 kb
Host smart-0f99a9cd-0f71-40d5-9c35-9b55c6cf4d3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307844324 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.1307844324
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1235832453
Short name T312
Test name
Test status
Simulation time 45036056 ps
CPU time 1.56 seconds
Started Aug 03 04:40:51 PM PDT 24
Finished Aug 03 04:40:53 PM PDT 24
Peak memory 238756 kb
Host smart-b01f6f20-cd7a-4cbf-8024-29fff33cc643
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235832453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.1235832453
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.4014556041
Short name T1266
Test name
Test status
Simulation time 547937831 ps
CPU time 1.44 seconds
Started Aug 03 04:40:38 PM PDT 24
Finished Aug 03 04:40:40 PM PDT 24
Peak memory 230164 kb
Host smart-94c8c812-4a8d-4937-abf0-47a0f4404245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014556041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.4014556041
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3142397023
Short name T1317
Test name
Test status
Simulation time 298798800 ps
CPU time 2.58 seconds
Started Aug 03 04:40:39 PM PDT 24
Finished Aug 03 04:40:41 PM PDT 24
Peak memory 238768 kb
Host smart-5fec850e-3557-47cf-94cb-0b93de1c71ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142397023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.3142397023
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1542561234
Short name T1241
Test name
Test status
Simulation time 299956889 ps
CPU time 6.83 seconds
Started Aug 03 04:40:54 PM PDT 24
Finished Aug 03 04:41:01 PM PDT 24
Peak memory 246096 kb
Host smart-b01449d2-a3a4-49b1-98d4-8069d9efa342
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542561234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1542561234
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2165599320
Short name T374
Test name
Test status
Simulation time 144275965 ps
CPU time 2.41 seconds
Started Aug 03 04:40:58 PM PDT 24
Finished Aug 03 04:41:01 PM PDT 24
Peak memory 238904 kb
Host smart-6fdb5878-726b-4465-b087-be84c0677e45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165599320 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.2165599320
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3751634493
Short name T308
Test name
Test status
Simulation time 519152272 ps
CPU time 2.22 seconds
Started Aug 03 04:40:40 PM PDT 24
Finished Aug 03 04:40:43 PM PDT 24
Peak memory 240920 kb
Host smart-cec957b7-ce37-493a-808d-04329aa0196f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751634493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3751634493
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1480028899
Short name T1279
Test name
Test status
Simulation time 541214964 ps
CPU time 1.97 seconds
Started Aug 03 04:40:53 PM PDT 24
Finished Aug 03 04:40:55 PM PDT 24
Peak memory 229896 kb
Host smart-4ebe1019-984d-423d-98ec-fd6d5d4f7d74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480028899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.1480028899
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3285384213
Short name T1236
Test name
Test status
Simulation time 316348183 ps
CPU time 2.9 seconds
Started Aug 03 04:40:58 PM PDT 24
Finished Aug 03 04:41:01 PM PDT 24
Peak memory 238748 kb
Host smart-dbd00b5c-6ca1-4d75-a554-fab8b1c107ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285384213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.3285384213
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.800647362
Short name T1244
Test name
Test status
Simulation time 110281530 ps
CPU time 3.22 seconds
Started Aug 03 04:40:51 PM PDT 24
Finished Aug 03 04:40:55 PM PDT 24
Peak memory 246064 kb
Host smart-687263b0-0340-4834-8c3b-025ba69ae257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800647362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.800647362
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2133829455
Short name T1300
Test name
Test status
Simulation time 229009998 ps
CPU time 3.34 seconds
Started Aug 03 04:41:01 PM PDT 24
Finished Aug 03 04:41:05 PM PDT 24
Peak memory 246956 kb
Host smart-e903ae91-de6c-487d-b346-45550cd27363
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133829455 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.2133829455
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3263532225
Short name T315
Test name
Test status
Simulation time 46392901 ps
CPU time 1.73 seconds
Started Aug 03 04:40:56 PM PDT 24
Finished Aug 03 04:40:58 PM PDT 24
Peak memory 241156 kb
Host smart-3d1314fd-762d-43fe-91e4-cfeff6146feb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263532225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.3263532225
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1524350182
Short name T1249
Test name
Test status
Simulation time 46847301 ps
CPU time 1.36 seconds
Started Aug 03 04:40:55 PM PDT 24
Finished Aug 03 04:40:56 PM PDT 24
Peak memory 230596 kb
Host smart-c6a238f3-4f09-4b28-90f4-b4355b3240db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524350182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.1524350182
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.654057983
Short name T326
Test name
Test status
Simulation time 74641134 ps
CPU time 2.31 seconds
Started Aug 03 04:40:50 PM PDT 24
Finished Aug 03 04:40:52 PM PDT 24
Peak memory 238596 kb
Host smart-9f5ac780-1a61-4e29-93f3-9ee14f174bcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654057983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_c
trl_same_csr_outstanding.654057983
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.835071155
Short name T1305
Test name
Test status
Simulation time 309499755 ps
CPU time 6.05 seconds
Started Aug 03 04:40:43 PM PDT 24
Finished Aug 03 04:40:49 PM PDT 24
Peak memory 246168 kb
Host smart-578a1af4-b688-4375-bfde-05531305b66b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835071155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.835071155
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.854924652
Short name T361
Test name
Test status
Simulation time 19975161935 ps
CPU time 42.57 seconds
Started Aug 03 04:40:38 PM PDT 24
Finished Aug 03 04:41:20 PM PDT 24
Peak memory 244604 kb
Host smart-4b64d407-bc89-4767-bd1b-52813c316b5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854924652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_in
tg_err.854924652
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.200950166
Short name T1276
Test name
Test status
Simulation time 66832068 ps
CPU time 2.12 seconds
Started Aug 03 04:40:39 PM PDT 24
Finished Aug 03 04:40:42 PM PDT 24
Peak memory 245464 kb
Host smart-125e235f-cf9b-4a8f-95f1-84683d0fa289
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200950166 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.200950166
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1160077541
Short name T1295
Test name
Test status
Simulation time 149455168 ps
CPU time 1.53 seconds
Started Aug 03 04:40:45 PM PDT 24
Finished Aug 03 04:40:47 PM PDT 24
Peak memory 240920 kb
Host smart-d8d6a3fc-a702-476e-afe8-e8d20b3b3442
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160077541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1160077541
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1460364460
Short name T1207
Test name
Test status
Simulation time 40100483 ps
CPU time 1.41 seconds
Started Aug 03 04:40:55 PM PDT 24
Finished Aug 03 04:40:56 PM PDT 24
Peak memory 229888 kb
Host smart-dbf94a23-06ae-4c6c-9e6e-f8536fa2a4c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460364460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1460364460
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.507180917
Short name T1264
Test name
Test status
Simulation time 52951277 ps
CPU time 1.91 seconds
Started Aug 03 04:40:39 PM PDT 24
Finished Aug 03 04:40:41 PM PDT 24
Peak memory 238688 kb
Host smart-57a122de-a601-4421-bedb-38879eb56a59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507180917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_c
trl_same_csr_outstanding.507180917
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2154361589
Short name T1206
Test name
Test status
Simulation time 106377239 ps
CPU time 3.68 seconds
Started Aug 03 04:40:54 PM PDT 24
Finished Aug 03 04:40:58 PM PDT 24
Peak memory 245756 kb
Host smart-a5eb3395-79da-467f-8b3e-0cb603b14e9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154361589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2154361589
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.981310684
Short name T311
Test name
Test status
Simulation time 172821011 ps
CPU time 4.65 seconds
Started Aug 03 04:40:29 PM PDT 24
Finished Aug 03 04:40:33 PM PDT 24
Peak memory 238284 kb
Host smart-a3070f7a-b5a8-4f86-9945-488459b56951
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981310684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alias
ing.981310684
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2773528286
Short name T1214
Test name
Test status
Simulation time 2012238520 ps
CPU time 7.49 seconds
Started Aug 03 04:40:29 PM PDT 24
Finished Aug 03 04:40:38 PM PDT 24
Peak memory 238792 kb
Host smart-ad654ea1-2d16-4f44-9161-e72c471b9a43
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773528286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.2773528286
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2934624376
Short name T324
Test name
Test status
Simulation time 131703659 ps
CPU time 1.85 seconds
Started Aug 03 04:40:28 PM PDT 24
Finished Aug 03 04:40:30 PM PDT 24
Peak memory 240252 kb
Host smart-9d1d9d4e-3b10-49af-9753-ea6d1d38b623
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934624376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.2934624376
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1711658469
Short name T1208
Test name
Test status
Simulation time 265066062 ps
CPU time 2.52 seconds
Started Aug 03 04:40:24 PM PDT 24
Finished Aug 03 04:40:27 PM PDT 24
Peak memory 247016 kb
Host smart-a3a3618c-d2b1-4028-adf3-8f05888368e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711658469 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.1711658469
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2055028849
Short name T1321
Test name
Test status
Simulation time 141117890 ps
CPU time 1.62 seconds
Started Aug 03 04:40:48 PM PDT 24
Finished Aug 03 04:40:49 PM PDT 24
Peak memory 240568 kb
Host smart-8c3ca163-fa96-41a9-bb59-ef908e6e1bc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055028849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.2055028849
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.867454428
Short name T1205
Test name
Test status
Simulation time 51896061 ps
CPU time 1.48 seconds
Started Aug 03 04:40:29 PM PDT 24
Finished Aug 03 04:40:30 PM PDT 24
Peak memory 230200 kb
Host smart-600d092e-7714-4ea9-841a-c4b36b15ba97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867454428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.867454428
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.737493559
Short name T1252
Test name
Test status
Simulation time 68746575 ps
CPU time 1.3 seconds
Started Aug 03 04:40:35 PM PDT 24
Finished Aug 03 04:40:41 PM PDT 24
Peak memory 229568 kb
Host smart-41163b93-a8ec-4e43-aee9-31799624ece5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737493559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl
_mem_partial_access.737493559
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.458007821
Short name T1242
Test name
Test status
Simulation time 502990641 ps
CPU time 1.64 seconds
Started Aug 03 04:40:47 PM PDT 24
Finished Aug 03 04:40:49 PM PDT 24
Peak memory 229680 kb
Host smart-21f7b2b5-9d91-463f-af29-19ecd8dd3aae
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458007821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.
458007821
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2965302495
Short name T1270
Test name
Test status
Simulation time 182652478 ps
CPU time 2.08 seconds
Started Aug 03 04:40:28 PM PDT 24
Finished Aug 03 04:40:31 PM PDT 24
Peak memory 238828 kb
Host smart-b16cfa2b-6ec7-485e-b869-89352851e928
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965302495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.2965302495
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3064923600
Short name T1285
Test name
Test status
Simulation time 140333813 ps
CPU time 4.48 seconds
Started Aug 03 04:40:44 PM PDT 24
Finished Aug 03 04:40:48 PM PDT 24
Peak memory 245608 kb
Host smart-7d5a6509-fcf7-4295-969a-929b004211fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064923600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3064923600
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1618211593
Short name T1311
Test name
Test status
Simulation time 5928908600 ps
CPU time 43.16 seconds
Started Aug 03 04:40:46 PM PDT 24
Finished Aug 03 04:41:29 PM PDT 24
Peak memory 244664 kb
Host smart-c9e82f3d-e341-47ea-bc43-5045bc54da11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618211593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.1618211593
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.2225364853
Short name T1226
Test name
Test status
Simulation time 89773481 ps
CPU time 1.53 seconds
Started Aug 03 04:40:39 PM PDT 24
Finished Aug 03 04:40:41 PM PDT 24
Peak memory 230160 kb
Host smart-f475c32b-d82a-47ab-b860-33684ec94567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225364853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.2225364853
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.4077244153
Short name T1291
Test name
Test status
Simulation time 74623269 ps
CPU time 1.46 seconds
Started Aug 03 04:40:45 PM PDT 24
Finished Aug 03 04:40:46 PM PDT 24
Peak memory 230180 kb
Host smart-723c884f-7b46-40cc-a31a-4eaf9e6d4281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077244153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.4077244153
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1430039267
Short name T1304
Test name
Test status
Simulation time 134440862 ps
CPU time 1.44 seconds
Started Aug 03 04:40:57 PM PDT 24
Finished Aug 03 04:40:58 PM PDT 24
Peak memory 230580 kb
Host smart-6b45ceb0-5f72-43a2-b004-3d1297119b52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430039267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1430039267
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3238176155
Short name T1299
Test name
Test status
Simulation time 51120915 ps
CPU time 1.49 seconds
Started Aug 03 04:41:00 PM PDT 24
Finished Aug 03 04:41:01 PM PDT 24
Peak memory 229924 kb
Host smart-7e0e8faf-2f0f-435b-adab-561e8bb3f678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238176155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3238176155
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.4224622616
Short name T1307
Test name
Test status
Simulation time 41061210 ps
CPU time 1.43 seconds
Started Aug 03 04:41:05 PM PDT 24
Finished Aug 03 04:41:06 PM PDT 24
Peak memory 229832 kb
Host smart-dee45637-f7ad-4bb0-93e9-50412197b1d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224622616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.4224622616
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1952569051
Short name T1196
Test name
Test status
Simulation time 76494106 ps
CPU time 1.47 seconds
Started Aug 03 04:41:10 PM PDT 24
Finished Aug 03 04:41:12 PM PDT 24
Peak memory 229884 kb
Host smart-308e8092-a350-4c86-aee5-851bcbc2f1eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952569051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1952569051
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.3697483063
Short name T1190
Test name
Test status
Simulation time 41864021 ps
CPU time 1.48 seconds
Started Aug 03 04:41:16 PM PDT 24
Finished Aug 03 04:41:17 PM PDT 24
Peak memory 230612 kb
Host smart-23e2cb32-1bc0-4279-ba7e-f8cb15638d6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697483063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.3697483063
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.73584566
Short name T1253
Test name
Test status
Simulation time 38548046 ps
CPU time 1.41 seconds
Started Aug 03 04:41:00 PM PDT 24
Finished Aug 03 04:41:06 PM PDT 24
Peak memory 230608 kb
Host smart-a62191b6-d47d-4035-b1b9-5e270fcad60d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73584566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.73584566
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.532873885
Short name T1195
Test name
Test status
Simulation time 537242914 ps
CPU time 1.58 seconds
Started Aug 03 04:41:01 PM PDT 24
Finished Aug 03 04:41:03 PM PDT 24
Peak memory 229856 kb
Host smart-09b95c9c-9cd9-45cf-923f-dc1442b53abe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532873885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.532873885
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.463797576
Short name T1296
Test name
Test status
Simulation time 76405517 ps
CPU time 1.4 seconds
Started Aug 03 04:41:02 PM PDT 24
Finished Aug 03 04:41:04 PM PDT 24
Peak memory 230192 kb
Host smart-f89f805f-1fe6-4c26-9171-69a6a7061759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463797576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.463797576
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2116614177
Short name T305
Test name
Test status
Simulation time 191688806 ps
CPU time 3.56 seconds
Started Aug 03 04:40:50 PM PDT 24
Finished Aug 03 04:40:54 PM PDT 24
Peak memory 238628 kb
Host smart-75721568-506b-4fde-a28b-e512513c7448
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116614177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.2116614177
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.428262518
Short name T314
Test name
Test status
Simulation time 1614584344 ps
CPU time 9.73 seconds
Started Aug 03 04:40:36 PM PDT 24
Finished Aug 03 04:40:45 PM PDT 24
Peak memory 238808 kb
Host smart-a506992d-10dc-4291-a42f-6d7a91071807
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428262518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_b
ash.428262518
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.4047344274
Short name T310
Test name
Test status
Simulation time 70355194 ps
CPU time 1.93 seconds
Started Aug 03 04:40:32 PM PDT 24
Finished Aug 03 04:40:34 PM PDT 24
Peak memory 238724 kb
Host smart-d8c10a11-a4d1-486f-b57a-7207408bf0f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047344274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.4047344274
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1858256006
Short name T1306
Test name
Test status
Simulation time 261648457 ps
CPU time 2.46 seconds
Started Aug 03 04:41:03 PM PDT 24
Finished Aug 03 04:41:06 PM PDT 24
Peak memory 244520 kb
Host smart-c6c3aee2-82e3-458a-9b57-d8f030aa690d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858256006 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.1858256006
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3337631677
Short name T1258
Test name
Test status
Simulation time 573842607 ps
CPU time 2.16 seconds
Started Aug 03 04:40:27 PM PDT 24
Finished Aug 03 04:40:29 PM PDT 24
Peak memory 240872 kb
Host smart-0766a4e8-931a-4df9-9399-a58f871783e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337631677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.3337631677
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.4278523894
Short name T1278
Test name
Test status
Simulation time 37385441 ps
CPU time 1.36 seconds
Started Aug 03 04:40:36 PM PDT 24
Finished Aug 03 04:40:37 PM PDT 24
Peak memory 230072 kb
Host smart-44033a8f-9308-4635-9ec1-d46b1e43440e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278523894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.4278523894
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1723281754
Short name T1220
Test name
Test status
Simulation time 139497330 ps
CPU time 1.44 seconds
Started Aug 03 04:40:34 PM PDT 24
Finished Aug 03 04:40:38 PM PDT 24
Peak memory 229532 kb
Host smart-7758081a-9bdc-497e-b0b6-0ee475ebf40c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723281754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.1723281754
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.83210569
Short name T1302
Test name
Test status
Simulation time 554327788 ps
CPU time 1.51 seconds
Started Aug 03 04:40:53 PM PDT 24
Finished Aug 03 04:40:55 PM PDT 24
Peak memory 229512 kb
Host smart-29b6f2c3-a923-4d43-ac68-d7655d5c8ea1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83210569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.83210569
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.681486154
Short name T332
Test name
Test status
Simulation time 82715918 ps
CPU time 2.22 seconds
Started Aug 03 04:40:35 PM PDT 24
Finished Aug 03 04:40:38 PM PDT 24
Peak memory 238716 kb
Host smart-fddb6ce7-ab0f-498a-8bc7-a3cc2e9b8865
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681486154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ct
rl_same_csr_outstanding.681486154
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.2251988443
Short name T1192
Test name
Test status
Simulation time 1290873667 ps
CPU time 6.5 seconds
Started Aug 03 04:40:29 PM PDT 24
Finished Aug 03 04:40:35 PM PDT 24
Peak memory 245868 kb
Host smart-a97f261f-c27e-4d42-8724-0c0b4b321c54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251988443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.2251988443
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2197700301
Short name T358
Test name
Test status
Simulation time 2404022367 ps
CPU time 10.3 seconds
Started Aug 03 04:40:28 PM PDT 24
Finished Aug 03 04:40:38 PM PDT 24
Peak memory 243860 kb
Host smart-a5c11647-b01d-4879-a5de-adc0c85a7a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197700301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.2197700301
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1200301711
Short name T1233
Test name
Test status
Simulation time 41847663 ps
CPU time 1.44 seconds
Started Aug 03 04:41:11 PM PDT 24
Finished Aug 03 04:41:18 PM PDT 24
Peak memory 229856 kb
Host smart-7cdbbe4f-eadb-4b0e-a02d-3ca07c9cb3dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200301711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1200301711
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.402638195
Short name T1201
Test name
Test status
Simulation time 94116450 ps
CPU time 1.32 seconds
Started Aug 03 04:41:09 PM PDT 24
Finished Aug 03 04:41:11 PM PDT 24
Peak memory 229804 kb
Host smart-aa39bfbb-8441-4dc0-b5b8-56169379d3b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402638195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.402638195
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.506855339
Short name T1193
Test name
Test status
Simulation time 40030732 ps
CPU time 1.41 seconds
Started Aug 03 04:41:05 PM PDT 24
Finished Aug 03 04:41:06 PM PDT 24
Peak memory 230580 kb
Host smart-e2231410-ca81-4122-b2ec-0588ab6a77ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506855339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.506855339
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.4011099591
Short name T1323
Test name
Test status
Simulation time 36291464 ps
CPU time 1.37 seconds
Started Aug 03 04:41:03 PM PDT 24
Finished Aug 03 04:41:05 PM PDT 24
Peak memory 230592 kb
Host smart-d122202e-262a-4c6c-a3d6-770611d00f86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011099591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.4011099591
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.4161695017
Short name T1221
Test name
Test status
Simulation time 74998832 ps
CPU time 1.37 seconds
Started Aug 03 04:41:12 PM PDT 24
Finished Aug 03 04:41:13 PM PDT 24
Peak memory 229884 kb
Host smart-663ac876-407b-4a84-be76-15535db2358c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161695017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.4161695017
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.1683069352
Short name T1200
Test name
Test status
Simulation time 140269574 ps
CPU time 1.4 seconds
Started Aug 03 04:40:51 PM PDT 24
Finished Aug 03 04:40:53 PM PDT 24
Peak memory 230044 kb
Host smart-73e6a538-df64-4507-ba64-b4a15488b045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683069352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.1683069352
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.651753465
Short name T1209
Test name
Test status
Simulation time 139263982 ps
CPU time 1.59 seconds
Started Aug 03 04:41:13 PM PDT 24
Finished Aug 03 04:41:15 PM PDT 24
Peak memory 230128 kb
Host smart-3a44c9f3-a255-445e-9d58-37ba26751d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651753465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.651753465
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3316597377
Short name T1228
Test name
Test status
Simulation time 608853176 ps
CPU time 1.75 seconds
Started Aug 03 04:41:10 PM PDT 24
Finished Aug 03 04:41:12 PM PDT 24
Peak memory 229916 kb
Host smart-0c937fc3-5b9a-49da-a099-672a2c795ac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316597377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3316597377
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2549511729
Short name T1303
Test name
Test status
Simulation time 46627545 ps
CPU time 1.52 seconds
Started Aug 03 04:40:53 PM PDT 24
Finished Aug 03 04:40:54 PM PDT 24
Peak memory 229876 kb
Host smart-0ac381e4-1044-4066-8ea5-94d843f55a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549511729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2549511729
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.196939444
Short name T1260
Test name
Test status
Simulation time 95955308 ps
CPU time 1.6 seconds
Started Aug 03 04:40:59 PM PDT 24
Finished Aug 03 04:41:06 PM PDT 24
Peak memory 229884 kb
Host smart-37119866-2ce5-4070-a48d-3592340de352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196939444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.196939444
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3587772838
Short name T1312
Test name
Test status
Simulation time 531878688 ps
CPU time 6.84 seconds
Started Aug 03 04:40:33 PM PDT 24
Finished Aug 03 04:40:40 PM PDT 24
Peak memory 238976 kb
Host smart-1f2d56c4-5fb0-4d9d-b6f1-22c3e34550b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587772838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.3587772838
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3952163038
Short name T1288
Test name
Test status
Simulation time 161996297 ps
CPU time 3.71 seconds
Started Aug 03 04:40:30 PM PDT 24
Finished Aug 03 04:40:34 PM PDT 24
Peak memory 238768 kb
Host smart-45c65345-cee8-4e0e-8fcb-49f8f7c396d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952163038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.3952163038
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2183275605
Short name T303
Test name
Test status
Simulation time 71729159 ps
CPU time 1.87 seconds
Started Aug 03 04:40:28 PM PDT 24
Finished Aug 03 04:40:30 PM PDT 24
Peak memory 238836 kb
Host smart-3e1cdf27-67b7-47e0-8897-d9c3ad916a1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183275605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.2183275605
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3672049329
Short name T1251
Test name
Test status
Simulation time 996619664 ps
CPU time 2.25 seconds
Started Aug 03 04:41:00 PM PDT 24
Finished Aug 03 04:41:02 PM PDT 24
Peak memory 244256 kb
Host smart-cb8e8dcf-0e75-4778-8670-1f4a19061968
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672049329 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.3672049329
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.1258382654
Short name T306
Test name
Test status
Simulation time 38970021 ps
CPU time 1.66 seconds
Started Aug 03 04:40:35 PM PDT 24
Finished Aug 03 04:40:37 PM PDT 24
Peak memory 240512 kb
Host smart-29d4d4f2-91bc-49b5-9773-9a8fa5bfe9c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258382654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.1258382654
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.592853954
Short name T1259
Test name
Test status
Simulation time 136262992 ps
CPU time 1.39 seconds
Started Aug 03 04:40:36 PM PDT 24
Finished Aug 03 04:40:38 PM PDT 24
Peak memory 230048 kb
Host smart-3568d37c-0fb4-482b-a71e-3e29e4c6a037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592853954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.592853954
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1856671583
Short name T1292
Test name
Test status
Simulation time 37437756 ps
CPU time 1.39 seconds
Started Aug 03 04:40:33 PM PDT 24
Finished Aug 03 04:40:35 PM PDT 24
Peak memory 229856 kb
Host smart-d5f84a54-7521-42ec-b9cd-4e6d711b4eec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856671583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.1856671583
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.558434694
Short name T1284
Test name
Test status
Simulation time 541223425 ps
CPU time 1.85 seconds
Started Aug 03 04:40:37 PM PDT 24
Finished Aug 03 04:40:39 PM PDT 24
Peak memory 229816 kb
Host smart-1eaf744f-0caa-47ca-9cc3-ea68cfc0b16b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558434694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.
558434694
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3918598734
Short name T1257
Test name
Test status
Simulation time 84411955 ps
CPU time 1.98 seconds
Started Aug 03 04:40:31 PM PDT 24
Finished Aug 03 04:40:33 PM PDT 24
Peak memory 238676 kb
Host smart-c951aa9d-1961-4c10-924c-1102c7a5b7e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918598734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.3918598734
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3687206511
Short name T1290
Test name
Test status
Simulation time 149467835 ps
CPU time 5.21 seconds
Started Aug 03 04:40:39 PM PDT 24
Finished Aug 03 04:40:45 PM PDT 24
Peak memory 245348 kb
Host smart-535dace4-16a9-445f-9407-56b98b4618e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687206511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3687206511
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2134036580
Short name T1240
Test name
Test status
Simulation time 592472006 ps
CPU time 2.04 seconds
Started Aug 03 04:41:19 PM PDT 24
Finished Aug 03 04:41:21 PM PDT 24
Peak memory 230176 kb
Host smart-c4b27c26-ddd3-4115-9edb-e83b3fdad30c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134036580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2134036580
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.381541132
Short name T1273
Test name
Test status
Simulation time 41054458 ps
CPU time 1.53 seconds
Started Aug 03 04:41:19 PM PDT 24
Finished Aug 03 04:41:21 PM PDT 24
Peak memory 230608 kb
Host smart-45afef11-be00-4776-b898-17b0bde66eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381541132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.381541132
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1861840836
Short name T1255
Test name
Test status
Simulation time 77168309 ps
CPU time 1.5 seconds
Started Aug 03 04:41:05 PM PDT 24
Finished Aug 03 04:41:07 PM PDT 24
Peak memory 229908 kb
Host smart-0f33ebc9-4a96-4584-a1b3-2d2745270d34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861840836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.1861840836
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3542592284
Short name T1204
Test name
Test status
Simulation time 36895074 ps
CPU time 1.37 seconds
Started Aug 03 04:41:09 PM PDT 24
Finished Aug 03 04:41:11 PM PDT 24
Peak memory 230124 kb
Host smart-52f41661-5089-42ad-9e81-5c54b4b03273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542592284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3542592284
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2849677964
Short name T1197
Test name
Test status
Simulation time 47316778 ps
CPU time 1.49 seconds
Started Aug 03 04:41:04 PM PDT 24
Finished Aug 03 04:41:05 PM PDT 24
Peak memory 229816 kb
Host smart-952ebc1c-f625-40d7-8df3-2cd887e44808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849677964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2849677964
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.3221423825
Short name T1283
Test name
Test status
Simulation time 517241673 ps
CPU time 1.48 seconds
Started Aug 03 04:40:55 PM PDT 24
Finished Aug 03 04:40:57 PM PDT 24
Peak memory 229820 kb
Host smart-a8222b70-0525-4a04-91cd-a3b338c5aa5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221423825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.3221423825
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2666077465
Short name T1235
Test name
Test status
Simulation time 73629829 ps
CPU time 1.42 seconds
Started Aug 03 04:40:56 PM PDT 24
Finished Aug 03 04:40:58 PM PDT 24
Peak memory 229720 kb
Host smart-db7ef028-0284-470d-a60e-c40185ec4d14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666077465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2666077465
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1252103088
Short name T1322
Test name
Test status
Simulation time 568894078 ps
CPU time 2.05 seconds
Started Aug 03 04:41:02 PM PDT 24
Finished Aug 03 04:41:04 PM PDT 24
Peak memory 230392 kb
Host smart-04020736-6908-40e0-85a4-d5fb5c4a3fd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252103088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.1252103088
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2971928511
Short name T1282
Test name
Test status
Simulation time 68649813 ps
CPU time 1.42 seconds
Started Aug 03 04:41:11 PM PDT 24
Finished Aug 03 04:41:12 PM PDT 24
Peak memory 230140 kb
Host smart-5193abd4-f926-4531-9f89-989c3161ed2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971928511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2971928511
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3932660068
Short name T1315
Test name
Test status
Simulation time 131576930 ps
CPU time 1.51 seconds
Started Aug 03 04:41:05 PM PDT 24
Finished Aug 03 04:41:07 PM PDT 24
Peak memory 229888 kb
Host smart-d226a872-68dc-4ea6-b9dd-e795680ea59f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932660068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3932660068
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.551913
Short name T1239
Test name
Test status
Simulation time 151201594 ps
CPU time 2.65 seconds
Started Aug 03 04:40:31 PM PDT 24
Finished Aug 03 04:40:33 PM PDT 24
Peak memory 247248 kb
Host smart-1d8b1dff-db32-4f5d-a059-cc4485eda179
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551913 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.551913
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.2039286656
Short name T1309
Test name
Test status
Simulation time 177182259 ps
CPU time 2.03 seconds
Started Aug 03 04:41:03 PM PDT 24
Finished Aug 03 04:41:05 PM PDT 24
Peak memory 240608 kb
Host smart-2568d39d-2aa3-4367-a2de-0382eebe3d31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039286656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.2039286656
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3862006817
Short name T1274
Test name
Test status
Simulation time 563067598 ps
CPU time 1.74 seconds
Started Aug 03 04:40:58 PM PDT 24
Finished Aug 03 04:41:00 PM PDT 24
Peak memory 230432 kb
Host smart-58058db5-291f-4512-b9ff-a31ff94ef7a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862006817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3862006817
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3947148707
Short name T1314
Test name
Test status
Simulation time 76178258 ps
CPU time 2.37 seconds
Started Aug 03 04:40:53 PM PDT 24
Finished Aug 03 04:40:56 PM PDT 24
Peak memory 238640 kb
Host smart-64ca1f6b-c8a2-4a33-b53e-e98610130207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947148707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.3947148707
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.587496698
Short name T1262
Test name
Test status
Simulation time 230513779 ps
CPU time 4.18 seconds
Started Aug 03 04:40:49 PM PDT 24
Finished Aug 03 04:40:53 PM PDT 24
Peak memory 245492 kb
Host smart-c1cb71ea-df2f-4a73-b160-91131482955b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587496698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.587496698
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1467388839
Short name T280
Test name
Test status
Simulation time 1688953876 ps
CPU time 4.93 seconds
Started Aug 03 04:40:37 PM PDT 24
Finished Aug 03 04:40:42 PM PDT 24
Peak memory 246980 kb
Host smart-b387d9e3-f7c6-4f41-b5bc-91022c26d631
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467388839 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.1467388839
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.4113909403
Short name T1281
Test name
Test status
Simulation time 89514845 ps
CPU time 1.77 seconds
Started Aug 03 04:40:30 PM PDT 24
Finished Aug 03 04:40:32 PM PDT 24
Peak memory 240996 kb
Host smart-277d7bde-bb23-44a7-981d-633603f9cd0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113909403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.4113909403
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.432795305
Short name T1301
Test name
Test status
Simulation time 75462797 ps
CPU time 1.41 seconds
Started Aug 03 04:40:33 PM PDT 24
Finished Aug 03 04:40:35 PM PDT 24
Peak memory 230560 kb
Host smart-6e4ec072-8c32-40eb-b496-1f820e31853e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432795305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.432795305
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.4256796538
Short name T331
Test name
Test status
Simulation time 59238242 ps
CPU time 1.93 seconds
Started Aug 03 04:40:32 PM PDT 24
Finished Aug 03 04:40:34 PM PDT 24
Peak memory 238792 kb
Host smart-96d8c261-164d-427b-9d6d-5daf411e5c6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256796538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.4256796538
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1740153914
Short name T1213
Test name
Test status
Simulation time 108269157 ps
CPU time 3.21 seconds
Started Aug 03 04:40:34 PM PDT 24
Finished Aug 03 04:40:37 PM PDT 24
Peak memory 245836 kb
Host smart-201bb1f7-d29e-49e5-aee8-82d3a90de9f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740153914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.1740153914
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.31098076
Short name T1246
Test name
Test status
Simulation time 1220837151 ps
CPU time 16.98 seconds
Started Aug 03 04:40:32 PM PDT 24
Finished Aug 03 04:40:49 PM PDT 24
Peak memory 243888 kb
Host smart-048aae09-5663-4192-8bfe-35f35e7f0889
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31098076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg
_err.31098076
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.690464722
Short name T1289
Test name
Test status
Simulation time 119128556 ps
CPU time 2.73 seconds
Started Aug 03 04:40:31 PM PDT 24
Finished Aug 03 04:40:34 PM PDT 24
Peak memory 246668 kb
Host smart-e1811c35-abc3-44de-8157-f04583e8cf71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690464722 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.690464722
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1300413274
Short name T1293
Test name
Test status
Simulation time 73392540 ps
CPU time 1.56 seconds
Started Aug 03 04:40:30 PM PDT 24
Finished Aug 03 04:40:31 PM PDT 24
Peak memory 241032 kb
Host smart-42c0f5b9-4791-4bae-977a-0a58941c46f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300413274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.1300413274
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.4228956507
Short name T1280
Test name
Test status
Simulation time 596372274 ps
CPU time 2.15 seconds
Started Aug 03 04:40:28 PM PDT 24
Finished Aug 03 04:40:30 PM PDT 24
Peak memory 229660 kb
Host smart-50e5d311-05db-44e8-baef-f475502d1636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228956507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.4228956507
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3204529102
Short name T325
Test name
Test status
Simulation time 56517624 ps
CPU time 1.91 seconds
Started Aug 03 04:40:31 PM PDT 24
Finished Aug 03 04:40:33 PM PDT 24
Peak memory 238772 kb
Host smart-35ac8977-408b-4fcb-a2d5-2d814ccba497
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204529102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.3204529102
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3401819116
Short name T1227
Test name
Test status
Simulation time 371398842 ps
CPU time 5.26 seconds
Started Aug 03 04:40:51 PM PDT 24
Finished Aug 03 04:40:57 PM PDT 24
Peak memory 238740 kb
Host smart-2b0d96cd-6da8-4db7-acbd-71a6166a77f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401819116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3401819116
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1762948218
Short name T277
Test name
Test status
Simulation time 1604287547 ps
CPU time 10.54 seconds
Started Aug 03 04:41:03 PM PDT 24
Finished Aug 03 04:41:14 PM PDT 24
Peak memory 243324 kb
Host smart-655c2989-9da7-4ef7-b2c5-b375e82677e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762948218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.1762948218
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.1907720909
Short name T1286
Test name
Test status
Simulation time 71181708 ps
CPU time 1.97 seconds
Started Aug 03 04:40:44 PM PDT 24
Finished Aug 03 04:40:46 PM PDT 24
Peak memory 243956 kb
Host smart-66c213bf-a044-40ea-a3bb-8b73a23a663f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907720909 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.1907720909
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1766745518
Short name T1287
Test name
Test status
Simulation time 167858442 ps
CPU time 1.79 seconds
Started Aug 03 04:40:34 PM PDT 24
Finished Aug 03 04:40:36 PM PDT 24
Peak memory 241112 kb
Host smart-8b1b8454-7d57-4c38-91ad-6f48a0b704f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766745518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.1766745518
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.140123640
Short name T1263
Test name
Test status
Simulation time 50049628 ps
CPU time 1.37 seconds
Started Aug 03 04:40:43 PM PDT 24
Finished Aug 03 04:40:45 PM PDT 24
Peak memory 229356 kb
Host smart-45fe8453-4041-48ad-8ee6-8c6f100f0604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140123640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.140123640
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.4052087065
Short name T1308
Test name
Test status
Simulation time 136090127 ps
CPU time 2.23 seconds
Started Aug 03 04:40:54 PM PDT 24
Finished Aug 03 04:40:56 PM PDT 24
Peak memory 238716 kb
Host smart-59b90ba7-9a9c-4aff-aa50-ddf233290be0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052087065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.4052087065
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.1609404662
Short name T1272
Test name
Test status
Simulation time 288322859 ps
CPU time 4.59 seconds
Started Aug 03 04:40:53 PM PDT 24
Finished Aug 03 04:40:58 PM PDT 24
Peak memory 245828 kb
Host smart-ed3d3a91-66db-439a-8bca-454afb1113b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609404662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.1609404662
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3206417130
Short name T1238
Test name
Test status
Simulation time 1977140962 ps
CPU time 22.07 seconds
Started Aug 03 04:40:36 PM PDT 24
Finished Aug 03 04:40:58 PM PDT 24
Peak memory 243908 kb
Host smart-049d1066-1cc0-4475-b6e7-0dc68d048fa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206417130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.3206417130
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1594982132
Short name T1254
Test name
Test status
Simulation time 105046165 ps
CPU time 2.86 seconds
Started Aug 03 04:40:39 PM PDT 24
Finished Aug 03 04:40:42 PM PDT 24
Peak memory 246884 kb
Host smart-c99f9375-ec2f-4ff8-b62a-2e975765a88e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594982132 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.1594982132
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.89793370
Short name T1275
Test name
Test status
Simulation time 623528845 ps
CPU time 1.56 seconds
Started Aug 03 04:40:40 PM PDT 24
Finished Aug 03 04:40:41 PM PDT 24
Peak memory 240452 kb
Host smart-8480a470-ab23-4bee-94ec-c214bd784750
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89793370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.89793370
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1713812354
Short name T1271
Test name
Test status
Simulation time 133811482 ps
CPU time 1.42 seconds
Started Aug 03 04:40:33 PM PDT 24
Finished Aug 03 04:40:35 PM PDT 24
Peak memory 229848 kb
Host smart-101dfc9c-eefa-43b8-acf0-5717b19d2dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713812354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1713812354
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.440522674
Short name T1265
Test name
Test status
Simulation time 310701679 ps
CPU time 2.74 seconds
Started Aug 03 04:40:50 PM PDT 24
Finished Aug 03 04:40:53 PM PDT 24
Peak memory 241840 kb
Host smart-9fda7418-4187-4ddc-b884-d2d5bb50620f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440522674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ct
rl_same_csr_outstanding.440522674
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1311055326
Short name T1202
Test name
Test status
Simulation time 1256923303 ps
CPU time 6.1 seconds
Started Aug 03 04:40:48 PM PDT 24
Finished Aug 03 04:40:54 PM PDT 24
Peak memory 246132 kb
Host smart-7196e5b3-a92b-441c-a164-f23f74172865
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311055326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.1311055326
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.266036088
Short name T364
Test name
Test status
Simulation time 10284339823 ps
CPU time 10.18 seconds
Started Aug 03 04:40:36 PM PDT 24
Finished Aug 03 04:40:47 PM PDT 24
Peak memory 244256 kb
Host smart-c21dea57-f83c-493e-a318-76f4cf478f80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266036088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_int
g_err.266036088
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.852770446
Short name T1113
Test name
Test status
Simulation time 110403121 ps
CPU time 1.99 seconds
Started Aug 03 06:34:24 PM PDT 24
Finished Aug 03 06:34:26 PM PDT 24
Peak memory 240524 kb
Host smart-b2b17827-d495-40e0-827a-cf004a545522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852770446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.852770446
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.836641222
Short name T119
Test name
Test status
Simulation time 2392344941 ps
CPU time 18.42 seconds
Started Aug 03 06:34:21 PM PDT 24
Finished Aug 03 06:34:39 PM PDT 24
Peak memory 248744 kb
Host smart-44b38802-f67c-43b8-8b73-c00b0d2cb992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836641222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.836641222
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.1326024960
Short name T613
Test name
Test status
Simulation time 664253811 ps
CPU time 8.78 seconds
Started Aug 03 06:34:28 PM PDT 24
Finished Aug 03 06:34:36 PM PDT 24
Peak memory 242568 kb
Host smart-cd21468b-614f-43b2-a146-40cc5472dcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326024960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.1326024960
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.1898514864
Short name T641
Test name
Test status
Simulation time 809093965 ps
CPU time 25.61 seconds
Started Aug 03 06:34:22 PM PDT 24
Finished Aug 03 06:34:47 PM PDT 24
Peak memory 242032 kb
Host smart-681accf2-cac1-4a5d-8ce1-d964c396dfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898514864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.1898514864
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.2289933113
Short name T409
Test name
Test status
Simulation time 264908535 ps
CPU time 5.53 seconds
Started Aug 03 06:34:20 PM PDT 24
Finished Aug 03 06:34:26 PM PDT 24
Peak memory 241968 kb
Host smart-8293ba6b-97f3-4a07-9b86-ac16e259e9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289933113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.2289933113
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.599449010
Short name T919
Test name
Test status
Simulation time 252474586 ps
CPU time 3.27 seconds
Started Aug 03 06:34:20 PM PDT 24
Finished Aug 03 06:34:23 PM PDT 24
Peak memory 242252 kb
Host smart-997f2d55-4e71-4dea-b79e-7280b622fe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599449010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.599449010
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.3847487963
Short name T1171
Test name
Test status
Simulation time 7272935031 ps
CPU time 14.96 seconds
Started Aug 03 06:34:21 PM PDT 24
Finished Aug 03 06:34:36 PM PDT 24
Peak memory 240624 kb
Host smart-11c8bcd3-112f-4224-9591-527f8cb6868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847487963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.3847487963
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.598959405
Short name T707
Test name
Test status
Simulation time 782836167 ps
CPU time 19.08 seconds
Started Aug 03 06:34:29 PM PDT 24
Finished Aug 03 06:34:48 PM PDT 24
Peak memory 242896 kb
Host smart-efa42fdd-a94c-4271-845f-64711a145ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598959405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.598959405
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.1564988753
Short name T387
Test name
Test status
Simulation time 735470624 ps
CPU time 19.37 seconds
Started Aug 03 06:34:26 PM PDT 24
Finished Aug 03 06:34:46 PM PDT 24
Peak memory 242192 kb
Host smart-fdecf713-7374-4ff8-80c3-6dd5da5370b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564988753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1564988753
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.2843799677
Short name T998
Test name
Test status
Simulation time 331588052 ps
CPU time 5.12 seconds
Started Aug 03 06:34:22 PM PDT 24
Finished Aug 03 06:34:27 PM PDT 24
Peak memory 242040 kb
Host smart-1b8ca84a-b6d9-447a-8439-6771db25bc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843799677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.2843799677
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.422434118
Short name T1164
Test name
Test status
Simulation time 741088010 ps
CPU time 21.62 seconds
Started Aug 03 06:34:19 PM PDT 24
Finished Aug 03 06:34:41 PM PDT 24
Peak memory 248636 kb
Host smart-7bd01b40-7f84-475c-bdd7-6eee640f2f7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=422434118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.422434118
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.271706329
Short name T637
Test name
Test status
Simulation time 402105842 ps
CPU time 18.33 seconds
Started Aug 03 06:34:16 PM PDT 24
Finished Aug 03 06:34:34 PM PDT 24
Peak memory 241588 kb
Host smart-6117f10f-09c9-4611-8247-2d47f6720a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271706329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.271706329
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.436038458
Short name T10
Test name
Test status
Simulation time 605945310 ps
CPU time 6.51 seconds
Started Aug 03 06:34:28 PM PDT 24
Finished Aug 03 06:34:34 PM PDT 24
Peak memory 241924 kb
Host smart-4a7618f7-3c72-46ca-abcb-17a4b72b7c70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=436038458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.436038458
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.472011867
Short name T23
Test name
Test status
Simulation time 20358534340 ps
CPU time 202 seconds
Started Aug 03 06:34:23 PM PDT 24
Finished Aug 03 06:37:45 PM PDT 24
Peak memory 271156 kb
Host smart-b5c50e0d-ff9c-499b-ba5b-fde92fc8abff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472011867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.472011867
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.354589026
Short name T1133
Test name
Test status
Simulation time 4719189547 ps
CPU time 8.95 seconds
Started Aug 03 06:34:15 PM PDT 24
Finished Aug 03 06:34:24 PM PDT 24
Peak memory 242536 kb
Host smart-891bb41b-3aef-4223-a9f5-765363098003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354589026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.354589026
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.1196903114
Short name T36
Test name
Test status
Simulation time 22078278279 ps
CPU time 520.95 seconds
Started Aug 03 06:34:27 PM PDT 24
Finished Aug 03 06:43:08 PM PDT 24
Peak memory 256968 kb
Host smart-042651c7-bfb3-4582-abae-2c7122597756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196903114 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.1196903114
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.3485554599
Short name T630
Test name
Test status
Simulation time 1155468823 ps
CPU time 14.76 seconds
Started Aug 03 06:34:26 PM PDT 24
Finished Aug 03 06:34:41 PM PDT 24
Peak memory 242360 kb
Host smart-87a9e96f-6604-44c3-9675-958b3a310890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485554599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.3485554599
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.213700457
Short name T954
Test name
Test status
Simulation time 78972634 ps
CPU time 1.56 seconds
Started Aug 03 06:34:39 PM PDT 24
Finished Aug 03 06:34:41 PM PDT 24
Peak memory 240404 kb
Host smart-84d97814-d606-4d74-bf6d-89750f1727be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213700457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.213700457
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.2905205887
Short name T114
Test name
Test status
Simulation time 554274608 ps
CPU time 17.67 seconds
Started Aug 03 06:34:34 PM PDT 24
Finished Aug 03 06:34:52 PM PDT 24
Peak memory 242244 kb
Host smart-754d276d-124b-4fb3-bac8-e7c59c6bc710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905205887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.2905205887
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.4135281087
Short name T981
Test name
Test status
Simulation time 226433816 ps
CPU time 13.33 seconds
Started Aug 03 06:34:42 PM PDT 24
Finished Aug 03 06:34:55 PM PDT 24
Peak memory 242292 kb
Host smart-592b80eb-9c0b-40cb-826d-57f5a5f51163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135281087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.4135281087
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.144971448
Short name T378
Test name
Test status
Simulation time 267577507 ps
CPU time 6.3 seconds
Started Aug 03 06:34:30 PM PDT 24
Finished Aug 03 06:34:36 PM PDT 24
Peak memory 241948 kb
Host smart-661309b7-ab5f-44dc-9636-20a4c8b1fb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144971448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.144971448
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.3269059623
Short name T685
Test name
Test status
Simulation time 645195330 ps
CPU time 4.07 seconds
Started Aug 03 06:34:29 PM PDT 24
Finished Aug 03 06:34:34 PM PDT 24
Peak memory 242296 kb
Host smart-0019609c-fb6d-45ba-bf55-2090ab446708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269059623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.3269059623
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.2142963157
Short name T640
Test name
Test status
Simulation time 4824221871 ps
CPU time 33.52 seconds
Started Aug 03 06:34:35 PM PDT 24
Finished Aug 03 06:35:08 PM PDT 24
Peak memory 247292 kb
Host smart-af20f2fe-aa63-454a-a983-386143e770f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142963157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.2142963157
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.4166253266
Short name T935
Test name
Test status
Simulation time 786243763 ps
CPU time 19.76 seconds
Started Aug 03 06:34:35 PM PDT 24
Finished Aug 03 06:34:55 PM PDT 24
Peak memory 242156 kb
Host smart-75e76de9-6498-47cc-8cfd-2eca823afd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166253266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.4166253266
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.629764705
Short name T1091
Test name
Test status
Simulation time 2862127935 ps
CPU time 11.12 seconds
Started Aug 03 06:34:32 PM PDT 24
Finished Aug 03 06:34:43 PM PDT 24
Peak memory 242352 kb
Host smart-216ced00-496e-4842-8f86-e55f1bd25cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629764705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.629764705
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.1530702881
Short name T571
Test name
Test status
Simulation time 3709417148 ps
CPU time 11.25 seconds
Started Aug 03 06:34:42 PM PDT 24
Finished Aug 03 06:34:53 PM PDT 24
Peak memory 248672 kb
Host smart-f08c13d7-e5ae-426a-94b1-37245bb5aec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1530702881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.1530702881
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.3535176107
Short name T1162
Test name
Test status
Simulation time 135874833 ps
CPU time 4.7 seconds
Started Aug 03 06:34:36 PM PDT 24
Finished Aug 03 06:34:40 PM PDT 24
Peak memory 241948 kb
Host smart-988c9e78-f6d5-4c36-9a92-2f8e0e2a9370
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3535176107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3535176107
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.1844710259
Short name T233
Test name
Test status
Simulation time 169812911898 ps
CPU time 325.69 seconds
Started Aug 03 06:34:34 PM PDT 24
Finished Aug 03 06:40:00 PM PDT 24
Peak memory 274652 kb
Host smart-3985bb07-9b0b-464d-b4e1-94cc34d60c90
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844710259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.1844710259
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.336588843
Short name T507
Test name
Test status
Simulation time 3078095710 ps
CPU time 5.67 seconds
Started Aug 03 06:34:30 PM PDT 24
Finished Aug 03 06:34:36 PM PDT 24
Peak memory 242180 kb
Host smart-596bc3d4-5f48-4ef8-9082-363837b4d5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336588843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.336588843
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.3693650969
Short name T1055
Test name
Test status
Simulation time 154260910407 ps
CPU time 923.44 seconds
Started Aug 03 06:34:37 PM PDT 24
Finished Aug 03 06:50:01 PM PDT 24
Peak memory 281328 kb
Host smart-4f7b24ae-0db4-454f-b0c7-c7aea1a1d64b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693650969 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.3693650969
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.1523801914
Short name T849
Test name
Test status
Simulation time 1414355872 ps
CPU time 37.6 seconds
Started Aug 03 06:34:35 PM PDT 24
Finished Aug 03 06:35:12 PM PDT 24
Peak memory 241932 kb
Host smart-0c2eb2dc-6f2f-44ad-ad59-1fe652d4a0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523801914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.1523801914
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.2691012936
Short name T1128
Test name
Test status
Simulation time 194696236 ps
CPU time 1.86 seconds
Started Aug 03 06:36:21 PM PDT 24
Finished Aug 03 06:36:23 PM PDT 24
Peak memory 240308 kb
Host smart-039501da-1bff-42cb-99d4-715a29baf03d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691012936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.2691012936
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.3953526128
Short name T1126
Test name
Test status
Simulation time 1957426352 ps
CPU time 18.06 seconds
Started Aug 03 06:36:21 PM PDT 24
Finished Aug 03 06:36:39 PM PDT 24
Peak memory 242260 kb
Host smart-ae40b453-6879-4cee-820a-6c5b13436af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953526128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.3953526128
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.294108899
Short name T657
Test name
Test status
Simulation time 989127962 ps
CPU time 16.51 seconds
Started Aug 03 06:36:18 PM PDT 24
Finished Aug 03 06:36:34 PM PDT 24
Peak memory 241812 kb
Host smart-5c42a595-3e6d-4298-a8ff-35511c414bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294108899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.294108899
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.3676220291
Short name T1111
Test name
Test status
Simulation time 13751192227 ps
CPU time 26.12 seconds
Started Aug 03 06:36:16 PM PDT 24
Finished Aug 03 06:36:42 PM PDT 24
Peak memory 242344 kb
Host smart-daf42c6f-4878-4006-b741-cd8a74da2f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676220291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.3676220291
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.3729840265
Short name T26
Test name
Test status
Simulation time 194076880 ps
CPU time 4.27 seconds
Started Aug 03 06:36:15 PM PDT 24
Finished Aug 03 06:36:20 PM PDT 24
Peak memory 242096 kb
Host smart-e8c279d2-767d-4410-a7de-45ecd9b64865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729840265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3729840265
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.1110966497
Short name T602
Test name
Test status
Simulation time 265608843 ps
CPU time 6.06 seconds
Started Aug 03 06:36:28 PM PDT 24
Finished Aug 03 06:36:34 PM PDT 24
Peak memory 242068 kb
Host smart-615a9575-f154-4042-b1bb-a27be1e490ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110966497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1110966497
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.3092322403
Short name T1061
Test name
Test status
Simulation time 852983871 ps
CPU time 19.93 seconds
Started Aug 03 06:36:21 PM PDT 24
Finished Aug 03 06:36:41 PM PDT 24
Peak memory 242488 kb
Host smart-09d1a8ac-c311-4b69-8dd3-96d6d655617c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092322403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.3092322403
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.644246435
Short name T850
Test name
Test status
Simulation time 350655810 ps
CPU time 6.37 seconds
Started Aug 03 06:36:15 PM PDT 24
Finished Aug 03 06:36:21 PM PDT 24
Peak memory 241788 kb
Host smart-e8b54842-8b42-4570-b455-014f2c1fcd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644246435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.644246435
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.3722696259
Short name T931
Test name
Test status
Simulation time 486040157 ps
CPU time 10.83 seconds
Started Aug 03 06:36:16 PM PDT 24
Finished Aug 03 06:36:27 PM PDT 24
Peak memory 248560 kb
Host smart-7e25f1ac-0c36-4856-9fb3-5e673bef8ca6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3722696259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.3722696259
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.1735014328
Short name T914
Test name
Test status
Simulation time 160414424 ps
CPU time 4.8 seconds
Started Aug 03 06:36:23 PM PDT 24
Finished Aug 03 06:36:28 PM PDT 24
Peak memory 242020 kb
Host smart-60ae0aca-3720-4acd-9849-11ed5c321074
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1735014328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.1735014328
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.1880308799
Short name T408
Test name
Test status
Simulation time 719111323 ps
CPU time 7.54 seconds
Started Aug 03 06:36:18 PM PDT 24
Finished Aug 03 06:36:26 PM PDT 24
Peak memory 242348 kb
Host smart-6d42d5e9-ef10-49b8-ba83-2e602c20d1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880308799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.1880308799
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.1701304664
Short name T256
Test name
Test status
Simulation time 7945101994 ps
CPU time 92.42 seconds
Started Aug 03 06:36:22 PM PDT 24
Finished Aug 03 06:37:55 PM PDT 24
Peak memory 244684 kb
Host smart-5ec18555-d919-414f-803f-fad42ba4ecc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701304664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.1701304664
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.2932232002
Short name T521
Test name
Test status
Simulation time 185272105568 ps
CPU time 968.71 seconds
Started Aug 03 06:36:28 PM PDT 24
Finished Aug 03 06:52:37 PM PDT 24
Peak memory 357516 kb
Host smart-a5e4595d-998e-400e-91ab-cf5945a47c85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932232002 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.2932232002
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.1999530006
Short name T790
Test name
Test status
Simulation time 182499487 ps
CPU time 6.26 seconds
Started Aug 03 06:36:22 PM PDT 24
Finished Aug 03 06:36:28 PM PDT 24
Peak memory 242092 kb
Host smart-e74e11f8-17d2-4776-a5e1-09dc6da3d8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999530006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.1999530006
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.72859796
Short name T1115
Test name
Test status
Simulation time 598415971 ps
CPU time 4.31 seconds
Started Aug 03 06:52:32 PM PDT 24
Finished Aug 03 06:52:36 PM PDT 24
Peak memory 242304 kb
Host smart-b1b4aeb2-b385-4c5a-b7d7-aff7870d21bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72859796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.72859796
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.3945825625
Short name T416
Test name
Test status
Simulation time 118189658 ps
CPU time 4.2 seconds
Started Aug 03 06:52:43 PM PDT 24
Finished Aug 03 06:52:48 PM PDT 24
Peak memory 242148 kb
Host smart-3e9276d4-3cd3-4a4d-b548-9eced7f786ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945825625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3945825625
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.2980696799
Short name T691
Test name
Test status
Simulation time 376254330 ps
CPU time 6.24 seconds
Started Aug 03 06:52:47 PM PDT 24
Finished Aug 03 06:52:53 PM PDT 24
Peak memory 242312 kb
Host smart-caf100a1-4b20-4fcf-aa38-998d187b4781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980696799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.2980696799
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.3383107772
Short name T695
Test name
Test status
Simulation time 143851505 ps
CPU time 4.05 seconds
Started Aug 03 06:52:48 PM PDT 24
Finished Aug 03 06:52:52 PM PDT 24
Peak memory 241968 kb
Host smart-41e57859-f832-4456-9b7d-30b6e070bd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383107772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.3383107772
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.1298310714
Short name T739
Test name
Test status
Simulation time 566126090 ps
CPU time 8.15 seconds
Started Aug 03 06:52:54 PM PDT 24
Finished Aug 03 06:53:02 PM PDT 24
Peak memory 241928 kb
Host smart-4d1510ba-cce5-4f65-92bf-7a2e293fe9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298310714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.1298310714
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.639650343
Short name T223
Test name
Test status
Simulation time 145336319 ps
CPU time 3.43 seconds
Started Aug 03 06:52:52 PM PDT 24
Finished Aug 03 06:52:56 PM PDT 24
Peak memory 242036 kb
Host smart-5111c80f-2a0f-4b78-a10a-787724da4d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639650343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.639650343
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.1741030501
Short name T140
Test name
Test status
Simulation time 259684356 ps
CPU time 11.4 seconds
Started Aug 03 06:53:04 PM PDT 24
Finished Aug 03 06:53:16 PM PDT 24
Peak memory 242176 kb
Host smart-525cf8a7-e419-4c8d-b84f-50127a3dcd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741030501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1741030501
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.2355572218
Short name T1014
Test name
Test status
Simulation time 2497235488 ps
CPU time 5.82 seconds
Started Aug 03 06:53:05 PM PDT 24
Finished Aug 03 06:53:11 PM PDT 24
Peak memory 242044 kb
Host smart-69eedbef-ff68-49c5-800a-bf43b2af91c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355572218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.2355572218
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.1851578020
Short name T994
Test name
Test status
Simulation time 221921921 ps
CPU time 10.26 seconds
Started Aug 03 06:53:13 PM PDT 24
Finished Aug 03 06:53:24 PM PDT 24
Peak memory 242100 kb
Host smart-38564879-2538-41be-94e6-4f0f47784d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851578020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.1851578020
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.211906895
Short name T1032
Test name
Test status
Simulation time 110143643 ps
CPU time 3.5 seconds
Started Aug 03 06:53:14 PM PDT 24
Finished Aug 03 06:53:18 PM PDT 24
Peak memory 242256 kb
Host smart-baf93054-6e29-426d-bd8c-9a77a475b3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211906895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.211906895
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.115837664
Short name T427
Test name
Test status
Simulation time 101713224 ps
CPU time 3.71 seconds
Started Aug 03 06:53:19 PM PDT 24
Finished Aug 03 06:53:23 PM PDT 24
Peak memory 242456 kb
Host smart-65c1850f-f4db-41d1-9c9b-30bcf75b2913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115837664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.115837664
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.1552211460
Short name T433
Test name
Test status
Simulation time 197055543 ps
CPU time 4.24 seconds
Started Aug 03 06:53:24 PM PDT 24
Finished Aug 03 06:53:28 PM PDT 24
Peak memory 242408 kb
Host smart-fe35a3f6-aa33-4db5-8085-50eae060c720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552211460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1552211460
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.695922196
Short name T174
Test name
Test status
Simulation time 641030342 ps
CPU time 5.67 seconds
Started Aug 03 06:53:22 PM PDT 24
Finished Aug 03 06:53:28 PM PDT 24
Peak memory 241864 kb
Host smart-1557ddd0-a434-4a51-bff3-f00b6630a63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695922196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.695922196
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.3332890967
Short name T71
Test name
Test status
Simulation time 1552603671 ps
CPU time 6.16 seconds
Started Aug 03 06:53:28 PM PDT 24
Finished Aug 03 06:53:34 PM PDT 24
Peak memory 242148 kb
Host smart-6c69b4b5-4f1f-45fd-8779-4380c5a67b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332890967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.3332890967
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.2320184861
Short name T796
Test name
Test status
Simulation time 267723382 ps
CPU time 10.93 seconds
Started Aug 03 06:53:29 PM PDT 24
Finished Aug 03 06:53:40 PM PDT 24
Peak memory 241892 kb
Host smart-f905e218-bec4-4638-be15-df68d1f422ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320184861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.2320184861
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.732076487
Short name T431
Test name
Test status
Simulation time 611154996 ps
CPU time 3.81 seconds
Started Aug 03 06:53:34 PM PDT 24
Finished Aug 03 06:53:38 PM PDT 24
Peak memory 242060 kb
Host smart-68226bc6-1621-47dc-9232-ac677e6faa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732076487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.732076487
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.3311378740
Short name T406
Test name
Test status
Simulation time 307879484 ps
CPU time 8.76 seconds
Started Aug 03 06:53:38 PM PDT 24
Finished Aug 03 06:53:47 PM PDT 24
Peak memory 241692 kb
Host smart-2f345088-fcf6-4722-86d3-01a2afcf52c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311378740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3311378740
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.1421238492
Short name T524
Test name
Test status
Simulation time 149753060 ps
CPU time 4.16 seconds
Started Aug 03 06:53:48 PM PDT 24
Finished Aug 03 06:53:52 PM PDT 24
Peak memory 242248 kb
Host smart-6c2caceb-b7e8-49aa-82d3-e82d121310f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421238492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.1421238492
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.1538977826
Short name T353
Test name
Test status
Simulation time 3520062189 ps
CPU time 14.28 seconds
Started Aug 03 06:53:52 PM PDT 24
Finished Aug 03 06:54:06 PM PDT 24
Peak memory 241940 kb
Host smart-322bc321-2859-4a62-a0ac-4d3c0ddcd956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538977826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.1538977826
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.1958569487
Short name T991
Test name
Test status
Simulation time 907808888 ps
CPU time 2.12 seconds
Started Aug 03 06:36:31 PM PDT 24
Finished Aug 03 06:36:33 PM PDT 24
Peak memory 240580 kb
Host smart-8f7aa5ae-baaf-4544-9c28-3b2e0e183a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958569487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.1958569487
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.1055562818
Short name T827
Test name
Test status
Simulation time 664569575 ps
CPU time 13.12 seconds
Started Aug 03 06:36:25 PM PDT 24
Finished Aug 03 06:36:38 PM PDT 24
Peak memory 242084 kb
Host smart-40ee3baa-c815-4e00-bf90-c36eeaf09c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055562818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.1055562818
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.1204430883
Short name T356
Test name
Test status
Simulation time 1046417415 ps
CPU time 31.17 seconds
Started Aug 03 06:36:27 PM PDT 24
Finished Aug 03 06:36:59 PM PDT 24
Peak memory 242184 kb
Host smart-6fb02eeb-51c9-49d7-a595-d489e2ef53ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204430883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1204430883
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.3785182397
Short name T289
Test name
Test status
Simulation time 642138052 ps
CPU time 9.22 seconds
Started Aug 03 06:36:28 PM PDT 24
Finished Aug 03 06:36:37 PM PDT 24
Peak memory 242180 kb
Host smart-7f00dfa3-9839-46d5-a151-cfb81dd74f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785182397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.3785182397
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.395190552
Short name T888
Test name
Test status
Simulation time 272727185 ps
CPU time 4.21 seconds
Started Aug 03 06:36:26 PM PDT 24
Finished Aug 03 06:36:31 PM PDT 24
Peak memory 242004 kb
Host smart-4e2f0359-a02a-4dea-af8b-e030df65059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395190552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.395190552
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.3517295523
Short name T205
Test name
Test status
Simulation time 1556339263 ps
CPU time 17.24 seconds
Started Aug 03 06:36:26 PM PDT 24
Finished Aug 03 06:36:43 PM PDT 24
Peak memory 244832 kb
Host smart-b3221222-3872-4167-888b-d3435186c23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517295523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.3517295523
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.2213937360
Short name T720
Test name
Test status
Simulation time 216100078 ps
CPU time 3.67 seconds
Started Aug 03 06:36:28 PM PDT 24
Finished Aug 03 06:36:32 PM PDT 24
Peak memory 248676 kb
Host smart-8ac470ca-82c4-47f4-b9d3-c34d768cebd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213937360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2213937360
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.2460669035
Short name T942
Test name
Test status
Simulation time 237268339 ps
CPU time 5.4 seconds
Started Aug 03 06:36:30 PM PDT 24
Finished Aug 03 06:36:35 PM PDT 24
Peak memory 241712 kb
Host smart-95748702-fcae-44b0-9877-2c5785463996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460669035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.2460669035
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.921315948
Short name T610
Test name
Test status
Simulation time 7444834529 ps
CPU time 17.25 seconds
Started Aug 03 06:36:28 PM PDT 24
Finished Aug 03 06:36:46 PM PDT 24
Peak memory 241988 kb
Host smart-c6502018-2dbe-4645-9ff1-7d34cf36b2c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=921315948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.921315948
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.963277928
Short name T219
Test name
Test status
Simulation time 4469542525 ps
CPU time 16.13 seconds
Started Aug 03 06:36:30 PM PDT 24
Finished Aug 03 06:36:46 PM PDT 24
Peak memory 242092 kb
Host smart-cc0dfd28-a45f-49be-8bcd-3f9d0cb609b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963277928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.963277928
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.2248454414
Short name T648
Test name
Test status
Simulation time 24301029587 ps
CPU time 142.92 seconds
Started Aug 03 06:36:31 PM PDT 24
Finished Aug 03 06:38:54 PM PDT 24
Peak memory 248868 kb
Host smart-86cd7195-8bfa-46ad-922f-21bfb1fada45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248454414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.2248454414
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.2406291645
Short name T20
Test name
Test status
Simulation time 101268904919 ps
CPU time 535.1 seconds
Started Aug 03 06:36:35 PM PDT 24
Finished Aug 03 06:45:30 PM PDT 24
Peak memory 277464 kb
Host smart-599205fd-faaf-44a8-81ca-ab155d015e8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406291645 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.2406291645
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.2448844461
Short name T98
Test name
Test status
Simulation time 1789967097 ps
CPU time 12.98 seconds
Started Aug 03 06:36:30 PM PDT 24
Finished Aug 03 06:36:43 PM PDT 24
Peak memory 242372 kb
Host smart-ce90574e-0f84-40e9-9d78-38e8f2c9b198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448844461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.2448844461
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.2556569633
Short name T872
Test name
Test status
Simulation time 331606645 ps
CPU time 4.11 seconds
Started Aug 03 06:53:52 PM PDT 24
Finished Aug 03 06:53:56 PM PDT 24
Peak memory 242200 kb
Host smart-760dcaed-c8f8-4cd8-b8da-d2464f3cc829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556569633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2556569633
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.2222937973
Short name T264
Test name
Test status
Simulation time 640946978 ps
CPU time 18.42 seconds
Started Aug 03 06:54:00 PM PDT 24
Finished Aug 03 06:54:18 PM PDT 24
Peak memory 241892 kb
Host smart-79a79f8b-e9fb-4d66-8dc1-6a3577f8d134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222937973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.2222937973
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.706873472
Short name T483
Test name
Test status
Simulation time 99804350 ps
CPU time 3.58 seconds
Started Aug 03 06:54:02 PM PDT 24
Finished Aug 03 06:54:05 PM PDT 24
Peak memory 241968 kb
Host smart-fe7b01da-71fa-43f5-8325-d8bfdcb176c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706873472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.706873472
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.3265052006
Short name T244
Test name
Test status
Simulation time 887369740 ps
CPU time 15.4 seconds
Started Aug 03 06:54:03 PM PDT 24
Finished Aug 03 06:54:18 PM PDT 24
Peak memory 241964 kb
Host smart-bb84dca8-04ca-459c-9a25-11c04d1e1cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265052006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.3265052006
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.2900616405
Short name T944
Test name
Test status
Simulation time 359093995 ps
CPU time 4.17 seconds
Started Aug 03 06:54:02 PM PDT 24
Finished Aug 03 06:54:07 PM PDT 24
Peak memory 242208 kb
Host smart-4b702af5-39c8-4549-a13e-4c09259a7f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900616405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.2900616405
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.124111778
Short name T1187
Test name
Test status
Simulation time 1172551281 ps
CPU time 14.44 seconds
Started Aug 03 06:54:10 PM PDT 24
Finished Aug 03 06:54:24 PM PDT 24
Peak memory 241908 kb
Host smart-7eb8c33d-690b-4f7b-8879-4cd404c5d9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124111778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.124111778
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.707590621
Short name T494
Test name
Test status
Simulation time 231123564 ps
CPU time 3.46 seconds
Started Aug 03 06:54:09 PM PDT 24
Finished Aug 03 06:54:13 PM PDT 24
Peak memory 242052 kb
Host smart-d765adb1-16f3-488b-8cd8-d83840c475cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707590621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.707590621
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.1448173129
Short name T375
Test name
Test status
Simulation time 15081803701 ps
CPU time 49.88 seconds
Started Aug 03 06:54:15 PM PDT 24
Finished Aug 03 06:55:05 PM PDT 24
Peak memory 242348 kb
Host smart-e2c5b3e1-1c2e-43c7-bd91-7cb01d969296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448173129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.1448173129
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.2141166741
Short name T958
Test name
Test status
Simulation time 226532109 ps
CPU time 3.98 seconds
Started Aug 03 06:54:13 PM PDT 24
Finished Aug 03 06:54:17 PM PDT 24
Peak memory 241916 kb
Host smart-a3e2527f-6dfa-4c57-a815-0f060bd61d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141166741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.2141166741
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.2746779067
Short name T786
Test name
Test status
Simulation time 161778232 ps
CPU time 4.12 seconds
Started Aug 03 06:54:18 PM PDT 24
Finished Aug 03 06:54:22 PM PDT 24
Peak memory 242280 kb
Host smart-1942cc69-7976-41ec-8547-145758bc0f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746779067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.2746779067
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.2386270664
Short name T168
Test name
Test status
Simulation time 420144396 ps
CPU time 10.01 seconds
Started Aug 03 06:54:25 PM PDT 24
Finished Aug 03 06:54:35 PM PDT 24
Peak memory 242108 kb
Host smart-5c73ed20-0767-4831-9836-65d6804e3398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386270664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.2386270664
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.2545686750
Short name T40
Test name
Test status
Simulation time 137460686 ps
CPU time 4.22 seconds
Started Aug 03 06:54:25 PM PDT 24
Finished Aug 03 06:54:29 PM PDT 24
Peak memory 242140 kb
Host smart-8751624d-f8fd-445a-a017-7afffebe3ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545686750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.2545686750
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.443771311
Short name T1092
Test name
Test status
Simulation time 280455979 ps
CPU time 6 seconds
Started Aug 03 06:54:34 PM PDT 24
Finished Aug 03 06:54:40 PM PDT 24
Peak memory 242040 kb
Host smart-2a8796fd-267e-4d17-8d04-d546e4efef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443771311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.443771311
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.621077883
Short name T705
Test name
Test status
Simulation time 1644401778 ps
CPU time 4.11 seconds
Started Aug 03 06:54:32 PM PDT 24
Finished Aug 03 06:54:36 PM PDT 24
Peak memory 242152 kb
Host smart-9e278e5d-1523-4891-9212-fd27dd46a71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621077883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.621077883
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.3911306526
Short name T617
Test name
Test status
Simulation time 306931189 ps
CPU time 16.26 seconds
Started Aug 03 06:54:45 PM PDT 24
Finished Aug 03 06:55:01 PM PDT 24
Peak memory 242056 kb
Host smart-059c8c0e-3e3a-4113-a325-2436feb8ec96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911306526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3911306526
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.3462500886
Short name T976
Test name
Test status
Simulation time 199765326 ps
CPU time 4.71 seconds
Started Aug 03 06:54:44 PM PDT 24
Finished Aug 03 06:54:49 PM PDT 24
Peak memory 242036 kb
Host smart-8e355064-022a-4b03-bf09-b464ab012cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462500886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.3462500886
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.2957051279
Short name T352
Test name
Test status
Simulation time 2512717065 ps
CPU time 21.83 seconds
Started Aug 03 06:54:43 PM PDT 24
Finished Aug 03 06:55:05 PM PDT 24
Peak memory 242236 kb
Host smart-57a5868a-0d4a-47d0-a82c-d5813707788e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957051279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2957051279
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.1509084769
Short name T669
Test name
Test status
Simulation time 98135382 ps
CPU time 3.42 seconds
Started Aug 03 06:54:49 PM PDT 24
Finished Aug 03 06:54:53 PM PDT 24
Peak memory 242128 kb
Host smart-e4bf56b7-229b-454e-916c-89d88f858e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509084769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.1509084769
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.843961510
Short name T351
Test name
Test status
Simulation time 192817755 ps
CPU time 4.83 seconds
Started Aug 03 06:54:53 PM PDT 24
Finished Aug 03 06:54:58 PM PDT 24
Peak memory 242164 kb
Host smart-93ec03c5-4d79-4bf0-a262-e4bdeb3c27f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843961510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.843961510
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.1978870140
Short name T1178
Test name
Test status
Simulation time 843050840 ps
CPU time 2.25 seconds
Started Aug 03 06:36:45 PM PDT 24
Finished Aug 03 06:36:47 PM PDT 24
Peak memory 240460 kb
Host smart-c64d1539-d02f-43f8-8468-cae76444ab2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978870140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1978870140
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.2653336326
Short name T1008
Test name
Test status
Simulation time 389329492 ps
CPU time 11.9 seconds
Started Aug 03 06:36:37 PM PDT 24
Finished Aug 03 06:36:49 PM PDT 24
Peak memory 241936 kb
Host smart-a3ad14eb-b226-4eec-875c-1063550618fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653336326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.2653336326
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.574882767
Short name T754
Test name
Test status
Simulation time 492354035 ps
CPU time 10.17 seconds
Started Aug 03 06:36:37 PM PDT 24
Finished Aug 03 06:36:47 PM PDT 24
Peak memory 242012 kb
Host smart-ef97993f-afe0-4d55-a351-450e494af5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574882767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.574882767
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.98458851
Short name T1105
Test name
Test status
Simulation time 177812788 ps
CPU time 3.3 seconds
Started Aug 03 06:36:36 PM PDT 24
Finished Aug 03 06:36:39 PM PDT 24
Peak memory 241976 kb
Host smart-e88ab16a-fecf-4d89-9b90-204e14ecb7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98458851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.98458851
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.4143996957
Short name T1183
Test name
Test status
Simulation time 427854692 ps
CPU time 9.52 seconds
Started Aug 03 06:36:38 PM PDT 24
Finished Aug 03 06:36:48 PM PDT 24
Peak memory 243648 kb
Host smart-838753d2-ce91-4268-adeb-6202e16da733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143996957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.4143996957
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.1127211047
Short name T628
Test name
Test status
Simulation time 642856571 ps
CPU time 15.01 seconds
Started Aug 03 06:36:36 PM PDT 24
Finished Aug 03 06:36:51 PM PDT 24
Peak memory 242048 kb
Host smart-409ee9a7-7909-40cf-9c23-1cf8d1d9f1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127211047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.1127211047
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.527948724
Short name T541
Test name
Test status
Simulation time 125717388 ps
CPU time 3.99 seconds
Started Aug 03 06:36:37 PM PDT 24
Finished Aug 03 06:36:41 PM PDT 24
Peak memory 241792 kb
Host smart-a2406bac-0933-4e40-a969-871560e2be92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527948724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.527948724
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.3083605721
Short name T441
Test name
Test status
Simulation time 430379723 ps
CPU time 7.6 seconds
Started Aug 03 06:36:36 PM PDT 24
Finished Aug 03 06:36:44 PM PDT 24
Peak memory 248540 kb
Host smart-33718fa8-32bd-48fb-83a0-aa65fa1fc934
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3083605721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.3083605721
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.3494716238
Short name T1090
Test name
Test status
Simulation time 2755841230 ps
CPU time 7.8 seconds
Started Aug 03 06:36:41 PM PDT 24
Finished Aug 03 06:36:49 PM PDT 24
Peak memory 241924 kb
Host smart-25bb534e-011b-4af1-92f0-0f7d87e241c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494716238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.3494716238
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.2660792054
Short name T621
Test name
Test status
Simulation time 3292031171 ps
CPU time 14.93 seconds
Started Aug 03 06:36:32 PM PDT 24
Finished Aug 03 06:36:47 PM PDT 24
Peak memory 242332 kb
Host smart-6e861446-f081-4ccd-ad21-31011f2ce92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660792054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2660792054
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.38692388
Short name T301
Test name
Test status
Simulation time 32773617142 ps
CPU time 63.71 seconds
Started Aug 03 06:36:44 PM PDT 24
Finished Aug 03 06:37:48 PM PDT 24
Peak memory 244296 kb
Host smart-fd8cea3a-da0a-4645-b2c9-521cb7e938f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38692388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.38692388
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.4078531405
Short name T891
Test name
Test status
Simulation time 75337545133 ps
CPU time 443.18 seconds
Started Aug 03 06:36:46 PM PDT 24
Finished Aug 03 06:44:09 PM PDT 24
Peak memory 257184 kb
Host smart-948a4503-77b3-4a8c-b90f-96517feedca5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078531405 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.4078531405
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.1256335242
Short name T588
Test name
Test status
Simulation time 630650990 ps
CPU time 11.83 seconds
Started Aug 03 06:36:41 PM PDT 24
Finished Aug 03 06:36:53 PM PDT 24
Peak memory 241992 kb
Host smart-a8a6f847-559d-47df-b62f-b3190358a171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256335242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1256335242
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.3160315217
Short name T1121
Test name
Test status
Simulation time 195643734 ps
CPU time 4.66 seconds
Started Aug 03 06:54:54 PM PDT 24
Finished Aug 03 06:54:58 PM PDT 24
Peak memory 242032 kb
Host smart-e0c788df-99a6-45ae-8d2a-db2aae27a246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160315217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.3160315217
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.3890415650
Short name T343
Test name
Test status
Simulation time 499881386 ps
CPU time 11.3 seconds
Started Aug 03 06:54:55 PM PDT 24
Finished Aug 03 06:55:06 PM PDT 24
Peak memory 242020 kb
Host smart-6ddd681f-59f4-4b6b-b19f-9ad1204bbec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890415650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.3890415650
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.2001646163
Short name T611
Test name
Test status
Simulation time 203560071 ps
CPU time 3.5 seconds
Started Aug 03 06:54:54 PM PDT 24
Finished Aug 03 06:54:57 PM PDT 24
Peak memory 242104 kb
Host smart-6af85b24-6361-4e1e-b707-d76ec3cbf398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001646163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2001646163
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.142084709
Short name T243
Test name
Test status
Simulation time 18708636891 ps
CPU time 43.45 seconds
Started Aug 03 06:54:54 PM PDT 24
Finished Aug 03 06:55:37 PM PDT 24
Peak memory 242864 kb
Host smart-352aa7e8-ceb9-4327-a265-394722191ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142084709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.142084709
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.1380443903
Short name T457
Test name
Test status
Simulation time 100226766 ps
CPU time 3.62 seconds
Started Aug 03 06:55:02 PM PDT 24
Finished Aug 03 06:55:06 PM PDT 24
Peak memory 242148 kb
Host smart-eb28131d-d50e-4a11-adfa-ce8b451a7cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380443903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.1380443903
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.2964541016
Short name T638
Test name
Test status
Simulation time 793751148 ps
CPU time 8.85 seconds
Started Aug 03 06:55:03 PM PDT 24
Finished Aug 03 06:55:12 PM PDT 24
Peak memory 242020 kb
Host smart-b97c8d59-4324-432d-898b-362a7353ad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964541016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.2964541016
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.748731235
Short name T92
Test name
Test status
Simulation time 239471312 ps
CPU time 2.94 seconds
Started Aug 03 06:55:09 PM PDT 24
Finished Aug 03 06:55:12 PM PDT 24
Peak memory 242412 kb
Host smart-3b3e11f5-b525-4a27-8b03-9d85080c0bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748731235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.748731235
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.2967454012
Short name T882
Test name
Test status
Simulation time 588184726 ps
CPU time 13.8 seconds
Started Aug 03 06:55:09 PM PDT 24
Finished Aug 03 06:55:23 PM PDT 24
Peak memory 241960 kb
Host smart-390424e0-8824-463d-adc6-dc889a1464a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967454012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.2967454012
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.3834219654
Short name T848
Test name
Test status
Simulation time 482626332 ps
CPU time 4.24 seconds
Started Aug 03 06:55:08 PM PDT 24
Finished Aug 03 06:55:13 PM PDT 24
Peak memory 241908 kb
Host smart-6cf18cb3-3bc1-47ed-890c-849d3e13e999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834219654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.3834219654
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.3678489872
Short name T634
Test name
Test status
Simulation time 7259782184 ps
CPU time 20.45 seconds
Started Aug 03 06:55:12 PM PDT 24
Finished Aug 03 06:55:33 PM PDT 24
Peak memory 242028 kb
Host smart-01a43518-b0f1-4f57-94a0-a94818ef7499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678489872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.3678489872
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.1077121463
Short name T1011
Test name
Test status
Simulation time 2692124218 ps
CPU time 4.97 seconds
Started Aug 03 06:55:20 PM PDT 24
Finished Aug 03 06:55:25 PM PDT 24
Peak memory 242276 kb
Host smart-7be6e726-08b5-41d2-b9be-475c91e7ac82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077121463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.1077121463
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.1529947243
Short name T428
Test name
Test status
Simulation time 254802426 ps
CPU time 6.27 seconds
Started Aug 03 06:55:31 PM PDT 24
Finished Aug 03 06:55:38 PM PDT 24
Peak memory 241724 kb
Host smart-cbeab760-dd5f-4109-8e94-899e039cdfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529947243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.1529947243
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.1931693725
Short name T913
Test name
Test status
Simulation time 158122430 ps
CPU time 3.43 seconds
Started Aug 03 06:55:34 PM PDT 24
Finished Aug 03 06:55:38 PM PDT 24
Peak memory 242320 kb
Host smart-da908b7f-9758-41da-ae5a-f1a87bbff98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931693725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.1931693725
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.2084526977
Short name T1068
Test name
Test status
Simulation time 514308262 ps
CPU time 4.34 seconds
Started Aug 03 06:55:35 PM PDT 24
Finished Aug 03 06:55:39 PM PDT 24
Peak memory 241932 kb
Host smart-56222bb0-9348-47f9-bbb8-60f8c98338ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084526977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2084526977
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.1200183634
Short name T633
Test name
Test status
Simulation time 2141811619 ps
CPU time 6.25 seconds
Started Aug 03 06:55:35 PM PDT 24
Finished Aug 03 06:55:41 PM PDT 24
Peak memory 241984 kb
Host smart-d696402a-0027-4d76-9b7a-fc362e5ac753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200183634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.1200183634
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.2855412710
Short name T344
Test name
Test status
Simulation time 193125463 ps
CPU time 5.78 seconds
Started Aug 03 06:55:40 PM PDT 24
Finished Aug 03 06:55:46 PM PDT 24
Peak memory 241892 kb
Host smart-92e3503e-148b-4228-bb85-69f8118b66ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855412710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.2855412710
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.371288907
Short name T503
Test name
Test status
Simulation time 309338532 ps
CPU time 4.13 seconds
Started Aug 03 06:55:40 PM PDT 24
Finished Aug 03 06:55:45 PM PDT 24
Peak memory 241972 kb
Host smart-f0684403-b60a-4a0a-a9c8-65236c0854a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371288907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.371288907
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.2552102735
Short name T1134
Test name
Test status
Simulation time 360413281 ps
CPU time 5.64 seconds
Started Aug 03 06:55:40 PM PDT 24
Finished Aug 03 06:55:46 PM PDT 24
Peak memory 248500 kb
Host smart-3871039d-89c6-439d-a5a6-f4ea70af2bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552102735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2552102735
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.448656041
Short name T615
Test name
Test status
Simulation time 66311247 ps
CPU time 1.87 seconds
Started Aug 03 06:36:52 PM PDT 24
Finished Aug 03 06:36:54 PM PDT 24
Peak memory 240424 kb
Host smart-beab20c9-5a99-4f25-86f2-42214111cd91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448656041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.448656041
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.3652193916
Short name T9
Test name
Test status
Simulation time 9760476923 ps
CPU time 19.7 seconds
Started Aug 03 06:36:46 PM PDT 24
Finished Aug 03 06:37:05 PM PDT 24
Peak memory 243352 kb
Host smart-30012b7d-309a-4357-918a-479f22bb07ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652193916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.3652193916
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.2790049780
Short name T607
Test name
Test status
Simulation time 7766673716 ps
CPU time 17.23 seconds
Started Aug 03 06:36:49 PM PDT 24
Finished Aug 03 06:37:06 PM PDT 24
Peak memory 241808 kb
Host smart-8af9e7e0-f33a-4b72-a389-9c71e1fec202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790049780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.2790049780
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.39313992
Short name T689
Test name
Test status
Simulation time 2261653736 ps
CPU time 24.36 seconds
Started Aug 03 06:36:47 PM PDT 24
Finished Aug 03 06:37:11 PM PDT 24
Peak memory 241968 kb
Host smart-90e5ba02-575a-4309-b8ba-61f3b3b29026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39313992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.39313992
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.1672439199
Short name T1104
Test name
Test status
Simulation time 1213009411 ps
CPU time 15.52 seconds
Started Aug 03 06:36:47 PM PDT 24
Finished Aug 03 06:37:03 PM PDT 24
Peak memory 242252 kb
Host smart-6665c376-f8e0-4d84-96ed-7c204862eb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672439199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.1672439199
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.3630209066
Short name T566
Test name
Test status
Simulation time 3830562410 ps
CPU time 26.91 seconds
Started Aug 03 06:36:48 PM PDT 24
Finished Aug 03 06:37:15 PM PDT 24
Peak memory 242092 kb
Host smart-22c758f4-2200-46eb-8fac-17d5d123250b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630209066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.3630209066
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.1065204788
Short name T769
Test name
Test status
Simulation time 276368833 ps
CPU time 4.19 seconds
Started Aug 03 06:36:47 PM PDT 24
Finished Aug 03 06:36:51 PM PDT 24
Peak memory 241880 kb
Host smart-533bf858-4afc-45aa-85fd-e4e759462729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065204788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1065204788
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.2420894784
Short name T973
Test name
Test status
Simulation time 649034564 ps
CPU time 18.92 seconds
Started Aug 03 06:36:46 PM PDT 24
Finished Aug 03 06:37:06 PM PDT 24
Peak memory 248532 kb
Host smart-1ea8c228-1585-4051-9c9b-b790f6c4fef6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2420894784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.2420894784
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.2940772593
Short name T574
Test name
Test status
Simulation time 315389280 ps
CPU time 9.58 seconds
Started Aug 03 06:36:52 PM PDT 24
Finished Aug 03 06:37:01 PM PDT 24
Peak memory 242076 kb
Host smart-0a430020-8926-4bde-8886-7a305eb07e81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2940772593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.2940772593
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.1422251476
Short name T1070
Test name
Test status
Simulation time 1612174317 ps
CPU time 4.08 seconds
Started Aug 03 06:36:42 PM PDT 24
Finished Aug 03 06:36:46 PM PDT 24
Peak memory 242048 kb
Host smart-9cd7169d-0f19-4932-8e7d-28b9aa927329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422251476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1422251476
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.3262421369
Short name T1174
Test name
Test status
Simulation time 52304012081 ps
CPU time 240.63 seconds
Started Aug 03 06:36:54 PM PDT 24
Finished Aug 03 06:40:55 PM PDT 24
Peak memory 265108 kb
Host smart-e970f822-ab49-4736-a011-d733a35c359d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262421369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.3262421369
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.3533707571
Short name T693
Test name
Test status
Simulation time 534052103518 ps
CPU time 1301.43 seconds
Started Aug 03 06:36:54 PM PDT 24
Finished Aug 03 06:58:36 PM PDT 24
Peak memory 272036 kb
Host smart-1523ea7c-fccc-4623-97ca-17f2fe8396f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533707571 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.3533707571
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.2864885459
Short name T96
Test name
Test status
Simulation time 577903867 ps
CPU time 11.45 seconds
Started Aug 03 06:36:51 PM PDT 24
Finished Aug 03 06:37:03 PM PDT 24
Peak memory 242296 kb
Host smart-763c7692-8851-4cde-9bcd-089858d17eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864885459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.2864885459
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.3630302240
Short name T1185
Test name
Test status
Simulation time 1885103794 ps
CPU time 4.76 seconds
Started Aug 03 06:55:46 PM PDT 24
Finished Aug 03 06:55:51 PM PDT 24
Peak memory 241852 kb
Host smart-d9246c28-98fb-4125-9942-8495efae7e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630302240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3630302240
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.3523632678
Short name T554
Test name
Test status
Simulation time 1646510794 ps
CPU time 4.03 seconds
Started Aug 03 06:55:45 PM PDT 24
Finished Aug 03 06:55:49 PM PDT 24
Peak memory 242248 kb
Host smart-cc313ade-c201-43ea-8b41-8e4dc5283a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523632678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.3523632678
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.2155732330
Short name T668
Test name
Test status
Simulation time 231381200 ps
CPU time 5.43 seconds
Started Aug 03 06:55:53 PM PDT 24
Finished Aug 03 06:55:58 PM PDT 24
Peak memory 241904 kb
Host smart-6d2362d1-3d97-4a21-aacf-fea93cbecf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155732330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.2155732330
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.1208578020
Short name T1033
Test name
Test status
Simulation time 283441762 ps
CPU time 3.57 seconds
Started Aug 03 06:55:58 PM PDT 24
Finished Aug 03 06:56:01 PM PDT 24
Peak memory 242380 kb
Host smart-c175e0f6-c07f-4bc6-841b-c7dbe4072527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208578020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.1208578020
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.2500915507
Short name T1012
Test name
Test status
Simulation time 416890998 ps
CPU time 4.8 seconds
Started Aug 03 06:55:57 PM PDT 24
Finished Aug 03 06:56:02 PM PDT 24
Peak memory 242232 kb
Host smart-50d4f34a-9c21-4555-aa79-8efe6845f471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500915507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.2500915507
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.2216328863
Short name T420
Test name
Test status
Simulation time 1961930575 ps
CPU time 3.89 seconds
Started Aug 03 06:56:04 PM PDT 24
Finished Aug 03 06:56:08 PM PDT 24
Peak memory 242220 kb
Host smart-f89e8eee-11f8-472a-8e91-9329fcca02ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216328863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.2216328863
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.960589745
Short name T144
Test name
Test status
Simulation time 910749094 ps
CPU time 13.52 seconds
Started Aug 03 06:56:05 PM PDT 24
Finished Aug 03 06:56:18 PM PDT 24
Peak memory 242132 kb
Host smart-d491d8a3-4913-4242-aa9e-0e4546b44d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960589745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.960589745
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.752324442
Short name T193
Test name
Test status
Simulation time 301645908 ps
CPU time 4.48 seconds
Started Aug 03 06:56:16 PM PDT 24
Finished Aug 03 06:56:20 PM PDT 24
Peak memory 242200 kb
Host smart-049cf94b-033a-4eb7-a483-ee5f696ec227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752324442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.752324442
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.2435271784
Short name T751
Test name
Test status
Simulation time 3526717542 ps
CPU time 22.82 seconds
Started Aug 03 06:56:15 PM PDT 24
Finished Aug 03 06:56:38 PM PDT 24
Peak memory 241932 kb
Host smart-c25d054a-e2ff-4792-a724-9b405029ca34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435271784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2435271784
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.1161415074
Short name T1063
Test name
Test status
Simulation time 403088370 ps
CPU time 8.75 seconds
Started Aug 03 06:56:13 PM PDT 24
Finished Aug 03 06:56:22 PM PDT 24
Peak memory 241748 kb
Host smart-ba22562b-180b-4544-95d8-387c460b87fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161415074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.1161415074
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.1081116806
Short name T899
Test name
Test status
Simulation time 130680966 ps
CPU time 3.56 seconds
Started Aug 03 06:56:15 PM PDT 24
Finished Aug 03 06:56:18 PM PDT 24
Peak memory 242064 kb
Host smart-4571f6ee-97c7-430f-863d-bfab49fb28a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081116806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.1081116806
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.3266793937
Short name T454
Test name
Test status
Simulation time 246167948 ps
CPU time 4.21 seconds
Started Aug 03 06:56:15 PM PDT 24
Finished Aug 03 06:56:19 PM PDT 24
Peak memory 242288 kb
Host smart-ca2df875-99c3-4e86-b74e-065e9b64d627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266793937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.3266793937
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.3151048869
Short name T966
Test name
Test status
Simulation time 708209087 ps
CPU time 9.02 seconds
Started Aug 03 06:56:19 PM PDT 24
Finished Aug 03 06:56:28 PM PDT 24
Peak memory 242232 kb
Host smart-471f41af-9ea1-4e98-8bb0-dc70011b2bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151048869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.3151048869
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.2762062146
Short name T187
Test name
Test status
Simulation time 1691740164 ps
CPU time 4.67 seconds
Started Aug 03 06:56:20 PM PDT 24
Finished Aug 03 06:56:25 PM PDT 24
Peak memory 241976 kb
Host smart-3ad9a1f8-20ae-4eeb-abbb-1f4702b52e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762062146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2762062146
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.2305923624
Short name T825
Test name
Test status
Simulation time 1931402751 ps
CPU time 17.14 seconds
Started Aug 03 06:56:20 PM PDT 24
Finished Aug 03 06:56:37 PM PDT 24
Peak memory 242312 kb
Host smart-2a50c839-43fe-439a-b9df-833df491a1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305923624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2305923624
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.90860612
Short name T876
Test name
Test status
Simulation time 140170491 ps
CPU time 4.73 seconds
Started Aug 03 06:56:21 PM PDT 24
Finished Aug 03 06:56:25 PM PDT 24
Peak memory 242124 kb
Host smart-fd131c20-653b-4e7a-aaea-b2cd668acb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90860612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.90860612
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.3909794562
Short name T1025
Test name
Test status
Simulation time 323085343 ps
CPU time 4.42 seconds
Started Aug 03 06:56:24 PM PDT 24
Finished Aug 03 06:56:29 PM PDT 24
Peak memory 242296 kb
Host smart-e1bda2fe-c56c-40eb-b0ea-71ec6d4bbf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909794562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.3909794562
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.3178053926
Short name T898
Test name
Test status
Simulation time 51450466 ps
CPU time 1.73 seconds
Started Aug 03 06:37:07 PM PDT 24
Finished Aug 03 06:37:09 PM PDT 24
Peak memory 240420 kb
Host smart-1249bf3e-ed2b-499f-acda-01d0d9fd5c41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178053926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.3178053926
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.475390709
Short name T58
Test name
Test status
Simulation time 528724587 ps
CPU time 7.45 seconds
Started Aug 03 06:36:56 PM PDT 24
Finished Aug 03 06:37:03 PM PDT 24
Peak memory 242120 kb
Host smart-201b67bc-620d-4367-a00e-c17a03b2bf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475390709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.475390709
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.471328823
Short name T520
Test name
Test status
Simulation time 1494784598 ps
CPU time 32.6 seconds
Started Aug 03 06:36:55 PM PDT 24
Finished Aug 03 06:37:28 PM PDT 24
Peak memory 243796 kb
Host smart-5f8184fd-ed3d-48ae-bf32-3d9f0bc13f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471328823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.471328823
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.3199724056
Short name T783
Test name
Test status
Simulation time 2071405039 ps
CPU time 5.81 seconds
Started Aug 03 06:36:58 PM PDT 24
Finished Aug 03 06:37:04 PM PDT 24
Peak memory 242216 kb
Host smart-c3c90b2b-0251-4902-9c13-98ec02b5a1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199724056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.3199724056
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.2681672840
Short name T1048
Test name
Test status
Simulation time 1541079762 ps
CPU time 6.33 seconds
Started Aug 03 06:36:58 PM PDT 24
Finished Aug 03 06:37:05 PM PDT 24
Peak memory 242064 kb
Host smart-ac3e1291-c65a-453f-bfa5-0593bdf85aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681672840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.2681672840
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.1178729087
Short name T199
Test name
Test status
Simulation time 572092848 ps
CPU time 19.65 seconds
Started Aug 03 06:36:59 PM PDT 24
Finished Aug 03 06:37:19 PM PDT 24
Peak memory 242076 kb
Host smart-0544b5de-a975-4908-979f-8b97c1b3d6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178729087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.1178729087
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.1894134065
Short name T1184
Test name
Test status
Simulation time 683920338 ps
CPU time 15.96 seconds
Started Aug 03 06:36:57 PM PDT 24
Finished Aug 03 06:37:13 PM PDT 24
Peak memory 241908 kb
Host smart-2bd3b10d-3748-4cda-9e39-43e7598f9857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894134065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.1894134065
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.2281387186
Short name T211
Test name
Test status
Simulation time 241447599 ps
CPU time 4.05 seconds
Started Aug 03 06:36:58 PM PDT 24
Finished Aug 03 06:37:03 PM PDT 24
Peak memory 247832 kb
Host smart-d14fefc4-b69e-45ea-974a-568ddc5df9e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281387186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.2281387186
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.2127629281
Short name T928
Test name
Test status
Simulation time 319770529 ps
CPU time 3.47 seconds
Started Aug 03 06:37:02 PM PDT 24
Finished Aug 03 06:37:06 PM PDT 24
Peak memory 241848 kb
Host smart-d5ee49e1-5be1-476e-992d-ba17b75bc8de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2127629281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.2127629281
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.1314419762
Short name T871
Test name
Test status
Simulation time 688723184 ps
CPU time 7.59 seconds
Started Aug 03 06:36:55 PM PDT 24
Finished Aug 03 06:37:02 PM PDT 24
Peak memory 242340 kb
Host smart-bb056b68-22f1-445c-8c32-31766e09b60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314419762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1314419762
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.773652391
Short name T1097
Test name
Test status
Simulation time 33044685493 ps
CPU time 230.91 seconds
Started Aug 03 06:37:04 PM PDT 24
Finished Aug 03 06:40:55 PM PDT 24
Peak memory 261648 kb
Host smart-4c04aa73-9874-4f07-88b3-ebff66aa7fa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773652391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.
773652391
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.437873494
Short name T296
Test name
Test status
Simulation time 522612781397 ps
CPU time 3804.71 seconds
Started Aug 03 06:37:02 PM PDT 24
Finished Aug 03 07:40:27 PM PDT 24
Peak memory 360988 kb
Host smart-c43a2a25-3201-4a32-aa49-8ea0f41fd104
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437873494 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.437873494
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.425061188
Short name T802
Test name
Test status
Simulation time 1133739703 ps
CPU time 14.84 seconds
Started Aug 03 06:37:03 PM PDT 24
Finished Aug 03 06:37:18 PM PDT 24
Peak memory 242308 kb
Host smart-0ea523af-fccc-4328-a2f8-225e1a7e3d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425061188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.425061188
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.2697196115
Short name T577
Test name
Test status
Simulation time 531083466 ps
CPU time 3.51 seconds
Started Aug 03 06:56:23 PM PDT 24
Finished Aug 03 06:56:27 PM PDT 24
Peak memory 242012 kb
Host smart-4c070b96-6bce-4eff-8088-295af3279d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697196115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2697196115
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.1337616548
Short name T415
Test name
Test status
Simulation time 1346358948 ps
CPU time 10.52 seconds
Started Aug 03 06:56:24 PM PDT 24
Finished Aug 03 06:56:34 PM PDT 24
Peak memory 242388 kb
Host smart-f93c2a2f-951d-4f7f-b625-3e5c01093dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337616548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.1337616548
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.1214393470
Short name T922
Test name
Test status
Simulation time 273524202 ps
CPU time 4.63 seconds
Started Aug 03 06:56:35 PM PDT 24
Finished Aug 03 06:56:40 PM PDT 24
Peak memory 242048 kb
Host smart-093fe969-5b1d-4378-8153-e19eddec1a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214393470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.1214393470
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.3353309427
Short name T746
Test name
Test status
Simulation time 204528346 ps
CPU time 4.15 seconds
Started Aug 03 06:56:34 PM PDT 24
Finished Aug 03 06:56:38 PM PDT 24
Peak memory 242444 kb
Host smart-4d6c4bcc-108d-4606-bfb7-a54036e8b3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353309427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.3353309427
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.538619721
Short name T983
Test name
Test status
Simulation time 347032713 ps
CPU time 4.58 seconds
Started Aug 03 06:56:35 PM PDT 24
Finished Aug 03 06:56:39 PM PDT 24
Peak memory 242188 kb
Host smart-4764777a-4209-4fff-8b41-f6ed3f3d15b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538619721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.538619721
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.758772045
Short name T932
Test name
Test status
Simulation time 684997510 ps
CPU time 9.04 seconds
Started Aug 03 06:56:35 PM PDT 24
Finished Aug 03 06:56:45 PM PDT 24
Peak memory 241844 kb
Host smart-22bf91fd-ef80-4c72-b4d2-f05f69a107ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758772045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.758772045
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.428572915
Short name T856
Test name
Test status
Simulation time 337207786 ps
CPU time 4.33 seconds
Started Aug 03 06:56:39 PM PDT 24
Finished Aug 03 06:56:44 PM PDT 24
Peak memory 241940 kb
Host smart-37fafcba-7ead-44dd-8b41-b27e36a4625d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428572915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.428572915
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.2652678354
Short name T1003
Test name
Test status
Simulation time 698495022 ps
CPU time 8.51 seconds
Started Aug 03 06:56:43 PM PDT 24
Finished Aug 03 06:56:51 PM PDT 24
Peak memory 242244 kb
Host smart-520c7346-6aa4-49f8-b54c-4655622b8598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652678354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.2652678354
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.4045870544
Short name T514
Test name
Test status
Simulation time 100426493 ps
CPU time 3.64 seconds
Started Aug 03 06:56:44 PM PDT 24
Finished Aug 03 06:56:48 PM PDT 24
Peak memory 241996 kb
Host smart-b1477bd8-2fc9-4eef-89e1-686e7e0acebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045870544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.4045870544
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.89285038
Short name T266
Test name
Test status
Simulation time 126325985 ps
CPU time 3.81 seconds
Started Aug 03 06:56:43 PM PDT 24
Finished Aug 03 06:56:47 PM PDT 24
Peak memory 241828 kb
Host smart-66bac748-6a15-4976-8c07-f61afa7617d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89285038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.89285038
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.1281200522
Short name T162
Test name
Test status
Simulation time 110408120 ps
CPU time 3.38 seconds
Started Aug 03 06:56:45 PM PDT 24
Finished Aug 03 06:56:48 PM PDT 24
Peak memory 242244 kb
Host smart-fd6eeed7-dbe0-4899-a5e4-30e7a1025fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281200522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.1281200522
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.3803307747
Short name T247
Test name
Test status
Simulation time 1624094566 ps
CPU time 21.91 seconds
Started Aug 03 06:56:49 PM PDT 24
Finished Aug 03 06:57:11 PM PDT 24
Peak memory 241976 kb
Host smart-a1205745-f406-4b2d-840b-1912746f8f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803307747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.3803307747
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.3231883109
Short name T453
Test name
Test status
Simulation time 115797299 ps
CPU time 4.52 seconds
Started Aug 03 06:56:55 PM PDT 24
Finished Aug 03 06:57:00 PM PDT 24
Peak memory 242212 kb
Host smart-86e2415f-3b21-4e94-ad0f-3e5abd433937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231883109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.3231883109
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.1333158124
Short name T1167
Test name
Test status
Simulation time 293626169 ps
CPU time 7.09 seconds
Started Aug 03 06:56:56 PM PDT 24
Finished Aug 03 06:57:03 PM PDT 24
Peak memory 241940 kb
Host smart-9c774a1a-3b3c-4611-bc31-cd6bade9c9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333158124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.1333158124
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.363026295
Short name T676
Test name
Test status
Simulation time 243996571 ps
CPU time 3.76 seconds
Started Aug 03 06:56:56 PM PDT 24
Finished Aug 03 06:57:00 PM PDT 24
Peak memory 242060 kb
Host smart-d2fad41a-ca07-487b-8274-0a055364144d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363026295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.363026295
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.123321205
Short name T395
Test name
Test status
Simulation time 1055831415 ps
CPU time 7.55 seconds
Started Aug 03 06:56:57 PM PDT 24
Finished Aug 03 06:57:04 PM PDT 24
Peak memory 242404 kb
Host smart-47b7e6fe-b985-43ed-a625-148076bee37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123321205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.123321205
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.2430571936
Short name T106
Test name
Test status
Simulation time 203370036 ps
CPU time 4.06 seconds
Started Aug 03 06:56:54 PM PDT 24
Finished Aug 03 06:56:58 PM PDT 24
Peak memory 242000 kb
Host smart-fcab2851-45ff-41c8-937b-4a0441e07e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430571936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.2430571936
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.2432752287
Short name T779
Test name
Test status
Simulation time 1279238081 ps
CPU time 5.62 seconds
Started Aug 03 06:56:53 PM PDT 24
Finished Aug 03 06:56:59 PM PDT 24
Peak memory 242196 kb
Host smart-83a54d70-480c-4e96-86d8-48d69a063754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432752287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.2432752287
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.654713288
Short name T190
Test name
Test status
Simulation time 306255910 ps
CPU time 3.65 seconds
Started Aug 03 06:56:52 PM PDT 24
Finished Aug 03 06:56:56 PM PDT 24
Peak memory 242100 kb
Host smart-2eac8e7f-f132-431f-a07a-b029b4ed1073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654713288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.654713288
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.593290247
Short name T476
Test name
Test status
Simulation time 619938677 ps
CPU time 18.43 seconds
Started Aug 03 06:56:56 PM PDT 24
Finished Aug 03 06:57:14 PM PDT 24
Peak memory 242224 kb
Host smart-9ce62442-eaf5-4664-b196-3191b53e182e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593290247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.593290247
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.451134466
Short name T580
Test name
Test status
Simulation time 55098593 ps
CPU time 1.84 seconds
Started Aug 03 06:37:12 PM PDT 24
Finished Aug 03 06:37:14 PM PDT 24
Peak memory 240484 kb
Host smart-ca069288-463c-4cf7-9356-34dfa79b5d2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451134466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.451134466
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.4236084710
Short name T1075
Test name
Test status
Simulation time 2491730563 ps
CPU time 17.25 seconds
Started Aug 03 06:37:07 PM PDT 24
Finished Aug 03 06:37:24 PM PDT 24
Peak memory 242284 kb
Host smart-24513879-7305-4485-a55d-a20774891b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236084710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.4236084710
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.2348333429
Short name T217
Test name
Test status
Simulation time 2108554208 ps
CPU time 36.62 seconds
Started Aug 03 06:37:09 PM PDT 24
Finished Aug 03 06:37:46 PM PDT 24
Peak memory 245792 kb
Host smart-d2e12034-d3de-4bc5-9d25-e7a0e5d598da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348333429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.2348333429
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.2160827135
Short name T317
Test name
Test status
Simulation time 1027686443 ps
CPU time 19.57 seconds
Started Aug 03 06:37:10 PM PDT 24
Finished Aug 03 06:37:30 PM PDT 24
Peak memory 242228 kb
Host smart-cd7ce729-6eb9-4def-80fd-5a601bcef1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160827135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.2160827135
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.2276801831
Short name T488
Test name
Test status
Simulation time 171274117 ps
CPU time 4.73 seconds
Started Aug 03 06:37:09 PM PDT 24
Finished Aug 03 06:37:14 PM PDT 24
Peak memory 242028 kb
Host smart-89bb18b3-156c-45ee-a624-9fd88613d7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276801831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.2276801831
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.269185213
Short name T1044
Test name
Test status
Simulation time 1130815467 ps
CPU time 12.89 seconds
Started Aug 03 06:37:11 PM PDT 24
Finished Aug 03 06:37:24 PM PDT 24
Peak memory 242000 kb
Host smart-ec51f298-da62-47e3-9c39-a4d459d3c785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269185213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.269185213
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.1848343665
Short name T911
Test name
Test status
Simulation time 667123286 ps
CPU time 24.8 seconds
Started Aug 03 06:37:13 PM PDT 24
Finished Aug 03 06:37:38 PM PDT 24
Peak memory 248656 kb
Host smart-0600afff-d9fa-475e-8b29-c867175daea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848343665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.1848343665
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.2955725497
Short name T639
Test name
Test status
Simulation time 810604514 ps
CPU time 11.99 seconds
Started Aug 03 06:37:09 PM PDT 24
Finished Aug 03 06:37:21 PM PDT 24
Peak memory 242444 kb
Host smart-34da36df-208f-4429-bc36-37d2ceea5371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955725497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.2955725497
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.3591158899
Short name T260
Test name
Test status
Simulation time 771306974 ps
CPU time 23.62 seconds
Started Aug 03 06:37:07 PM PDT 24
Finished Aug 03 06:37:31 PM PDT 24
Peak memory 241836 kb
Host smart-52e9936d-d2d7-4929-9816-0f4f9afed64d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591158899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.3591158899
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.2422176330
Short name T224
Test name
Test status
Simulation time 527013533 ps
CPU time 3.95 seconds
Started Aug 03 06:37:12 PM PDT 24
Finished Aug 03 06:37:16 PM PDT 24
Peak memory 242084 kb
Host smart-3d8d4999-717a-408d-ab8d-aaef1962c168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422176330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.2422176330
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.3969489225
Short name T346
Test name
Test status
Simulation time 1054591444 ps
CPU time 11.88 seconds
Started Aug 03 06:37:10 PM PDT 24
Finished Aug 03 06:37:22 PM PDT 24
Peak memory 242012 kb
Host smart-b3542edb-2398-4ee0-bceb-6c303ef923ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969489225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.3969489225
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.3477313617
Short name T567
Test name
Test status
Simulation time 4945462915 ps
CPU time 38.02 seconds
Started Aug 03 06:37:14 PM PDT 24
Finished Aug 03 06:37:52 PM PDT 24
Peak memory 258200 kb
Host smart-d8697940-b04f-41a4-82b3-b84531d1b0ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477313617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.3477313617
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.464266104
Short name T461
Test name
Test status
Simulation time 973724310 ps
CPU time 7.71 seconds
Started Aug 03 06:37:12 PM PDT 24
Finished Aug 03 06:37:20 PM PDT 24
Peak memory 242112 kb
Host smart-5ded1cb8-b7a5-451c-956c-024d1e22b5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464266104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.464266104
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.7613762
Short name T112
Test name
Test status
Simulation time 759912873 ps
CPU time 9.86 seconds
Started Aug 03 06:56:59 PM PDT 24
Finished Aug 03 06:57:09 PM PDT 24
Peak memory 242012 kb
Host smart-eb9b814b-5ec0-43ac-a2b5-47f505c4cb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7613762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.7613762
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.614452194
Short name T534
Test name
Test status
Simulation time 2703422535 ps
CPU time 6.16 seconds
Started Aug 03 06:56:59 PM PDT 24
Finished Aug 03 06:57:05 PM PDT 24
Peak memory 242272 kb
Host smart-5824dba7-aa79-463a-85fd-94283b9292ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614452194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.614452194
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.1141196175
Short name T881
Test name
Test status
Simulation time 1539589012 ps
CPU time 5.63 seconds
Started Aug 03 06:57:00 PM PDT 24
Finished Aug 03 06:57:06 PM PDT 24
Peak memory 241912 kb
Host smart-a2431921-a79a-41da-a281-67b711f9fa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141196175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.1141196175
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.738859148
Short name T715
Test name
Test status
Simulation time 184999363 ps
CPU time 5.04 seconds
Started Aug 03 06:57:00 PM PDT 24
Finished Aug 03 06:57:05 PM PDT 24
Peak memory 241828 kb
Host smart-ee7beab3-9423-4d3b-9f56-cffdb19f60fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738859148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.738859148
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.3857657917
Short name T561
Test name
Test status
Simulation time 156393534 ps
CPU time 3.94 seconds
Started Aug 03 06:57:05 PM PDT 24
Finished Aug 03 06:57:09 PM PDT 24
Peak memory 242056 kb
Host smart-35d15739-9598-4d37-8afd-b3452763e9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857657917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.3857657917
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.774936718
Short name T464
Test name
Test status
Simulation time 2405490334 ps
CPU time 10.19 seconds
Started Aug 03 06:57:07 PM PDT 24
Finished Aug 03 06:57:17 PM PDT 24
Peak memory 242112 kb
Host smart-4238fa1f-f4ae-463d-abc2-f7ff851e2a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774936718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.774936718
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.290409031
Short name T480
Test name
Test status
Simulation time 2305866241 ps
CPU time 16.57 seconds
Started Aug 03 06:57:05 PM PDT 24
Finished Aug 03 06:57:22 PM PDT 24
Peak memory 242032 kb
Host smart-3b754842-6305-473a-a9f5-daabb4268851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290409031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.290409031
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.3906147446
Short name T178
Test name
Test status
Simulation time 225223529 ps
CPU time 3.55 seconds
Started Aug 03 06:57:03 PM PDT 24
Finished Aug 03 06:57:07 PM PDT 24
Peak memory 242124 kb
Host smart-b4030ec4-49f9-411b-bae6-5f394cce020c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906147446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.3906147446
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.918021626
Short name T388
Test name
Test status
Simulation time 1099714583 ps
CPU time 14.78 seconds
Started Aug 03 06:57:05 PM PDT 24
Finished Aug 03 06:57:19 PM PDT 24
Peak memory 241904 kb
Host smart-6333c977-5b3a-4cac-b812-b91446eb43df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918021626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.918021626
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.1599834272
Short name T445
Test name
Test status
Simulation time 334348958 ps
CPU time 6.93 seconds
Started Aug 03 06:57:09 PM PDT 24
Finished Aug 03 06:57:16 PM PDT 24
Peak memory 242228 kb
Host smart-fc065514-49d0-434d-8e66-ac614d3b8dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599834272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.1599834272
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.1141736515
Short name T955
Test name
Test status
Simulation time 1709961599 ps
CPU time 4.42 seconds
Started Aug 03 06:57:13 PM PDT 24
Finished Aug 03 06:57:18 PM PDT 24
Peak memory 242000 kb
Host smart-4a34df91-d091-48a1-8391-900165b39162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141736515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.1141736515
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.1831195875
Short name T1006
Test name
Test status
Simulation time 511664716 ps
CPU time 4.33 seconds
Started Aug 03 06:57:16 PM PDT 24
Finished Aug 03 06:57:20 PM PDT 24
Peak memory 242000 kb
Host smart-67675afc-cccc-4853-aa09-8d8fbe4685e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831195875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.1831195875
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.2239874485
Short name T77
Test name
Test status
Simulation time 1845789056 ps
CPU time 5.5 seconds
Started Aug 03 06:57:15 PM PDT 24
Finished Aug 03 06:57:21 PM PDT 24
Peak memory 241912 kb
Host smart-9ce8f198-a4af-42d2-9b75-98bccc4058ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239874485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.2239874485
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.3431169810
Short name T631
Test name
Test status
Simulation time 527784053 ps
CPU time 4.68 seconds
Started Aug 03 06:57:19 PM PDT 24
Finished Aug 03 06:57:24 PM PDT 24
Peak memory 242000 kb
Host smart-9151da54-0e20-43c2-8a47-6b955c3d052e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431169810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.3431169810
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.1972578067
Short name T46
Test name
Test status
Simulation time 149746728 ps
CPU time 3.44 seconds
Started Aug 03 06:57:17 PM PDT 24
Finished Aug 03 06:57:20 PM PDT 24
Peak memory 242064 kb
Host smart-87170a9b-f6bb-4213-b0f4-56fecb73376a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972578067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1972578067
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.1668770921
Short name T1151
Test name
Test status
Simulation time 231739352 ps
CPU time 5.69 seconds
Started Aug 03 06:57:15 PM PDT 24
Finished Aug 03 06:57:21 PM PDT 24
Peak memory 242308 kb
Host smart-cf8400db-e820-46de-9f18-d8ab5829afee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668770921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1668770921
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.3107072632
Short name T830
Test name
Test status
Simulation time 126654757 ps
CPU time 1.76 seconds
Started Aug 03 06:37:27 PM PDT 24
Finished Aug 03 06:37:29 PM PDT 24
Peak memory 240756 kb
Host smart-bba8ec64-ee01-4f4b-9d16-d0da60b3128b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107072632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.3107072632
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.1120948679
Short name T789
Test name
Test status
Simulation time 235648809 ps
CPU time 5.08 seconds
Started Aug 03 06:37:25 PM PDT 24
Finished Aug 03 06:37:30 PM PDT 24
Peak memory 248576 kb
Host smart-4adc4bc0-25b3-4d7c-901a-1f003f6d7adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120948679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.1120948679
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.2067199314
Short name T5
Test name
Test status
Simulation time 280167049 ps
CPU time 16.39 seconds
Started Aug 03 06:37:22 PM PDT 24
Finished Aug 03 06:37:38 PM PDT 24
Peak memory 241896 kb
Host smart-5b33cd92-4a2e-402e-833d-3a51b5c20c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067199314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.2067199314
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.3174573515
Short name T526
Test name
Test status
Simulation time 2076151317 ps
CPU time 12.63 seconds
Started Aug 03 06:37:17 PM PDT 24
Finished Aug 03 06:37:30 PM PDT 24
Peak memory 241864 kb
Host smart-ebad599d-c7fe-49c6-bfdc-a15b24ff77fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174573515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.3174573515
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.2303177634
Short name T51
Test name
Test status
Simulation time 559050480 ps
CPU time 4.15 seconds
Started Aug 03 06:37:16 PM PDT 24
Finished Aug 03 06:37:20 PM PDT 24
Peak memory 242000 kb
Host smart-cf8de6bd-3d16-4d64-a5b1-b3e8f1337c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303177634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2303177634
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.2564612327
Short name T624
Test name
Test status
Simulation time 778694151 ps
CPU time 5.55 seconds
Started Aug 03 06:37:22 PM PDT 24
Finished Aug 03 06:37:28 PM PDT 24
Peak memory 248580 kb
Host smart-7d465aeb-5fd9-46f6-8135-88af521a3d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564612327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.2564612327
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.4099783231
Short name T502
Test name
Test status
Simulation time 1526279211 ps
CPU time 32.54 seconds
Started Aug 03 06:37:23 PM PDT 24
Finished Aug 03 06:37:56 PM PDT 24
Peak memory 242504 kb
Host smart-4691397c-5105-4970-be62-08b5b7c78ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099783231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.4099783231
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.579161411
Short name T121
Test name
Test status
Simulation time 3581802853 ps
CPU time 13.09 seconds
Started Aug 03 06:37:18 PM PDT 24
Finished Aug 03 06:37:31 PM PDT 24
Peak memory 242016 kb
Host smart-1e85f998-6614-4fe3-a7ff-d0ca48de4762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579161411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.579161411
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.3044127354
Short name T940
Test name
Test status
Simulation time 683614580 ps
CPU time 11.76 seconds
Started Aug 03 06:37:17 PM PDT 24
Finished Aug 03 06:37:29 PM PDT 24
Peak memory 242160 kb
Host smart-4535ecce-af64-4bce-a654-823cd0803ddf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3044127354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.3044127354
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.71970335
Short name T459
Test name
Test status
Simulation time 456113337 ps
CPU time 8.22 seconds
Started Aug 03 06:37:22 PM PDT 24
Finished Aug 03 06:37:30 PM PDT 24
Peak memory 242036 kb
Host smart-0959e348-fa5b-4b58-a296-4ed164164c41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71970335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.71970335
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.2178003461
Short name T550
Test name
Test status
Simulation time 431349910 ps
CPU time 5.36 seconds
Started Aug 03 06:37:17 PM PDT 24
Finished Aug 03 06:37:23 PM PDT 24
Peak memory 242104 kb
Host smart-ea7f3e36-3456-4ffc-b6e9-9bcd6e37520a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178003461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2178003461
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.2669472215
Short name T963
Test name
Test status
Simulation time 20413462961 ps
CPU time 329.24 seconds
Started Aug 03 06:37:24 PM PDT 24
Finished Aug 03 06:42:53 PM PDT 24
Peak memory 276392 kb
Host smart-1dfb555b-af68-4d29-b3e1-661fac75cc09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669472215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.2669472215
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.2611253234
Short name T133
Test name
Test status
Simulation time 253159641935 ps
CPU time 1153.49 seconds
Started Aug 03 06:37:23 PM PDT 24
Finished Aug 03 06:56:37 PM PDT 24
Peak memory 264880 kb
Host smart-25244f2d-bb0b-41b6-b6f3-32cdb5a6b0d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611253234 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.2611253234
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.2837577177
Short name T236
Test name
Test status
Simulation time 3673832274 ps
CPU time 29.42 seconds
Started Aug 03 06:37:23 PM PDT 24
Finished Aug 03 06:37:52 PM PDT 24
Peak memory 242164 kb
Host smart-c33c43dc-3bf4-4a2b-81a3-8df0ed0a2f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837577177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.2837577177
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.2231229789
Short name T656
Test name
Test status
Simulation time 439253528 ps
CPU time 4.06 seconds
Started Aug 03 06:57:19 PM PDT 24
Finished Aug 03 06:57:24 PM PDT 24
Peak memory 242200 kb
Host smart-43afa7b1-8d22-4cb0-868f-6e97a64c4d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231229789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.2231229789
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.3558325517
Short name T1007
Test name
Test status
Simulation time 781517405 ps
CPU time 10.08 seconds
Started Aug 03 06:57:19 PM PDT 24
Finished Aug 03 06:57:30 PM PDT 24
Peak memory 241856 kb
Host smart-e04a8a7a-fb11-44d4-ace9-3baf35e7a358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558325517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3558325517
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.4279741283
Short name T510
Test name
Test status
Simulation time 137424550 ps
CPU time 5.45 seconds
Started Aug 03 06:57:21 PM PDT 24
Finished Aug 03 06:57:26 PM PDT 24
Peak memory 241852 kb
Host smart-616e5940-8d9c-440a-a40e-7b7546f02f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279741283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.4279741283
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.4219809147
Short name T546
Test name
Test status
Simulation time 2048296415 ps
CPU time 3.52 seconds
Started Aug 03 06:57:20 PM PDT 24
Finished Aug 03 06:57:23 PM PDT 24
Peak memory 242032 kb
Host smart-7e66fbb9-798f-4746-a381-4807a2f35ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219809147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.4219809147
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.3089059911
Short name T547
Test name
Test status
Simulation time 124193171 ps
CPU time 3.91 seconds
Started Aug 03 06:57:19 PM PDT 24
Finished Aug 03 06:57:23 PM PDT 24
Peak memory 241812 kb
Host smart-4f33775d-547f-420a-a012-e98158c2cba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089059911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.3089059911
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.873852750
Short name T1177
Test name
Test status
Simulation time 340154877 ps
CPU time 5.01 seconds
Started Aug 03 06:57:20 PM PDT 24
Finished Aug 03 06:57:25 PM PDT 24
Peak memory 242016 kb
Host smart-42a39372-9017-4feb-8a1b-b1227f20c92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873852750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.873852750
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.936886322
Short name T274
Test name
Test status
Simulation time 221312401 ps
CPU time 9.03 seconds
Started Aug 03 06:57:20 PM PDT 24
Finished Aug 03 06:57:29 PM PDT 24
Peak memory 242036 kb
Host smart-23655fc3-ff99-4ea9-963f-66b05a955a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936886322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.936886322
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.1806460747
Short name T1077
Test name
Test status
Simulation time 906591453 ps
CPU time 9.86 seconds
Started Aug 03 06:57:26 PM PDT 24
Finished Aug 03 06:57:36 PM PDT 24
Peak memory 242020 kb
Host smart-0bb37dbc-022c-460b-a49c-bd8a083a34fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806460747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.1806460747
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.532554857
Short name T1022
Test name
Test status
Simulation time 376816732 ps
CPU time 3.3 seconds
Started Aug 03 06:57:23 PM PDT 24
Finished Aug 03 06:57:26 PM PDT 24
Peak memory 242080 kb
Host smart-a59e843c-cb5d-4cd6-90cf-66aec00f6164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532554857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.532554857
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.2571393465
Short name T533
Test name
Test status
Simulation time 249773904 ps
CPU time 9.51 seconds
Started Aug 03 06:57:24 PM PDT 24
Finished Aug 03 06:57:33 PM PDT 24
Peak memory 242276 kb
Host smart-5a4a32d8-e15c-4849-84e7-f83eef5f9d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571393465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.2571393465
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.4100521509
Short name T465
Test name
Test status
Simulation time 384221078 ps
CPU time 4.49 seconds
Started Aug 03 06:57:23 PM PDT 24
Finished Aug 03 06:57:28 PM PDT 24
Peak memory 242296 kb
Host smart-99afe1fd-34b5-432f-81c7-67aed1ba91e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100521509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.4100521509
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.875837620
Short name T962
Test name
Test status
Simulation time 5756834513 ps
CPU time 18.75 seconds
Started Aug 03 06:57:25 PM PDT 24
Finished Aug 03 06:57:44 PM PDT 24
Peak memory 241872 kb
Host smart-5a6ff726-7f5c-4643-9136-c8957337c374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875837620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.875837620
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.2960482602
Short name T287
Test name
Test status
Simulation time 315475971 ps
CPU time 4.14 seconds
Started Aug 03 06:57:28 PM PDT 24
Finished Aug 03 06:57:32 PM PDT 24
Peak memory 242096 kb
Host smart-88d766ea-5959-42fe-9016-0993a3d4e14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960482602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.2960482602
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.1873977815
Short name T234
Test name
Test status
Simulation time 3680514255 ps
CPU time 14.31 seconds
Started Aug 03 06:57:34 PM PDT 24
Finished Aug 03 06:57:49 PM PDT 24
Peak memory 241864 kb
Host smart-813cdf03-4a91-4641-ac2d-5e67a881fb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873977815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.1873977815
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.3070744947
Short name T959
Test name
Test status
Simulation time 164440623 ps
CPU time 3.9 seconds
Started Aug 03 06:57:34 PM PDT 24
Finished Aug 03 06:57:38 PM PDT 24
Peak memory 242060 kb
Host smart-1f2be4dc-0163-44dd-88e2-005ff28275f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070744947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.3070744947
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.1331240797
Short name T238
Test name
Test status
Simulation time 851049491 ps
CPU time 19.2 seconds
Started Aug 03 06:57:33 PM PDT 24
Finished Aug 03 06:57:52 PM PDT 24
Peak memory 242208 kb
Host smart-9cc8e3fb-c94f-4dca-8d85-d7b04b8e9575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331240797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.1331240797
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.2168456571
Short name T1052
Test name
Test status
Simulation time 144990242 ps
CPU time 3.76 seconds
Started Aug 03 06:57:33 PM PDT 24
Finished Aug 03 06:57:37 PM PDT 24
Peak memory 241884 kb
Host smart-e2da9ca9-c10d-4393-a529-58fa1250afad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168456571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.2168456571
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.3265642745
Short name T142
Test name
Test status
Simulation time 1280340232 ps
CPU time 22.22 seconds
Started Aug 03 06:57:35 PM PDT 24
Finished Aug 03 06:57:57 PM PDT 24
Peak memory 241880 kb
Host smart-e76b813f-f259-4c33-9ebc-72eb408c1c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265642745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.3265642745
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.3013621232
Short name T936
Test name
Test status
Simulation time 320605562 ps
CPU time 2.66 seconds
Started Aug 03 06:37:43 PM PDT 24
Finished Aug 03 06:37:45 PM PDT 24
Peak memory 240792 kb
Host smart-56c1d5b2-358e-4cda-982b-06a7c9637e9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013621232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.3013621232
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.1959014735
Short name T784
Test name
Test status
Simulation time 963233888 ps
CPU time 20.92 seconds
Started Aug 03 06:37:33 PM PDT 24
Finished Aug 03 06:37:54 PM PDT 24
Peak memory 241904 kb
Host smart-c7357800-a35c-4c14-8557-c521787201cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959014735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.1959014735
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.1658063825
Short name T383
Test name
Test status
Simulation time 2937026653 ps
CPU time 34.51 seconds
Started Aug 03 06:37:31 PM PDT 24
Finished Aug 03 06:38:06 PM PDT 24
Peak memory 241848 kb
Host smart-83e3603f-e6ef-4b82-be67-e53a6ceb1f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658063825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.1658063825
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.3843082343
Short name T967
Test name
Test status
Simulation time 319482911 ps
CPU time 3.15 seconds
Started Aug 03 06:37:32 PM PDT 24
Finished Aug 03 06:37:35 PM PDT 24
Peak memory 242216 kb
Host smart-9be84baa-a339-4e9b-b21a-90ccef1ad53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843082343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.3843082343
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.1839802219
Short name T626
Test name
Test status
Simulation time 800857025 ps
CPU time 23.86 seconds
Started Aug 03 06:37:39 PM PDT 24
Finished Aug 03 06:38:03 PM PDT 24
Peak memory 248340 kb
Host smart-eefbb60c-3515-47d6-89ba-0260cf909b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839802219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.1839802219
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.2024916096
Short name T570
Test name
Test status
Simulation time 3988192418 ps
CPU time 44.06 seconds
Started Aug 03 06:37:38 PM PDT 24
Finished Aug 03 06:38:22 PM PDT 24
Peak memory 241988 kb
Host smart-6cb4a179-a141-4dc0-bc57-7bbd14774e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024916096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.2024916096
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.3519357693
Short name T467
Test name
Test status
Simulation time 2066379355 ps
CPU time 15.86 seconds
Started Aug 03 06:37:33 PM PDT 24
Finished Aug 03 06:37:49 PM PDT 24
Peak memory 241892 kb
Host smart-ab7f7c63-5984-4f81-b769-c28d114f4dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519357693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3519357693
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.3233931762
Short name T674
Test name
Test status
Simulation time 693787193 ps
CPU time 20.86 seconds
Started Aug 03 06:37:33 PM PDT 24
Finished Aug 03 06:37:54 PM PDT 24
Peak memory 242352 kb
Host smart-2dd28a16-fba8-47fe-b0b4-12de4f0eb8a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233931762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.3233931762
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.2720275486
Short name T412
Test name
Test status
Simulation time 345889306 ps
CPU time 5.76 seconds
Started Aug 03 06:37:39 PM PDT 24
Finished Aug 03 06:37:45 PM PDT 24
Peak memory 241964 kb
Host smart-27bbf0ab-bce0-4d15-b8ae-c391b8668d24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720275486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.2720275486
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.162768075
Short name T401
Test name
Test status
Simulation time 992432566 ps
CPU time 10.24 seconds
Started Aug 03 06:37:26 PM PDT 24
Finished Aug 03 06:37:37 PM PDT 24
Peak memory 242392 kb
Host smart-ae395b49-4e81-4e6d-ab5e-2b5bc261c7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162768075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.162768075
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.3394979718
Short name T99
Test name
Test status
Simulation time 2017574534 ps
CPU time 28.95 seconds
Started Aug 03 06:37:42 PM PDT 24
Finished Aug 03 06:38:11 PM PDT 24
Peak memory 242240 kb
Host smart-8aa6d396-8085-4f3a-9698-38152048354b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394979718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.3394979718
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.2232702217
Short name T1037
Test name
Test status
Simulation time 9073184273 ps
CPU time 20.46 seconds
Started Aug 03 06:37:41 PM PDT 24
Finished Aug 03 06:38:01 PM PDT 24
Peak memory 248728 kb
Host smart-d7e9c77c-f224-41af-a5f7-b5106357fe90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232702217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.2232702217
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.1544346450
Short name T659
Test name
Test status
Simulation time 238599777 ps
CPU time 4.81 seconds
Started Aug 03 06:57:33 PM PDT 24
Finished Aug 03 06:57:37 PM PDT 24
Peak memory 242192 kb
Host smart-4d44a6e3-09ef-434f-b5ae-d04eabc5a56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544346450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.1544346450
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.2414804650
Short name T866
Test name
Test status
Simulation time 237860025 ps
CPU time 11.76 seconds
Started Aug 03 06:57:41 PM PDT 24
Finished Aug 03 06:57:53 PM PDT 24
Peak memory 241812 kb
Host smart-c3ab1d8b-32cf-414b-b668-dbff4a1522c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414804650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.2414804650
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.2658538531
Short name T426
Test name
Test status
Simulation time 128597423 ps
CPU time 3.93 seconds
Started Aug 03 06:57:42 PM PDT 24
Finished Aug 03 06:57:46 PM PDT 24
Peak memory 242172 kb
Host smart-a13c7d39-a7de-45ee-a0cd-51fb660f87de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658538531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.2658538531
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.2836211681
Short name T444
Test name
Test status
Simulation time 1565461344 ps
CPU time 21.31 seconds
Started Aug 03 06:57:41 PM PDT 24
Finished Aug 03 06:58:03 PM PDT 24
Peak memory 241904 kb
Host smart-e26e3177-be0f-47ef-8dcb-f32924739414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836211681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2836211681
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.4294378596
Short name T910
Test name
Test status
Simulation time 334337073 ps
CPU time 4.06 seconds
Started Aug 03 06:57:40 PM PDT 24
Finished Aug 03 06:57:44 PM PDT 24
Peak memory 242152 kb
Host smart-a1cf0a92-eef2-4aae-b133-bbe90c5cd4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294378596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.4294378596
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.3251248890
Short name T143
Test name
Test status
Simulation time 1976258951 ps
CPU time 15.41 seconds
Started Aug 03 06:57:43 PM PDT 24
Finished Aug 03 06:57:58 PM PDT 24
Peak memory 242016 kb
Host smart-5732fbc9-a831-4680-8363-156f4836fe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251248890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.3251248890
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.391683749
Short name T975
Test name
Test status
Simulation time 1683118307 ps
CPU time 4.08 seconds
Started Aug 03 06:57:39 PM PDT 24
Finished Aug 03 06:57:44 PM PDT 24
Peak memory 241988 kb
Host smart-5539c42f-9209-4e3b-9831-817737e04f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391683749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.391683749
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.1751338296
Short name T826
Test name
Test status
Simulation time 153161570 ps
CPU time 4.57 seconds
Started Aug 03 06:57:43 PM PDT 24
Finished Aug 03 06:57:47 PM PDT 24
Peak memory 242008 kb
Host smart-69d40999-feff-447b-9a83-165745a5911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751338296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.1751338296
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.348168908
Short name T477
Test name
Test status
Simulation time 476619706 ps
CPU time 3.38 seconds
Started Aug 03 06:57:41 PM PDT 24
Finished Aug 03 06:57:44 PM PDT 24
Peak memory 242144 kb
Host smart-a8a6014b-0848-45c5-87dc-42d655290ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348168908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.348168908
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.3868327381
Short name T939
Test name
Test status
Simulation time 408669817 ps
CPU time 11.39 seconds
Started Aug 03 06:57:43 PM PDT 24
Finished Aug 03 06:57:54 PM PDT 24
Peak memory 242088 kb
Host smart-df44775c-7590-4f49-bdbd-7b1c69420f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868327381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.3868327381
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.3857843365
Short name T487
Test name
Test status
Simulation time 261868561 ps
CPU time 4.04 seconds
Started Aug 03 06:57:42 PM PDT 24
Finished Aug 03 06:57:46 PM PDT 24
Peak memory 242368 kb
Host smart-d4a2afb2-dcae-4e40-a1bd-10e90e7483a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857843365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.3857843365
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.3029095927
Short name T772
Test name
Test status
Simulation time 364514807 ps
CPU time 12.09 seconds
Started Aug 03 06:57:45 PM PDT 24
Finished Aug 03 06:57:57 PM PDT 24
Peak memory 242312 kb
Host smart-4eff5daa-4a54-40bf-92e1-86a1c5519e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029095927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.3029095927
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.3809148773
Short name T951
Test name
Test status
Simulation time 98185768 ps
CPU time 3.67 seconds
Started Aug 03 06:57:44 PM PDT 24
Finished Aug 03 06:57:48 PM PDT 24
Peak memory 242028 kb
Host smart-ba27cde8-195a-4651-9e6e-2d34864389bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809148773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3809148773
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.2025290755
Short name T839
Test name
Test status
Simulation time 13086996506 ps
CPU time 35.61 seconds
Started Aug 03 06:57:45 PM PDT 24
Finished Aug 03 06:58:21 PM PDT 24
Peak memory 242060 kb
Host smart-adb8ddac-a4fe-432c-936b-8b556cca580a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025290755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2025290755
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.897836167
Short name T1041
Test name
Test status
Simulation time 143159483 ps
CPU time 4.99 seconds
Started Aug 03 06:57:42 PM PDT 24
Finished Aug 03 06:57:47 PM PDT 24
Peak memory 242128 kb
Host smart-7573eefd-9ccc-4b85-a472-1b34d9b07aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897836167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.897836167
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.28630563
Short name T470
Test name
Test status
Simulation time 646026581 ps
CPU time 8.79 seconds
Started Aug 03 06:57:44 PM PDT 24
Finished Aug 03 06:57:53 PM PDT 24
Peak memory 242300 kb
Host smart-8c81495b-cc20-43dc-959e-72a371aa3055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28630563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.28630563
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.3700588950
Short name T429
Test name
Test status
Simulation time 148013688 ps
CPU time 4.33 seconds
Started Aug 03 06:57:44 PM PDT 24
Finished Aug 03 06:57:48 PM PDT 24
Peak memory 242188 kb
Host smart-fdafd7c6-08cb-49ee-ab69-0cd4221cb785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700588950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.3700588950
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.2529085369
Short name T468
Test name
Test status
Simulation time 280761992 ps
CPU time 10.47 seconds
Started Aug 03 06:57:49 PM PDT 24
Finished Aug 03 06:57:59 PM PDT 24
Peak memory 242372 kb
Host smart-1f8985a8-fefd-493a-a955-3bbcd373761c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529085369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.2529085369
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.479881142
Short name T1172
Test name
Test status
Simulation time 131863159 ps
CPU time 3.61 seconds
Started Aug 03 06:57:49 PM PDT 24
Finished Aug 03 06:57:53 PM PDT 24
Peak memory 242196 kb
Host smart-2fe5a12c-b685-4a63-8610-339ba0fc588d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479881142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.479881142
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.1254415354
Short name T396
Test name
Test status
Simulation time 1237628199 ps
CPU time 21.72 seconds
Started Aug 03 06:57:49 PM PDT 24
Finished Aug 03 06:58:11 PM PDT 24
Peak memory 242428 kb
Host smart-172e1901-3664-4c01-b8df-24fe311d08f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254415354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.1254415354
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.1164067270
Short name T1166
Test name
Test status
Simulation time 213215560 ps
CPU time 1.81 seconds
Started Aug 03 06:37:53 PM PDT 24
Finished Aug 03 06:37:55 PM PDT 24
Peak memory 240412 kb
Host smart-b270ceba-d568-4e59-ab0a-674492d7d327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164067270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.1164067270
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.4271870063
Short name T557
Test name
Test status
Simulation time 3755627935 ps
CPU time 22.98 seconds
Started Aug 03 06:37:48 PM PDT 24
Finished Aug 03 06:38:11 PM PDT 24
Peak memory 242156 kb
Host smart-2bb972b0-9ba3-4fc8-bef9-6bd8dfd053a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271870063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.4271870063
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.2709155509
Short name T842
Test name
Test status
Simulation time 3925973196 ps
CPU time 38.28 seconds
Started Aug 03 06:37:50 PM PDT 24
Finished Aug 03 06:38:28 PM PDT 24
Peak memory 247132 kb
Host smart-003d2119-b003-4b4b-b1ca-7e15bf53d1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709155509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.2709155509
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.1678908767
Short name T756
Test name
Test status
Simulation time 784826654 ps
CPU time 5.38 seconds
Started Aug 03 06:37:44 PM PDT 24
Finished Aug 03 06:37:49 PM PDT 24
Peak memory 241968 kb
Host smart-103cd4ff-4bc6-4cfe-9646-310d2e5e8195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678908767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.1678908767
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.535008730
Short name T104
Test name
Test status
Simulation time 106734760 ps
CPU time 4.04 seconds
Started Aug 03 06:37:42 PM PDT 24
Finished Aug 03 06:37:46 PM PDT 24
Peak memory 242000 kb
Host smart-371b7355-7ffd-4ce4-bf4e-59b027a64a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535008730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.535008730
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.2343164968
Short name T154
Test name
Test status
Simulation time 798679752 ps
CPU time 10.42 seconds
Started Aug 03 06:37:47 PM PDT 24
Finished Aug 03 06:37:58 PM PDT 24
Peak memory 242220 kb
Host smart-b07da25e-be2f-4e4d-9c11-0dde26c700aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343164968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.2343164968
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.992318331
Short name T714
Test name
Test status
Simulation time 1288012683 ps
CPU time 31.23 seconds
Started Aug 03 06:37:51 PM PDT 24
Finished Aug 03 06:38:22 PM PDT 24
Peak memory 242400 kb
Host smart-5ec7e758-ea35-48f6-9c54-2a9a43462508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992318331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.992318331
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.4123962500
Short name T1081
Test name
Test status
Simulation time 2037967359 ps
CPU time 19.92 seconds
Started Aug 03 06:37:41 PM PDT 24
Finished Aug 03 06:38:01 PM PDT 24
Peak memory 242088 kb
Host smart-a1180b04-217a-4d25-b337-ffc69fba88eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123962500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.4123962500
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.3800405260
Short name T829
Test name
Test status
Simulation time 296043543 ps
CPU time 12.02 seconds
Started Aug 03 06:37:52 PM PDT 24
Finished Aug 03 06:38:04 PM PDT 24
Peak memory 242024 kb
Host smart-1700053e-8b2c-462a-9074-6c7e077af870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800405260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.3800405260
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.643114368
Short name T734
Test name
Test status
Simulation time 955367340 ps
CPU time 7.86 seconds
Started Aug 03 06:37:41 PM PDT 24
Finished Aug 03 06:37:49 PM PDT 24
Peak memory 241948 kb
Host smart-91920fbf-bce6-4f21-b9e6-3d0f2100ce3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643114368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.643114368
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.3437612142
Short name T945
Test name
Test status
Simulation time 12704769410 ps
CPU time 97.85 seconds
Started Aug 03 06:37:52 PM PDT 24
Finished Aug 03 06:39:30 PM PDT 24
Peak memory 278380 kb
Host smart-4be21f9d-8516-4c93-8236-b13af78212a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437612142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.3437612142
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.957142953
Short name T552
Test name
Test status
Simulation time 6348494983 ps
CPU time 14.79 seconds
Started Aug 03 06:37:56 PM PDT 24
Finished Aug 03 06:38:11 PM PDT 24
Peak memory 242844 kb
Host smart-0e69bb7c-d8a4-43dd-a559-3c09dd83e506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957142953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.957142953
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.1060200338
Short name T716
Test name
Test status
Simulation time 1583175969 ps
CPU time 4.62 seconds
Started Aug 03 06:57:53 PM PDT 24
Finished Aug 03 06:57:58 PM PDT 24
Peak memory 242028 kb
Host smart-8e079515-30e7-466b-9355-82db87b254b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060200338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.1060200338
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.2749048857
Short name T823
Test name
Test status
Simulation time 3439036288 ps
CPU time 32.27 seconds
Started Aug 03 06:57:54 PM PDT 24
Finished Aug 03 06:58:26 PM PDT 24
Peak memory 242392 kb
Host smart-23a4ba11-67e0-4aaf-988a-9ca1800037ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749048857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.2749048857
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.3952528275
Short name T833
Test name
Test status
Simulation time 582731558 ps
CPU time 4.72 seconds
Started Aug 03 06:57:53 PM PDT 24
Finished Aug 03 06:57:57 PM PDT 24
Peak memory 242184 kb
Host smart-403b45a4-43a0-429a-945b-41a81f8993b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952528275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3952528275
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.2433060655
Short name T422
Test name
Test status
Simulation time 6381686791 ps
CPU time 13.63 seconds
Started Aug 03 06:57:54 PM PDT 24
Finished Aug 03 06:58:08 PM PDT 24
Peak memory 241860 kb
Host smart-96c06bcc-7ff4-4262-9bce-5cc7ed595934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433060655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.2433060655
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.2623485128
Short name T977
Test name
Test status
Simulation time 319942674 ps
CPU time 3.89 seconds
Started Aug 03 06:57:53 PM PDT 24
Finished Aug 03 06:57:57 PM PDT 24
Peak memory 241920 kb
Host smart-10a0d519-d23d-4bf6-b373-4c93547fe421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623485128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.2623485128
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.2245882888
Short name T606
Test name
Test status
Simulation time 396975806 ps
CPU time 9.18 seconds
Started Aug 03 06:57:56 PM PDT 24
Finished Aug 03 06:58:05 PM PDT 24
Peak memory 241832 kb
Host smart-df4fa53f-c08c-4dca-bac2-998e97e35f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245882888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.2245882888
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.4011360020
Short name T539
Test name
Test status
Simulation time 1669075655 ps
CPU time 4.55 seconds
Started Aug 03 06:57:54 PM PDT 24
Finished Aug 03 06:57:59 PM PDT 24
Peak memory 242252 kb
Host smart-66435e06-7c0a-482c-a5dd-df20280d46c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011360020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.4011360020
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.3467351036
Short name T1023
Test name
Test status
Simulation time 3568925205 ps
CPU time 7.92 seconds
Started Aug 03 06:57:53 PM PDT 24
Finished Aug 03 06:58:01 PM PDT 24
Peak memory 242300 kb
Host smart-6563b65f-d018-41fa-8dc1-c1af73ddbc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467351036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.3467351036
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.323832406
Short name T658
Test name
Test status
Simulation time 353335933 ps
CPU time 4.02 seconds
Started Aug 03 06:57:52 PM PDT 24
Finished Aug 03 06:57:56 PM PDT 24
Peak memory 242236 kb
Host smart-95a78d1d-e496-43df-9970-32775aeca419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323832406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.323832406
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.1685232112
Short name T989
Test name
Test status
Simulation time 2397652314 ps
CPU time 8.24 seconds
Started Aug 03 06:58:01 PM PDT 24
Finished Aug 03 06:58:09 PM PDT 24
Peak memory 242104 kb
Host smart-fea4ff65-bedf-4eca-9fdc-d2e9f321962b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685232112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.1685232112
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.927746116
Short name T859
Test name
Test status
Simulation time 235341656 ps
CPU time 4.31 seconds
Started Aug 03 06:58:00 PM PDT 24
Finished Aug 03 06:58:04 PM PDT 24
Peak memory 242020 kb
Host smart-70ad1b3b-77c5-48a8-9c81-5ef5fb249729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927746116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.927746116
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.2179020847
Short name T145
Test name
Test status
Simulation time 424284510 ps
CPU time 10.7 seconds
Started Aug 03 06:58:01 PM PDT 24
Finished Aug 03 06:58:12 PM PDT 24
Peak memory 242316 kb
Host smart-49acc137-8268-4bab-93ea-8311e47ee6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179020847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.2179020847
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.3447379491
Short name T103
Test name
Test status
Simulation time 308027696 ps
CPU time 3.98 seconds
Started Aug 03 06:58:00 PM PDT 24
Finished Aug 03 06:58:04 PM PDT 24
Peak memory 242028 kb
Host smart-a8fae8e5-2d91-4a04-9299-2f7966402883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447379491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.3447379491
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.2511159707
Short name T350
Test name
Test status
Simulation time 10505313606 ps
CPU time 24.59 seconds
Started Aug 03 06:58:00 PM PDT 24
Finished Aug 03 06:58:25 PM PDT 24
Peak memory 242096 kb
Host smart-2b82e231-ae36-4741-b4e6-c8c8bca908a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511159707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.2511159707
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.2651504353
Short name T165
Test name
Test status
Simulation time 155202694 ps
CPU time 4.59 seconds
Started Aug 03 06:57:58 PM PDT 24
Finished Aug 03 06:58:03 PM PDT 24
Peak memory 241948 kb
Host smart-f6ca83cd-5320-4d5d-931b-4ecfb7ae6b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651504353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.2651504353
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.1009282510
Short name T1039
Test name
Test status
Simulation time 1681716668 ps
CPU time 11.69 seconds
Started Aug 03 06:57:59 PM PDT 24
Finished Aug 03 06:58:11 PM PDT 24
Peak memory 241988 kb
Host smart-a4d0dcfd-3234-4884-8724-b78b038b19a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009282510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.1009282510
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.90866157
Short name T681
Test name
Test status
Simulation time 519404160 ps
CPU time 3.71 seconds
Started Aug 03 06:58:04 PM PDT 24
Finished Aug 03 06:58:07 PM PDT 24
Peak memory 242196 kb
Host smart-b5ad9423-d089-4b38-901a-80334030e811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90866157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.90866157
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.2605170629
Short name T907
Test name
Test status
Simulation time 147931845 ps
CPU time 1.88 seconds
Started Aug 03 06:38:05 PM PDT 24
Finished Aug 03 06:38:07 PM PDT 24
Peak memory 240476 kb
Host smart-5e975a3d-51b8-4b61-867f-7e38faf68ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605170629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.2605170629
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.2894150054
Short name T599
Test name
Test status
Simulation time 15442891255 ps
CPU time 39.9 seconds
Started Aug 03 06:37:58 PM PDT 24
Finished Aug 03 06:38:38 PM PDT 24
Peak memory 246776 kb
Host smart-2f8df80a-21de-43c2-a1fd-73d873155432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894150054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.2894150054
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.3608400381
Short name T780
Test name
Test status
Simulation time 1175317568 ps
CPU time 13.39 seconds
Started Aug 03 06:37:58 PM PDT 24
Finished Aug 03 06:38:12 PM PDT 24
Peak memory 241948 kb
Host smart-e197c233-63ce-4f53-bf86-03811915c5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608400381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.3608400381
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.409153718
Short name T573
Test name
Test status
Simulation time 122636236 ps
CPU time 4.64 seconds
Started Aug 03 06:37:54 PM PDT 24
Finished Aug 03 06:37:58 PM PDT 24
Peak memory 241984 kb
Host smart-ae279765-e851-4528-a575-7537498ae308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409153718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.409153718
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.2124081342
Short name T660
Test name
Test status
Simulation time 1565196093 ps
CPU time 9.4 seconds
Started Aug 03 06:37:59 PM PDT 24
Finished Aug 03 06:38:09 PM PDT 24
Peak memory 242160 kb
Host smart-9a199091-866f-4671-a961-1bb3b6c40d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124081342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.2124081342
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.2807472130
Short name T812
Test name
Test status
Simulation time 2591275307 ps
CPU time 20.85 seconds
Started Aug 03 06:37:59 PM PDT 24
Finished Aug 03 06:38:20 PM PDT 24
Peak memory 248692 kb
Host smart-afe508ac-7b6a-480d-86e6-db64f47e373f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807472130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.2807472130
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.2768564258
Short name T686
Test name
Test status
Simulation time 4043532643 ps
CPU time 12.88 seconds
Started Aug 03 06:37:56 PM PDT 24
Finished Aug 03 06:38:09 PM PDT 24
Peak memory 241972 kb
Host smart-2eb49820-77db-4ecf-acbe-2e45cd0433d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768564258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.2768564258
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.2959549973
Short name T725
Test name
Test status
Simulation time 1417752638 ps
CPU time 12.52 seconds
Started Aug 03 06:37:55 PM PDT 24
Finished Aug 03 06:38:07 PM PDT 24
Peak memory 242400 kb
Host smart-ebb32b79-2bfd-411a-8b5d-6b6bf89db1ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2959549973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2959549973
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.312969384
Short name T916
Test name
Test status
Simulation time 628200668 ps
CPU time 5.8 seconds
Started Aug 03 06:37:58 PM PDT 24
Finished Aug 03 06:38:04 PM PDT 24
Peak memory 248528 kb
Host smart-523075b3-9c30-4472-93a0-2071332ae22d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312969384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.312969384
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.1624070
Short name T89
Test name
Test status
Simulation time 896376471 ps
CPU time 7.18 seconds
Started Aug 03 06:37:52 PM PDT 24
Finished Aug 03 06:37:59 PM PDT 24
Peak memory 242320 kb
Host smart-e0deca85-6586-41e5-8579-3d8df0d6ec4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.1624070
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.459470396
Short name T498
Test name
Test status
Simulation time 181380578 ps
CPU time 4.1 seconds
Started Aug 03 06:58:06 PM PDT 24
Finished Aug 03 06:58:10 PM PDT 24
Peak memory 241968 kb
Host smart-f3bc8e14-8d45-4205-b1d0-0d8229de8108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459470396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.459470396
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.3768140061
Short name T335
Test name
Test status
Simulation time 464308578 ps
CPU time 4.89 seconds
Started Aug 03 06:58:03 PM PDT 24
Finished Aug 03 06:58:08 PM PDT 24
Peak memory 241844 kb
Host smart-f6c89cc8-2919-4144-b766-b4c33bf4a0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768140061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3768140061
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.1853210061
Short name T518
Test name
Test status
Simulation time 610623473 ps
CPU time 5.07 seconds
Started Aug 03 06:58:05 PM PDT 24
Finished Aug 03 06:58:11 PM PDT 24
Peak memory 242184 kb
Host smart-23dc7551-086d-4d08-9f55-2cdd2da08107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853210061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.1853210061
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.1856587612
Short name T248
Test name
Test status
Simulation time 1382515067 ps
CPU time 4.77 seconds
Started Aug 03 06:58:09 PM PDT 24
Finished Aug 03 06:58:14 PM PDT 24
Peak memory 242240 kb
Host smart-09b866ee-2a4d-4361-a3f6-1534030c137a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856587612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.1856587612
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.1356250223
Short name T1176
Test name
Test status
Simulation time 561405829 ps
CPU time 4.89 seconds
Started Aug 03 06:58:10 PM PDT 24
Finished Aug 03 06:58:15 PM PDT 24
Peak memory 242152 kb
Host smart-8488f1ca-db84-485e-bf04-5cd93db8746b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356250223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.1356250223
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.57187556
Short name T666
Test name
Test status
Simulation time 1172150146 ps
CPU time 8.74 seconds
Started Aug 03 06:58:09 PM PDT 24
Finished Aug 03 06:58:18 PM PDT 24
Peak memory 242216 kb
Host smart-bc2fd4ef-f7da-437d-bd92-6611423d38b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57187556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.57187556
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.1587167952
Short name T777
Test name
Test status
Simulation time 267373692 ps
CPU time 3.91 seconds
Started Aug 03 06:58:13 PM PDT 24
Finished Aug 03 06:58:17 PM PDT 24
Peak memory 242012 kb
Host smart-db037414-88c7-4446-8650-99137b775444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587167952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1587167952
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.671132573
Short name T1188
Test name
Test status
Simulation time 1471904234 ps
CPU time 21.25 seconds
Started Aug 03 06:58:13 PM PDT 24
Finished Aug 03 06:58:34 PM PDT 24
Peak memory 242080 kb
Host smart-420b78ac-41d0-4705-bc01-876c901a1699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671132573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.671132573
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.189423302
Short name T586
Test name
Test status
Simulation time 130822415 ps
CPU time 4.18 seconds
Started Aug 03 06:58:14 PM PDT 24
Finished Aug 03 06:58:19 PM PDT 24
Peak memory 242312 kb
Host smart-51b7af55-75a9-4c50-9e9e-3faa1616341a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189423302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.189423302
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.283918519
Short name T336
Test name
Test status
Simulation time 1324997066 ps
CPU time 4.82 seconds
Started Aug 03 06:58:19 PM PDT 24
Finished Aug 03 06:58:23 PM PDT 24
Peak memory 242216 kb
Host smart-235754d2-2b2a-4d2b-b1d7-74a073168d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283918519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.283918519
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.861162621
Short name T1069
Test name
Test status
Simulation time 1642319453 ps
CPU time 5.18 seconds
Started Aug 03 06:58:20 PM PDT 24
Finished Aug 03 06:58:25 PM PDT 24
Peak memory 242208 kb
Host smart-ae9d37bd-1cdd-4c17-9bbd-28fed12317d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861162621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.861162621
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.711600055
Short name T239
Test name
Test status
Simulation time 144358654 ps
CPU time 3.86 seconds
Started Aug 03 06:58:19 PM PDT 24
Finished Aug 03 06:58:23 PM PDT 24
Peak memory 242072 kb
Host smart-9ef30a68-257b-4c33-a22f-1d8f0e04b641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711600055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.711600055
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.1176889389
Short name T654
Test name
Test status
Simulation time 473724665 ps
CPU time 4.47 seconds
Started Aug 03 06:58:19 PM PDT 24
Finished Aug 03 06:58:24 PM PDT 24
Peak memory 241952 kb
Host smart-22ccee45-fc0d-4709-844c-35c794764a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176889389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.1176889389
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.869148194
Short name T505
Test name
Test status
Simulation time 164726785 ps
CPU time 4.2 seconds
Started Aug 03 06:58:19 PM PDT 24
Finished Aug 03 06:58:23 PM PDT 24
Peak memory 241916 kb
Host smart-29356620-11ed-4e72-99fb-6d55e2e2da4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869148194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.869148194
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.1776008937
Short name T1080
Test name
Test status
Simulation time 526223779 ps
CPU time 3.73 seconds
Started Aug 03 06:58:18 PM PDT 24
Finished Aug 03 06:58:22 PM PDT 24
Peak memory 242252 kb
Host smart-786a3c22-2cb1-487d-bcee-013e00fd7c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776008937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.1776008937
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.3355995569
Short name T815
Test name
Test status
Simulation time 985657244 ps
CPU time 15 seconds
Started Aug 03 06:58:24 PM PDT 24
Finished Aug 03 06:58:39 PM PDT 24
Peak memory 241948 kb
Host smart-9fa219b4-bab1-4171-9c40-fe53b52950a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355995569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.3355995569
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.1254757686
Short name T73
Test name
Test status
Simulation time 2067431480 ps
CPU time 4.6 seconds
Started Aug 03 06:58:25 PM PDT 24
Finished Aug 03 06:58:29 PM PDT 24
Peak memory 241968 kb
Host smart-4f387b49-6d51-4862-985d-a6f04d7241de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254757686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1254757686
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.3475977703
Short name T727
Test name
Test status
Simulation time 733170000 ps
CPU time 8.98 seconds
Started Aug 03 06:58:25 PM PDT 24
Finished Aug 03 06:58:34 PM PDT 24
Peak memory 241872 kb
Host smart-e45d282b-435e-4c0e-9feb-f54b06a4295d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475977703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.3475977703
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.3245893944
Short name T1053
Test name
Test status
Simulation time 1596340450 ps
CPU time 4.53 seconds
Started Aug 03 06:58:25 PM PDT 24
Finished Aug 03 06:58:29 PM PDT 24
Peak memory 242236 kb
Host smart-2e7d5207-065e-44e8-b2e7-39b96fb5c8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245893944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.3245893944
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.3782301707
Short name T1017
Test name
Test status
Simulation time 646782590 ps
CPU time 8.53 seconds
Started Aug 03 06:58:24 PM PDT 24
Finished Aug 03 06:58:33 PM PDT 24
Peak memory 241844 kb
Host smart-ecc93d8e-9c00-4a45-8e9c-0c6ed8fb2c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782301707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.3782301707
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.3756402735
Short name T491
Test name
Test status
Simulation time 98127237 ps
CPU time 2 seconds
Started Aug 03 06:34:57 PM PDT 24
Finished Aug 03 06:34:59 PM PDT 24
Peak memory 240484 kb
Host smart-d3a77b40-bd54-4083-8bad-46d53f095f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756402735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.3756402735
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.1081040774
Short name T584
Test name
Test status
Simulation time 15790968395 ps
CPU time 29.39 seconds
Started Aug 03 06:34:40 PM PDT 24
Finished Aug 03 06:35:10 PM PDT 24
Peak memory 242548 kb
Host smart-48d7e2d1-40af-4a3c-8e8e-37f3b49d7187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081040774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.1081040774
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.4032536792
Short name T902
Test name
Test status
Simulation time 685485914 ps
CPU time 24.88 seconds
Started Aug 03 06:34:45 PM PDT 24
Finished Aug 03 06:35:10 PM PDT 24
Peak memory 248648 kb
Host smart-6455b1f5-d655-4e6c-8506-b3f2889be4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032536792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.4032536792
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.1766354682
Short name T801
Test name
Test status
Simulation time 1019423648 ps
CPU time 24.99 seconds
Started Aug 03 06:34:44 PM PDT 24
Finished Aug 03 06:35:09 PM PDT 24
Peak memory 242332 kb
Host smart-db1c2db1-9c12-44b3-b797-aa8885afd92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766354682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1766354682
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.1914371844
Short name T272
Test name
Test status
Simulation time 693631017 ps
CPU time 17.09 seconds
Started Aug 03 06:34:47 PM PDT 24
Finished Aug 03 06:35:04 PM PDT 24
Peak memory 248660 kb
Host smart-2e1f797c-9127-43ea-aef6-bbb734f9ed55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914371844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1914371844
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.2501463365
Short name T854
Test name
Test status
Simulation time 395632058 ps
CPU time 4.14 seconds
Started Aug 03 06:34:41 PM PDT 24
Finished Aug 03 06:34:45 PM PDT 24
Peak memory 242452 kb
Host smart-63eb74b2-f0f1-4c1b-8222-42f8e27c1910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501463365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.2501463365
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.1002330544
Short name T208
Test name
Test status
Simulation time 500969919 ps
CPU time 10.43 seconds
Started Aug 03 06:34:47 PM PDT 24
Finished Aug 03 06:34:58 PM PDT 24
Peak memory 242080 kb
Host smart-5525daa7-3abf-4257-b43c-920eb1d9bc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002330544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.1002330544
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.664499367
Short name T870
Test name
Test status
Simulation time 9938699889 ps
CPU time 35.91 seconds
Started Aug 03 06:34:47 PM PDT 24
Finished Aug 03 06:35:23 PM PDT 24
Peak memory 242880 kb
Host smart-6376382d-ef06-4283-bcb0-4e734d32bb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664499367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.664499367
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.1004486851
Short name T925
Test name
Test status
Simulation time 244048832 ps
CPU time 5.5 seconds
Started Aug 03 06:34:46 PM PDT 24
Finished Aug 03 06:34:51 PM PDT 24
Peak memory 241832 kb
Host smart-ce24cffd-edcb-450a-940a-b31a830599a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004486851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.1004486851
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.2393104998
Short name T403
Test name
Test status
Simulation time 166947344 ps
CPU time 4.89 seconds
Started Aug 03 06:34:47 PM PDT 24
Finished Aug 03 06:34:52 PM PDT 24
Peak memory 242136 kb
Host smart-e046c925-6502-4b73-9899-148bb798649c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2393104998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.2393104998
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.2528869978
Short name T368
Test name
Test status
Simulation time 144307403 ps
CPU time 5.17 seconds
Started Aug 03 06:34:53 PM PDT 24
Finished Aug 03 06:34:58 PM PDT 24
Peak memory 242076 kb
Host smart-25966e69-b742-4719-9310-f5ed02a9f4c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528869978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.2528869978
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.2242823093
Short name T1004
Test name
Test status
Simulation time 230535376 ps
CPU time 4.02 seconds
Started Aug 03 06:34:40 PM PDT 24
Finished Aug 03 06:34:44 PM PDT 24
Peak memory 248516 kb
Host smart-41d05016-3826-475f-bb9d-8d7af9400897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242823093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.2242823093
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.2138183088
Short name T284
Test name
Test status
Simulation time 247537611912 ps
CPU time 396.25 seconds
Started Aug 03 06:34:55 PM PDT 24
Finished Aug 03 06:41:32 PM PDT 24
Peak memory 262856 kb
Host smart-c35e601b-5275-4b5c-8ff4-222047e04487
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138183088 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.2138183088
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.2602799941
Short name T865
Test name
Test status
Simulation time 8607656414 ps
CPU time 82.59 seconds
Started Aug 03 06:34:55 PM PDT 24
Finished Aug 03 06:36:18 PM PDT 24
Peak memory 242168 kb
Host smart-96e495d3-e663-4560-915c-49491a45b0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602799941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.2602799941
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.506532901
Short name T814
Test name
Test status
Simulation time 4356078031 ps
CPU time 9.7 seconds
Started Aug 03 06:38:07 PM PDT 24
Finished Aug 03 06:38:17 PM PDT 24
Peak memory 242084 kb
Host smart-bb00d7df-0aa5-4c95-9b6a-712277002e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506532901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.506532901
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.863964037
Short name T915
Test name
Test status
Simulation time 480256974 ps
CPU time 12.93 seconds
Started Aug 03 06:38:08 PM PDT 24
Finished Aug 03 06:38:21 PM PDT 24
Peak memory 242328 kb
Host smart-b601228e-fd5c-4cae-b25a-7ff9a4a78eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863964037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.863964037
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.3540571152
Short name T820
Test name
Test status
Simulation time 657890290 ps
CPU time 13.85 seconds
Started Aug 03 06:38:08 PM PDT 24
Finished Aug 03 06:38:22 PM PDT 24
Peak memory 242008 kb
Host smart-48f2610e-bf1e-4e3f-8f5b-8d6dd9e02f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540571152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3540571152
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.1821512183
Short name T192
Test name
Test status
Simulation time 2403303149 ps
CPU time 7.68 seconds
Started Aug 03 06:38:03 PM PDT 24
Finished Aug 03 06:38:11 PM PDT 24
Peak memory 242280 kb
Host smart-6a573def-17ff-42f4-a576-a2416fa4226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821512183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.1821512183
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.3754701679
Short name T449
Test name
Test status
Simulation time 1234043888 ps
CPU time 25.51 seconds
Started Aug 03 06:38:09 PM PDT 24
Finished Aug 03 06:38:34 PM PDT 24
Peak memory 248628 kb
Host smart-0d0c70fa-683d-4ba5-8124-1a1708c7bd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754701679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.3754701679
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.2669236751
Short name T202
Test name
Test status
Simulation time 402929428 ps
CPU time 8.45 seconds
Started Aug 03 06:38:13 PM PDT 24
Finished Aug 03 06:38:22 PM PDT 24
Peak memory 242444 kb
Host smart-9b1795e1-3010-4a22-be83-621977226e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669236751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.2669236751
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.2952332568
Short name T173
Test name
Test status
Simulation time 2086986493 ps
CPU time 4.61 seconds
Started Aug 03 06:38:07 PM PDT 24
Finished Aug 03 06:38:12 PM PDT 24
Peak memory 242364 kb
Host smart-d71b89bc-7de1-4f4a-b5f8-2d8c64589b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952332568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.2952332568
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.3804492737
Short name T1107
Test name
Test status
Simulation time 6653606941 ps
CPU time 17.15 seconds
Started Aug 03 06:38:04 PM PDT 24
Finished Aug 03 06:38:21 PM PDT 24
Peak memory 242324 kb
Host smart-64594789-87eb-4184-87cd-a3fe73efba58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804492737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.3804492737
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.3832747638
Short name T373
Test name
Test status
Simulation time 254640110 ps
CPU time 7.77 seconds
Started Aug 03 06:38:11 PM PDT 24
Finished Aug 03 06:38:19 PM PDT 24
Peak memory 242208 kb
Host smart-b79816f0-151a-4f2f-a468-463683b4d74c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832747638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.3832747638
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.3090778205
Short name T847
Test name
Test status
Simulation time 1080668315 ps
CPU time 16.26 seconds
Started Aug 03 06:38:02 PM PDT 24
Finished Aug 03 06:38:19 PM PDT 24
Peak memory 248604 kb
Host smart-2bea4311-e8d4-4a31-83f2-0aa1cfdf5622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090778205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.3090778205
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.3157227624
Short name T399
Test name
Test status
Simulation time 7681916281 ps
CPU time 19.86 seconds
Started Aug 03 06:38:14 PM PDT 24
Finished Aug 03 06:38:34 PM PDT 24
Peak memory 242020 kb
Host smart-2f816b55-77bf-46fe-889d-e4c24f81cfec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157227624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.3157227624
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.1805702591
Short name T811
Test name
Test status
Simulation time 95921817713 ps
CPU time 576.64 seconds
Started Aug 03 06:38:14 PM PDT 24
Finished Aug 03 06:47:51 PM PDT 24
Peak memory 342040 kb
Host smart-39331cf2-d9c1-4530-81a1-e256b1de5115
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805702591 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.1805702591
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.3527160970
Short name T719
Test name
Test status
Simulation time 1428560029 ps
CPU time 22.19 seconds
Started Aug 03 06:38:13 PM PDT 24
Finished Aug 03 06:38:36 PM PDT 24
Peak memory 242340 kb
Host smart-618284ce-5e6e-4970-aa24-5fc3070ce481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527160970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.3527160970
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.3288119784
Short name T761
Test name
Test status
Simulation time 201225454 ps
CPU time 4.72 seconds
Started Aug 03 06:58:23 PM PDT 24
Finished Aug 03 06:58:28 PM PDT 24
Peak memory 241944 kb
Host smart-12dae6bc-5ef5-45e5-8ea1-0dc69d3ac72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288119784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3288119784
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.3409916939
Short name T927
Test name
Test status
Simulation time 604011491 ps
CPU time 4.85 seconds
Started Aug 03 06:58:24 PM PDT 24
Finished Aug 03 06:58:29 PM PDT 24
Peak memory 242172 kb
Host smart-fe2ae7ae-6fc9-4a9f-8ac8-166307c4f95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409916939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.3409916939
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.4041636635
Short name T930
Test name
Test status
Simulation time 2037778897 ps
CPU time 5.54 seconds
Started Aug 03 06:58:24 PM PDT 24
Finished Aug 03 06:58:29 PM PDT 24
Peak memory 242248 kb
Host smart-1ff6aad4-c279-4453-8482-8535db9595f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041636635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.4041636635
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.3450640282
Short name T1021
Test name
Test status
Simulation time 593618114 ps
CPU time 4.69 seconds
Started Aug 03 06:58:31 PM PDT 24
Finished Aug 03 06:58:35 PM PDT 24
Peak memory 242168 kb
Host smart-79ebab7d-9d0f-450f-bc7a-753ed67d2c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450640282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.3450640282
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.3192816340
Short name T68
Test name
Test status
Simulation time 262463202 ps
CPU time 4.5 seconds
Started Aug 03 06:58:31 PM PDT 24
Finished Aug 03 06:58:35 PM PDT 24
Peak memory 242188 kb
Host smart-241636c5-6a2f-460c-8692-a948561169b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192816340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.3192816340
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.3543124892
Short name T768
Test name
Test status
Simulation time 124265093 ps
CPU time 4.22 seconds
Started Aug 03 06:58:27 PM PDT 24
Finished Aug 03 06:58:31 PM PDT 24
Peak memory 241924 kb
Host smart-3e753c84-dbd6-4c0d-82f9-7658d60e96a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543124892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.3543124892
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.1186112130
Short name T127
Test name
Test status
Simulation time 146439653 ps
CPU time 4.87 seconds
Started Aug 03 06:58:32 PM PDT 24
Finished Aug 03 06:58:37 PM PDT 24
Peak memory 242376 kb
Host smart-d752751f-66c0-4547-945b-fdbbc5bf8ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186112130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.1186112130
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.1373382956
Short name T450
Test name
Test status
Simulation time 283060120 ps
CPU time 4.31 seconds
Started Aug 03 06:58:31 PM PDT 24
Finished Aug 03 06:58:36 PM PDT 24
Peak memory 242200 kb
Host smart-c6b81693-bfb5-45da-b848-333d312a8663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373382956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.1373382956
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.2045027681
Short name T1156
Test name
Test status
Simulation time 213521826 ps
CPU time 3.81 seconds
Started Aug 03 06:58:30 PM PDT 24
Finished Aug 03 06:58:34 PM PDT 24
Peak memory 242208 kb
Host smart-a1ab9c58-d5a9-4ddf-87f8-92e77d6d595f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045027681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.2045027681
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.2627118861
Short name T1089
Test name
Test status
Simulation time 263236912 ps
CPU time 4.47 seconds
Started Aug 03 06:58:29 PM PDT 24
Finished Aug 03 06:58:33 PM PDT 24
Peak memory 242396 kb
Host smart-24025ed7-f20b-4b3a-819b-8a23eac18659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627118861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.2627118861
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.3308258373
Short name T198
Test name
Test status
Simulation time 83703233 ps
CPU time 2.19 seconds
Started Aug 03 06:38:29 PM PDT 24
Finished Aug 03 06:38:31 PM PDT 24
Peak memory 240404 kb
Host smart-0344a22d-c656-4ded-a251-8e5c37aabe21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308258373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.3308258373
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.3621563625
Short name T1079
Test name
Test status
Simulation time 789385710 ps
CPU time 13.12 seconds
Started Aug 03 06:38:23 PM PDT 24
Finished Aug 03 06:38:36 PM PDT 24
Peak memory 242224 kb
Host smart-1f36c05c-5c7b-4970-b4d0-ffd01988b038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621563625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.3621563625
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.683867019
Short name T15
Test name
Test status
Simulation time 1011252445 ps
CPU time 12.28 seconds
Started Aug 03 06:38:22 PM PDT 24
Finished Aug 03 06:38:34 PM PDT 24
Peak memory 242004 kb
Host smart-29fb3d91-9b8a-4a0f-9e18-31c756236674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683867019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.683867019
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.1738039090
Short name T1129
Test name
Test status
Simulation time 21726403810 ps
CPU time 45.41 seconds
Started Aug 03 06:38:23 PM PDT 24
Finished Aug 03 06:39:09 PM PDT 24
Peak memory 248636 kb
Host smart-d42802fb-2a6b-41a1-89c2-d116ed84afcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738039090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1738039090
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.2193262619
Short name T594
Test name
Test status
Simulation time 2530879099 ps
CPU time 5.43 seconds
Started Aug 03 06:38:18 PM PDT 24
Finished Aug 03 06:38:23 PM PDT 24
Peak memory 242048 kb
Host smart-5aa5e19a-c6db-4c23-91a3-c12c70c29dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193262619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.2193262619
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.743021070
Short name T917
Test name
Test status
Simulation time 794418612 ps
CPU time 10.87 seconds
Started Aug 03 06:38:25 PM PDT 24
Finished Aug 03 06:38:36 PM PDT 24
Peak memory 243120 kb
Host smart-05fddc23-b80e-43de-a72e-f3bcad88ca39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743021070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.743021070
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.998903345
Short name T513
Test name
Test status
Simulation time 1140918394 ps
CPU time 23.04 seconds
Started Aug 03 06:38:25 PM PDT 24
Finished Aug 03 06:38:48 PM PDT 24
Peak memory 242364 kb
Host smart-64c22de9-8e43-4e85-8052-17eb4fc9affa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998903345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.998903345
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.4072283652
Short name T884
Test name
Test status
Simulation time 391859093 ps
CPU time 5.95 seconds
Started Aug 03 06:38:24 PM PDT 24
Finished Aug 03 06:38:30 PM PDT 24
Peak memory 241968 kb
Host smart-f8210a2d-7382-4fda-a117-98443fcae72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072283652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.4072283652
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.313193064
Short name T957
Test name
Test status
Simulation time 7193711032 ps
CPU time 17.13 seconds
Started Aug 03 06:38:23 PM PDT 24
Finished Aug 03 06:38:40 PM PDT 24
Peak memory 241996 kb
Host smart-075f8352-3f88-4641-9dec-836508dd4f1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313193064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.313193064
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.1128937382
Short name T473
Test name
Test status
Simulation time 1222127335 ps
CPU time 13.34 seconds
Started Aug 03 06:38:28 PM PDT 24
Finished Aug 03 06:38:42 PM PDT 24
Peak memory 242252 kb
Host smart-cb5f3022-7d63-4ac1-9c11-1a26bf24947a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1128937382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.1128937382
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.427813355
Short name T886
Test name
Test status
Simulation time 497981986 ps
CPU time 7.58 seconds
Started Aug 03 06:38:17 PM PDT 24
Finished Aug 03 06:38:25 PM PDT 24
Peak memory 241984 kb
Host smart-5355e57f-b85b-4da5-b9f2-855eba90b742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427813355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.427813355
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.4259504734
Short name T349
Test name
Test status
Simulation time 12852285016 ps
CPU time 182.96 seconds
Started Aug 03 06:38:30 PM PDT 24
Finished Aug 03 06:41:33 PM PDT 24
Peak memory 260060 kb
Host smart-c7dd7306-41c3-4139-8c45-615e9c6d558d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259504734 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.4259504734
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.2382491814
Short name T673
Test name
Test status
Simulation time 7188852853 ps
CPU time 21.47 seconds
Started Aug 03 06:38:28 PM PDT 24
Finished Aug 03 06:38:50 PM PDT 24
Peak memory 242196 kb
Host smart-b7a22c42-4e05-493e-9004-82fe15ff0ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382491814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.2382491814
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.3902159417
Short name T122
Test name
Test status
Simulation time 445045915 ps
CPU time 3.86 seconds
Started Aug 03 06:58:32 PM PDT 24
Finished Aug 03 06:58:36 PM PDT 24
Peak memory 242360 kb
Host smart-c01719af-5619-43a2-9a05-cfa5ac49bece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902159417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.3902159417
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.460447690
Short name T999
Test name
Test status
Simulation time 130401711 ps
CPU time 4.11 seconds
Started Aug 03 06:58:33 PM PDT 24
Finished Aug 03 06:58:37 PM PDT 24
Peak memory 242312 kb
Host smart-895e2d08-654e-496f-99a0-194c8a95bec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460447690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.460447690
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.88761801
Short name T816
Test name
Test status
Simulation time 314671943 ps
CPU time 4.33 seconds
Started Aug 03 06:58:34 PM PDT 24
Finished Aug 03 06:58:39 PM PDT 24
Peak memory 242012 kb
Host smart-c48876e9-210b-4c6f-9092-ad9b39c3fdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88761801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.88761801
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.1750604288
Short name T943
Test name
Test status
Simulation time 423535159 ps
CPU time 4.61 seconds
Started Aug 03 06:58:39 PM PDT 24
Finished Aug 03 06:58:44 PM PDT 24
Peak memory 242144 kb
Host smart-7d45406c-f7e2-45b2-98fa-52d94f587e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750604288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.1750604288
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.3869461746
Short name T771
Test name
Test status
Simulation time 467346406 ps
CPU time 3.71 seconds
Started Aug 03 06:58:38 PM PDT 24
Finished Aug 03 06:58:42 PM PDT 24
Peak memory 241872 kb
Host smart-3ff00e8e-58dd-4851-97aa-964a9697766c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869461746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.3869461746
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.3065706118
Short name T110
Test name
Test status
Simulation time 451535682 ps
CPU time 4.29 seconds
Started Aug 03 06:58:35 PM PDT 24
Finished Aug 03 06:58:39 PM PDT 24
Peak memory 242248 kb
Host smart-4a618f31-fd8d-4d5b-a4c6-f8bde6378633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065706118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.3065706118
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.1773165034
Short name T808
Test name
Test status
Simulation time 120897457 ps
CPU time 4.04 seconds
Started Aug 03 06:58:39 PM PDT 24
Finished Aug 03 06:58:43 PM PDT 24
Peak memory 241888 kb
Host smart-358338ed-e9ff-4551-846f-19809a6f2fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773165034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.1773165034
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.2892621556
Short name T1026
Test name
Test status
Simulation time 150679446 ps
CPU time 4.03 seconds
Started Aug 03 06:58:39 PM PDT 24
Finished Aug 03 06:58:43 PM PDT 24
Peak memory 242016 kb
Host smart-77c9f684-d442-4ede-84e1-0c1dab0d288f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892621556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2892621556
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.2446749037
Short name T793
Test name
Test status
Simulation time 389083934 ps
CPU time 4.75 seconds
Started Aug 03 06:58:35 PM PDT 24
Finished Aug 03 06:58:40 PM PDT 24
Peak memory 242008 kb
Host smart-f658eb39-14c7-43fe-b103-237bb71b2500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446749037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.2446749037
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.1850333719
Short name T66
Test name
Test status
Simulation time 1791488764 ps
CPU time 5.56 seconds
Started Aug 03 06:58:34 PM PDT 24
Finished Aug 03 06:58:40 PM PDT 24
Peak memory 242188 kb
Host smart-1190f4ce-2ca3-4bc1-9232-93329bb965a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850333719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.1850333719
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.975281477
Short name T400
Test name
Test status
Simulation time 236393703 ps
CPU time 2.21 seconds
Started Aug 03 06:38:40 PM PDT 24
Finished Aug 03 06:38:42 PM PDT 24
Peak memory 240536 kb
Host smart-df688a66-0364-4f17-9eaa-a21758aeb2fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975281477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.975281477
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.3215804964
Short name T125
Test name
Test status
Simulation time 1244728878 ps
CPU time 18.89 seconds
Started Aug 03 06:38:41 PM PDT 24
Finished Aug 03 06:39:00 PM PDT 24
Peak memory 242432 kb
Host smart-8810ec32-1866-4b35-95ba-63715d512539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215804964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.3215804964
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.2854750758
Short name T434
Test name
Test status
Simulation time 1252314408 ps
CPU time 18.41 seconds
Started Aug 03 06:38:41 PM PDT 24
Finished Aug 03 06:39:00 PM PDT 24
Peak memory 241980 kb
Host smart-9c2f004e-944c-4e84-9531-e66e45293e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854750758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.2854750758
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.1915129052
Short name T237
Test name
Test status
Simulation time 520839586 ps
CPU time 4.97 seconds
Started Aug 03 06:38:39 PM PDT 24
Finished Aug 03 06:38:44 PM PDT 24
Peak memory 242296 kb
Host smart-a83b3ac0-d23d-4084-986f-68b32987c1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915129052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.1915129052
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.3025362831
Short name T737
Test name
Test status
Simulation time 283390170 ps
CPU time 5.26 seconds
Started Aug 03 06:38:37 PM PDT 24
Finished Aug 03 06:38:42 PM PDT 24
Peak memory 242036 kb
Host smart-a23b3f4a-c15a-4b4e-b5f9-d65e252b46b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025362831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3025362831
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.114328101
Short name T822
Test name
Test status
Simulation time 12852663171 ps
CPU time 32.26 seconds
Started Aug 03 06:38:38 PM PDT 24
Finished Aug 03 06:39:11 PM PDT 24
Peak memory 244936 kb
Host smart-191b8433-048e-4d36-bda5-a2a808f5ec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114328101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.114328101
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.286550410
Short name T101
Test name
Test status
Simulation time 6660776689 ps
CPU time 52.2 seconds
Started Aug 03 06:38:40 PM PDT 24
Finished Aug 03 06:39:33 PM PDT 24
Peak memory 242464 kb
Host smart-35dc0431-dbdb-48b4-947d-f673c0cdbcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286550410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.286550410
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.2170373745
Short name T181
Test name
Test status
Simulation time 973314704 ps
CPU time 7.1 seconds
Started Aug 03 06:38:36 PM PDT 24
Finished Aug 03 06:38:44 PM PDT 24
Peak memory 242392 kb
Host smart-5e079c22-8c05-4106-a48f-42dae6ec268a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170373745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.2170373745
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.2506329342
Short name T529
Test name
Test status
Simulation time 728236621 ps
CPU time 21.29 seconds
Started Aug 03 06:38:40 PM PDT 24
Finished Aug 03 06:39:01 PM PDT 24
Peak memory 248632 kb
Host smart-8c20b1ca-ccad-4e1c-abb8-3678eed485e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2506329342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.2506329342
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.169003776
Short name T425
Test name
Test status
Simulation time 143268489 ps
CPU time 5.01 seconds
Started Aug 03 06:38:40 PM PDT 24
Finished Aug 03 06:38:45 PM PDT 24
Peak memory 242192 kb
Host smart-313206c7-bac8-4284-b9fe-f52667ae902c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169003776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.169003776
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.728743628
Short name T889
Test name
Test status
Simulation time 3478880356 ps
CPU time 9.81 seconds
Started Aug 03 06:38:37 PM PDT 24
Finished Aug 03 06:38:47 PM PDT 24
Peak memory 242388 kb
Host smart-a69fb3fc-84c0-44e6-be31-57333b716f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728743628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.728743628
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.1334134376
Short name T218
Test name
Test status
Simulation time 18493182659 ps
CPU time 224.9 seconds
Started Aug 03 06:38:38 PM PDT 24
Finished Aug 03 06:42:23 PM PDT 24
Peak memory 256972 kb
Host smart-46260091-5371-475a-be04-35733d35e07e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334134376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.1334134376
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.208006638
Short name T1072
Test name
Test status
Simulation time 1324428832 ps
CPU time 22.23 seconds
Started Aug 03 06:38:39 PM PDT 24
Finished Aug 03 06:39:02 PM PDT 24
Peak memory 242108 kb
Host smart-26511249-5d3f-4acf-826e-162f59fa4fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208006638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.208006638
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.3229157050
Short name T496
Test name
Test status
Simulation time 191572974 ps
CPU time 4.13 seconds
Started Aug 03 06:58:39 PM PDT 24
Finished Aug 03 06:58:43 PM PDT 24
Peak memory 242216 kb
Host smart-4ecd9ee2-7c57-4ccb-846c-429381728017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229157050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.3229157050
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.563056783
Short name T1064
Test name
Test status
Simulation time 234270984 ps
CPU time 4.64 seconds
Started Aug 03 06:58:39 PM PDT 24
Finished Aug 03 06:58:44 PM PDT 24
Peak memory 241948 kb
Host smart-8e881322-ba5b-4daa-afa8-cba6df18f6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563056783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.563056783
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.2676728778
Short name T189
Test name
Test status
Simulation time 120719501 ps
CPU time 3.85 seconds
Started Aug 03 06:58:39 PM PDT 24
Finished Aug 03 06:58:43 PM PDT 24
Peak memory 241928 kb
Host smart-e00ff26e-3077-4b08-af86-b542210d0841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676728778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.2676728778
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.491932276
Short name T1054
Test name
Test status
Simulation time 268546260 ps
CPU time 4.11 seconds
Started Aug 03 06:58:39 PM PDT 24
Finished Aug 03 06:58:43 PM PDT 24
Peak memory 242008 kb
Host smart-45b3d192-ba5a-457d-a989-8fcf96b44545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491932276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.491932276
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.303234480
Short name T109
Test name
Test status
Simulation time 121150725 ps
CPU time 3.64 seconds
Started Aug 03 06:58:39 PM PDT 24
Finished Aug 03 06:58:43 PM PDT 24
Peak memory 242112 kb
Host smart-0a481c7d-8216-449f-924b-7d2852e03be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303234480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.303234480
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.2246083710
Short name T1049
Test name
Test status
Simulation time 449610768 ps
CPU time 3.84 seconds
Started Aug 03 06:58:38 PM PDT 24
Finished Aug 03 06:58:42 PM PDT 24
Peak memory 242404 kb
Host smart-fc650e81-0dc2-4ec8-9423-eaec9e63abad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246083710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2246083710
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.2263570165
Short name T1157
Test name
Test status
Simulation time 127513787 ps
CPU time 3.68 seconds
Started Aug 03 06:58:40 PM PDT 24
Finished Aug 03 06:58:43 PM PDT 24
Peak memory 241876 kb
Host smart-5ec18a59-e911-420e-9850-856b13996b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263570165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.2263570165
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.3677201651
Short name T1098
Test name
Test status
Simulation time 752315556 ps
CPU time 5.04 seconds
Started Aug 03 06:58:39 PM PDT 24
Finished Aug 03 06:58:44 PM PDT 24
Peak memory 242172 kb
Host smart-bad40b22-d259-4c28-b4fe-1189e8ddf337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677201651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.3677201651
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.2341187089
Short name T32
Test name
Test status
Simulation time 325148102 ps
CPU time 3.57 seconds
Started Aug 03 06:58:43 PM PDT 24
Finished Aug 03 06:58:46 PM PDT 24
Peak memory 242192 kb
Host smart-968db5e6-53dd-4d26-b05a-368d26a71e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341187089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.2341187089
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.1174272338
Short name T980
Test name
Test status
Simulation time 335993171 ps
CPU time 4.27 seconds
Started Aug 03 06:58:43 PM PDT 24
Finished Aug 03 06:58:48 PM PDT 24
Peak memory 242212 kb
Host smart-b99bab57-22f5-4588-8b13-87466d3b7c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174272338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.1174272338
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.1689074949
Short name T972
Test name
Test status
Simulation time 791801001 ps
CPU time 2.23 seconds
Started Aug 03 06:39:00 PM PDT 24
Finished Aug 03 06:39:03 PM PDT 24
Peak memory 240520 kb
Host smart-c750be9b-1675-4444-9971-0c446a7ca904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689074949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.1689074949
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.3963519411
Short name T837
Test name
Test status
Simulation time 1110891873 ps
CPU time 14.11 seconds
Started Aug 03 06:38:42 PM PDT 24
Finished Aug 03 06:38:56 PM PDT 24
Peak memory 242332 kb
Host smart-68dd8585-87aa-456c-abe2-ac3d0f37abf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963519411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3963519411
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.3301876931
Short name T664
Test name
Test status
Simulation time 4001529252 ps
CPU time 39.05 seconds
Started Aug 03 06:38:48 PM PDT 24
Finished Aug 03 06:39:27 PM PDT 24
Peak memory 242060 kb
Host smart-2bbe0c43-31e8-495f-a797-f2f0639f9f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301876931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.3301876931
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.1039350493
Short name T874
Test name
Test status
Simulation time 180224542 ps
CPU time 4.69 seconds
Started Aug 03 06:38:43 PM PDT 24
Finished Aug 03 06:38:48 PM PDT 24
Peak memory 242128 kb
Host smart-87f40dea-89f7-4015-9ce0-4fcd33e315f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039350493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.1039350493
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.3551245606
Short name T504
Test name
Test status
Simulation time 965214226 ps
CPU time 16.91 seconds
Started Aug 03 06:38:52 PM PDT 24
Finished Aug 03 06:39:08 PM PDT 24
Peak memory 248584 kb
Host smart-35a46656-4b3c-4734-b584-02f800c62ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551245606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3551245606
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.473652549
Short name T551
Test name
Test status
Simulation time 217649822 ps
CPU time 7.73 seconds
Started Aug 03 06:38:52 PM PDT 24
Finished Aug 03 06:38:59 PM PDT 24
Peak memory 242112 kb
Host smart-acc2732d-8e9a-4b88-8248-aa7859468e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473652549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.473652549
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.2276928301
Short name T285
Test name
Test status
Simulation time 160989864 ps
CPU time 5.38 seconds
Started Aug 03 06:38:45 PM PDT 24
Finished Aug 03 06:38:50 PM PDT 24
Peak memory 242172 kb
Host smart-06634cb7-50b0-40ac-b183-fce513b0925e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2276928301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.2276928301
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.3080179098
Short name T593
Test name
Test status
Simulation time 430447067 ps
CPU time 3.49 seconds
Started Aug 03 06:38:50 PM PDT 24
Finished Aug 03 06:38:53 PM PDT 24
Peak memory 242048 kb
Host smart-41e07da3-e7a0-4e49-989d-6b928acfe7c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080179098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.3080179098
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.2184711230
Short name T1034
Test name
Test status
Simulation time 4056654057 ps
CPU time 7.19 seconds
Started Aug 03 06:38:38 PM PDT 24
Finished Aug 03 06:38:46 PM PDT 24
Peak memory 242488 kb
Host smart-da709b1e-e9bd-473d-9874-c50356db93fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184711230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2184711230
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.3208076386
Short name T625
Test name
Test status
Simulation time 1234221301 ps
CPU time 13.92 seconds
Started Aug 03 06:38:56 PM PDT 24
Finished Aug 03 06:39:10 PM PDT 24
Peak memory 242084 kb
Host smart-c8bf6f67-a46f-4cf2-b942-71ac2d5ad16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208076386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3208076386
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.3701404109
Short name T595
Test name
Test status
Simulation time 343098448 ps
CPU time 3.92 seconds
Started Aug 03 06:58:42 PM PDT 24
Finished Aug 03 06:58:46 PM PDT 24
Peak memory 242100 kb
Host smart-7b614ff0-ce66-4834-b05f-de9bc4940902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701404109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.3701404109
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.1404620497
Short name T632
Test name
Test status
Simulation time 2268942710 ps
CPU time 7.44 seconds
Started Aug 03 06:58:44 PM PDT 24
Finished Aug 03 06:58:51 PM PDT 24
Peak memory 242252 kb
Host smart-d93a322a-6971-467c-9e49-21c9f6a9d15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404620497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.1404620497
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.3781694033
Short name T559
Test name
Test status
Simulation time 149131046 ps
CPU time 3.82 seconds
Started Aug 03 06:58:44 PM PDT 24
Finished Aug 03 06:58:48 PM PDT 24
Peak memory 241976 kb
Host smart-7bee6776-0a4a-4e7f-9a46-e35f7efe2631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781694033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.3781694033
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.2923939686
Short name T545
Test name
Test status
Simulation time 162714370 ps
CPU time 3.95 seconds
Started Aug 03 06:58:43 PM PDT 24
Finished Aug 03 06:58:47 PM PDT 24
Peak memory 241900 kb
Host smart-575a54f2-b990-4fc0-9bc0-84ee3b4e58be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923939686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.2923939686
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.4021970272
Short name T598
Test name
Test status
Simulation time 248697826 ps
CPU time 3.6 seconds
Started Aug 03 06:58:50 PM PDT 24
Finished Aug 03 06:58:53 PM PDT 24
Peak memory 242248 kb
Host smart-685e37d5-75e3-4f11-a07c-4cc532c336f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021970272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.4021970272
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.1905147556
Short name T1120
Test name
Test status
Simulation time 231774874 ps
CPU time 4.54 seconds
Started Aug 03 06:58:49 PM PDT 24
Finished Aug 03 06:58:53 PM PDT 24
Peak memory 242132 kb
Host smart-c6c66052-f0cd-44b6-b84e-dc0f7ca9b88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905147556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.1905147556
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.4155445627
Short name T532
Test name
Test status
Simulation time 278462868 ps
CPU time 5.21 seconds
Started Aug 03 06:58:49 PM PDT 24
Finished Aug 03 06:58:55 PM PDT 24
Peak memory 241956 kb
Host smart-d581e529-6eba-49dd-913f-df1c0cb81168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155445627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.4155445627
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.812965832
Short name T569
Test name
Test status
Simulation time 106835273 ps
CPU time 2.19 seconds
Started Aug 03 06:39:05 PM PDT 24
Finished Aug 03 06:39:08 PM PDT 24
Peak memory 240356 kb
Host smart-80d40806-5dd7-4de1-991e-5fdd45ec01ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812965832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.812965832
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.1491496289
Short name T852
Test name
Test status
Simulation time 552699832 ps
CPU time 7.32 seconds
Started Aug 03 06:39:00 PM PDT 24
Finished Aug 03 06:39:07 PM PDT 24
Peak memory 242320 kb
Host smart-3d51c046-9b19-4ae8-910e-b6afd3a115f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491496289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1491496289
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.4208823284
Short name T1083
Test name
Test status
Simulation time 1143762843 ps
CPU time 18.64 seconds
Started Aug 03 06:38:59 PM PDT 24
Finished Aug 03 06:39:18 PM PDT 24
Peak memory 241928 kb
Host smart-6d7310c9-fba2-48bc-90b9-de58782f04f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208823284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.4208823284
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.2152440921
Short name T565
Test name
Test status
Simulation time 11546963224 ps
CPU time 16.4 seconds
Started Aug 03 06:38:58 PM PDT 24
Finished Aug 03 06:39:15 PM PDT 24
Peak memory 243316 kb
Host smart-1d4f6346-8590-4f0b-a281-65ccda5980b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152440921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.2152440921
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.414078866
Short name T475
Test name
Test status
Simulation time 354660896 ps
CPU time 5.89 seconds
Started Aug 03 06:38:58 PM PDT 24
Finished Aug 03 06:39:04 PM PDT 24
Peak memory 242000 kb
Host smart-2dcdc8da-607b-4f48-b1a8-67d7f9a5d258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414078866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.414078866
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.240009279
Short name T555
Test name
Test status
Simulation time 1586650902 ps
CPU time 19.66 seconds
Started Aug 03 06:39:08 PM PDT 24
Finished Aug 03 06:39:28 PM PDT 24
Peak memory 242136 kb
Host smart-15a09dcf-8444-4b3a-afe3-145b0ece298d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240009279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.240009279
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.135042167
Short name T601
Test name
Test status
Simulation time 260690953 ps
CPU time 6.87 seconds
Started Aug 03 06:38:55 PM PDT 24
Finished Aug 03 06:39:01 PM PDT 24
Peak memory 242360 kb
Host smart-8306b535-c407-4135-9b99-5631cb371531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135042167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.135042167
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.209665276
Short name T1
Test name
Test status
Simulation time 5084806392 ps
CPU time 13.15 seconds
Started Aug 03 06:38:55 PM PDT 24
Finished Aug 03 06:39:08 PM PDT 24
Peak memory 242148 kb
Host smart-29a382f2-678c-4dd7-825e-cfd94edbfe5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209665276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.209665276
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.1651650379
Short name T952
Test name
Test status
Simulation time 188024013 ps
CPU time 3.71 seconds
Started Aug 03 06:39:06 PM PDT 24
Finished Aug 03 06:39:09 PM PDT 24
Peak memory 241868 kb
Host smart-6c0a93b3-2587-483d-a7af-79099693a3f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651650379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.1651650379
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.2075205246
Short name T338
Test name
Test status
Simulation time 481561565673 ps
CPU time 1163.59 seconds
Started Aug 03 06:39:10 PM PDT 24
Finished Aug 03 06:58:33 PM PDT 24
Peak memory 274260 kb
Host smart-3c161e0a-7f3e-4827-9312-66821918d994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075205246 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.2075205246
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.640583412
Short name T385
Test name
Test status
Simulation time 2623586447 ps
CPU time 25.79 seconds
Started Aug 03 06:39:05 PM PDT 24
Finished Aug 03 06:39:31 PM PDT 24
Peak memory 248624 kb
Host smart-03e36a1f-670a-4aee-b84b-1b694850dfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640583412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.640583412
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.2927690159
Short name T741
Test name
Test status
Simulation time 201700242 ps
CPU time 3.89 seconds
Started Aug 03 06:58:48 PM PDT 24
Finished Aug 03 06:58:52 PM PDT 24
Peak memory 242004 kb
Host smart-a943e7d0-9294-45e8-87aa-4838ae8885ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927690159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.2927690159
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.368551686
Short name T61
Test name
Test status
Simulation time 302162166 ps
CPU time 4.91 seconds
Started Aug 03 06:58:48 PM PDT 24
Finished Aug 03 06:58:53 PM PDT 24
Peak memory 242172 kb
Host smart-123054df-b127-4443-97c1-aba72a083314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368551686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.368551686
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.2963641475
Short name T711
Test name
Test status
Simulation time 150127827 ps
CPU time 4.15 seconds
Started Aug 03 06:58:51 PM PDT 24
Finished Aug 03 06:58:55 PM PDT 24
Peak memory 241968 kb
Host smart-897d0299-bffa-46cf-bfb1-25b3ab9e3d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963641475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.2963641475
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.3203201222
Short name T227
Test name
Test status
Simulation time 195081570 ps
CPU time 4.32 seconds
Started Aug 03 06:58:51 PM PDT 24
Finished Aug 03 06:58:55 PM PDT 24
Peak memory 242416 kb
Host smart-acdb1490-a981-41c4-83c2-d1b782d3c00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203201222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.3203201222
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.1520799793
Short name T644
Test name
Test status
Simulation time 201121128 ps
CPU time 3.25 seconds
Started Aug 03 06:58:53 PM PDT 24
Finished Aug 03 06:58:56 PM PDT 24
Peak memory 241980 kb
Host smart-b6ac3c03-92ed-4b8b-b646-c259c0a0afec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520799793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.1520799793
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.1001385852
Short name T680
Test name
Test status
Simulation time 327126523 ps
CPU time 4.43 seconds
Started Aug 03 06:58:53 PM PDT 24
Finished Aug 03 06:58:58 PM PDT 24
Peak memory 242232 kb
Host smart-de6d918c-5dc2-4ae4-9ef2-7d29139a2a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001385852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.1001385852
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.1380899502
Short name T511
Test name
Test status
Simulation time 336179032 ps
CPU time 3.74 seconds
Started Aug 03 06:58:54 PM PDT 24
Finished Aug 03 06:58:58 PM PDT 24
Peak memory 241984 kb
Host smart-e28384e6-680e-4884-bfdf-76019a2887e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380899502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1380899502
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.138756677
Short name T413
Test name
Test status
Simulation time 227721192 ps
CPU time 4.25 seconds
Started Aug 03 06:58:59 PM PDT 24
Finished Aug 03 06:59:03 PM PDT 24
Peak memory 242252 kb
Host smart-cfc6d4c0-10ff-484f-9189-0dbb264ec351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138756677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.138756677
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.698912134
Short name T1181
Test name
Test status
Simulation time 113556513 ps
CPU time 4.22 seconds
Started Aug 03 06:58:58 PM PDT 24
Finished Aug 03 06:59:02 PM PDT 24
Peak memory 242196 kb
Host smart-84ce2bda-3ee5-422e-9e55-977e1d7e91bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698912134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.698912134
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.1622015921
Short name T180
Test name
Test status
Simulation time 168866092 ps
CPU time 4.6 seconds
Started Aug 03 06:58:59 PM PDT 24
Finished Aug 03 06:59:04 PM PDT 24
Peak memory 242356 kb
Host smart-f0dbb341-70d0-41ab-95f3-6cdedc258c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622015921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.1622015921
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.1396635760
Short name T493
Test name
Test status
Simulation time 45781100 ps
CPU time 1.58 seconds
Started Aug 03 06:39:21 PM PDT 24
Finished Aug 03 06:39:22 PM PDT 24
Peak memory 240300 kb
Host smart-f2ea4ad5-5e99-4a31-ad79-9683f1d6c329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396635760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1396635760
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.778973719
Short name T29
Test name
Test status
Simulation time 4029751135 ps
CPU time 14.34 seconds
Started Aug 03 06:39:14 PM PDT 24
Finished Aug 03 06:39:28 PM PDT 24
Peak memory 248628 kb
Host smart-fe5d62c5-dbb0-4401-ab11-70546c5fd5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778973719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.778973719
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.1477641242
Short name T992
Test name
Test status
Simulation time 826839994 ps
CPU time 13.22 seconds
Started Aug 03 06:39:12 PM PDT 24
Finished Aug 03 06:39:26 PM PDT 24
Peak memory 241936 kb
Host smart-4f6c95b9-0013-4e11-bdf0-3f47795838d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477641242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.1477641242
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.3344811072
Short name T781
Test name
Test status
Simulation time 8781297563 ps
CPU time 12.56 seconds
Started Aug 03 06:39:12 PM PDT 24
Finished Aug 03 06:39:24 PM PDT 24
Peak memory 242912 kb
Host smart-8fbba00a-7e44-4cb5-b092-98a8b12f0df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344811072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.3344811072
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.1148693278
Short name T950
Test name
Test status
Simulation time 92432863 ps
CPU time 3.24 seconds
Started Aug 03 06:39:13 PM PDT 24
Finished Aug 03 06:39:16 PM PDT 24
Peak memory 241864 kb
Host smart-642c3bb7-7e9d-4a97-8441-a5b88fa7f0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148693278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1148693278
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.913552772
Short name T949
Test name
Test status
Simulation time 2392979928 ps
CPU time 28.75 seconds
Started Aug 03 06:39:13 PM PDT 24
Finished Aug 03 06:39:42 PM PDT 24
Peak memory 245588 kb
Host smart-bc1077e3-59ba-4dab-a280-cc49b91db172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913552772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.913552772
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.1600699538
Short name T937
Test name
Test status
Simulation time 1185338409 ps
CPU time 34.4 seconds
Started Aug 03 06:39:16 PM PDT 24
Finished Aug 03 06:39:51 PM PDT 24
Peak memory 248576 kb
Host smart-61b74297-ad95-481d-926f-797988f96382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600699538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.1600699538
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.532771445
Short name T245
Test name
Test status
Simulation time 102042298 ps
CPU time 2.81 seconds
Started Aug 03 06:39:13 PM PDT 24
Finished Aug 03 06:39:16 PM PDT 24
Peak memory 241960 kb
Host smart-d8bcca47-a849-4fd4-b2c5-a6b69c00c71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532771445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.532771445
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.1813269914
Short name T982
Test name
Test status
Simulation time 12011379989 ps
CPU time 34.6 seconds
Started Aug 03 06:39:12 PM PDT 24
Finished Aug 03 06:39:47 PM PDT 24
Peak memory 241968 kb
Host smart-67794f7d-659d-49c0-96ea-8605d216a84b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1813269914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.1813269914
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.24029829
Short name T1139
Test name
Test status
Simulation time 987402510 ps
CPU time 8.88 seconds
Started Aug 03 06:39:19 PM PDT 24
Finished Aug 03 06:39:28 PM PDT 24
Peak memory 248592 kb
Host smart-e9ce4dd1-ca34-4704-aab0-f30ed58da94a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24029829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.24029829
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.3622819658
Short name T556
Test name
Test status
Simulation time 3992062777 ps
CPU time 10 seconds
Started Aug 03 06:39:15 PM PDT 24
Finished Aug 03 06:39:25 PM PDT 24
Peak memory 248672 kb
Host smart-a45d8977-225f-4ed1-88f5-57f1b5fe39f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622819658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.3622819658
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.3422020149
Short name T1024
Test name
Test status
Simulation time 45227336904 ps
CPU time 226.45 seconds
Started Aug 03 06:39:20 PM PDT 24
Finished Aug 03 06:43:07 PM PDT 24
Peak memory 267176 kb
Host smart-f9f629a8-4902-42ee-aa35-e2d2430c96cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422020149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.3422020149
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.1415139254
Short name T341
Test name
Test status
Simulation time 30662001062 ps
CPU time 734.7 seconds
Started Aug 03 06:39:18 PM PDT 24
Finished Aug 03 06:51:33 PM PDT 24
Peak memory 248760 kb
Host smart-c2955e33-46a7-4a7c-a1b9-0452ef2beefb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415139254 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.1415139254
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.4192680396
Short name T1161
Test name
Test status
Simulation time 1303405160 ps
CPU time 22.44 seconds
Started Aug 03 06:39:20 PM PDT 24
Finished Aug 03 06:39:42 PM PDT 24
Peak memory 242264 kb
Host smart-fa9af2eb-17e8-459f-a62e-b05689d7dbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192680396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.4192680396
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.2621782981
Short name T27
Test name
Test status
Simulation time 356700482 ps
CPU time 3.86 seconds
Started Aug 03 06:58:58 PM PDT 24
Finished Aug 03 06:59:02 PM PDT 24
Peak memory 241936 kb
Host smart-1b0f2b82-05bd-42bf-bb06-b8851cafe9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621782981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.2621782981
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.62045391
Short name T563
Test name
Test status
Simulation time 674612319 ps
CPU time 5.01 seconds
Started Aug 03 06:59:00 PM PDT 24
Finished Aug 03 06:59:05 PM PDT 24
Peak memory 242280 kb
Host smart-4228da3b-c8b3-42ab-9015-03e614a5ae4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62045391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.62045391
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.1759193930
Short name T800
Test name
Test status
Simulation time 144895510 ps
CPU time 4.25 seconds
Started Aug 03 06:58:58 PM PDT 24
Finished Aug 03 06:59:03 PM PDT 24
Peak memory 242164 kb
Host smart-d253853c-a1d2-4791-8ef7-e0d593739257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759193930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.1759193930
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.2007192822
Short name T692
Test name
Test status
Simulation time 105387819 ps
CPU time 3.35 seconds
Started Aug 03 06:59:00 PM PDT 24
Finished Aug 03 06:59:03 PM PDT 24
Peak memory 242240 kb
Host smart-78bbae27-a174-4c14-bc58-4919742711aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007192822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.2007192822
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.310347373
Short name T164
Test name
Test status
Simulation time 182336381 ps
CPU time 3.79 seconds
Started Aug 03 06:59:00 PM PDT 24
Finished Aug 03 06:59:04 PM PDT 24
Peak memory 242220 kb
Host smart-3910f5b8-aa5c-425d-b0d5-fa5ec5ef8946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310347373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.310347373
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.924866159
Short name T862
Test name
Test status
Simulation time 2430251776 ps
CPU time 7.03 seconds
Started Aug 03 06:59:05 PM PDT 24
Finished Aug 03 06:59:12 PM PDT 24
Peak memory 241928 kb
Host smart-4d178145-9cc3-4e4e-823b-b0e7999b5238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924866159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.924866159
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.4197786355
Short name T548
Test name
Test status
Simulation time 176231278 ps
CPU time 4.39 seconds
Started Aug 03 06:59:03 PM PDT 24
Finished Aug 03 06:59:07 PM PDT 24
Peak memory 242060 kb
Host smart-ac81e93f-a755-4147-a3b6-f477a81e075a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197786355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.4197786355
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.3629902939
Short name T44
Test name
Test status
Simulation time 244406782 ps
CPU time 4.86 seconds
Started Aug 03 06:59:04 PM PDT 24
Finished Aug 03 06:59:09 PM PDT 24
Peak memory 241892 kb
Host smart-dd60dc6b-6465-4755-a2ff-76a9ea97a400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629902939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.3629902939
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.4010029175
Short name T407
Test name
Test status
Simulation time 126211313 ps
CPU time 1.67 seconds
Started Aug 03 06:39:34 PM PDT 24
Finished Aug 03 06:39:35 PM PDT 24
Peak memory 240652 kb
Host smart-a96d9708-b9df-45a9-b814-51527fee03ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010029175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.4010029175
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.3573331272
Short name T59
Test name
Test status
Simulation time 12301967950 ps
CPU time 33.26 seconds
Started Aug 03 06:39:22 PM PDT 24
Finished Aug 03 06:39:56 PM PDT 24
Peak memory 248636 kb
Host smart-d7f9250c-b6b2-428f-8c32-418fbf31cf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573331272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3573331272
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.4111644412
Short name T506
Test name
Test status
Simulation time 267166967 ps
CPU time 13.94 seconds
Started Aug 03 06:39:22 PM PDT 24
Finished Aug 03 06:39:36 PM PDT 24
Peak memory 242424 kb
Host smart-1146a485-eba9-472f-b1bd-83ed84fd3f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111644412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.4111644412
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.3644066247
Short name T709
Test name
Test status
Simulation time 10875166449 ps
CPU time 16.26 seconds
Started Aug 03 06:39:21 PM PDT 24
Finished Aug 03 06:39:38 PM PDT 24
Peak memory 243128 kb
Host smart-879e4279-8a3e-4a8d-9e58-e0ef0e0d31cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644066247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.3644066247
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.1599413463
Short name T752
Test name
Test status
Simulation time 203243745 ps
CPU time 4.03 seconds
Started Aug 03 06:39:21 PM PDT 24
Finished Aug 03 06:39:25 PM PDT 24
Peak memory 242176 kb
Host smart-af88b85e-e34f-4cbb-944f-eef8f222b7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599413463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.1599413463
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.714712654
Short name T419
Test name
Test status
Simulation time 3403556183 ps
CPU time 26.48 seconds
Started Aug 03 06:39:21 PM PDT 24
Finished Aug 03 06:39:48 PM PDT 24
Peak memory 248584 kb
Host smart-7f3f17c8-45fe-4e90-923b-f749db5a7bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714712654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.714712654
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.2393083445
Short name T1000
Test name
Test status
Simulation time 6058643553 ps
CPU time 50.57 seconds
Started Aug 03 06:39:28 PM PDT 24
Finished Aug 03 06:40:19 PM PDT 24
Peak memory 248680 kb
Host smart-557a9f4b-eb6d-452d-99d1-a91feca86860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393083445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2393083445
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.146339552
Short name T985
Test name
Test status
Simulation time 5060353718 ps
CPU time 13.7 seconds
Started Aug 03 06:39:21 PM PDT 24
Finished Aug 03 06:39:35 PM PDT 24
Peak memory 241956 kb
Host smart-23988567-ff91-40cd-b827-c54b27d4a756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146339552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.146339552
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.78628284
Short name T603
Test name
Test status
Simulation time 273509119 ps
CPU time 4.28 seconds
Started Aug 03 06:39:23 PM PDT 24
Finished Aug 03 06:39:27 PM PDT 24
Peak memory 242028 kb
Host smart-ab2d6c4a-d022-428c-89a4-4922502c0a1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78628284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.78628284
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.3057943682
Short name T1154
Test name
Test status
Simulation time 672176260 ps
CPU time 5.61 seconds
Started Aug 03 06:39:27 PM PDT 24
Finished Aug 03 06:39:33 PM PDT 24
Peak memory 241988 kb
Host smart-ea30749f-0902-4741-a01e-406d644b8201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3057943682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.3057943682
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.2387662934
Short name T785
Test name
Test status
Simulation time 441679537 ps
CPU time 9.81 seconds
Started Aug 03 06:39:20 PM PDT 24
Finished Aug 03 06:39:31 PM PDT 24
Peak memory 241964 kb
Host smart-94bf0faf-0c07-4050-897e-0ec81f6ab444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387662934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2387662934
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.1481264798
Short name T355
Test name
Test status
Simulation time 54804715341 ps
CPU time 142.3 seconds
Started Aug 03 06:39:33 PM PDT 24
Finished Aug 03 06:41:55 PM PDT 24
Peak memory 257864 kb
Host smart-5d452226-c6ac-467a-90a8-d4d719a056c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481264798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.1481264798
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.3039323657
Short name T646
Test name
Test status
Simulation time 312613219112 ps
CPU time 804.87 seconds
Started Aug 03 06:39:32 PM PDT 24
Finished Aug 03 06:52:58 PM PDT 24
Peak memory 327388 kb
Host smart-01453d62-ac9a-4e72-a46e-0adfb883d070
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039323657 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.3039323657
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.3872132854
Short name T286
Test name
Test status
Simulation time 10407381109 ps
CPU time 31.83 seconds
Started Aug 03 06:39:29 PM PDT 24
Finished Aug 03 06:40:01 PM PDT 24
Peak memory 242456 kb
Host smart-ea19ff8c-efa6-4e3a-afd7-9fd48e6a919a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872132854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.3872132854
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.2964501862
Short name T1158
Test name
Test status
Simulation time 292448074 ps
CPU time 4.29 seconds
Started Aug 03 06:59:05 PM PDT 24
Finished Aug 03 06:59:10 PM PDT 24
Peak memory 242132 kb
Host smart-4a97e1d1-158d-4d9b-8996-080ebc1fe53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964501862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2964501862
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.3308585991
Short name T877
Test name
Test status
Simulation time 1562660600 ps
CPU time 3.18 seconds
Started Aug 03 06:59:04 PM PDT 24
Finished Aug 03 06:59:07 PM PDT 24
Peak memory 242160 kb
Host smart-6e16d036-92d5-4194-ac45-befde69d4ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308585991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.3308585991
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.1384966295
Short name T623
Test name
Test status
Simulation time 472364689 ps
CPU time 4.3 seconds
Started Aug 03 06:59:04 PM PDT 24
Finished Aug 03 06:59:08 PM PDT 24
Peak memory 242088 kb
Host smart-bf1fb254-91cd-4aed-80fb-9a26a52a36f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384966295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.1384966295
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.1086366937
Short name T492
Test name
Test status
Simulation time 125785184 ps
CPU time 4.25 seconds
Started Aug 03 06:59:05 PM PDT 24
Finished Aug 03 06:59:09 PM PDT 24
Peak memory 242168 kb
Host smart-ad30a7c3-9da7-432e-8468-7bb17bd34528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086366937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.1086366937
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.3812882972
Short name T512
Test name
Test status
Simulation time 600483732 ps
CPU time 4.44 seconds
Started Aug 03 06:59:03 PM PDT 24
Finished Aug 03 06:59:08 PM PDT 24
Peak memory 242176 kb
Host smart-9be98eb6-7287-4770-bc06-801a53625fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812882972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.3812882972
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.1409047313
Short name T435
Test name
Test status
Simulation time 645100847 ps
CPU time 3.93 seconds
Started Aug 03 06:59:04 PM PDT 24
Finished Aug 03 06:59:08 PM PDT 24
Peak memory 241896 kb
Host smart-59b677f5-f596-41b8-9d3e-1dee158b5f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409047313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.1409047313
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.1300407225
Short name T1088
Test name
Test status
Simulation time 144077465 ps
CPU time 3.69 seconds
Started Aug 03 06:59:04 PM PDT 24
Finished Aug 03 06:59:08 PM PDT 24
Peak memory 242416 kb
Host smart-98af5534-d7a9-486c-8e99-1cf6741b9cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300407225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.1300407225
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.2893528432
Short name T890
Test name
Test status
Simulation time 2097896758 ps
CPU time 5.55 seconds
Started Aug 03 06:59:05 PM PDT 24
Finished Aug 03 06:59:11 PM PDT 24
Peak memory 242008 kb
Host smart-420272c9-157d-4bbf-a67f-2f086f69d02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893528432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.2893528432
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.1158366842
Short name T185
Test name
Test status
Simulation time 463829220 ps
CPU time 3.95 seconds
Started Aug 03 06:59:09 PM PDT 24
Finished Aug 03 06:59:13 PM PDT 24
Peak memory 241996 kb
Host smart-83a7c435-3fff-40ba-a843-a86de6a644cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158366842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.1158366842
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.2794816467
Short name T688
Test name
Test status
Simulation time 784965640 ps
CPU time 1.74 seconds
Started Aug 03 06:39:43 PM PDT 24
Finished Aug 03 06:39:45 PM PDT 24
Peak memory 240472 kb
Host smart-4ecba225-9035-447c-9a58-ff3a7a165e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794816467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2794816467
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.2061398962
Short name T48
Test name
Test status
Simulation time 20926951114 ps
CPU time 37.08 seconds
Started Aug 03 06:39:37 PM PDT 24
Finished Aug 03 06:40:14 PM PDT 24
Peak memory 244200 kb
Host smart-ed586e51-0786-4fff-ac30-336584d28962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061398962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.2061398962
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.3825031890
Short name T230
Test name
Test status
Simulation time 1866862067 ps
CPU time 30.15 seconds
Started Aug 03 06:39:38 PM PDT 24
Finished Aug 03 06:40:08 PM PDT 24
Peak memory 245300 kb
Host smart-4ec9a173-7b4e-4897-86a4-7dba0e968dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825031890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.3825031890
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.197289667
Short name T451
Test name
Test status
Simulation time 1469281058 ps
CPU time 29.09 seconds
Started Aug 03 06:39:36 PM PDT 24
Finished Aug 03 06:40:06 PM PDT 24
Peak memory 242112 kb
Host smart-10e33683-3da6-49df-9583-02a2d026259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197289667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.197289667
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.3456539136
Short name T91
Test name
Test status
Simulation time 98859465 ps
CPU time 3.68 seconds
Started Aug 03 06:39:32 PM PDT 24
Finished Aug 03 06:39:35 PM PDT 24
Peak memory 242068 kb
Host smart-86431197-5d61-4457-bf87-be92ced988d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456539136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3456539136
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.1658532779
Short name T1042
Test name
Test status
Simulation time 1556439656 ps
CPU time 26.55 seconds
Started Aug 03 06:39:38 PM PDT 24
Finished Aug 03 06:40:05 PM PDT 24
Peak memory 248500 kb
Host smart-36db019b-ff11-437c-bb21-0539a94c99bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658532779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.1658532779
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.4203004478
Short name T851
Test name
Test status
Simulation time 4188268189 ps
CPU time 46.38 seconds
Started Aug 03 06:39:36 PM PDT 24
Finished Aug 03 06:40:23 PM PDT 24
Peak memory 242444 kb
Host smart-3be0da60-0ca3-46e1-b929-8cb8e6cff594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203004478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.4203004478
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.660154109
Short name T687
Test name
Test status
Simulation time 2911210215 ps
CPU time 8.63 seconds
Started Aug 03 06:39:34 PM PDT 24
Finished Aug 03 06:39:43 PM PDT 24
Peak memory 241964 kb
Host smart-3f9a3019-4afa-46fd-9bfb-cb0ca98fda02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660154109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.660154109
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.955056555
Short name T386
Test name
Test status
Simulation time 1432790147 ps
CPU time 11.58 seconds
Started Aug 03 06:39:35 PM PDT 24
Finished Aug 03 06:39:46 PM PDT 24
Peak memory 241952 kb
Host smart-3162ffcf-16b9-4eb9-a66f-b484dc9b277f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955056555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.955056555
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.3919206383
Short name T663
Test name
Test status
Simulation time 318534930 ps
CPU time 10.61 seconds
Started Aug 03 06:39:35 PM PDT 24
Finished Aug 03 06:39:46 PM PDT 24
Peak memory 242368 kb
Host smart-7daaa3f3-0244-45a3-bf08-d1d3852d9182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919206383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.3919206383
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.2525560369
Short name T860
Test name
Test status
Simulation time 304793789 ps
CPU time 5.8 seconds
Started Aug 03 06:39:31 PM PDT 24
Finished Aug 03 06:39:37 PM PDT 24
Peak memory 242304 kb
Host smart-9093f62f-bd43-4d53-86d4-52b93307ed65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525560369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2525560369
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.2851549147
Short name T806
Test name
Test status
Simulation time 15374519855 ps
CPU time 263.86 seconds
Started Aug 03 06:39:45 PM PDT 24
Finished Aug 03 06:44:09 PM PDT 24
Peak memory 289640 kb
Host smart-eab6bd6d-861e-452d-82ba-c4da257377fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851549147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.2851549147
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.1294395501
Short name T671
Test name
Test status
Simulation time 3212289859 ps
CPU time 21.74 seconds
Started Aug 03 06:39:45 PM PDT 24
Finished Aug 03 06:40:07 PM PDT 24
Peak memory 248600 kb
Host smart-cadb10d5-0db0-4eee-9dc2-60c972b9cb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294395501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.1294395501
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.1560449369
Short name T43
Test name
Test status
Simulation time 289097287 ps
CPU time 4.48 seconds
Started Aug 03 06:59:10 PM PDT 24
Finished Aug 03 06:59:14 PM PDT 24
Peak memory 241964 kb
Host smart-782e4fc9-07d2-4c88-8dd3-2778ebf249a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560449369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.1560449369
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.1056010397
Short name T76
Test name
Test status
Simulation time 212280919 ps
CPU time 4.89 seconds
Started Aug 03 06:59:10 PM PDT 24
Finished Aug 03 06:59:15 PM PDT 24
Peak memory 241912 kb
Host smart-7236fd53-c617-4124-8d8f-463a56e7bb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056010397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.1056010397
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.3903293218
Short name T540
Test name
Test status
Simulation time 350810160 ps
CPU time 5.04 seconds
Started Aug 03 06:59:14 PM PDT 24
Finished Aug 03 06:59:19 PM PDT 24
Peak memory 242224 kb
Host smart-82cb6e18-2d34-4f05-b05d-a65249e56185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903293218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.3903293218
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.3901087057
Short name T1132
Test name
Test status
Simulation time 488522353 ps
CPU time 3.2 seconds
Started Aug 03 06:59:12 PM PDT 24
Finished Aug 03 06:59:15 PM PDT 24
Peak memory 242396 kb
Host smart-4ea7bda3-4bea-45bf-b657-6b6bd206d73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901087057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.3901087057
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.3179967868
Short name T924
Test name
Test status
Simulation time 131081235 ps
CPU time 3.87 seconds
Started Aug 03 06:59:10 PM PDT 24
Finished Aug 03 06:59:14 PM PDT 24
Peak memory 242148 kb
Host smart-bba58c14-ffec-4417-83f9-f1b45a67dfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179967868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.3179967868
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.2124764673
Short name T903
Test name
Test status
Simulation time 322033303 ps
CPU time 5.52 seconds
Started Aug 03 06:59:08 PM PDT 24
Finished Aug 03 06:59:14 PM PDT 24
Peak memory 242396 kb
Host smart-cd2cc1bf-b61e-466a-98e5-5c482c6ac77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124764673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.2124764673
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.858572075
Short name T831
Test name
Test status
Simulation time 137630470 ps
CPU time 5.15 seconds
Started Aug 03 06:59:09 PM PDT 24
Finished Aug 03 06:59:14 PM PDT 24
Peak memory 241988 kb
Host smart-c36717dc-5075-4e5d-b971-24db9242aead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858572075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.858572075
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.3755857925
Short name T987
Test name
Test status
Simulation time 176199390 ps
CPU time 3.95 seconds
Started Aug 03 06:59:09 PM PDT 24
Finished Aug 03 06:59:13 PM PDT 24
Peak memory 242388 kb
Host smart-2855105b-70e7-4b63-b2e8-9524bae47990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755857925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3755857925
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.1044915853
Short name T1145
Test name
Test status
Simulation time 227396431 ps
CPU time 3.81 seconds
Started Aug 03 06:59:10 PM PDT 24
Finished Aug 03 06:59:14 PM PDT 24
Peak memory 242236 kb
Host smart-90b5d313-e42a-4d1a-b9c5-a28c97e91f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044915853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.1044915853
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.172703274
Short name T726
Test name
Test status
Simulation time 170021555 ps
CPU time 1.61 seconds
Started Aug 03 06:39:57 PM PDT 24
Finished Aug 03 06:39:59 PM PDT 24
Peak memory 240700 kb
Host smart-7edf2ae9-174b-48a5-8a99-6c5812102c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172703274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.172703274
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.597853581
Short name T55
Test name
Test status
Simulation time 1634965324 ps
CPU time 13.63 seconds
Started Aug 03 06:39:51 PM PDT 24
Finished Aug 03 06:40:05 PM PDT 24
Peak memory 242856 kb
Host smart-82716f7e-adc2-45ed-9dcb-0d03b6d78922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597853581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.597853581
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.3263570419
Short name T832
Test name
Test status
Simulation time 337811515 ps
CPU time 7.18 seconds
Started Aug 03 06:39:48 PM PDT 24
Finished Aug 03 06:39:55 PM PDT 24
Peak memory 242260 kb
Host smart-ba5c4b32-2c1c-4952-ad8d-15dd8ca3a168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263570419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.3263570419
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.212332345
Short name T675
Test name
Test status
Simulation time 156550317 ps
CPU time 4.37 seconds
Started Aug 03 06:39:44 PM PDT 24
Finished Aug 03 06:39:49 PM PDT 24
Peak memory 242024 kb
Host smart-2d72954a-8ab7-4b1e-9ae3-e17b7b155bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212332345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.212332345
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.1418807791
Short name T1066
Test name
Test status
Simulation time 1371529626 ps
CPU time 27.83 seconds
Started Aug 03 06:39:50 PM PDT 24
Finished Aug 03 06:40:18 PM PDT 24
Peak memory 244536 kb
Host smart-7aaf27e1-dd08-4652-ba06-6913b06de788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418807791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.1418807791
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.4177677085
Short name T807
Test name
Test status
Simulation time 582104479 ps
CPU time 24.86 seconds
Started Aug 03 06:39:53 PM PDT 24
Finished Aug 03 06:40:18 PM PDT 24
Peak memory 242488 kb
Host smart-e3e057ea-c51a-45a9-a7b6-19ff985fe25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177677085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.4177677085
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.3062803941
Short name T723
Test name
Test status
Simulation time 15226182481 ps
CPU time 46.49 seconds
Started Aug 03 06:39:46 PM PDT 24
Finished Aug 03 06:40:33 PM PDT 24
Peak memory 242276 kb
Host smart-68a1bb94-3b6f-460a-b86c-4553b4064c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062803941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.3062803941
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.3001921390
Short name T1087
Test name
Test status
Simulation time 1015473481 ps
CPU time 22.26 seconds
Started Aug 03 06:39:48 PM PDT 24
Finished Aug 03 06:40:10 PM PDT 24
Peak memory 242104 kb
Host smart-569517a3-2cd9-4693-9488-7f9d6e22ee89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3001921390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.3001921390
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.820607719
Short name T853
Test name
Test status
Simulation time 306423449 ps
CPU time 11.41 seconds
Started Aug 03 06:39:54 PM PDT 24
Finished Aug 03 06:40:05 PM PDT 24
Peak memory 242228 kb
Host smart-a7448418-242b-4b96-ba75-05acbfb5eb9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820607719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.820607719
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.1847373321
Short name T717
Test name
Test status
Simulation time 206046481 ps
CPU time 7.76 seconds
Started Aug 03 06:39:41 PM PDT 24
Finished Aug 03 06:39:49 PM PDT 24
Peak memory 241984 kb
Host smart-f285583b-1021-4465-bed6-c2c70df5706b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847373321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1847373321
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.3775618610
Short name T651
Test name
Test status
Simulation time 23254945218 ps
CPU time 59.06 seconds
Started Aug 03 06:39:56 PM PDT 24
Finished Aug 03 06:40:55 PM PDT 24
Peak memory 248588 kb
Host smart-e0b70791-4a7b-4d62-9b5f-b6be7d7fbadc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775618610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.3775618610
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.4102989091
Short name T206
Test name
Test status
Simulation time 354472602737 ps
CPU time 976.04 seconds
Started Aug 03 06:39:53 PM PDT 24
Finished Aug 03 06:56:10 PM PDT 24
Peak memory 327172 kb
Host smart-50104e67-f033-45d4-b72a-549a7fdee36a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102989091 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.4102989091
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.2520934656
Short name T382
Test name
Test status
Simulation time 686037102 ps
CPU time 13.83 seconds
Started Aug 03 06:39:51 PM PDT 24
Finished Aug 03 06:40:05 PM PDT 24
Peak memory 242224 kb
Host smart-b1d67f57-162b-4789-9562-d60037114256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520934656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.2520934656
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.3167232401
Short name T509
Test name
Test status
Simulation time 257524934 ps
CPU time 3.69 seconds
Started Aug 03 06:59:15 PM PDT 24
Finished Aug 03 06:59:18 PM PDT 24
Peak memory 242328 kb
Host smart-e8746320-9395-4a83-b3b3-eaf60f86ad8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167232401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.3167232401
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.3216203435
Short name T1152
Test name
Test status
Simulation time 458388231 ps
CPU time 3.77 seconds
Started Aug 03 06:59:14 PM PDT 24
Finished Aug 03 06:59:18 PM PDT 24
Peak memory 241956 kb
Host smart-c31accef-324f-40e5-ad30-ba93b5210119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216203435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.3216203435
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.767824643
Short name T31
Test name
Test status
Simulation time 177116990 ps
CPU time 4.05 seconds
Started Aug 03 06:59:13 PM PDT 24
Finished Aug 03 06:59:17 PM PDT 24
Peak memory 242412 kb
Host smart-20ac3c32-37cf-4c4d-b67c-bf0775a06d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767824643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.767824643
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.3096831899
Short name T1078
Test name
Test status
Simulation time 158370767 ps
CPU time 3.52 seconds
Started Aug 03 06:59:15 PM PDT 24
Finished Aug 03 06:59:18 PM PDT 24
Peak memory 242292 kb
Host smart-ace18cb2-b6d8-46e6-9ce9-5e1e0bd97430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096831899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.3096831899
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.4135016944
Short name T414
Test name
Test status
Simulation time 647811465 ps
CPU time 4.92 seconds
Started Aug 03 06:59:16 PM PDT 24
Finished Aug 03 06:59:21 PM PDT 24
Peak memory 242272 kb
Host smart-1a6757b7-e3b9-4ca8-93a6-0f8840121634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135016944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.4135016944
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.369915670
Short name T665
Test name
Test status
Simulation time 117330805 ps
CPU time 3.8 seconds
Started Aug 03 06:59:15 PM PDT 24
Finished Aug 03 06:59:19 PM PDT 24
Peak memory 242060 kb
Host smart-a8ea308f-9964-408f-a8fe-50c5399301c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369915670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.369915670
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.3182388886
Short name T54
Test name
Test status
Simulation time 141064819 ps
CPU time 3.91 seconds
Started Aug 03 06:59:14 PM PDT 24
Finished Aug 03 06:59:18 PM PDT 24
Peak memory 242344 kb
Host smart-b72c520b-81ab-4bc6-af4e-31b8e6a78e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182388886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.3182388886
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.1085254652
Short name T608
Test name
Test status
Simulation time 590482053 ps
CPU time 4.46 seconds
Started Aug 03 06:59:15 PM PDT 24
Finished Aug 03 06:59:20 PM PDT 24
Peak memory 242000 kb
Host smart-d3ea8c95-13a6-438d-a878-bc726459cc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085254652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.1085254652
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.3886867047
Short name T424
Test name
Test status
Simulation time 105953793 ps
CPU time 1.99 seconds
Started Aug 03 06:40:12 PM PDT 24
Finished Aug 03 06:40:14 PM PDT 24
Peak memory 240420 kb
Host smart-1ddaf23a-87d6-4725-b0d6-98b1ef44dd38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886867047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3886867047
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.158246138
Short name T591
Test name
Test status
Simulation time 1227271303 ps
CPU time 22.08 seconds
Started Aug 03 06:40:03 PM PDT 24
Finished Aug 03 06:40:26 PM PDT 24
Peak memory 242528 kb
Host smart-d95250fe-1084-40b2-a449-1f138c3eb019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158246138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.158246138
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.1366801413
Short name T828
Test name
Test status
Simulation time 3215381427 ps
CPU time 42.17 seconds
Started Aug 03 06:40:01 PM PDT 24
Finished Aug 03 06:40:44 PM PDT 24
Peak memory 248872 kb
Host smart-d1e20121-1589-46a9-a6cc-58f0275b1f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366801413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.1366801413
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.2660316034
Short name T1122
Test name
Test status
Simulation time 6887087600 ps
CPU time 19.52 seconds
Started Aug 03 06:40:04 PM PDT 24
Finished Aug 03 06:40:23 PM PDT 24
Peak memory 242924 kb
Host smart-933b61d2-28b1-47a9-a21c-8adc2b05d2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660316034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.2660316034
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.1609922503
Short name T694
Test name
Test status
Simulation time 426345651 ps
CPU time 4.99 seconds
Started Aug 03 06:40:01 PM PDT 24
Finished Aug 03 06:40:07 PM PDT 24
Peak memory 241936 kb
Host smart-34c6ff2d-4ed3-4554-a602-f5f8f3f02427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609922503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.1609922503
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.1827380110
Short name T207
Test name
Test status
Simulation time 677057384 ps
CPU time 8.3 seconds
Started Aug 03 06:40:06 PM PDT 24
Finished Aug 03 06:40:14 PM PDT 24
Peak memory 242240 kb
Host smart-00587f05-022c-4cc9-95b8-11947895c8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827380110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.1827380110
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.4078782359
Short name T875
Test name
Test status
Simulation time 107664849 ps
CPU time 2.88 seconds
Started Aug 03 06:40:06 PM PDT 24
Finished Aug 03 06:40:09 PM PDT 24
Peak memory 247168 kb
Host smart-eb8a7f81-1c06-4894-9799-ba6d6a1dce43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078782359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.4078782359
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.3874000919
Short name T448
Test name
Test status
Simulation time 911887370 ps
CPU time 20.79 seconds
Started Aug 03 06:40:03 PM PDT 24
Finished Aug 03 06:40:23 PM PDT 24
Peak memory 241760 kb
Host smart-2c220384-11a0-4ce6-befd-c9c77db21bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874000919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.3874000919
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.331496578
Short name T627
Test name
Test status
Simulation time 254503284 ps
CPU time 4.77 seconds
Started Aug 03 06:40:05 PM PDT 24
Finished Aug 03 06:40:10 PM PDT 24
Peak memory 242076 kb
Host smart-c4ac701f-cabf-43de-bcdb-a6e1596a4201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=331496578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.331496578
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.1040382067
Short name T736
Test name
Test status
Simulation time 175810094 ps
CPU time 3.37 seconds
Started Aug 03 06:39:56 PM PDT 24
Finished Aug 03 06:40:00 PM PDT 24
Peak memory 241948 kb
Host smart-78f59126-5339-4c89-8d63-6e379ee32ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040382067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1040382067
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.1603140905
Short name T16
Test name
Test status
Simulation time 12860463412 ps
CPU time 20.33 seconds
Started Aug 03 06:40:12 PM PDT 24
Finished Aug 03 06:40:32 PM PDT 24
Peak memory 242732 kb
Host smart-107efbb0-9641-4226-b06b-461d959b5ead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603140905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.1603140905
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.1094883668
Short name T394
Test name
Test status
Simulation time 1017536452 ps
CPU time 34.19 seconds
Started Aug 03 06:40:06 PM PDT 24
Finished Aug 03 06:40:41 PM PDT 24
Peak memory 242436 kb
Host smart-bf873dc8-eba3-40c4-9c31-024e522dd6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094883668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.1094883668
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.3751249680
Short name T124
Test name
Test status
Simulation time 238479417 ps
CPU time 3.57 seconds
Started Aug 03 06:59:19 PM PDT 24
Finished Aug 03 06:59:22 PM PDT 24
Peak memory 241864 kb
Host smart-8646df30-57a6-4d53-bb86-841765db08c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751249680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.3751249680
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.3975682017
Short name T65
Test name
Test status
Simulation time 261364200 ps
CPU time 3.51 seconds
Started Aug 03 06:59:20 PM PDT 24
Finished Aug 03 06:59:23 PM PDT 24
Peak memory 241968 kb
Host smart-625d8bc0-5cfb-4775-adae-b4bce6cabdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975682017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3975682017
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.3046758808
Short name T1059
Test name
Test status
Simulation time 356952651 ps
CPU time 4.93 seconds
Started Aug 03 06:59:20 PM PDT 24
Finished Aug 03 06:59:25 PM PDT 24
Peak memory 241968 kb
Host smart-0486c99b-142d-4fc2-b09a-326e6380f31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046758808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.3046758808
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.3807921519
Short name T215
Test name
Test status
Simulation time 623511838 ps
CPU time 3.89 seconds
Started Aug 03 06:59:18 PM PDT 24
Finished Aug 03 06:59:22 PM PDT 24
Peak memory 242000 kb
Host smart-ecc36189-aa42-4964-95b7-3d7337d8a3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807921519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.3807921519
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.2109840517
Short name T938
Test name
Test status
Simulation time 177736854 ps
CPU time 3.49 seconds
Started Aug 03 06:59:20 PM PDT 24
Finished Aug 03 06:59:23 PM PDT 24
Peak memory 242144 kb
Host smart-03244ef0-d930-40d5-8d00-b16a2b76bfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109840517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.2109840517
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.1291054675
Short name T896
Test name
Test status
Simulation time 168926381 ps
CPU time 4.94 seconds
Started Aug 03 06:59:21 PM PDT 24
Finished Aug 03 06:59:26 PM PDT 24
Peak memory 242216 kb
Host smart-f7c829de-8f06-4979-a7bb-3101bed5c68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291054675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.1291054675
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.4202643864
Short name T1163
Test name
Test status
Simulation time 122424743 ps
CPU time 3.37 seconds
Started Aug 03 06:59:20 PM PDT 24
Finished Aug 03 06:59:24 PM PDT 24
Peak memory 242132 kb
Host smart-cb761fc6-4876-45ac-a099-c82e0d3dacde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202643864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.4202643864
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.1214664459
Short name T1135
Test name
Test status
Simulation time 268846847 ps
CPU time 4.28 seconds
Started Aug 03 06:59:19 PM PDT 24
Finished Aug 03 06:59:24 PM PDT 24
Peak memory 242388 kb
Host smart-3922e8d5-cbeb-4c3e-a1e6-8bc97081bfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214664459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.1214664459
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.4033291709
Short name T708
Test name
Test status
Simulation time 348564174 ps
CPU time 3.95 seconds
Started Aug 03 06:59:18 PM PDT 24
Finished Aug 03 06:59:22 PM PDT 24
Peak memory 242168 kb
Host smart-72e57d0f-6744-4fdb-9a89-e1029ebabafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033291709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.4033291709
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.709261006
Short name T582
Test name
Test status
Simulation time 134050466 ps
CPU time 1.8 seconds
Started Aug 03 06:35:13 PM PDT 24
Finished Aug 03 06:35:15 PM PDT 24
Peak memory 240584 kb
Host smart-23445713-d909-4675-aaa4-8a95478abf22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709261006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.709261006
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.2668544791
Short name T766
Test name
Test status
Simulation time 20555967340 ps
CPU time 31.86 seconds
Started Aug 03 06:35:01 PM PDT 24
Finished Aug 03 06:35:33 PM PDT 24
Peak memory 243064 kb
Host smart-8d721dbb-2fb9-4660-bec1-68e8cf032d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668544791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.2668544791
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.2441264953
Short name T1165
Test name
Test status
Simulation time 9762867274 ps
CPU time 21.24 seconds
Started Aug 03 06:35:06 PM PDT 24
Finished Aug 03 06:35:27 PM PDT 24
Peak memory 244824 kb
Host smart-fd0c24b6-7ec9-4947-9a20-392ddc79031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441264953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.2441264953
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.1128930225
Short name T984
Test name
Test status
Simulation time 8991792085 ps
CPU time 28.61 seconds
Started Aug 03 06:35:00 PM PDT 24
Finished Aug 03 06:35:29 PM PDT 24
Peak memory 242456 kb
Host smart-ce0b1ff3-075d-44a1-bb02-baa657d955e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128930225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.1128930225
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.3507099743
Short name T710
Test name
Test status
Simulation time 1811659997 ps
CPU time 18.25 seconds
Started Aug 03 06:35:03 PM PDT 24
Finished Aug 03 06:35:21 PM PDT 24
Peak memory 248676 kb
Host smart-fb807488-5ce1-492e-b67d-b7571be95a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507099743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.3507099743
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.2662882750
Short name T912
Test name
Test status
Simulation time 642761333 ps
CPU time 3.6 seconds
Started Aug 03 06:35:01 PM PDT 24
Finished Aug 03 06:35:05 PM PDT 24
Peak memory 242256 kb
Host smart-f4b5e98e-e286-4c6c-8f43-51f510a2afd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662882750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.2662882750
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.1623499517
Short name T712
Test name
Test status
Simulation time 959991657 ps
CPU time 5.99 seconds
Started Aug 03 06:35:07 PM PDT 24
Finished Aug 03 06:35:13 PM PDT 24
Peak memory 241948 kb
Host smart-05afad87-ce27-452b-9ae4-d7bfdae25458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623499517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.1623499517
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.2712278744
Short name T880
Test name
Test status
Simulation time 1517367566 ps
CPU time 26.31 seconds
Started Aug 03 06:35:08 PM PDT 24
Finished Aug 03 06:35:34 PM PDT 24
Peak memory 242592 kb
Host smart-5b2aebfa-3114-43fd-8182-8978ba51b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712278744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.2712278744
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.1085193385
Short name T1050
Test name
Test status
Simulation time 156841733 ps
CPU time 2.6 seconds
Started Aug 03 06:35:02 PM PDT 24
Finished Aug 03 06:35:05 PM PDT 24
Peak memory 246856 kb
Host smart-c56e45f7-3110-40b7-89c6-0e1485fc2347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085193385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.1085193385
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.1767873884
Short name T1141
Test name
Test status
Simulation time 846968703 ps
CPU time 16.42 seconds
Started Aug 03 06:35:01 PM PDT 24
Finished Aug 03 06:35:17 PM PDT 24
Peak memory 242172 kb
Host smart-4aa8636f-3767-4d26-8910-7ff25cf97661
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767873884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.1767873884
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.2804783396
Short name T371
Test name
Test status
Simulation time 554479011 ps
CPU time 10.36 seconds
Started Aug 03 06:35:04 PM PDT 24
Finished Aug 03 06:35:15 PM PDT 24
Peak memory 242012 kb
Host smart-79215894-957b-4ac8-9163-780f74a5db62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2804783396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.2804783396
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.2193267527
Short name T232
Test name
Test status
Simulation time 22041185071 ps
CPU time 189.25 seconds
Started Aug 03 06:35:12 PM PDT 24
Finished Aug 03 06:38:21 PM PDT 24
Peak memory 274520 kb
Host smart-7a77933a-f10d-4cc1-b0ff-e9c3fe9ac211
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193267527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.2193267527
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.1916694045
Short name T515
Test name
Test status
Simulation time 301570045 ps
CPU time 3.53 seconds
Started Aug 03 06:35:04 PM PDT 24
Finished Aug 03 06:35:08 PM PDT 24
Peak memory 248620 kb
Host smart-5fda5723-324e-4c7d-9961-a6941662dbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916694045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.1916694045
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.3969011924
Short name T1140
Test name
Test status
Simulation time 69159216886 ps
CPU time 157.28 seconds
Started Aug 03 06:35:12 PM PDT 24
Finished Aug 03 06:37:49 PM PDT 24
Peak memory 256776 kb
Host smart-04d1bf9c-6db4-4001-b9a9-6fc6fc1f9033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969011924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
3969011924
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.2196128591
Short name T997
Test name
Test status
Simulation time 71959282953 ps
CPU time 2070.58 seconds
Started Aug 03 06:35:07 PM PDT 24
Finished Aug 03 07:09:38 PM PDT 24
Peak memory 277152 kb
Host smart-7c06e83f-1426-4fda-a9a3-1cbbb2616d90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196128591 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.2196128591
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.3142662565
Short name T612
Test name
Test status
Simulation time 17096182525 ps
CPU time 21.77 seconds
Started Aug 03 06:35:07 PM PDT 24
Finished Aug 03 06:35:29 PM PDT 24
Peak memory 243300 kb
Host smart-9076d507-3dd5-42a0-bb83-bb92e06dc8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142662565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.3142662565
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.2095651556
Short name T221
Test name
Test status
Simulation time 68064000 ps
CPU time 1.74 seconds
Started Aug 03 06:40:23 PM PDT 24
Finished Aug 03 06:40:25 PM PDT 24
Peak memory 240824 kb
Host smart-14bba8d9-2d3c-4886-ba7d-c52676eaa9b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095651556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.2095651556
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.118484841
Short name T576
Test name
Test status
Simulation time 331896521 ps
CPU time 4.3 seconds
Started Aug 03 06:40:17 PM PDT 24
Finished Aug 03 06:40:22 PM PDT 24
Peak memory 241988 kb
Host smart-6a804aa9-f4df-4dd0-b7c0-c45cb7613665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118484841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.118484841
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.361801123
Short name T718
Test name
Test status
Simulation time 920518821 ps
CPU time 13.96 seconds
Started Aug 03 06:40:19 PM PDT 24
Finished Aug 03 06:40:33 PM PDT 24
Peak memory 241920 kb
Host smart-342bc553-a2dc-4729-b17f-5145bcdc7315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361801123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.361801123
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.4180644308
Short name T392
Test name
Test status
Simulation time 873570869 ps
CPU time 16.67 seconds
Started Aug 03 06:40:20 PM PDT 24
Finished Aug 03 06:40:36 PM PDT 24
Peak memory 248660 kb
Host smart-892cbdd8-45b5-49f5-8532-9c509c856641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180644308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.4180644308
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.815024504
Short name T700
Test name
Test status
Simulation time 251531757 ps
CPU time 3.51 seconds
Started Aug 03 06:40:12 PM PDT 24
Finished Aug 03 06:40:16 PM PDT 24
Peak memory 241960 kb
Host smart-0d8d14b8-1d81-4484-9fd1-3b70c3ae34e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815024504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.815024504
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.1865289389
Short name T161
Test name
Test status
Simulation time 4946050801 ps
CPU time 8.55 seconds
Started Aug 03 06:40:20 PM PDT 24
Finished Aug 03 06:40:29 PM PDT 24
Peak memory 242312 kb
Host smart-918eb561-5444-4491-abcd-6c24d36a29eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865289389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.1865289389
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.1652016259
Short name T1095
Test name
Test status
Simulation time 1712773783 ps
CPU time 39.58 seconds
Started Aug 03 06:40:18 PM PDT 24
Finished Aug 03 06:40:57 PM PDT 24
Peak memory 248512 kb
Host smart-ade8200c-f8f2-41d1-9fcd-dd4bf1b3c762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652016259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.1652016259
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.958767754
Short name T861
Test name
Test status
Simulation time 171818602 ps
CPU time 3.33 seconds
Started Aug 03 06:40:13 PM PDT 24
Finished Aug 03 06:40:16 PM PDT 24
Peak memory 242012 kb
Host smart-d64bbcc7-e5dc-4576-ac93-5a896892257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958767754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.958767754
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.3898298597
Short name T747
Test name
Test status
Simulation time 604675227 ps
CPU time 22.01 seconds
Started Aug 03 06:40:12 PM PDT 24
Finished Aug 03 06:40:34 PM PDT 24
Peak memory 242224 kb
Host smart-2dc23d0d-862f-4d50-89f1-eb3ae6b1a60a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3898298597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3898298597
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.1733992855
Short name T971
Test name
Test status
Simulation time 366380604 ps
CPU time 5.32 seconds
Started Aug 03 06:40:23 PM PDT 24
Finished Aug 03 06:40:29 PM PDT 24
Peak memory 241884 kb
Host smart-ecd84177-e459-448b-852c-9fc294c724f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1733992855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.1733992855
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.1683313553
Short name T1114
Test name
Test status
Simulation time 120327655 ps
CPU time 4.42 seconds
Started Aug 03 06:40:13 PM PDT 24
Finished Aug 03 06:40:17 PM PDT 24
Peak memory 248272 kb
Host smart-42700cff-7104-421d-8bc7-9a106aebe3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683313553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.1683313553
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.3277648463
Short name T840
Test name
Test status
Simulation time 17233885263 ps
CPU time 99.33 seconds
Started Aug 03 06:40:22 PM PDT 24
Finished Aug 03 06:42:01 PM PDT 24
Peak memory 248612 kb
Host smart-d5892519-5424-41ad-9a8f-0bd7554b8e8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277648463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.3277648463
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.868665503
Short name T339
Test name
Test status
Simulation time 170666148820 ps
CPU time 845.53 seconds
Started Aug 03 06:40:22 PM PDT 24
Finished Aug 03 06:54:28 PM PDT 24
Peak memory 281512 kb
Host smart-10a9652c-1ef3-410a-b86f-9885e42bd57c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868665503 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.868665503
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.606526222
Short name T377
Test name
Test status
Simulation time 2925091434 ps
CPU time 18.96 seconds
Started Aug 03 06:40:24 PM PDT 24
Finished Aug 03 06:40:43 PM PDT 24
Peak memory 243156 kb
Host smart-edb48957-4e55-476d-b742-881ad053b461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606526222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.606526222
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.3724620855
Short name T531
Test name
Test status
Simulation time 54408306 ps
CPU time 1.63 seconds
Started Aug 03 06:40:42 PM PDT 24
Finished Aug 03 06:40:44 PM PDT 24
Peak memory 240500 kb
Host smart-ddce3c12-4539-4eb5-9861-72da22197a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724620855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.3724620855
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.1992810059
Short name T568
Test name
Test status
Simulation time 868601262 ps
CPU time 24.53 seconds
Started Aug 03 06:40:34 PM PDT 24
Finished Aug 03 06:40:58 PM PDT 24
Peak memory 242036 kb
Host smart-165177e8-2891-43a1-8f0f-3e8218562f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992810059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.1992810059
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.1212877400
Short name T701
Test name
Test status
Simulation time 16108306620 ps
CPU time 46.99 seconds
Started Aug 03 06:40:33 PM PDT 24
Finished Aug 03 06:41:20 PM PDT 24
Peak memory 242472 kb
Host smart-bdc3d914-2566-48a6-b1a1-4be747aec6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212877400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.1212877400
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.1211099257
Short name T883
Test name
Test status
Simulation time 328455106 ps
CPU time 3.66 seconds
Started Aug 03 06:40:31 PM PDT 24
Finished Aug 03 06:40:34 PM PDT 24
Peak memory 242116 kb
Host smart-5d8542b5-f593-4883-9872-6e6183690c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211099257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.1211099257
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.2389867381
Short name T923
Test name
Test status
Simulation time 5074684756 ps
CPU time 36.31 seconds
Started Aug 03 06:40:39 PM PDT 24
Finished Aug 03 06:41:16 PM PDT 24
Peak memory 256924 kb
Host smart-a0e93bea-a496-4633-b31d-95dd5535abe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389867381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2389867381
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.3412244332
Short name T379
Test name
Test status
Simulation time 1147251860 ps
CPU time 20.47 seconds
Started Aug 03 06:40:39 PM PDT 24
Finished Aug 03 06:40:59 PM PDT 24
Peak memory 242284 kb
Host smart-a9bae4e8-a686-4aef-8403-515fbbc62dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412244332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.3412244332
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.2717313473
Short name T417
Test name
Test status
Simulation time 3806792691 ps
CPU time 30.75 seconds
Started Aug 03 06:40:30 PM PDT 24
Finished Aug 03 06:41:01 PM PDT 24
Peak memory 242012 kb
Host smart-f1f146b7-2740-40e4-bab5-4a97bf3bdb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717313473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.2717313473
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.913696213
Short name T1138
Test name
Test status
Simulation time 497635988 ps
CPU time 18.96 seconds
Started Aug 03 06:40:31 PM PDT 24
Finished Aug 03 06:40:50 PM PDT 24
Peak memory 241908 kb
Host smart-ea72dc59-7339-4f58-98bc-d4a703e96f6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=913696213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.913696213
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.1117284892
Short name T843
Test name
Test status
Simulation time 969425594 ps
CPU time 9.64 seconds
Started Aug 03 06:40:40 PM PDT 24
Finished Aug 03 06:40:49 PM PDT 24
Peak memory 241960 kb
Host smart-05c7c385-daef-4cd3-823c-0831db082138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117284892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.1117284892
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.3354637914
Short name T1073
Test name
Test status
Simulation time 411156751 ps
CPU time 6.31 seconds
Started Aug 03 06:40:32 PM PDT 24
Finished Aug 03 06:40:39 PM PDT 24
Peak memory 242380 kb
Host smart-6551eb27-a327-45b5-ba68-68fbb38fc109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354637914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3354637914
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.2893667871
Short name T1108
Test name
Test status
Simulation time 5043721286 ps
CPU time 176.25 seconds
Started Aug 03 06:40:42 PM PDT 24
Finished Aug 03 06:43:38 PM PDT 24
Peak memory 248852 kb
Host smart-f3cec352-5137-4cfd-a218-bcfe509bc3c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893667871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.2893667871
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.49343150
Short name T320
Test name
Test status
Simulation time 1658368359 ps
CPU time 18.34 seconds
Started Aug 03 06:40:38 PM PDT 24
Finished Aug 03 06:40:56 PM PDT 24
Peak memory 242184 kb
Host smart-c8609d56-82d6-4d35-bd79-690915a0d51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49343150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.49343150
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.3839656418
Short name T1013
Test name
Test status
Simulation time 66107161 ps
CPU time 1.83 seconds
Started Aug 03 06:40:54 PM PDT 24
Finished Aug 03 06:40:56 PM PDT 24
Peak memory 240412 kb
Host smart-3407ca27-36cf-4dfe-95f8-47618c53ccbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839656418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.3839656418
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.1023071374
Short name T120
Test name
Test status
Simulation time 1225324764 ps
CPU time 29.92 seconds
Started Aug 03 06:40:47 PM PDT 24
Finished Aug 03 06:41:17 PM PDT 24
Peak memory 242312 kb
Host smart-e72a5379-1523-4eea-94cc-9b16a076b6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023071374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.1023071374
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.2395524973
Short name T1018
Test name
Test status
Simulation time 281204992 ps
CPU time 15.68 seconds
Started Aug 03 06:40:50 PM PDT 24
Finished Aug 03 06:41:05 PM PDT 24
Peak memory 241972 kb
Host smart-72764116-5861-4ea6-89fa-ef416a5f070d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395524973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.2395524973
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.4035374778
Short name T1084
Test name
Test status
Simulation time 5488864746 ps
CPU time 12.26 seconds
Started Aug 03 06:40:48 PM PDT 24
Finished Aug 03 06:41:00 PM PDT 24
Peak memory 242152 kb
Host smart-cb808c07-e077-48bf-938f-7766d2e74beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035374778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.4035374778
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.3295773216
Short name T721
Test name
Test status
Simulation time 212268802 ps
CPU time 4.02 seconds
Started Aug 03 06:40:43 PM PDT 24
Finished Aug 03 06:40:47 PM PDT 24
Peak memory 241952 kb
Host smart-787569e2-d099-4e65-891e-69d6197afddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295773216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.3295773216
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.513660893
Short name T1101
Test name
Test status
Simulation time 1085760350 ps
CPU time 15.08 seconds
Started Aug 03 06:40:49 PM PDT 24
Finished Aug 03 06:41:04 PM PDT 24
Peak memory 244020 kb
Host smart-08cce573-a399-4309-ae79-5498b944c89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513660893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.513660893
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.3072487590
Short name T1015
Test name
Test status
Simulation time 1229414025 ps
CPU time 28.1 seconds
Started Aug 03 06:40:54 PM PDT 24
Finished Aug 03 06:41:23 PM PDT 24
Peak memory 242632 kb
Host smart-767a96e3-6d55-4c65-b099-a40b3468fc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072487590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.3072487590
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.268356012
Short name T662
Test name
Test status
Simulation time 4746794722 ps
CPU time 19.72 seconds
Started Aug 03 06:40:48 PM PDT 24
Finished Aug 03 06:41:08 PM PDT 24
Peak memory 242392 kb
Host smart-0caa75a1-35ca-48a0-9dd8-dc6ab3bdd39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268356012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.268356012
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.858503852
Short name T384
Test name
Test status
Simulation time 666228432 ps
CPU time 17.53 seconds
Started Aug 03 06:40:43 PM PDT 24
Finished Aug 03 06:41:01 PM PDT 24
Peak memory 248668 kb
Host smart-43277cc8-15ac-4969-bfe6-5b3375bbe231
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=858503852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.858503852
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.1705914810
Short name T268
Test name
Test status
Simulation time 407790918 ps
CPU time 5.81 seconds
Started Aug 03 06:40:53 PM PDT 24
Finished Aug 03 06:40:58 PM PDT 24
Peak memory 248516 kb
Host smart-02ab6e00-7de2-4c46-bb8f-a3b475313670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705914810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1705914810
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.3756936851
Short name T1117
Test name
Test status
Simulation time 26428067336 ps
CPU time 371.62 seconds
Started Aug 03 06:40:53 PM PDT 24
Finished Aug 03 06:47:05 PM PDT 24
Peak memory 293920 kb
Host smart-30940f46-efe3-491f-8758-f49bdcb6de96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756936851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.3756936851
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.1057489450
Short name T462
Test name
Test status
Simulation time 59244018529 ps
CPU time 505.97 seconds
Started Aug 03 06:40:52 PM PDT 24
Finished Aug 03 06:49:18 PM PDT 24
Peak memory 249216 kb
Host smart-3cdc36bf-6d83-4e42-81e0-325c90e05fdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057489450 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.1057489450
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.2528505941
Short name T1046
Test name
Test status
Simulation time 144863798 ps
CPU time 1.76 seconds
Started Aug 03 06:41:14 PM PDT 24
Finished Aug 03 06:41:16 PM PDT 24
Peak memory 240556 kb
Host smart-23229552-0c44-4a9c-bb1f-30f9108240c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528505941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.2528505941
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.2616161573
Short name T1020
Test name
Test status
Simulation time 247916670 ps
CPU time 5.92 seconds
Started Aug 03 06:40:59 PM PDT 24
Finished Aug 03 06:41:05 PM PDT 24
Peak memory 248524 kb
Host smart-f5762afc-ec04-44c4-9ac9-7b5fafb2f62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616161573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2616161573
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.1141581534
Short name T703
Test name
Test status
Simulation time 23882883386 ps
CPU time 51.34 seconds
Started Aug 03 06:40:58 PM PDT 24
Finished Aug 03 06:41:49 PM PDT 24
Peak memory 256252 kb
Host smart-84c39f6b-e6d4-48aa-b55b-e653078e2fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141581534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.1141581534
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.1647158020
Short name T960
Test name
Test status
Simulation time 4225612804 ps
CPU time 23.56 seconds
Started Aug 03 06:41:00 PM PDT 24
Finished Aug 03 06:41:24 PM PDT 24
Peak memory 248560 kb
Host smart-29fc0c74-0a7d-4a90-a4b6-995030860965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647158020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.1647158020
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.3312799746
Short name T791
Test name
Test status
Simulation time 160486156 ps
CPU time 4.23 seconds
Started Aug 03 06:40:59 PM PDT 24
Finished Aug 03 06:41:03 PM PDT 24
Peak memory 242248 kb
Host smart-fe62e487-00c9-457b-a9ed-dc08bfe9318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312799746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.3312799746
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.3894190090
Short name T699
Test name
Test status
Simulation time 1821100601 ps
CPU time 18.07 seconds
Started Aug 03 06:41:04 PM PDT 24
Finished Aug 03 06:41:22 PM PDT 24
Peak memory 242244 kb
Host smart-03105a3a-993e-4229-b490-41f35ea4666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894190090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.3894190090
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.3083024573
Short name T609
Test name
Test status
Simulation time 4873078531 ps
CPU time 14.56 seconds
Started Aug 03 06:40:58 PM PDT 24
Finished Aug 03 06:41:13 PM PDT 24
Peak memory 242480 kb
Host smart-a17b4ac2-9856-4888-b36a-a7ead680d8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083024573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3083024573
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.1776506956
Short name T290
Test name
Test status
Simulation time 1970610750 ps
CPU time 18.87 seconds
Started Aug 03 06:40:56 PM PDT 24
Finished Aug 03 06:41:15 PM PDT 24
Peak memory 241900 kb
Host smart-a12e7a44-a8a4-4561-9146-9d0758fd0d2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776506956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1776506956
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.2591021249
Short name T653
Test name
Test status
Simulation time 245691620 ps
CPU time 3.56 seconds
Started Aug 03 06:41:03 PM PDT 24
Finished Aug 03 06:41:06 PM PDT 24
Peak memory 242024 kb
Host smart-bdb160b6-0ca2-40bf-abef-83ea3e0a504b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591021249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.2591021249
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.2576146421
Short name T763
Test name
Test status
Simulation time 515840046 ps
CPU time 5.89 seconds
Started Aug 03 06:40:52 PM PDT 24
Finished Aug 03 06:40:58 PM PDT 24
Peak memory 241956 kb
Host smart-07e20ca0-0de4-4daa-9554-18166435a664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576146421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2576146421
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.1497163972
Short name T750
Test name
Test status
Simulation time 18908748065 ps
CPU time 201.82 seconds
Started Aug 03 06:41:09 PM PDT 24
Finished Aug 03 06:44:31 PM PDT 24
Peak memory 256788 kb
Host smart-af180e56-2bf4-47e1-a703-dd097890a309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497163972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.1497163972
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.3622251543
Short name T855
Test name
Test status
Simulation time 1045509902 ps
CPU time 13.21 seconds
Started Aug 03 06:41:08 PM PDT 24
Finished Aug 03 06:41:22 PM PDT 24
Peak memory 241992 kb
Host smart-59d31a00-c03b-4cdc-8c68-e3c2062da03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622251543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.3622251543
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.1741030422
Short name T440
Test name
Test status
Simulation time 48129656 ps
CPU time 1.67 seconds
Started Aug 03 06:41:32 PM PDT 24
Finished Aug 03 06:41:34 PM PDT 24
Peak memory 240360 kb
Host smart-0d4e62d0-e0ca-4a27-8704-43e834aacd01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741030422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.1741030422
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.3249203564
Short name T740
Test name
Test status
Simulation time 1964065636 ps
CPU time 15.61 seconds
Started Aug 03 06:41:23 PM PDT 24
Finished Aug 03 06:41:38 PM PDT 24
Peak memory 242088 kb
Host smart-522fc2a3-2efc-4048-a817-85e9bc1d6134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249203564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.3249203564
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.2094159634
Short name T765
Test name
Test status
Simulation time 973199284 ps
CPU time 32.33 seconds
Started Aug 03 06:41:20 PM PDT 24
Finished Aug 03 06:41:52 PM PDT 24
Peak memory 242516 kb
Host smart-46ef2559-a9a0-479e-b78f-89c4424bac36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094159634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2094159634
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.1145573113
Short name T452
Test name
Test status
Simulation time 111457177 ps
CPU time 3.34 seconds
Started Aug 03 06:41:21 PM PDT 24
Finished Aug 03 06:41:24 PM PDT 24
Peak memory 241960 kb
Host smart-501815ef-498c-49d2-ad30-9bac3994ee34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145573113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.1145573113
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.494379213
Short name T838
Test name
Test status
Simulation time 148292206 ps
CPU time 3.31 seconds
Started Aug 03 06:41:17 PM PDT 24
Finished Aug 03 06:41:21 PM PDT 24
Peak memory 242116 kb
Host smart-d8fcace3-d458-4637-91e8-8703064e5485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494379213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.494379213
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.430215460
Short name T649
Test name
Test status
Simulation time 4781094824 ps
CPU time 41.48 seconds
Started Aug 03 06:41:19 PM PDT 24
Finished Aug 03 06:42:00 PM PDT 24
Peak memory 256880 kb
Host smart-cd735dbb-1264-4232-a5b7-d9a184862dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430215460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.430215460
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.3773218452
Short name T421
Test name
Test status
Simulation time 336494181 ps
CPU time 4.69 seconds
Started Aug 03 06:41:20 PM PDT 24
Finished Aug 03 06:41:25 PM PDT 24
Peak memory 241852 kb
Host smart-ccceda99-50b3-415a-b8d8-1288aa2df11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773218452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3773218452
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.2316100552
Short name T836
Test name
Test status
Simulation time 229966535 ps
CPU time 5.66 seconds
Started Aug 03 06:41:21 PM PDT 24
Finished Aug 03 06:41:27 PM PDT 24
Peak memory 241944 kb
Host smart-94ca4801-bab0-4724-82ee-24b4f79eb7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316100552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.2316100552
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.2990956837
Short name T993
Test name
Test status
Simulation time 515960033 ps
CPU time 5.01 seconds
Started Aug 03 06:41:19 PM PDT 24
Finished Aug 03 06:41:24 PM PDT 24
Peak memory 242276 kb
Host smart-2be28720-93eb-4901-b57e-f7b349d01d2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990956837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.2990956837
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.2486732376
Short name T270
Test name
Test status
Simulation time 1226195999 ps
CPU time 9.58 seconds
Started Aug 03 06:41:26 PM PDT 24
Finished Aug 03 06:41:36 PM PDT 24
Peak memory 241980 kb
Host smart-27033b17-b340-4c48-b438-d08fecedf5ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486732376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2486732376
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.176500492
Short name T636
Test name
Test status
Simulation time 729405504 ps
CPU time 6.76 seconds
Started Aug 03 06:41:14 PM PDT 24
Finished Aug 03 06:41:21 PM PDT 24
Peak memory 241936 kb
Host smart-8230be20-75e2-4e4d-bcde-6442ac3f1981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176500492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.176500492
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.671225378
Short name T1057
Test name
Test status
Simulation time 19587026042 ps
CPU time 90.83 seconds
Started Aug 03 06:41:25 PM PDT 24
Finished Aug 03 06:42:56 PM PDT 24
Peak memory 245140 kb
Host smart-124731bc-7d07-4fe7-8ad2-91985a0f45b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671225378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.
671225378
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.1632088181
Short name T183
Test name
Test status
Simulation time 68883537312 ps
CPU time 1133.27 seconds
Started Aug 03 06:41:27 PM PDT 24
Finished Aug 03 07:00:20 PM PDT 24
Peak memory 428616 kb
Host smart-d2c9055e-1335-469f-b66e-c3d1b68dfd54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632088181 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.1632088181
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.759954037
Short name T600
Test name
Test status
Simulation time 949869308 ps
CPU time 19.69 seconds
Started Aug 03 06:41:26 PM PDT 24
Finished Aug 03 06:41:46 PM PDT 24
Peak memory 241864 kb
Host smart-685bf588-f54d-43ae-bc57-5cba5c6f9507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759954037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.759954037
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.4122617272
Short name T564
Test name
Test status
Simulation time 72441333 ps
CPU time 1.95 seconds
Started Aug 03 06:41:45 PM PDT 24
Finished Aug 03 06:41:47 PM PDT 24
Peak memory 240740 kb
Host smart-9bcf3ec9-1e76-4be4-8c9f-3efdfc335c9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122617272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.4122617272
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.1830165570
Short name T542
Test name
Test status
Simulation time 4439707316 ps
CPU time 12.32 seconds
Started Aug 03 06:41:34 PM PDT 24
Finished Aug 03 06:41:47 PM PDT 24
Peak memory 243340 kb
Host smart-9dbe0a2c-aff1-499e-bc27-3e56972d9589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830165570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.1830165570
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.801014727
Short name T171
Test name
Test status
Simulation time 1265137988 ps
CPU time 16.47 seconds
Started Aug 03 06:41:36 PM PDT 24
Finished Aug 03 06:41:52 PM PDT 24
Peak memory 242072 kb
Host smart-e740b471-df74-437f-b22e-1f7b6b2fde4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801014727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.801014727
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.2099409023
Short name T818
Test name
Test status
Simulation time 609421715 ps
CPU time 4.57 seconds
Started Aug 03 06:41:35 PM PDT 24
Finished Aug 03 06:41:40 PM PDT 24
Peak memory 241924 kb
Host smart-a40431d0-54fe-477a-ab41-55c94b501575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099409023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.2099409023
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.820383414
Short name T589
Test name
Test status
Simulation time 333922295 ps
CPU time 4.58 seconds
Started Aug 03 06:41:31 PM PDT 24
Finished Aug 03 06:41:36 PM PDT 24
Peak memory 242148 kb
Host smart-a2d0b31a-ea6f-44f5-b90c-e6ae6ee9fb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820383414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.820383414
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.4106496745
Short name T678
Test name
Test status
Simulation time 1982392116 ps
CPU time 5.28 seconds
Started Aug 03 06:41:35 PM PDT 24
Finished Aug 03 06:41:40 PM PDT 24
Peak memory 242052 kb
Host smart-5ad95833-3dff-44ab-be70-94fab3324d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106496745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.4106496745
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.1073612649
Short name T229
Test name
Test status
Simulation time 363724288 ps
CPU time 10.8 seconds
Started Aug 03 06:41:34 PM PDT 24
Finished Aug 03 06:41:45 PM PDT 24
Peak memory 242048 kb
Host smart-c4192340-9432-4c63-891f-1880b8e77516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073612649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1073612649
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.3839615941
Short name T1019
Test name
Test status
Simulation time 349009935 ps
CPU time 3.33 seconds
Started Aug 03 06:41:35 PM PDT 24
Finished Aug 03 06:41:38 PM PDT 24
Peak memory 241988 kb
Host smart-d141b663-0387-454c-9532-59f8e2c55ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839615941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.3839615941
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.2941067624
Short name T762
Test name
Test status
Simulation time 568774468 ps
CPU time 6.16 seconds
Started Aug 03 06:41:45 PM PDT 24
Finished Aug 03 06:41:51 PM PDT 24
Peak memory 241984 kb
Host smart-f68c0158-a3ff-4f9e-b340-6e52a64648ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2941067624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.2941067624
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.2062595552
Short name T347
Test name
Test status
Simulation time 1346770833 ps
CPU time 9.34 seconds
Started Aug 03 06:41:33 PM PDT 24
Finished Aug 03 06:41:42 PM PDT 24
Peak memory 248528 kb
Host smart-94e003c7-9016-474a-ae61-d11b2c8440c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062595552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.2062595552
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.4124342379
Short name T376
Test name
Test status
Simulation time 4863829524 ps
CPU time 58.13 seconds
Started Aug 03 06:41:45 PM PDT 24
Finished Aug 03 06:42:43 PM PDT 24
Peak memory 244112 kb
Host smart-749b4420-77c0-45c5-a0b8-10723575ec51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124342379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.4124342379
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.2074953005
Short name T767
Test name
Test status
Simulation time 2823686375 ps
CPU time 39.88 seconds
Started Aug 03 06:41:41 PM PDT 24
Finished Aug 03 06:42:21 PM PDT 24
Peak memory 243200 kb
Host smart-0ad6c5f9-9952-4dbc-b051-1758465f02ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074953005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.2074953005
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.1369438438
Short name T764
Test name
Test status
Simulation time 97230332 ps
CPU time 1.61 seconds
Started Aug 03 06:41:59 PM PDT 24
Finished Aug 03 06:42:01 PM PDT 24
Peak memory 240572 kb
Host smart-c6485018-b546-4884-9b3a-bb0e341ad513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369438438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.1369438438
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.2410889396
Short name T85
Test name
Test status
Simulation time 589634818 ps
CPU time 11.17 seconds
Started Aug 03 06:41:55 PM PDT 24
Finished Aug 03 06:42:06 PM PDT 24
Peak memory 242604 kb
Host smart-f0878dbb-bf74-49ab-8c51-ef609da25b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410889396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.2410889396
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.2250714789
Short name T834
Test name
Test status
Simulation time 689446892 ps
CPU time 8.4 seconds
Started Aug 03 06:41:50 PM PDT 24
Finished Aug 03 06:41:59 PM PDT 24
Peak memory 242372 kb
Host smart-5f717689-3e19-486e-9140-892aedf0335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250714789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.2250714789
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.1176053646
Short name T869
Test name
Test status
Simulation time 1265881215 ps
CPU time 18.14 seconds
Started Aug 03 06:41:54 PM PDT 24
Finished Aug 03 06:42:12 PM PDT 24
Peak memory 242236 kb
Host smart-6236007f-219e-4001-8e3b-4145d6ff35c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176053646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.1176053646
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.2930440631
Short name T753
Test name
Test status
Simulation time 139346744 ps
CPU time 3.64 seconds
Started Aug 03 06:41:45 PM PDT 24
Finished Aug 03 06:41:48 PM PDT 24
Peak memory 241992 kb
Host smart-377801a4-8b4b-417b-9473-7576de234dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930440631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.2930440631
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.4045900084
Short name T996
Test name
Test status
Simulation time 3998538651 ps
CPU time 8.02 seconds
Started Aug 03 06:41:52 PM PDT 24
Finished Aug 03 06:42:00 PM PDT 24
Peak memory 245180 kb
Host smart-f47cf877-5985-486e-80de-64296d510efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045900084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.4045900084
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.2071082143
Short name T543
Test name
Test status
Simulation time 6081846890 ps
CPU time 21.27 seconds
Started Aug 03 06:41:56 PM PDT 24
Finished Aug 03 06:42:17 PM PDT 24
Peak memory 242332 kb
Host smart-79c1c628-6a4b-4936-8d04-4cf04ef325ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071082143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.2071082143
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.880438990
Short name T1031
Test name
Test status
Simulation time 386386662 ps
CPU time 9.99 seconds
Started Aug 03 06:41:51 PM PDT 24
Finished Aug 03 06:42:01 PM PDT 24
Peak memory 241864 kb
Host smart-fae68d29-26a6-4a8d-8c94-5531405e2cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880438990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.880438990
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.3307843862
Short name T489
Test name
Test status
Simulation time 9556106933 ps
CPU time 25.86 seconds
Started Aug 03 06:41:50 PM PDT 24
Finished Aug 03 06:42:16 PM PDT 24
Peak memory 242148 kb
Host smart-331a5d6d-c244-4287-b25d-647e8e5aacd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3307843862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.3307843862
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.3609368896
Short name T3
Test name
Test status
Simulation time 517892404 ps
CPU time 10.46 seconds
Started Aug 03 06:41:45 PM PDT 24
Finished Aug 03 06:41:55 PM PDT 24
Peak memory 242088 kb
Host smart-504c7d55-b72a-42c5-b7ba-29916a4a965a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609368896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3609368896
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.3043514104
Short name T1028
Test name
Test status
Simulation time 13440622502 ps
CPU time 164.93 seconds
Started Aug 03 06:41:58 PM PDT 24
Finished Aug 03 06:44:44 PM PDT 24
Peak memory 265008 kb
Host smart-0598856d-e187-4e40-9dd9-30d70f704136
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043514104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.3043514104
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.2803496078
Short name T432
Test name
Test status
Simulation time 51598316883 ps
CPU time 255.26 seconds
Started Aug 03 06:41:57 PM PDT 24
Finished Aug 03 06:46:13 PM PDT 24
Peak memory 248704 kb
Host smart-51ae0d50-769e-43c4-9116-b272f3efe96b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803496078 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.2803496078
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.546459583
Short name T857
Test name
Test status
Simulation time 1988343588 ps
CPU time 14.88 seconds
Started Aug 03 06:41:56 PM PDT 24
Finished Aug 03 06:42:11 PM PDT 24
Peak memory 241988 kb
Host smart-6a87dc73-4367-4c56-abb7-0f67663091ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546459583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.546459583
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.2990960553
Short name T810
Test name
Test status
Simulation time 362595779 ps
CPU time 2.24 seconds
Started Aug 03 06:42:16 PM PDT 24
Finished Aug 03 06:42:18 PM PDT 24
Peak memory 240704 kb
Host smart-59258f5b-caed-4bb5-81d7-a1c1011333db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990960553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2990960553
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.2377989787
Short name T47
Test name
Test status
Simulation time 351643453 ps
CPU time 8.26 seconds
Started Aug 03 06:42:12 PM PDT 24
Finished Aug 03 06:42:21 PM PDT 24
Peak memory 242508 kb
Host smart-aac22224-801f-48d6-881d-3128ef20a830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377989787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.2377989787
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.936211683
Short name T1180
Test name
Test status
Simulation time 15799350899 ps
CPU time 40.74 seconds
Started Aug 03 06:42:08 PM PDT 24
Finished Aug 03 06:42:49 PM PDT 24
Peak memory 246256 kb
Host smart-c3b7e9e5-ea4e-4366-bce7-ec8fed156350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936211683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.936211683
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.255407768
Short name T867
Test name
Test status
Simulation time 3111693900 ps
CPU time 27.96 seconds
Started Aug 03 06:42:07 PM PDT 24
Finished Aug 03 06:42:35 PM PDT 24
Peak memory 242188 kb
Host smart-59dbff93-8b4c-443b-8a05-0a5b1c291632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255407768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.255407768
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.2491485034
Short name T1103
Test name
Test status
Simulation time 116931690 ps
CPU time 3.91 seconds
Started Aug 03 06:42:01 PM PDT 24
Finished Aug 03 06:42:05 PM PDT 24
Peak memory 241968 kb
Host smart-fd6a73db-973a-4ab4-8bd1-e1760f622714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491485034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2491485034
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.4213622761
Short name T906
Test name
Test status
Simulation time 867305660 ps
CPU time 30.68 seconds
Started Aug 03 06:42:14 PM PDT 24
Finished Aug 03 06:42:45 PM PDT 24
Peak memory 242072 kb
Host smart-1f142738-bd6e-4cd2-bf8a-c4ccb4055b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213622761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.4213622761
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.3331884704
Short name T527
Test name
Test status
Simulation time 1265237493 ps
CPU time 27.5 seconds
Started Aug 03 06:42:13 PM PDT 24
Finished Aug 03 06:42:40 PM PDT 24
Peak memory 248656 kb
Host smart-f7eee1b8-29f0-498c-804d-cfe5b7303e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331884704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.3331884704
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.142504265
Short name T1109
Test name
Test status
Simulation time 10713111707 ps
CPU time 36.74 seconds
Started Aug 03 06:42:01 PM PDT 24
Finished Aug 03 06:42:37 PM PDT 24
Peak memory 242072 kb
Host smart-7fd35ddd-0748-423b-8662-c0506f5ff76c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=142504265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.142504265
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.382665095
Short name T370
Test name
Test status
Simulation time 1658208604 ps
CPU time 6.78 seconds
Started Aug 03 06:42:17 PM PDT 24
Finished Aug 03 06:42:24 PM PDT 24
Peak memory 241852 kb
Host smart-e1df0be0-0cad-47f5-b7c9-2aebe87ce469
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382665095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.382665095
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.2729460928
Short name T544
Test name
Test status
Simulation time 171330733 ps
CPU time 3.85 seconds
Started Aug 03 06:41:56 PM PDT 24
Finished Aug 03 06:42:00 PM PDT 24
Peak memory 242248 kb
Host smart-480df4c9-966c-4c21-8b51-9d0a5be8805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729460928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.2729460928
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.110034899
Short name T682
Test name
Test status
Simulation time 28254569790 ps
CPU time 162.85 seconds
Started Aug 03 06:42:16 PM PDT 24
Finished Aug 03 06:44:59 PM PDT 24
Peak memory 256856 kb
Host smart-2f632463-8b74-4819-967e-8c675d5be949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110034899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.
110034899
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.4070291036
Short name T1160
Test name
Test status
Simulation time 610994028 ps
CPU time 10.01 seconds
Started Aug 03 06:42:15 PM PDT 24
Finished Aug 03 06:42:25 PM PDT 24
Peak memory 242192 kb
Host smart-7b5df801-721b-4d15-865b-41e7a3d7709a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070291036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.4070291036
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.1767936110
Short name T841
Test name
Test status
Simulation time 51409859 ps
CPU time 1.68 seconds
Started Aug 03 06:42:38 PM PDT 24
Finished Aug 03 06:42:40 PM PDT 24
Peak memory 240480 kb
Host smart-aacf81fb-3418-47be-bbee-f489ff169ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767936110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.1767936110
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.2085310922
Short name T102
Test name
Test status
Simulation time 2140994461 ps
CPU time 14.77 seconds
Started Aug 03 06:42:26 PM PDT 24
Finished Aug 03 06:42:41 PM PDT 24
Peak memory 244672 kb
Host smart-410e83f5-397e-435c-971c-72a662c70731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085310922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.2085310922
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.2408840087
Short name T684
Test name
Test status
Simulation time 3113877074 ps
CPU time 45.05 seconds
Started Aug 03 06:42:26 PM PDT 24
Finished Aug 03 06:43:11 PM PDT 24
Peak memory 250928 kb
Host smart-f4137577-259d-46fa-aba7-a18d02ece482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408840087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.2408840087
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.2825269255
Short name T1148
Test name
Test status
Simulation time 2413496694 ps
CPU time 8.38 seconds
Started Aug 03 06:42:22 PM PDT 24
Finished Aug 03 06:42:31 PM PDT 24
Peak memory 242420 kb
Host smart-c7a643b3-ca0e-48db-ad26-7b16734fcdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825269255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.2825269255
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.4140081953
Short name T439
Test name
Test status
Simulation time 256973815 ps
CPU time 4.27 seconds
Started Aug 03 06:42:23 PM PDT 24
Finished Aug 03 06:42:27 PM PDT 24
Peak memory 242136 kb
Host smart-3d726294-fe76-46b0-801f-80979456589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140081953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.4140081953
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.250088490
Short name T391
Test name
Test status
Simulation time 9614316441 ps
CPU time 16.72 seconds
Started Aug 03 06:42:26 PM PDT 24
Finished Aug 03 06:42:43 PM PDT 24
Peak memory 242516 kb
Host smart-1e5ff3e0-7a2a-434a-b706-2c5ea12993d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250088490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.250088490
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.3294992140
Short name T455
Test name
Test status
Simulation time 16000037100 ps
CPU time 37.48 seconds
Started Aug 03 06:42:26 PM PDT 24
Finished Aug 03 06:43:04 PM PDT 24
Peak memory 243684 kb
Host smart-4cc96afe-fded-494d-b0aa-8ab70cb9012f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294992140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.3294992140
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.137804673
Short name T728
Test name
Test status
Simulation time 589948732 ps
CPU time 7.37 seconds
Started Aug 03 06:42:24 PM PDT 24
Finished Aug 03 06:42:31 PM PDT 24
Peak memory 248092 kb
Host smart-83175adc-a512-4388-91e2-b1362ef6d628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137804673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.137804673
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.50122055
Short name T616
Test name
Test status
Simulation time 826800223 ps
CPU time 27.95 seconds
Started Aug 03 06:42:21 PM PDT 24
Finished Aug 03 06:42:49 PM PDT 24
Peak memory 242136 kb
Host smart-fb8399e0-8e0d-46b0-a435-af557e6e8ae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50122055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.50122055
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.3012927258
Short name T1106
Test name
Test status
Simulation time 913210051 ps
CPU time 9.5 seconds
Started Aug 03 06:42:22 PM PDT 24
Finished Aug 03 06:42:32 PM PDT 24
Peak memory 242096 kb
Host smart-dad8d5f0-37a1-48ac-a35f-8ce5cfa74220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012927258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.3012927258
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.794358151
Short name T1144
Test name
Test status
Simulation time 7987644820 ps
CPU time 46.46 seconds
Started Aug 03 06:42:38 PM PDT 24
Finished Aug 03 06:43:25 PM PDT 24
Peak memory 244860 kb
Host smart-5a108975-1fb5-4d32-b5bc-0dde4c6fac8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794358151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.
794358151
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.182902104
Short name T702
Test name
Test status
Simulation time 20363775950 ps
CPU time 563.67 seconds
Started Aug 03 06:42:32 PM PDT 24
Finished Aug 03 06:51:55 PM PDT 24
Peak memory 297992 kb
Host smart-84e6cada-e193-45c8-8856-ff83f9947b5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182902104 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.182902104
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.2531096010
Short name T941
Test name
Test status
Simulation time 838085398 ps
CPU time 9.65 seconds
Started Aug 03 06:42:32 PM PDT 24
Finished Aug 03 06:42:42 PM PDT 24
Peak memory 242500 kb
Host smart-893d4a89-5911-4c4e-8126-adc58c06e211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531096010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.2531096010
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.340799841
Short name T1076
Test name
Test status
Simulation time 100233181 ps
CPU time 1.66 seconds
Started Aug 03 06:42:57 PM PDT 24
Finished Aug 03 06:42:58 PM PDT 24
Peak memory 240456 kb
Host smart-a089617e-0a66-42ff-b296-ca49cb98b38b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340799841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.340799841
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.3894936186
Short name T84
Test name
Test status
Simulation time 2435792665 ps
CPU time 13.16 seconds
Started Aug 03 06:42:47 PM PDT 24
Finished Aug 03 06:43:00 PM PDT 24
Peak memory 248572 kb
Host smart-dde065fa-fafd-4e18-baba-e95d284a4e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894936186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.3894936186
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.1762207799
Short name T864
Test name
Test status
Simulation time 2318723053 ps
CPU time 15.77 seconds
Started Aug 03 06:42:43 PM PDT 24
Finished Aug 03 06:42:59 PM PDT 24
Peak memory 242016 kb
Host smart-e71def9a-dc51-4bbc-aacf-95199e7edc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762207799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1762207799
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.4090772331
Short name T629
Test name
Test status
Simulation time 766985778 ps
CPU time 8.74 seconds
Started Aug 03 06:42:43 PM PDT 24
Finished Aug 03 06:42:52 PM PDT 24
Peak memory 242304 kb
Host smart-a5a5397b-eadb-46e4-8006-ec2bbf8fbeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090772331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.4090772331
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.1204517118
Short name T39
Test name
Test status
Simulation time 174089557 ps
CPU time 4.31 seconds
Started Aug 03 06:42:38 PM PDT 24
Finished Aug 03 06:42:43 PM PDT 24
Peak memory 241948 kb
Host smart-41dea8ed-9342-4256-b10f-5c6554665242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204517118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.1204517118
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.2493320804
Short name T683
Test name
Test status
Simulation time 6967719813 ps
CPU time 41.74 seconds
Started Aug 03 06:42:47 PM PDT 24
Finished Aug 03 06:43:29 PM PDT 24
Peak memory 248672 kb
Host smart-b7b0f413-7484-4cc7-94e5-c6db66848fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493320804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.2493320804
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.2287679450
Short name T1119
Test name
Test status
Simulation time 1764096706 ps
CPU time 33.82 seconds
Started Aug 03 06:42:52 PM PDT 24
Finished Aug 03 06:43:26 PM PDT 24
Peak memory 242244 kb
Host smart-b03a5f79-ee1c-43a5-8386-4bef3c285a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287679450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.2287679450
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.1808610150
Short name T1030
Test name
Test status
Simulation time 561517556 ps
CPU time 5.62 seconds
Started Aug 03 06:42:39 PM PDT 24
Finished Aug 03 06:42:45 PM PDT 24
Peak memory 242012 kb
Host smart-23354c27-c73b-4ec5-8570-07957ba9d908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808610150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.1808610150
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.4184434692
Short name T635
Test name
Test status
Simulation time 622470172 ps
CPU time 7.63 seconds
Started Aug 03 06:42:36 PM PDT 24
Finished Aug 03 06:42:44 PM PDT 24
Peak memory 248616 kb
Host smart-fb7c84fd-e258-4224-8704-9765a972f53f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4184434692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.4184434692
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.3448125930
Short name T528
Test name
Test status
Simulation time 275825832 ps
CPU time 6.98 seconds
Started Aug 03 06:42:52 PM PDT 24
Finished Aug 03 06:42:59 PM PDT 24
Peak memory 241932 kb
Host smart-de38956a-e026-42fa-824a-e3bbff35bac7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448125930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.3448125930
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.537136878
Short name T953
Test name
Test status
Simulation time 10303689662 ps
CPU time 20.57 seconds
Started Aug 03 06:42:40 PM PDT 24
Finished Aug 03 06:43:00 PM PDT 24
Peak memory 242024 kb
Host smart-1c77d22d-84e1-4b49-ba78-401054827e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537136878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.537136878
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.3743237586
Short name T1056
Test name
Test status
Simulation time 2641684312 ps
CPU time 60.03 seconds
Started Aug 03 06:42:58 PM PDT 24
Finished Aug 03 06:43:58 PM PDT 24
Peak memory 243532 kb
Host smart-909eb809-a631-4cda-bc3e-5d57a733ca8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743237586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.3743237586
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.4108682538
Short name T298
Test name
Test status
Simulation time 89306477326 ps
CPU time 1637.28 seconds
Started Aug 03 06:42:57 PM PDT 24
Finished Aug 03 07:10:15 PM PDT 24
Peak memory 314400 kb
Host smart-4c391e66-daae-4af1-abb6-8ee4de524e4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108682538 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.4108682538
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.1242592117
Short name T742
Test name
Test status
Simulation time 255340285 ps
CPU time 6.05 seconds
Started Aug 03 06:42:52 PM PDT 24
Finished Aug 03 06:42:59 PM PDT 24
Peak memory 242260 kb
Host smart-65a4872f-5bfd-4f76-81b4-48bd87b028ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242592117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.1242592117
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.3540825880
Short name T235
Test name
Test status
Simulation time 50726075 ps
CPU time 1.65 seconds
Started Aug 03 06:35:22 PM PDT 24
Finished Aug 03 06:35:23 PM PDT 24
Peak memory 240412 kb
Host smart-50e232a5-c5f8-44f7-a373-5846db8b7da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540825880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.3540825880
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.2467763838
Short name T787
Test name
Test status
Simulation time 2320530435 ps
CPU time 5.08 seconds
Started Aug 03 06:35:13 PM PDT 24
Finished Aug 03 06:35:18 PM PDT 24
Peak memory 248624 kb
Host smart-c24a3790-a5fa-4687-8f55-a31db5fb932c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467763838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.2467763838
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.3941030441
Short name T1186
Test name
Test status
Simulation time 6692485476 ps
CPU time 37.01 seconds
Started Aug 03 06:35:19 PM PDT 24
Finished Aug 03 06:35:56 PM PDT 24
Peak memory 245236 kb
Host smart-aa918dfa-51e6-4673-b954-460110abd9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941030441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.3941030441
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.564536101
Short name T978
Test name
Test status
Simulation time 3332248052 ps
CPU time 28.18 seconds
Started Aug 03 06:35:19 PM PDT 24
Finished Aug 03 06:35:48 PM PDT 24
Peak memory 244664 kb
Host smart-947ed1da-5052-4f26-b61f-ca50efd46412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564536101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.564536101
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.558162702
Short name T904
Test name
Test status
Simulation time 1385315332 ps
CPU time 13.05 seconds
Started Aug 03 06:35:13 PM PDT 24
Finished Aug 03 06:35:27 PM PDT 24
Peak memory 242072 kb
Host smart-fae6cedd-8394-44a4-8d0c-a7125355b332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558162702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.558162702
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.2540447082
Short name T1051
Test name
Test status
Simulation time 229440987 ps
CPU time 3.68 seconds
Started Aug 03 06:35:12 PM PDT 24
Finished Aug 03 06:35:16 PM PDT 24
Peak memory 242044 kb
Host smart-0c7a48df-a96a-4b30-9ff3-0abadb812188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540447082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.2540447082
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.3021968500
Short name T201
Test name
Test status
Simulation time 16221289833 ps
CPU time 28.13 seconds
Started Aug 03 06:35:18 PM PDT 24
Finished Aug 03 06:35:46 PM PDT 24
Peak memory 244644 kb
Host smart-9c62f36a-d1dc-46f4-9d07-bb319ef09c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021968500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.3021968500
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.4246787337
Short name T466
Test name
Test status
Simulation time 382109448 ps
CPU time 13.33 seconds
Started Aug 03 06:35:16 PM PDT 24
Finished Aug 03 06:35:29 PM PDT 24
Peak memory 242144 kb
Host smart-2eced3b3-9895-421c-bde1-5b45a31592ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246787337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.4246787337
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.3604711623
Short name T147
Test name
Test status
Simulation time 168927421 ps
CPU time 6.23 seconds
Started Aug 03 06:35:12 PM PDT 24
Finished Aug 03 06:35:18 PM PDT 24
Peak memory 242052 kb
Host smart-f406d3fa-6dac-4f62-83c7-07241c8d598f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604711623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.3604711623
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.3474220202
Short name T1005
Test name
Test status
Simulation time 6977360387 ps
CPU time 20.27 seconds
Started Aug 03 06:35:15 PM PDT 24
Finished Aug 03 06:35:35 PM PDT 24
Peak memory 248676 kb
Host smart-d80d2281-ed33-4a5d-945f-33afa7f350d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3474220202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.3474220202
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.2240122665
Short name T738
Test name
Test status
Simulation time 3567083218 ps
CPU time 9.72 seconds
Started Aug 03 06:35:19 PM PDT 24
Finished Aug 03 06:35:29 PM PDT 24
Peak memory 242100 kb
Host smart-ee3417b8-e470-44bc-8a48-dcce23000c7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2240122665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.2240122665
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.1960677231
Short name T776
Test name
Test status
Simulation time 121574819 ps
CPU time 4.94 seconds
Started Aug 03 06:35:12 PM PDT 24
Finished Aug 03 06:35:17 PM PDT 24
Peak memory 242108 kb
Host smart-db9c0a12-297e-455d-8ee7-693f18662af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960677231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1960677231
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.1037503351
Short name T618
Test name
Test status
Simulation time 75263705842 ps
CPU time 194.95 seconds
Started Aug 03 06:35:20 PM PDT 24
Finished Aug 03 06:38:35 PM PDT 24
Peak memory 249220 kb
Host smart-2aa7d3df-2f24-4a6c-9d25-67dd35228d65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037503351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
1037503351
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.176123590
Short name T246
Test name
Test status
Simulation time 301959701727 ps
CPU time 687.92 seconds
Started Aug 03 06:35:18 PM PDT 24
Finished Aug 03 06:46:46 PM PDT 24
Peak memory 346988 kb
Host smart-adad62fa-0edd-495d-b0c7-f446f2930387
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176123590 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.176123590
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.2386231079
Short name T381
Test name
Test status
Simulation time 1032260334 ps
CPU time 28.43 seconds
Started Aug 03 06:35:19 PM PDT 24
Finished Aug 03 06:35:48 PM PDT 24
Peak memory 242180 kb
Host smart-709fb023-1e74-4d8d-97b3-a9983c3a8bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386231079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.2386231079
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.2385067061
Short name T495
Test name
Test status
Simulation time 73872313 ps
CPU time 1.75 seconds
Started Aug 03 06:43:17 PM PDT 24
Finished Aug 03 06:43:19 PM PDT 24
Peak memory 240388 kb
Host smart-3d92db4d-180a-4d3a-8995-f9ed8e903986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385067061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.2385067061
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.3672204194
Short name T62
Test name
Test status
Simulation time 3048379048 ps
CPU time 19.32 seconds
Started Aug 03 06:43:08 PM PDT 24
Finished Aug 03 06:43:28 PM PDT 24
Peak memory 242504 kb
Host smart-47ed7886-e11f-4620-93c1-046c48a0ea0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672204194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.3672204194
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.1267032084
Short name T647
Test name
Test status
Simulation time 291268974 ps
CPU time 15.08 seconds
Started Aug 03 06:43:05 PM PDT 24
Finished Aug 03 06:43:21 PM PDT 24
Peak memory 242100 kb
Host smart-de98736b-f5a0-41ae-89f9-c906281cad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267032084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.1267032084
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.2413629457
Short name T486
Test name
Test status
Simulation time 7369517815 ps
CPU time 46.86 seconds
Started Aug 03 06:43:09 PM PDT 24
Finished Aug 03 06:43:56 PM PDT 24
Peak memory 248572 kb
Host smart-1ea34f45-2a09-44bb-ab48-aa025c3dd69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413629457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.2413629457
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.482303931
Short name T873
Test name
Test status
Simulation time 2475096704 ps
CPU time 5.45 seconds
Started Aug 03 06:43:03 PM PDT 24
Finished Aug 03 06:43:09 PM PDT 24
Peak memory 242172 kb
Host smart-a9be0af5-4a84-4640-937a-f8738ac595e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482303931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.482303931
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.496375777
Short name T153
Test name
Test status
Simulation time 3080212940 ps
CPU time 26.68 seconds
Started Aug 03 06:43:09 PM PDT 24
Finished Aug 03 06:43:35 PM PDT 24
Peak memory 248688 kb
Host smart-527a86fe-f901-447d-bcc9-c3ea7577923a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496375777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.496375777
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.1814710271
Short name T442
Test name
Test status
Simulation time 482792625 ps
CPU time 10.98 seconds
Started Aug 03 06:43:11 PM PDT 24
Finished Aug 03 06:43:22 PM PDT 24
Peak memory 242344 kb
Host smart-4a7570e3-158b-4887-a99c-a1fa5d24b503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814710271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.1814710271
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.3961357825
Short name T345
Test name
Test status
Simulation time 415609726 ps
CPU time 11.68 seconds
Started Aug 03 06:43:02 PM PDT 24
Finished Aug 03 06:43:13 PM PDT 24
Peak memory 241936 kb
Host smart-60249274-7f6c-48f6-9428-74edf0b49294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961357825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.3961357825
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.1204106802
Short name T179
Test name
Test status
Simulation time 1989054049 ps
CPU time 12.05 seconds
Started Aug 03 06:43:01 PM PDT 24
Finished Aug 03 06:43:13 PM PDT 24
Peak memory 242260 kb
Host smart-ebda6d5c-9fcb-4868-9f3a-4149e408a7a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1204106802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.1204106802
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.2550546731
Short name T706
Test name
Test status
Simulation time 111184378 ps
CPU time 4.53 seconds
Started Aug 03 06:43:10 PM PDT 24
Finished Aug 03 06:43:15 PM PDT 24
Peak memory 241952 kb
Host smart-336ce632-ade7-49a6-a6dd-b5782aabfdfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2550546731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.2550546731
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.1522946222
Short name T1001
Test name
Test status
Simulation time 500693053 ps
CPU time 4.8 seconds
Started Aug 03 06:42:58 PM PDT 24
Finished Aug 03 06:43:03 PM PDT 24
Peak memory 242028 kb
Host smart-2135ca82-3a23-47bc-a138-ecb8b7324670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522946222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.1522946222
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.3260893730
Short name T770
Test name
Test status
Simulation time 5895219298 ps
CPU time 82.28 seconds
Started Aug 03 06:43:16 PM PDT 24
Finished Aug 03 06:44:38 PM PDT 24
Peak memory 245256 kb
Host smart-9d44ce0c-fa8f-42d1-883f-0deec64f2ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260893730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.3260893730
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.3000870783
Short name T357
Test name
Test status
Simulation time 53623957968 ps
CPU time 723.8 seconds
Started Aug 03 06:43:16 PM PDT 24
Finished Aug 03 06:55:20 PM PDT 24
Peak memory 256996 kb
Host smart-c63e04ed-031a-40ea-865b-20d031943401
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000870783 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.3000870783
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.601603258
Short name T481
Test name
Test status
Simulation time 508711200 ps
CPU time 9.8 seconds
Started Aug 03 06:43:11 PM PDT 24
Finished Aug 03 06:43:21 PM PDT 24
Peak memory 242328 kb
Host smart-fb1a4ca5-d57c-4463-baa2-65baa172997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601603258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.601603258
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.4195651151
Short name T724
Test name
Test status
Simulation time 60953437 ps
CPU time 1.54 seconds
Started Aug 03 06:43:35 PM PDT 24
Finished Aug 03 06:43:36 PM PDT 24
Peak memory 240352 kb
Host smart-1e7f5b8b-11f6-41d1-ad52-ce4f9b88c4d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195651151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.4195651151
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.2475122455
Short name T690
Test name
Test status
Simulation time 227393032 ps
CPU time 4.58 seconds
Started Aug 03 06:43:21 PM PDT 24
Finished Aug 03 06:43:26 PM PDT 24
Peak memory 242200 kb
Host smart-02193826-9080-4c73-9bee-8e4977fefb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475122455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.2475122455
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.3919350935
Short name T918
Test name
Test status
Simulation time 2122765639 ps
CPU time 34.43 seconds
Started Aug 03 06:43:20 PM PDT 24
Finished Aug 03 06:43:55 PM PDT 24
Peak memory 244444 kb
Host smart-6904a6eb-c5d1-48ff-af2b-9519addf4932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919350935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.3919350935
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.1801846319
Short name T8
Test name
Test status
Simulation time 2775990866 ps
CPU time 20.38 seconds
Started Aug 03 06:43:22 PM PDT 24
Finished Aug 03 06:43:43 PM PDT 24
Peak memory 242472 kb
Host smart-26c3b28a-ce7f-4459-8ef3-e30a275e241a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801846319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.1801846319
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.3884898216
Short name T1062
Test name
Test status
Simulation time 407629873 ps
CPU time 3.52 seconds
Started Aug 03 06:43:15 PM PDT 24
Finished Aug 03 06:43:19 PM PDT 24
Peak memory 242192 kb
Host smart-bf11f2c3-9196-4cbc-bc2c-2726980b020a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884898216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.3884898216
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.1578856587
Short name T130
Test name
Test status
Simulation time 19320943558 ps
CPU time 61.75 seconds
Started Aug 03 06:43:25 PM PDT 24
Finished Aug 03 06:44:27 PM PDT 24
Peak memory 248712 kb
Host smart-ae6ff7b3-1a65-4090-a4d2-24c66833b931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578856587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.1578856587
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.3969708617
Short name T1086
Test name
Test status
Simulation time 943352575 ps
CPU time 24.84 seconds
Started Aug 03 06:43:26 PM PDT 24
Finished Aug 03 06:43:51 PM PDT 24
Peak memory 241916 kb
Host smart-cace8e2a-aa6f-421d-a844-31b559c9f9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969708617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.3969708617
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.2079240180
Short name T894
Test name
Test status
Simulation time 259713275 ps
CPU time 3.85 seconds
Started Aug 03 06:43:15 PM PDT 24
Finished Aug 03 06:43:19 PM PDT 24
Peak memory 241780 kb
Host smart-0407cad1-e0ae-40b8-b818-20d0ea43a9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079240180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.2079240180
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.1010955426
Short name T516
Test name
Test status
Simulation time 1241238158 ps
CPU time 10.61 seconds
Started Aug 03 06:43:17 PM PDT 24
Finished Aug 03 06:43:28 PM PDT 24
Peak memory 248656 kb
Host smart-e0f5a462-d120-4c8b-9a69-8dfbb9a76080
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010955426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.1010955426
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.246322833
Short name T1040
Test name
Test status
Simulation time 324531433 ps
CPU time 5.69 seconds
Started Aug 03 06:43:31 PM PDT 24
Finished Aug 03 06:43:37 PM PDT 24
Peak memory 241876 kb
Host smart-b8c56bfd-91f5-4a1f-886e-e8248f4b85fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246322833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.246322833
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.3929596671
Short name T273
Test name
Test status
Simulation time 268189221 ps
CPU time 9.45 seconds
Started Aug 03 06:43:16 PM PDT 24
Finished Aug 03 06:43:25 PM PDT 24
Peak memory 242004 kb
Host smart-2f2b626f-4aec-4367-b19b-87afa445f853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929596671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.3929596671
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.1716445329
Short name T538
Test name
Test status
Simulation time 897931150 ps
CPU time 15.96 seconds
Started Aug 03 06:43:35 PM PDT 24
Finished Aug 03 06:43:51 PM PDT 24
Peak memory 241528 kb
Host smart-2711d8c3-9610-4fdb-acee-98b87b16d944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716445329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.1716445329
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.936332094
Short name T553
Test name
Test status
Simulation time 2984166171 ps
CPU time 42.4 seconds
Started Aug 03 06:43:31 PM PDT 24
Finished Aug 03 06:44:14 PM PDT 24
Peak memory 242480 kb
Host smart-bb68d12d-1b40-4e2c-99c5-374cd06a7292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936332094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.936332094
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.2201431777
Short name T94
Test name
Test status
Simulation time 82990728 ps
CPU time 2.11 seconds
Started Aug 03 06:44:00 PM PDT 24
Finished Aug 03 06:44:02 PM PDT 24
Peak memory 240708 kb
Host smart-eb3a23a4-35f3-4c7e-ac1b-e00e8cf40b41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201431777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.2201431777
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.3637841316
Short name T81
Test name
Test status
Simulation time 746126058 ps
CPU time 12.28 seconds
Started Aug 03 06:43:54 PM PDT 24
Finished Aug 03 06:44:06 PM PDT 24
Peak memory 242080 kb
Host smart-80a8ff21-cc34-4246-b33b-2230305603c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637841316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.3637841316
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.1795328781
Short name T411
Test name
Test status
Simulation time 1620648637 ps
CPU time 19.79 seconds
Started Aug 03 06:43:47 PM PDT 24
Finished Aug 03 06:44:07 PM PDT 24
Peak memory 241932 kb
Host smart-0370b4ed-4e5b-4c88-a26a-df42d5184198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795328781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.1795328781
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.2792710489
Short name T722
Test name
Test status
Simulation time 1685831298 ps
CPU time 18.31 seconds
Started Aug 03 06:43:46 PM PDT 24
Finished Aug 03 06:44:04 PM PDT 24
Peak memory 242412 kb
Host smart-8fd4b4e7-27e4-4103-aee7-edcf044c2998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792710489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.2792710489
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.2103303129
Short name T56
Test name
Test status
Simulation time 259165094 ps
CPU time 3.86 seconds
Started Aug 03 06:43:43 PM PDT 24
Finished Aug 03 06:43:47 PM PDT 24
Peak memory 242028 kb
Host smart-3ca3ee85-2d7f-4c9b-bbf2-6d080722a866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103303129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.2103303129
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.1418038292
Short name T961
Test name
Test status
Simulation time 269303565 ps
CPU time 6.11 seconds
Started Aug 03 06:43:57 PM PDT 24
Finished Aug 03 06:44:03 PM PDT 24
Peak memory 248608 kb
Host smart-aff6b35b-8ea2-4f1f-96e5-022455722633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418038292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1418038292
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.2944236409
Short name T322
Test name
Test status
Simulation time 558898339 ps
CPU time 6.94 seconds
Started Aug 03 06:43:55 PM PDT 24
Finished Aug 03 06:44:02 PM PDT 24
Peak memory 241892 kb
Host smart-aeaeee31-8b12-4af0-ae84-69ca3a0fa309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944236409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.2944236409
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.796557673
Short name T677
Test name
Test status
Simulation time 731882542 ps
CPU time 12.25 seconds
Started Aug 03 06:43:43 PM PDT 24
Finished Aug 03 06:43:55 PM PDT 24
Peak memory 241956 kb
Host smart-f9ae0548-cad6-4589-8e5d-484698144200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796557673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.796557673
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.1151603474
Short name T650
Test name
Test status
Simulation time 598655880 ps
CPU time 9.2 seconds
Started Aug 03 06:43:42 PM PDT 24
Finished Aug 03 06:43:51 PM PDT 24
Peak memory 241960 kb
Host smart-eeebfba7-3516-43c1-b549-8425c1e337e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1151603474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1151603474
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.2793038490
Short name T216
Test name
Test status
Simulation time 121274826 ps
CPU time 4.58 seconds
Started Aug 03 06:43:58 PM PDT 24
Finished Aug 03 06:44:02 PM PDT 24
Peak memory 242332 kb
Host smart-daa74189-77f0-4f6b-be2c-22ad50548556
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2793038490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.2793038490
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.1518497915
Short name T1029
Test name
Test status
Simulation time 7119588972 ps
CPU time 15.55 seconds
Started Aug 03 06:43:37 PM PDT 24
Finished Aug 03 06:43:52 PM PDT 24
Peak memory 242308 kb
Host smart-dd014fab-bde6-4561-91e4-f7b0b802c7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518497915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.1518497915
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.3638298699
Short name T254
Test name
Test status
Simulation time 8189057977 ps
CPU time 53.93 seconds
Started Aug 03 06:43:59 PM PDT 24
Finished Aug 03 06:44:53 PM PDT 24
Peak memory 245292 kb
Host smart-96ab2d94-1400-4573-a4f6-1fe84860e566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638298699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.3638298699
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.2788479767
Short name T1082
Test name
Test status
Simulation time 1764003368 ps
CPU time 11.59 seconds
Started Aug 03 06:43:59 PM PDT 24
Finished Aug 03 06:44:10 PM PDT 24
Peak memory 248500 kb
Host smart-d530b930-d871-43d0-a248-a961dcfc22c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788479767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.2788479767
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.18396557
Short name T878
Test name
Test status
Simulation time 505906153 ps
CPU time 3.56 seconds
Started Aug 03 06:44:16 PM PDT 24
Finished Aug 03 06:44:20 PM PDT 24
Peak memory 240900 kb
Host smart-89cae759-a1f4-4f6b-b7c5-669c01610b63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18396557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.18396557
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.3707009784
Short name T819
Test name
Test status
Simulation time 330536060 ps
CPU time 12.87 seconds
Started Aug 03 06:44:04 PM PDT 24
Finished Aug 03 06:44:17 PM PDT 24
Peak memory 248664 kb
Host smart-aea871f0-892f-46e7-83e4-648a5cbfea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707009784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.3707009784
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.3813072596
Short name T835
Test name
Test status
Simulation time 3775285535 ps
CPU time 14.28 seconds
Started Aug 03 06:44:04 PM PDT 24
Finished Aug 03 06:44:18 PM PDT 24
Peak memory 242000 kb
Host smart-6728904d-b2b0-4aee-9491-69b4ea1bbd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813072596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.3813072596
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.1390820514
Short name T490
Test name
Test status
Simulation time 11974069991 ps
CPU time 29.69 seconds
Started Aug 03 06:44:05 PM PDT 24
Finished Aug 03 06:44:35 PM PDT 24
Peak memory 243132 kb
Host smart-a897477b-da5b-48e3-b14a-9552b7fa91d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390820514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.1390820514
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.1187531249
Short name T38
Test name
Test status
Simulation time 664904357 ps
CPU time 4.56 seconds
Started Aug 03 06:43:59 PM PDT 24
Finished Aug 03 06:44:04 PM PDT 24
Peak memory 242456 kb
Host smart-5453029c-47e7-4fa4-aea3-42cbd1ed5fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187531249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.1187531249
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.2348197915
Short name T758
Test name
Test status
Simulation time 664743141 ps
CPU time 7.52 seconds
Started Aug 03 06:44:11 PM PDT 24
Finished Aug 03 06:44:19 PM PDT 24
Peak memory 242176 kb
Host smart-e6f1217b-f18e-4234-ab32-344a7506c3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348197915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.2348197915
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.3983785926
Short name T920
Test name
Test status
Simulation time 1603519545 ps
CPU time 13.51 seconds
Started Aug 03 06:44:04 PM PDT 24
Finished Aug 03 06:44:17 PM PDT 24
Peak memory 241920 kb
Host smart-918abe38-f183-469b-a6fd-841be40eb5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983785926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.3983785926
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.1085313027
Short name T679
Test name
Test status
Simulation time 2963386805 ps
CPU time 6.37 seconds
Started Aug 03 06:43:59 PM PDT 24
Finished Aug 03 06:44:05 PM PDT 24
Peak memory 242396 kb
Host smart-4d7162cc-5d30-469b-885b-6fd6fbe6d132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085313027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.1085313027
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.2041914587
Short name T1136
Test name
Test status
Simulation time 275506065 ps
CPU time 9.06 seconds
Started Aug 03 06:44:09 PM PDT 24
Finished Aug 03 06:44:18 PM PDT 24
Peak memory 241864 kb
Host smart-0e704a8e-07f7-433a-b495-dff908dd08d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041914587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.2041914587
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.1834871259
Short name T696
Test name
Test status
Simulation time 1509645836 ps
CPU time 10.81 seconds
Started Aug 03 06:44:00 PM PDT 24
Finished Aug 03 06:44:11 PM PDT 24
Peak memory 242268 kb
Host smart-79c6f2b9-ee2e-4779-994c-7c24eedde82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834871259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.1834871259
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.2054281061
Short name T261
Test name
Test status
Simulation time 30826191591 ps
CPU time 159.41 seconds
Started Aug 03 06:44:14 PM PDT 24
Finished Aug 03 06:46:54 PM PDT 24
Peak memory 260524 kb
Host smart-f88fa566-82ad-48e0-82cf-6bad160ea8e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054281061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.2054281061
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.3702194628
Short name T535
Test name
Test status
Simulation time 110592718482 ps
CPU time 1586.71 seconds
Started Aug 03 06:44:08 PM PDT 24
Finished Aug 03 07:10:35 PM PDT 24
Peak memory 256148 kb
Host smart-db15e27c-e0ef-4173-9fce-38913fdb1ce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702194628 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.3702194628
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.2281217685
Short name T909
Test name
Test status
Simulation time 5941142381 ps
CPU time 14.02 seconds
Started Aug 03 06:44:10 PM PDT 24
Finished Aug 03 06:44:24 PM PDT 24
Peak memory 242628 kb
Host smart-e1cdd7d9-d31d-491e-be55-0de18078bef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281217685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.2281217685
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.862383806
Short name T402
Test name
Test status
Simulation time 187325766 ps
CPU time 1.86 seconds
Started Aug 03 06:44:38 PM PDT 24
Finished Aug 03 06:44:40 PM PDT 24
Peak memory 240356 kb
Host smart-60d04138-2417-4965-b262-2bf984697728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862383806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.862383806
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.2855722770
Short name T288
Test name
Test status
Simulation time 5978346668 ps
CPU time 45.08 seconds
Started Aug 03 06:44:29 PM PDT 24
Finished Aug 03 06:45:14 PM PDT 24
Peak memory 248028 kb
Host smart-f902dc80-c2ef-4de8-bf99-cf56dfece506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855722770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.2855722770
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.4063727345
Short name T934
Test name
Test status
Simulation time 108928025 ps
CPU time 3.41 seconds
Started Aug 03 06:44:28 PM PDT 24
Finished Aug 03 06:44:31 PM PDT 24
Peak memory 242292 kb
Host smart-911f3771-bb99-4f3a-baf7-179c1bb99f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063727345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.4063727345
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.2873992029
Short name T157
Test name
Test status
Simulation time 11688485378 ps
CPU time 27.03 seconds
Started Aug 03 06:44:29 PM PDT 24
Finished Aug 03 06:44:56 PM PDT 24
Peak memory 248672 kb
Host smart-9f49b4e8-5868-4207-b671-c67e5f2dc9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873992029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2873992029
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.3648406145
Short name T200
Test name
Test status
Simulation time 4063761638 ps
CPU time 28.83 seconds
Started Aug 03 06:44:33 PM PDT 24
Finished Aug 03 06:45:02 PM PDT 24
Peak memory 242520 kb
Host smart-f8634cfb-b1fb-4f10-a420-aff192627e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648406145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.3648406145
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.3271411442
Short name T172
Test name
Test status
Simulation time 661319224 ps
CPU time 4.39 seconds
Started Aug 03 06:44:29 PM PDT 24
Finished Aug 03 06:44:34 PM PDT 24
Peak memory 241828 kb
Host smart-933e5d02-dd40-45c5-bf21-bfabb289acea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271411442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.3271411442
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.3590749139
Short name T1146
Test name
Test status
Simulation time 1016512509 ps
CPU time 18.21 seconds
Started Aug 03 06:44:21 PM PDT 24
Finished Aug 03 06:44:40 PM PDT 24
Peak memory 248660 kb
Host smart-698fec3c-572b-4910-8cf9-0069c6af59f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590749139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.3590749139
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.1545681602
Short name T1094
Test name
Test status
Simulation time 205504686 ps
CPU time 6.27 seconds
Started Aug 03 06:44:30 PM PDT 24
Finished Aug 03 06:44:37 PM PDT 24
Peak memory 241940 kb
Host smart-4f0e0724-7523-4dc4-abd7-0a3ea0aa87ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1545681602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.1545681602
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.2888889616
Short name T423
Test name
Test status
Simulation time 131707548 ps
CPU time 5.12 seconds
Started Aug 03 06:44:15 PM PDT 24
Finished Aug 03 06:44:20 PM PDT 24
Peak memory 242356 kb
Host smart-5f50715e-c477-4e15-b60d-ddff72fe7ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888889616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.2888889616
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.1894596381
Short name T970
Test name
Test status
Simulation time 1137888829 ps
CPU time 15.83 seconds
Started Aug 03 06:44:34 PM PDT 24
Finished Aug 03 06:44:50 PM PDT 24
Peak memory 242108 kb
Host smart-f89348ef-4603-4ae0-b501-4d30a03a2c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894596381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.1894596381
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.4125905414
Short name T17
Test name
Test status
Simulation time 264443161 ps
CPU time 2.05 seconds
Started Aug 03 06:44:58 PM PDT 24
Finished Aug 03 06:45:00 PM PDT 24
Peak memory 240836 kb
Host smart-a7495b11-9eec-429a-905c-f8f73eb040ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125905414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.4125905414
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.2219144031
Short name T974
Test name
Test status
Simulation time 596212373 ps
CPU time 17.12 seconds
Started Aug 03 06:44:47 PM PDT 24
Finished Aug 03 06:45:04 PM PDT 24
Peak memory 242024 kb
Host smart-16d2f414-789d-4f4d-9acf-b7f72239f690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219144031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.2219144031
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.1800219561
Short name T1116
Test name
Test status
Simulation time 1167276365 ps
CPU time 10.78 seconds
Started Aug 03 06:44:46 PM PDT 24
Finished Aug 03 06:44:57 PM PDT 24
Peak memory 242392 kb
Host smart-ce86af81-b9f3-4f9a-90c7-8a0172a22d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800219561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1800219561
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.1338518154
Short name T560
Test name
Test status
Simulation time 1507153486 ps
CPU time 5.41 seconds
Started Aug 03 06:44:38 PM PDT 24
Finished Aug 03 06:44:44 PM PDT 24
Peak memory 242108 kb
Host smart-ffac89bc-cc6a-4ff9-ab0a-e9c90cd1771a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338518154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1338518154
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.137293393
Short name T578
Test name
Test status
Simulation time 432330078 ps
CPU time 6.01 seconds
Started Aug 03 06:44:52 PM PDT 24
Finished Aug 03 06:44:58 PM PDT 24
Peak memory 242488 kb
Host smart-fed4812d-2cb2-4089-8b30-7c7ad69ef681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137293393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.137293393
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.2654083943
Short name T1169
Test name
Test status
Simulation time 162016018 ps
CPU time 4.14 seconds
Started Aug 03 06:44:53 PM PDT 24
Finished Aug 03 06:44:57 PM PDT 24
Peak memory 248020 kb
Host smart-c6b57f37-36b5-40d2-94ef-9be5943cf918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654083943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.2654083943
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.7621758
Short name T995
Test name
Test status
Simulation time 136654039 ps
CPU time 3.54 seconds
Started Aug 03 06:44:47 PM PDT 24
Finished Aug 03 06:44:50 PM PDT 24
Peak memory 242044 kb
Host smart-1ab5ce41-c575-4ed9-99be-a84f6bde68ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7621758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.7621758
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.1607036720
Short name T536
Test name
Test status
Simulation time 503095143 ps
CPU time 14.46 seconds
Started Aug 03 06:44:47 PM PDT 24
Finished Aug 03 06:45:02 PM PDT 24
Peak memory 242124 kb
Host smart-4e013155-cef7-4f4d-a98e-3dff67743930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1607036720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.1607036720
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.843962319
Short name T1143
Test name
Test status
Simulation time 206322398 ps
CPU time 4.79 seconds
Started Aug 03 06:44:50 PM PDT 24
Finished Aug 03 06:44:55 PM PDT 24
Peak memory 242020 kb
Host smart-b832260c-43e4-44dd-a0bc-d2cff3a67a8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=843962319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.843962319
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.222143462
Short name T472
Test name
Test status
Simulation time 333095636 ps
CPU time 5.87 seconds
Started Aug 03 06:44:39 PM PDT 24
Finished Aug 03 06:44:44 PM PDT 24
Peak memory 241940 kb
Host smart-a4409f5a-6b5d-4763-b849-ab193e015ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222143462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.222143462
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.402364220
Short name T501
Test name
Test status
Simulation time 56197845783 ps
CPU time 127.99 seconds
Started Aug 03 06:44:55 PM PDT 24
Finished Aug 03 06:47:03 PM PDT 24
Peak memory 264988 kb
Host smart-6defe5cd-6ace-472e-ae9e-3e4b0a4a05b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402364220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.
402364220
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.1439228881
Short name T251
Test name
Test status
Simulation time 78375849097 ps
CPU time 475.29 seconds
Started Aug 03 06:44:52 PM PDT 24
Finished Aug 03 06:52:47 PM PDT 24
Peak memory 260740 kb
Host smart-f767de75-0963-41c0-bd7e-fd7c34116b10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439228881 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.1439228881
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.1390699921
Short name T946
Test name
Test status
Simulation time 3181743937 ps
CPU time 30.91 seconds
Started Aug 03 06:44:51 PM PDT 24
Finished Aug 03 06:45:22 PM PDT 24
Peak memory 242060 kb
Host smart-0c25d82e-ccbb-4e4e-92db-4fae0d426d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390699921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.1390699921
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.1493636595
Short name T929
Test name
Test status
Simulation time 67337917 ps
CPU time 1.98 seconds
Started Aug 03 06:45:21 PM PDT 24
Finished Aug 03 06:45:23 PM PDT 24
Peak memory 240480 kb
Host smart-32f780ec-1506-4d9d-a28e-00ce74be45e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493636595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1493636595
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.689198622
Short name T979
Test name
Test status
Simulation time 1217731692 ps
CPU time 20.6 seconds
Started Aug 03 06:45:10 PM PDT 24
Finished Aug 03 06:45:31 PM PDT 24
Peak memory 248552 kb
Host smart-b636c853-50e4-4a2e-b799-f8e0cbcb3212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689198622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.689198622
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.3432957600
Short name T969
Test name
Test status
Simulation time 16220157393 ps
CPU time 49.87 seconds
Started Aug 03 06:45:10 PM PDT 24
Finished Aug 03 06:46:00 PM PDT 24
Peak memory 247332 kb
Host smart-8884ce7e-aad9-44b1-9dbc-4fc859738232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432957600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.3432957600
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.616182754
Short name T1173
Test name
Test status
Simulation time 10900927683 ps
CPU time 21.39 seconds
Started Aug 03 06:45:06 PM PDT 24
Finished Aug 03 06:45:27 PM PDT 24
Peak memory 243108 kb
Host smart-430ee9f4-9f92-4029-a23c-b4ad1340f156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616182754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.616182754
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.960561893
Short name T908
Test name
Test status
Simulation time 158770705 ps
CPU time 4.27 seconds
Started Aug 03 06:44:56 PM PDT 24
Finished Aug 03 06:45:01 PM PDT 24
Peak memory 242328 kb
Host smart-e0788ab7-9969-4cb3-be47-03c383c949c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960561893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.960561893
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.436494253
Short name T167
Test name
Test status
Simulation time 1420581375 ps
CPU time 24.73 seconds
Started Aug 03 06:45:12 PM PDT 24
Finished Aug 03 06:45:37 PM PDT 24
Peak memory 243352 kb
Host smart-b35b8b8d-ae68-46ee-b1dc-2266c14fa85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436494253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.436494253
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.3181567592
Short name T321
Test name
Test status
Simulation time 919849288 ps
CPU time 7.63 seconds
Started Aug 03 06:45:11 PM PDT 24
Finished Aug 03 06:45:19 PM PDT 24
Peak memory 242252 kb
Host smart-1d6106e6-1fd8-4f85-9abc-23898e1751b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181567592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.3181567592
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.2430473095
Short name T1147
Test name
Test status
Simulation time 398434094 ps
CPU time 6.21 seconds
Started Aug 03 06:45:01 PM PDT 24
Finished Aug 03 06:45:07 PM PDT 24
Peak memory 242284 kb
Host smart-4d879b5d-7990-4cec-b360-9db294c36273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430473095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.2430473095
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.729700492
Short name T731
Test name
Test status
Simulation time 1949922380 ps
CPU time 25.52 seconds
Started Aug 03 06:44:56 PM PDT 24
Finished Aug 03 06:45:22 PM PDT 24
Peak memory 241900 kb
Host smart-b683c8c5-11e4-4c31-a6cc-629bf74e5135
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=729700492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.729700492
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.259876901
Short name T1036
Test name
Test status
Simulation time 741565427 ps
CPU time 9.59 seconds
Started Aug 03 06:45:17 PM PDT 24
Finished Aug 03 06:45:27 PM PDT 24
Peak memory 242036 kb
Host smart-3f79cd60-ec3c-4e46-9d2c-d3a29cbea7eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=259876901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.259876901
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.3473398060
Short name T788
Test name
Test status
Simulation time 132912526 ps
CPU time 4.38 seconds
Started Aug 03 06:44:57 PM PDT 24
Finished Aug 03 06:45:01 PM PDT 24
Peak memory 242248 kb
Host smart-0db2b19e-5eb0-41cc-99fa-3bf78ac56b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473398060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3473398060
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.3810513214
Short name T905
Test name
Test status
Simulation time 23495275801 ps
CPU time 275.04 seconds
Started Aug 03 06:45:22 PM PDT 24
Finished Aug 03 06:49:57 PM PDT 24
Peak memory 257424 kb
Host smart-b94246f1-f79c-41a4-b28f-3ab6698035c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810513214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.3810513214
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.1745467787
Short name T134
Test name
Test status
Simulation time 77744517307 ps
CPU time 1333.08 seconds
Started Aug 03 06:45:20 PM PDT 24
Finished Aug 03 07:07:34 PM PDT 24
Peak memory 280692 kb
Host smart-002d2d2f-2061-4f40-bac9-61fb55a96016
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745467787 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.1745467787
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.878215268
Short name T197
Test name
Test status
Simulation time 809138268 ps
CPU time 8.42 seconds
Started Aug 03 06:45:16 PM PDT 24
Finished Aug 03 06:45:24 PM PDT 24
Peak memory 241968 kb
Host smart-bd92d495-b3ef-4521-9711-e463e3664fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878215268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.878215268
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.35677285
Short name T463
Test name
Test status
Simulation time 99760722 ps
CPU time 1.87 seconds
Started Aug 03 06:45:35 PM PDT 24
Finished Aug 03 06:45:37 PM PDT 24
Peak memory 240736 kb
Host smart-89ac22b4-a7db-4670-b43d-08add3e44184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35677285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.35677285
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.3670351006
Short name T87
Test name
Test status
Simulation time 15053591404 ps
CPU time 37.34 seconds
Started Aug 03 06:45:30 PM PDT 24
Finished Aug 03 06:46:08 PM PDT 24
Peak memory 248576 kb
Host smart-d35f5daa-0349-42fd-916c-d9bff16e0143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670351006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3670351006
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.4088240051
Short name T885
Test name
Test status
Simulation time 894796832 ps
CPU time 30.56 seconds
Started Aug 03 06:45:31 PM PDT 24
Finished Aug 03 06:46:02 PM PDT 24
Peak memory 243664 kb
Host smart-4ca39532-d0a2-4c33-9ed0-186160871f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088240051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.4088240051
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.3154302238
Short name T222
Test name
Test status
Simulation time 4351084635 ps
CPU time 22.5 seconds
Started Aug 03 06:45:27 PM PDT 24
Finished Aug 03 06:45:49 PM PDT 24
Peak memory 242284 kb
Host smart-72aaaf23-293f-46e4-a870-34845ebf21ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154302238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.3154302238
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.2997641372
Short name T1130
Test name
Test status
Simulation time 255612347 ps
CPU time 4.55 seconds
Started Aug 03 06:45:26 PM PDT 24
Finished Aug 03 06:45:31 PM PDT 24
Peak memory 241996 kb
Host smart-423b5609-c313-412c-b776-96be07e43708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997641372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.2997641372
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.1421030757
Short name T760
Test name
Test status
Simulation time 270425059 ps
CPU time 4.81 seconds
Started Aug 03 06:45:30 PM PDT 24
Finished Aug 03 06:45:35 PM PDT 24
Peak memory 242080 kb
Host smart-0355b93f-52c6-4ff1-ab52-e206b7d9eb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421030757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.1421030757
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.2498559044
Short name T1159
Test name
Test status
Simulation time 355986565 ps
CPU time 6.03 seconds
Started Aug 03 06:45:27 PM PDT 24
Finished Aug 03 06:45:33 PM PDT 24
Peak memory 242268 kb
Host smart-80a75598-a643-4bba-9b26-36e06d2b20e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498559044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.2498559044
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.1775803832
Short name T813
Test name
Test status
Simulation time 494907936 ps
CPU time 7.53 seconds
Started Aug 03 06:45:36 PM PDT 24
Finished Aug 03 06:45:43 PM PDT 24
Peak memory 242328 kb
Host smart-72a30b03-206c-4432-80e3-f9cf4b7e7cec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775803832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.1775803832
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.1452756605
Short name T590
Test name
Test status
Simulation time 355998211 ps
CPU time 8.12 seconds
Started Aug 03 06:45:20 PM PDT 24
Finished Aug 03 06:45:28 PM PDT 24
Peak memory 241916 kb
Host smart-1a0ac015-b768-4f90-968f-0a6b084242d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452756605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1452756605
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.3343276730
Short name T749
Test name
Test status
Simulation time 222573145 ps
CPU time 4.18 seconds
Started Aug 03 06:45:36 PM PDT 24
Finished Aug 03 06:45:40 PM PDT 24
Peak memory 242336 kb
Host smart-99f20827-4a92-484b-9ebd-2feb0b58b6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343276730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.3343276730
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.187273953
Short name T809
Test name
Test status
Simulation time 928083863 ps
CPU time 2.61 seconds
Started Aug 03 06:46:01 PM PDT 24
Finished Aug 03 06:46:04 PM PDT 24
Peak memory 240320 kb
Host smart-69c6867f-970a-4eee-971c-52fa7efb8456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187273953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.187273953
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.4286799900
Short name T901
Test name
Test status
Simulation time 735248401 ps
CPU time 4.09 seconds
Started Aug 03 06:45:51 PM PDT 24
Finished Aug 03 06:45:55 PM PDT 24
Peak memory 241944 kb
Host smart-a36ece64-54df-4a23-acdf-e428c6202415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286799900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.4286799900
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.2468637633
Short name T410
Test name
Test status
Simulation time 501351561 ps
CPU time 15.81 seconds
Started Aug 03 06:45:46 PM PDT 24
Finished Aug 03 06:46:02 PM PDT 24
Peak memory 242340 kb
Host smart-71409b19-5d50-42d5-b186-b5302ba1496c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468637633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.2468637633
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.464825903
Short name T1043
Test name
Test status
Simulation time 816886915 ps
CPU time 11.15 seconds
Started Aug 03 06:45:40 PM PDT 24
Finished Aug 03 06:45:52 PM PDT 24
Peak memory 241948 kb
Host smart-478f895e-4e75-40a5-ac27-b1c2a37af51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464825903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.464825903
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.1678092283
Short name T965
Test name
Test status
Simulation time 25825505655 ps
CPU time 52.31 seconds
Started Aug 03 06:45:55 PM PDT 24
Finished Aug 03 06:46:48 PM PDT 24
Peak memory 256844 kb
Host smart-3f786cd2-a47c-4789-9312-3d1b754382fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678092283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.1678092283
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.532839359
Short name T670
Test name
Test status
Simulation time 5481048812 ps
CPU time 43.01 seconds
Started Aug 03 06:45:55 PM PDT 24
Finished Aug 03 06:46:38 PM PDT 24
Peak memory 248660 kb
Host smart-6be8f799-f08f-4752-9f99-4594214d1a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532839359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.532839359
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.1428797477
Short name T1170
Test name
Test status
Simulation time 168318062 ps
CPU time 5.59 seconds
Started Aug 03 06:45:41 PM PDT 24
Finished Aug 03 06:45:47 PM PDT 24
Peak memory 242440 kb
Host smart-cbe9174a-9024-4009-b031-8d1210d2d747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428797477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.1428797477
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.2015684827
Short name T438
Test name
Test status
Simulation time 657342108 ps
CPU time 16.82 seconds
Started Aug 03 06:45:41 PM PDT 24
Finished Aug 03 06:45:58 PM PDT 24
Peak memory 248672 kb
Host smart-d34fddb3-ff63-44b6-89a7-ad061a1e66a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015684827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.2015684827
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.1258834303
Short name T845
Test name
Test status
Simulation time 191919907 ps
CPU time 5.57 seconds
Started Aug 03 06:46:02 PM PDT 24
Finished Aug 03 06:46:08 PM PDT 24
Peak memory 242036 kb
Host smart-9767e9f0-7bbb-4e90-8e7d-26fc5c46128c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258834303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.1258834303
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.424819318
Short name T460
Test name
Test status
Simulation time 641249978 ps
CPU time 10.53 seconds
Started Aug 03 06:45:37 PM PDT 24
Finished Aug 03 06:45:48 PM PDT 24
Peak memory 242020 kb
Host smart-2014d612-49fc-4627-8f51-0e05af3defb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424819318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.424819318
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.840169937
Short name T150
Test name
Test status
Simulation time 33117278987 ps
CPU time 156.86 seconds
Started Aug 03 06:46:01 PM PDT 24
Finished Aug 03 06:48:38 PM PDT 24
Peak memory 248616 kb
Host smart-3f4e2764-99d8-419f-b605-c59cecd77844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840169937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.
840169937
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.3229473211
Short name T795
Test name
Test status
Simulation time 177630053 ps
CPU time 5.32 seconds
Started Aug 03 06:46:01 PM PDT 24
Finished Aug 03 06:46:06 PM PDT 24
Peak memory 242032 kb
Host smart-0c4b6749-820b-4be9-af5d-3a4ddeb9b5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229473211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.3229473211
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.3024218712
Short name T667
Test name
Test status
Simulation time 77368333 ps
CPU time 1.96 seconds
Started Aug 03 06:46:22 PM PDT 24
Finished Aug 03 06:46:24 PM PDT 24
Peak memory 240316 kb
Host smart-e7167138-115b-493d-881c-845ca404ad45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024218712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.3024218712
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.1475680092
Short name T471
Test name
Test status
Simulation time 1476381515 ps
CPU time 13.97 seconds
Started Aug 03 06:46:14 PM PDT 24
Finished Aug 03 06:46:28 PM PDT 24
Peak memory 243688 kb
Host smart-81ec5297-9619-44d2-9eaa-4ff78f27fae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475680092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.1475680092
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.2128544623
Short name T1096
Test name
Test status
Simulation time 4531879831 ps
CPU time 42.77 seconds
Started Aug 03 06:46:13 PM PDT 24
Finished Aug 03 06:46:56 PM PDT 24
Peak memory 247988 kb
Host smart-774f2a11-42fd-4896-aa0c-8c7d08cb8505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128544623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.2128544623
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.1164069421
Short name T1047
Test name
Test status
Simulation time 2047196172 ps
CPU time 12.93 seconds
Started Aug 03 06:46:15 PM PDT 24
Finished Aug 03 06:46:28 PM PDT 24
Peak memory 248612 kb
Host smart-b3df0073-3211-4e2e-8b2c-a682d8fbc4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164069421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.1164069421
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.1956657589
Short name T209
Test name
Test status
Simulation time 982144866 ps
CPU time 25.91 seconds
Started Aug 03 06:46:12 PM PDT 24
Finished Aug 03 06:46:38 PM PDT 24
Peak memory 242380 kb
Host smart-c2fe34a8-d4f7-488e-ab13-1917a324f4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956657589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.1956657589
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.2488671048
Short name T265
Test name
Test status
Simulation time 2733553789 ps
CPU time 10.74 seconds
Started Aug 03 06:46:06 PM PDT 24
Finished Aug 03 06:46:17 PM PDT 24
Peak memory 241848 kb
Host smart-4013987d-012e-430c-9c30-838937604663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488671048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.2488671048
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.1192010713
Short name T155
Test name
Test status
Simulation time 871637408 ps
CPU time 7.39 seconds
Started Aug 03 06:46:08 PM PDT 24
Finished Aug 03 06:46:16 PM PDT 24
Peak memory 241964 kb
Host smart-0e5910bf-8a12-4733-bd34-929b8740a124
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192010713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.1192010713
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.1883735008
Short name T372
Test name
Test status
Simulation time 3785730736 ps
CPU time 8.93 seconds
Started Aug 03 06:46:15 PM PDT 24
Finished Aug 03 06:46:24 PM PDT 24
Peak memory 242328 kb
Host smart-a5d8988d-c441-4484-8e63-241c21b8d3a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1883735008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.1883735008
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.3484958039
Short name T1016
Test name
Test status
Simulation time 108682214 ps
CPU time 4.03 seconds
Started Aug 03 06:46:07 PM PDT 24
Finished Aug 03 06:46:11 PM PDT 24
Peak memory 241888 kb
Host smart-d2c413d6-10b1-4f7e-9bb5-1ef924dae8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484958039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.3484958039
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.2467182664
Short name T319
Test name
Test status
Simulation time 19124981347 ps
CPU time 107.76 seconds
Started Aug 03 06:46:24 PM PDT 24
Finished Aug 03 06:48:11 PM PDT 24
Peak memory 244548 kb
Host smart-8998d062-c3a1-4944-add4-71a9db3cf617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467182664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.2467182664
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.2101970945
Short name T342
Test name
Test status
Simulation time 67282285180 ps
CPU time 1757.53 seconds
Started Aug 03 06:46:17 PM PDT 24
Finished Aug 03 07:15:34 PM PDT 24
Peak memory 398888 kb
Host smart-7cb12a94-a305-4acf-beff-bf3230f37be8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101970945 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.2101970945
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.1321935256
Short name T458
Test name
Test status
Simulation time 483078820 ps
CPU time 7.13 seconds
Started Aug 03 06:46:17 PM PDT 24
Finished Aug 03 06:46:24 PM PDT 24
Peak memory 241856 kb
Host smart-fc3c3592-a859-4a4e-9e7b-b4d6cfd86448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321935256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.1321935256
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.190829751
Short name T947
Test name
Test status
Simulation time 139289203 ps
CPU time 1.75 seconds
Started Aug 03 06:35:35 PM PDT 24
Finished Aug 03 06:35:37 PM PDT 24
Peak memory 240604 kb
Host smart-cebff455-6920-4a5c-a52f-b1ad7e175338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190829751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.190829751
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.3027543499
Short name T537
Test name
Test status
Simulation time 1518232042 ps
CPU time 7.18 seconds
Started Aug 03 06:35:23 PM PDT 24
Finished Aug 03 06:35:30 PM PDT 24
Peak memory 248652 kb
Host smart-634caef3-9ac6-431b-9259-8bd092a59f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027543499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.3027543499
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.2895700578
Short name T72
Test name
Test status
Simulation time 2629548394 ps
CPU time 16.3 seconds
Started Aug 03 06:35:22 PM PDT 24
Finished Aug 03 06:35:38 PM PDT 24
Peak memory 248644 kb
Host smart-f713b680-67d3-4241-8a5d-fac1923f1a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895700578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2895700578
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.700029367
Short name T1038
Test name
Test status
Simulation time 420475721 ps
CPU time 12.32 seconds
Started Aug 03 06:35:21 PM PDT 24
Finished Aug 03 06:35:34 PM PDT 24
Peak memory 242036 kb
Host smart-58d6d625-a5c9-4882-b7de-2d962577a91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700029367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.700029367
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.854090864
Short name T893
Test name
Test status
Simulation time 5023191041 ps
CPU time 26.36 seconds
Started Aug 03 06:35:23 PM PDT 24
Finished Aug 03 06:35:49 PM PDT 24
Peak memory 243448 kb
Host smart-2023848d-47a4-4f8f-90a2-0e809378a048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854090864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.854090864
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.1537492694
Short name T479
Test name
Test status
Simulation time 603645406 ps
CPU time 4.32 seconds
Started Aug 03 06:35:22 PM PDT 24
Finished Aug 03 06:35:27 PM PDT 24
Peak memory 242232 kb
Host smart-c5f2b8a8-8089-42b6-98e0-de3ef832c695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537492694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.1537492694
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.736868599
Short name T1150
Test name
Test status
Simulation time 579375700 ps
CPU time 11.18 seconds
Started Aug 03 06:35:29 PM PDT 24
Finished Aug 03 06:35:40 PM PDT 24
Peak memory 243812 kb
Host smart-847527bc-4c42-4fad-aa62-acaf6cde4578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736868599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.736868599
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.3047994740
Short name T97
Test name
Test status
Simulation time 1879907087 ps
CPU time 38.51 seconds
Started Aug 03 06:35:30 PM PDT 24
Finished Aug 03 06:36:09 PM PDT 24
Peak memory 242536 kb
Host smart-6eac4353-4550-413a-94c1-141b0e93319b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047994740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3047994740
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.430098720
Short name T148
Test name
Test status
Simulation time 131742799 ps
CPU time 4.99 seconds
Started Aug 03 06:35:23 PM PDT 24
Finished Aug 03 06:35:29 PM PDT 24
Peak memory 242096 kb
Host smart-154af598-617f-40ae-841f-fbeeb2e0e952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430098720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.430098720
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.3282441506
Short name T1060
Test name
Test status
Simulation time 762766895 ps
CPU time 19.85 seconds
Started Aug 03 06:35:22 PM PDT 24
Finished Aug 03 06:35:41 PM PDT 24
Peak memory 248552 kb
Host smart-d63d7752-b793-4241-9fa8-a9dd1dc83f20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3282441506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.3282441506
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.107821972
Short name T1085
Test name
Test status
Simulation time 413196355 ps
CPU time 4.57 seconds
Started Aug 03 06:35:31 PM PDT 24
Finished Aug 03 06:35:36 PM PDT 24
Peak memory 242216 kb
Host smart-16384daf-d2cd-40bd-be31-1a889df703c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107821972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.107821972
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.579917240
Short name T642
Test name
Test status
Simulation time 6172393208 ps
CPU time 19.52 seconds
Started Aug 03 06:35:17 PM PDT 24
Finished Aug 03 06:35:37 PM PDT 24
Peak memory 242108 kb
Host smart-4e06b89b-3830-4032-afad-cc84d17238f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579917240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.579917240
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.2283075843
Short name T1009
Test name
Test status
Simulation time 30570004814 ps
CPU time 264.64 seconds
Started Aug 03 06:35:36 PM PDT 24
Finished Aug 03 06:40:01 PM PDT 24
Peak memory 256728 kb
Host smart-412e5ced-fb68-4a91-8265-b571aa35286b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283075843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
2283075843
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.3226039116
Short name T986
Test name
Test status
Simulation time 12556610131 ps
CPU time 18.8 seconds
Started Aug 03 06:35:28 PM PDT 24
Finished Aug 03 06:35:47 PM PDT 24
Peak memory 242532 kb
Host smart-183da3c7-6b02-43b0-87a3-5fd97e13f776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226039116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.3226039116
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.1355739693
Short name T1002
Test name
Test status
Simulation time 92983045 ps
CPU time 3.38 seconds
Started Aug 03 06:46:28 PM PDT 24
Finished Aug 03 06:46:32 PM PDT 24
Peak memory 242328 kb
Host smart-186abec3-dd9e-4a09-8236-47cb9659a076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355739693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.1355739693
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.4096332053
Short name T74
Test name
Test status
Simulation time 369281600 ps
CPU time 5.75 seconds
Started Aug 03 06:46:28 PM PDT 24
Finished Aug 03 06:46:33 PM PDT 24
Peak memory 241804 kb
Host smart-b2eb798f-9f40-4a78-99c9-0ee683938719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096332053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.4096332053
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.3087104375
Short name T252
Test name
Test status
Simulation time 573038048037 ps
CPU time 823.36 seconds
Started Aug 03 06:46:36 PM PDT 24
Finished Aug 03 07:00:19 PM PDT 24
Peak memory 265192 kb
Host smart-969663e6-174d-4d10-abc0-a769b0b155d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087104375 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.3087104375
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.4264833561
Short name T170
Test name
Test status
Simulation time 108595476 ps
CPU time 3.05 seconds
Started Aug 03 06:46:33 PM PDT 24
Finished Aug 03 06:46:37 PM PDT 24
Peak memory 242024 kb
Host smart-42f765d5-2412-46e1-9263-6ea63c312a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264833561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.4264833561
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.1850947324
Short name T12
Test name
Test status
Simulation time 90490552 ps
CPU time 3.47 seconds
Started Aug 03 06:46:34 PM PDT 24
Finished Aug 03 06:46:38 PM PDT 24
Peak memory 242028 kb
Host smart-fb54aa83-d128-4dea-b78d-aa18a921811e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850947324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.1850947324
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.2720488263
Short name T519
Test name
Test status
Simulation time 360279835 ps
CPU time 3.46 seconds
Started Aug 03 06:46:38 PM PDT 24
Finished Aug 03 06:46:42 PM PDT 24
Peak memory 241888 kb
Host smart-9a3deba2-f693-42c5-a43a-bbb957ae3af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720488263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.2720488263
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.2576981494
Short name T318
Test name
Test status
Simulation time 199862112 ps
CPU time 4.75 seconds
Started Aug 03 06:46:44 PM PDT 24
Finished Aug 03 06:46:49 PM PDT 24
Peak memory 241976 kb
Host smart-2a2e4275-e3b6-4ee9-9ca1-0f5130c652cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576981494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.2576981494
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.787649609
Short name T652
Test name
Test status
Simulation time 1712424818 ps
CPU time 4.87 seconds
Started Aug 03 06:46:49 PM PDT 24
Finished Aug 03 06:46:54 PM PDT 24
Peak memory 242184 kb
Host smart-bc21692b-dbe6-47af-bff6-7b68f48ce675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787649609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.787649609
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.4089173591
Short name T139
Test name
Test status
Simulation time 160327433 ps
CPU time 7.48 seconds
Started Aug 03 06:46:49 PM PDT 24
Finished Aug 03 06:46:57 PM PDT 24
Peak memory 241940 kb
Host smart-b0325250-7cb2-4878-9ec2-e76a8669f444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089173591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.4089173591
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.1111947728
Short name T297
Test name
Test status
Simulation time 36079235687 ps
CPU time 917.66 seconds
Started Aug 03 06:46:49 PM PDT 24
Finished Aug 03 07:02:07 PM PDT 24
Peak memory 372384 kb
Host smart-7bbc1927-a74d-4eb9-8d4f-6c3e23441a75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111947728 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.1111947728
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.2355600882
Short name T194
Test name
Test status
Simulation time 377584306 ps
CPU time 4.48 seconds
Started Aug 03 06:46:50 PM PDT 24
Finished Aug 03 06:46:55 PM PDT 24
Peak memory 241984 kb
Host smart-1ff74b1d-a759-4391-83ed-517144770aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355600882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.2355600882
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.2195915482
Short name T579
Test name
Test status
Simulation time 690714091 ps
CPU time 11.19 seconds
Started Aug 03 06:46:54 PM PDT 24
Finished Aug 03 06:47:05 PM PDT 24
Peak memory 241780 kb
Host smart-a237674b-ea2e-4745-b2e7-6f43876a240a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195915482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.2195915482
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.2610550178
Short name T733
Test name
Test status
Simulation time 79752387363 ps
CPU time 1685.49 seconds
Started Aug 03 06:47:02 PM PDT 24
Finished Aug 03 07:15:07 PM PDT 24
Peak memory 305772 kb
Host smart-6c1b5712-9ef4-4e5d-af43-cdf337152cb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610550178 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.2610550178
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.2904821825
Short name T214
Test name
Test status
Simulation time 135150405 ps
CPU time 4.14 seconds
Started Aug 03 06:47:05 PM PDT 24
Finished Aug 03 06:47:09 PM PDT 24
Peak memory 242264 kb
Host smart-2a8b257f-20de-45c3-a724-a6723aee4904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904821825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2904821825
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.3067389072
Short name T249
Test name
Test status
Simulation time 1586162465 ps
CPU time 4.87 seconds
Started Aug 03 06:47:06 PM PDT 24
Finished Aug 03 06:47:11 PM PDT 24
Peak memory 241968 kb
Host smart-6eb6ce14-e6f2-4a2e-85c7-5b3c4b72d723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067389072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.3067389072
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.1238049391
Short name T340
Test name
Test status
Simulation time 30532666753 ps
CPU time 222.98 seconds
Started Aug 03 06:47:06 PM PDT 24
Finished Aug 03 06:50:49 PM PDT 24
Peak memory 266440 kb
Host smart-feac06b5-72c5-41ff-9e54-cc73bfa5760d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238049391 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.1238049391
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.1727035852
Short name T191
Test name
Test status
Simulation time 569556209 ps
CPU time 3.91 seconds
Started Aug 03 06:47:11 PM PDT 24
Finished Aug 03 06:47:15 PM PDT 24
Peak memory 242296 kb
Host smart-0c737613-147c-49e3-8928-42c7f675cf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727035852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.1727035852
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.3220445536
Short name T1071
Test name
Test status
Simulation time 297518613 ps
CPU time 7.83 seconds
Started Aug 03 06:47:12 PM PDT 24
Finished Aug 03 06:47:20 PM PDT 24
Peak memory 241984 kb
Host smart-45034b0d-662c-4ed7-a96f-11ef02b070dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220445536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.3220445536
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.1006044216
Short name T354
Test name
Test status
Simulation time 62554069690 ps
CPU time 767.22 seconds
Started Aug 03 06:47:12 PM PDT 24
Finished Aug 03 07:00:00 PM PDT 24
Peak memory 308436 kb
Host smart-1fca6264-87ea-48dc-bbe6-3f5154b04387
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006044216 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.1006044216
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.1494233862
Short name T900
Test name
Test status
Simulation time 1598992437 ps
CPU time 2.88 seconds
Started Aug 03 06:47:10 PM PDT 24
Finished Aug 03 06:47:13 PM PDT 24
Peak memory 242420 kb
Host smart-51176450-b403-4355-acaa-7c0341512cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494233862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1494233862
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.2940613447
Short name T773
Test name
Test status
Simulation time 243750535 ps
CPU time 3.25 seconds
Started Aug 03 06:47:16 PM PDT 24
Finished Aug 03 06:47:19 PM PDT 24
Peak memory 241764 kb
Host smart-2139cf90-c0de-47b7-94c9-8c396323f242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940613447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.2940613447
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.3267337109
Short name T430
Test name
Test status
Simulation time 111814652 ps
CPU time 3.42 seconds
Started Aug 03 06:47:16 PM PDT 24
Finished Aug 03 06:47:19 PM PDT 24
Peak memory 242296 kb
Host smart-dd1d4b3c-4a63-4f65-98c6-03fdd2b808a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267337109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.3267337109
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.3848052386
Short name T794
Test name
Test status
Simulation time 524741882 ps
CPU time 8.61 seconds
Started Aug 03 06:47:16 PM PDT 24
Finished Aug 03 06:47:24 PM PDT 24
Peak memory 241944 kb
Host smart-7c35d820-75f3-44ea-9716-63866650eb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848052386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.3848052386
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.1382903340
Short name T1175
Test name
Test status
Simulation time 112229546271 ps
CPU time 1293.34 seconds
Started Aug 03 06:47:15 PM PDT 24
Finished Aug 03 07:08:48 PM PDT 24
Peak memory 280036 kb
Host smart-e4d25068-7dec-472f-9030-a83f36cae378
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382903340 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.1382903340
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.535176928
Short name T743
Test name
Test status
Simulation time 292491202 ps
CPU time 4.88 seconds
Started Aug 03 06:47:23 PM PDT 24
Finished Aug 03 06:47:28 PM PDT 24
Peak memory 242056 kb
Host smart-172021a3-9489-4d9b-a64b-374f11ddae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535176928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.535176928
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.458920785
Short name T1127
Test name
Test status
Simulation time 302259113 ps
CPU time 7.46 seconds
Started Aug 03 06:47:22 PM PDT 24
Finished Aug 03 06:47:30 PM PDT 24
Peak memory 242220 kb
Host smart-e7a8dad9-f9f7-43ba-a328-0f26c97ffb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458920785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.458920785
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.2714156488
Short name T1168
Test name
Test status
Simulation time 55877045812 ps
CPU time 1510.57 seconds
Started Aug 03 06:47:22 PM PDT 24
Finished Aug 03 07:12:33 PM PDT 24
Peak memory 344060 kb
Host smart-c9e0ccc8-9d35-4270-b8bd-188a8c2f00fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714156488 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.2714156488
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.1954827683
Short name T661
Test name
Test status
Simulation time 227856032 ps
CPU time 1.84 seconds
Started Aug 03 06:35:44 PM PDT 24
Finished Aug 03 06:35:46 PM PDT 24
Peak memory 240712 kb
Host smart-cdf4c070-80c0-4fe2-ba64-891a08900d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954827683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.1954827683
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.1689199922
Short name T948
Test name
Test status
Simulation time 2750752105 ps
CPU time 19.57 seconds
Started Aug 03 06:35:37 PM PDT 24
Finished Aug 03 06:35:56 PM PDT 24
Peak memory 242280 kb
Host smart-a2aba47c-01ea-480f-930e-ae7accc202bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689199922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.1689199922
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.1762024234
Short name T108
Test name
Test status
Simulation time 179933942 ps
CPU time 4.57 seconds
Started Aug 03 06:35:37 PM PDT 24
Finished Aug 03 06:35:41 PM PDT 24
Peak memory 248524 kb
Host smart-2085157f-2577-4eca-b5ab-275bf6c5372c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762024234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.1762024234
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.2437790530
Short name T645
Test name
Test status
Simulation time 3416868738 ps
CPU time 13.41 seconds
Started Aug 03 06:35:38 PM PDT 24
Finished Aug 03 06:35:52 PM PDT 24
Peak memory 241972 kb
Host smart-04a862a5-4b41-42e0-bd78-6add68ed125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437790530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.2437790530
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.2106879516
Short name T437
Test name
Test status
Simulation time 802764737 ps
CPU time 11.43 seconds
Started Aug 03 06:35:35 PM PDT 24
Finished Aug 03 06:35:46 PM PDT 24
Peak memory 242052 kb
Host smart-0c365707-febd-4821-8614-a76d65b46fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106879516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.2106879516
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.2132815668
Short name T160
Test name
Test status
Simulation time 1453133609 ps
CPU time 5.44 seconds
Started Aug 03 06:35:36 PM PDT 24
Finished Aug 03 06:35:41 PM PDT 24
Peak memory 241920 kb
Host smart-be0ced0e-2ae3-4e1d-9675-85d60277b5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132815668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.2132815668
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.629671358
Short name T759
Test name
Test status
Simulation time 17722561120 ps
CPU time 26.13 seconds
Started Aug 03 06:35:33 PM PDT 24
Finished Aug 03 06:35:59 PM PDT 24
Peak memory 243752 kb
Host smart-a8d40f43-1782-42c7-b9ee-1ed98010527e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629671358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.629671358
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.1770207057
Short name T525
Test name
Test status
Simulation time 139135896 ps
CPU time 6.22 seconds
Started Aug 03 06:35:40 PM PDT 24
Finished Aug 03 06:35:46 PM PDT 24
Peak memory 241900 kb
Host smart-aeb0fd14-a09d-4df9-a14c-0156b8b09a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770207057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.1770207057
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.2002474567
Short name T397
Test name
Test status
Simulation time 125432109 ps
CPU time 3.91 seconds
Started Aug 03 06:35:35 PM PDT 24
Finished Aug 03 06:35:39 PM PDT 24
Peak memory 242024 kb
Host smart-36bba9bf-4b4a-47c0-b5a5-dd37c2869009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002474567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.2002474567
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.2375990013
Short name T259
Test name
Test status
Simulation time 973174764 ps
CPU time 28.46 seconds
Started Aug 03 06:35:34 PM PDT 24
Finished Aug 03 06:36:03 PM PDT 24
Peak memory 242132 kb
Host smart-df69f3cd-79a8-4267-a16e-ad7c0f28e804
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375990013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.2375990013
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.1496178610
Short name T365
Test name
Test status
Simulation time 1131367597 ps
CPU time 8.88 seconds
Started Aug 03 06:35:40 PM PDT 24
Finished Aug 03 06:35:49 PM PDT 24
Peak memory 242004 kb
Host smart-13ae4d10-9689-409d-89c3-883964e81759
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496178610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.1496178610
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.142888281
Short name T858
Test name
Test status
Simulation time 1812203719 ps
CPU time 12.95 seconds
Started Aug 03 06:35:37 PM PDT 24
Finished Aug 03 06:35:50 PM PDT 24
Peak memory 248600 kb
Host smart-9c1a0693-cd41-418a-bb98-23cb90075e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142888281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.142888281
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.3573003442
Short name T1099
Test name
Test status
Simulation time 44536452500 ps
CPU time 607.91 seconds
Started Aug 03 06:35:40 PM PDT 24
Finished Aug 03 06:45:48 PM PDT 24
Peak memory 287852 kb
Host smart-2fab98e9-0def-495c-acbc-d8ca69ec160d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573003442 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.3573003442
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.2791926827
Short name T799
Test name
Test status
Simulation time 12358489968 ps
CPU time 27.8 seconds
Started Aug 03 06:35:39 PM PDT 24
Finished Aug 03 06:36:07 PM PDT 24
Peak memory 242788 kb
Host smart-6737d3b4-4511-4ed7-9eb2-4b243493bbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791926827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2791926827
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.2345093310
Short name T79
Test name
Test status
Simulation time 2043063445 ps
CPU time 5.52 seconds
Started Aug 03 06:47:28 PM PDT 24
Finished Aug 03 06:47:33 PM PDT 24
Peak memory 242256 kb
Host smart-ede982fc-0929-45b8-ae31-e69b6d5961d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345093310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.2345093310
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.1068826741
Short name T672
Test name
Test status
Simulation time 331613715 ps
CPU time 9.63 seconds
Started Aug 03 06:47:27 PM PDT 24
Finished Aug 03 06:47:36 PM PDT 24
Peak memory 248492 kb
Host smart-88ddaa9c-75d6-4963-bba6-1c16adb0225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068826741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1068826741
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.85651384
Short name T1110
Test name
Test status
Simulation time 25919243605 ps
CPU time 310.39 seconds
Started Aug 03 06:47:33 PM PDT 24
Finished Aug 03 06:52:43 PM PDT 24
Peak memory 256940 kb
Host smart-ea494abe-8a47-472f-8d5b-29e7daf20f2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85651384 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.85651384
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.3738114096
Short name T846
Test name
Test status
Simulation time 1906000036 ps
CPU time 4.38 seconds
Started Aug 03 06:47:31 PM PDT 24
Finished Aug 03 06:47:35 PM PDT 24
Peak memory 242176 kb
Host smart-43e72236-9ea7-428a-b28e-089c1b7dbbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738114096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.3738114096
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.3846698781
Short name T64
Test name
Test status
Simulation time 515396093 ps
CPU time 6.04 seconds
Started Aug 03 06:47:32 PM PDT 24
Finished Aug 03 06:47:39 PM PDT 24
Peak memory 242284 kb
Host smart-1c406426-3d21-4b1b-9337-f3c0fbd7cd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846698781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3846698781
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.2370784133
Short name T1137
Test name
Test status
Simulation time 1752995510 ps
CPU time 6.54 seconds
Started Aug 03 06:47:37 PM PDT 24
Finished Aug 03 06:47:44 PM PDT 24
Peak memory 242172 kb
Host smart-8cd1454a-137d-4c27-bd7c-4e3e45384dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370784133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.2370784133
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.4137591495
Short name T887
Test name
Test status
Simulation time 309818164 ps
CPU time 8.39 seconds
Started Aug 03 06:47:41 PM PDT 24
Finished Aug 03 06:47:49 PM PDT 24
Peak memory 242220 kb
Host smart-3cd61f8a-3a70-4d57-9b08-9470c4e964c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137591495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.4137591495
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.305900186
Short name T549
Test name
Test status
Simulation time 218539621847 ps
CPU time 525.63 seconds
Started Aug 03 06:47:43 PM PDT 24
Finished Aug 03 06:56:29 PM PDT 24
Peak memory 328088 kb
Host smart-2ba867cc-1c42-497f-b740-5f95ab1d8147
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305900186 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.305900186
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.2849055196
Short name T713
Test name
Test status
Simulation time 337149024 ps
CPU time 5.04 seconds
Started Aug 03 06:47:42 PM PDT 24
Finished Aug 03 06:47:48 PM PDT 24
Peak memory 242380 kb
Host smart-8accd9cd-10e6-4ad3-9ee9-84bb6abf2f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849055196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.2849055196
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.3122795137
Short name T447
Test name
Test status
Simulation time 1818081202 ps
CPU time 17.02 seconds
Started Aug 03 06:47:47 PM PDT 24
Finished Aug 03 06:48:04 PM PDT 24
Peak memory 241956 kb
Host smart-8d29ff51-11ae-49c4-b7d2-196737998df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122795137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.3122795137
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.1851119844
Short name T1027
Test name
Test status
Simulation time 57187069995 ps
CPU time 1076.89 seconds
Started Aug 03 06:47:46 PM PDT 24
Finished Aug 03 07:05:43 PM PDT 24
Peak memory 395540 kb
Host smart-394c84fb-b86a-4c4b-95ab-0fb55b2593ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851119844 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.1851119844
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.1753679105
Short name T213
Test name
Test status
Simulation time 416233202 ps
CPU time 3.72 seconds
Started Aug 03 06:47:46 PM PDT 24
Finished Aug 03 06:47:50 PM PDT 24
Peak memory 242136 kb
Host smart-84491164-3a2f-4fa8-b21b-fc97ab0294dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753679105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.1753679105
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.2908352558
Short name T517
Test name
Test status
Simulation time 607881504 ps
CPU time 7.48 seconds
Started Aug 03 06:47:45 PM PDT 24
Finished Aug 03 06:47:53 PM PDT 24
Peak memory 242108 kb
Host smart-ddfcf003-ccd8-46ba-8aa1-92a018065599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908352558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.2908352558
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.529969603
Short name T879
Test name
Test status
Simulation time 125723852056 ps
CPU time 1131.68 seconds
Started Aug 03 06:47:52 PM PDT 24
Finished Aug 03 07:06:44 PM PDT 24
Peak memory 359800 kb
Host smart-c92b1a08-ce95-4133-9f72-de32af917f92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529969603 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.529969603
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.1059048236
Short name T186
Test name
Test status
Simulation time 440636752 ps
CPU time 3.84 seconds
Started Aug 03 06:47:53 PM PDT 24
Finished Aug 03 06:47:57 PM PDT 24
Peak memory 242220 kb
Host smart-d14a8491-3516-48d3-a994-ebfc3f3a8134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059048236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.1059048236
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.3253426633
Short name T798
Test name
Test status
Simulation time 420451626 ps
CPU time 9.86 seconds
Started Aug 03 06:47:50 PM PDT 24
Finished Aug 03 06:48:00 PM PDT 24
Peak memory 241960 kb
Host smart-00fc76ca-f099-423e-b9b6-6a410aae4fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253426633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3253426633
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.2888204489
Short name T131
Test name
Test status
Simulation time 284367101018 ps
CPU time 2103.73 seconds
Started Aug 03 06:47:56 PM PDT 24
Finished Aug 03 07:23:00 PM PDT 24
Peak memory 373964 kb
Host smart-ff14f435-cf62-4a62-a99c-1302157356f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888204489 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.2888204489
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.1358449462
Short name T956
Test name
Test status
Simulation time 282088538 ps
CPU time 3.93 seconds
Started Aug 03 06:47:58 PM PDT 24
Finished Aug 03 06:48:02 PM PDT 24
Peak memory 242380 kb
Host smart-953ce1b8-7114-4adb-9a45-98bbe753d320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358449462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.1358449462
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.3144564068
Short name T575
Test name
Test status
Simulation time 597943466 ps
CPU time 6.87 seconds
Started Aug 03 06:47:56 PM PDT 24
Finished Aug 03 06:48:03 PM PDT 24
Peak memory 242232 kb
Host smart-d08a0247-fec7-472a-8622-411d37e2b08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144564068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3144564068
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.1511041585
Short name T1142
Test name
Test status
Simulation time 160430372 ps
CPU time 4.07 seconds
Started Aug 03 06:48:01 PM PDT 24
Finished Aug 03 06:48:05 PM PDT 24
Peak memory 242144 kb
Host smart-dcc80dd6-3d07-47cf-9e17-526a083450f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511041585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.1511041585
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.1988287531
Short name T581
Test name
Test status
Simulation time 320538954 ps
CPU time 9.27 seconds
Started Aug 03 06:48:01 PM PDT 24
Finished Aug 03 06:48:11 PM PDT 24
Peak memory 248244 kb
Host smart-e15b0f7f-a43d-4bb2-9489-e6f202be8bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988287531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.1988287531
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.534732867
Short name T774
Test name
Test status
Simulation time 414235010 ps
CPU time 4.25 seconds
Started Aug 03 06:48:08 PM PDT 24
Finished Aug 03 06:48:12 PM PDT 24
Peak memory 242312 kb
Host smart-a4e9a0f5-50f5-4747-b0be-5a4186f9f723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534732867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.534732867
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.1807356194
Short name T1093
Test name
Test status
Simulation time 642250300 ps
CPU time 13.63 seconds
Started Aug 03 06:48:12 PM PDT 24
Finished Aug 03 06:48:26 PM PDT 24
Peak memory 241876 kb
Host smart-376babd7-4588-41cf-8d6d-b35f641acacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807356194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.1807356194
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.3165268453
Short name T1102
Test name
Test status
Simulation time 226738886386 ps
CPU time 2654.53 seconds
Started Aug 03 06:48:15 PM PDT 24
Finished Aug 03 07:32:30 PM PDT 24
Peak memory 298344 kb
Host smart-ebea8de0-60b9-490e-9a59-daae494c868c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165268453 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.3165268453
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.3351387881
Short name T1131
Test name
Test status
Simulation time 168122443 ps
CPU time 4.14 seconds
Started Aug 03 06:48:17 PM PDT 24
Finished Aug 03 06:48:21 PM PDT 24
Peak memory 242192 kb
Host smart-7eaa4ce2-baf8-4380-b1f6-6b6bcdd0b45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351387881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.3351387881
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.512423306
Short name T474
Test name
Test status
Simulation time 783008571 ps
CPU time 9.3 seconds
Started Aug 03 06:48:14 PM PDT 24
Finished Aug 03 06:48:23 PM PDT 24
Peak memory 242008 kb
Host smart-8fb502b9-286f-4594-ac85-6cd7af28625b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512423306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.512423306
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.1403274249
Short name T1074
Test name
Test status
Simulation time 65109519253 ps
CPU time 438.63 seconds
Started Aug 03 06:48:20 PM PDT 24
Finished Aug 03 06:55:38 PM PDT 24
Peak memory 314340 kb
Host smart-238bd3e2-b0bc-45ab-8987-0dfafda9def9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403274249 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.1403274249
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.3352144694
Short name T730
Test name
Test status
Simulation time 169395712 ps
CPU time 2.73 seconds
Started Aug 03 06:35:56 PM PDT 24
Finished Aug 03 06:35:59 PM PDT 24
Peak memory 240696 kb
Host smart-92359091-25f1-45e4-9433-3a312f3bcc7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352144694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.3352144694
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.2645094581
Short name T868
Test name
Test status
Simulation time 825190741 ps
CPU time 20.04 seconds
Started Aug 03 06:35:43 PM PDT 24
Finished Aug 03 06:36:03 PM PDT 24
Peak memory 242264 kb
Host smart-ae071258-ea1c-4119-946a-77e736867b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645094581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.2645094581
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.1209171866
Short name T587
Test name
Test status
Simulation time 1793113190 ps
CPU time 22.34 seconds
Started Aug 03 06:35:49 PM PDT 24
Finished Aug 03 06:36:11 PM PDT 24
Peak memory 244032 kb
Host smart-da6a4bcc-33f9-42c0-ab18-b43aaf0bbb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209171866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.1209171866
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.3884809071
Short name T482
Test name
Test status
Simulation time 9516289728 ps
CPU time 23.42 seconds
Started Aug 03 06:35:54 PM PDT 24
Finished Aug 03 06:36:17 PM PDT 24
Peak memory 241900 kb
Host smart-948827d2-8945-45bf-94f3-6c59bfff029d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884809071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.3884809071
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.2996768316
Short name T271
Test name
Test status
Simulation time 4028184249 ps
CPU time 37.81 seconds
Started Aug 03 06:35:49 PM PDT 24
Finished Aug 03 06:36:27 PM PDT 24
Peak memory 242132 kb
Host smart-ddc4e93e-f6e2-4658-a7d2-9b1c15c13eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996768316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.2996768316
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.3237109279
Short name T177
Test name
Test status
Simulation time 131080915 ps
CPU time 3.93 seconds
Started Aug 03 06:35:45 PM PDT 24
Finished Aug 03 06:35:49 PM PDT 24
Peak memory 242180 kb
Host smart-3e7dd7c3-be16-4231-aa90-04ad49a2e04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237109279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.3237109279
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.4184736102
Short name T824
Test name
Test status
Simulation time 1738191284 ps
CPU time 22.56 seconds
Started Aug 03 06:35:50 PM PDT 24
Finished Aug 03 06:36:12 PM PDT 24
Peak memory 247312 kb
Host smart-5b57f993-c055-406c-8a81-1f9657f4733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184736102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.4184736102
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.1818879444
Short name T933
Test name
Test status
Simulation time 564296043 ps
CPU time 14.03 seconds
Started Aug 03 06:35:53 PM PDT 24
Finished Aug 03 06:36:07 PM PDT 24
Peak memory 242008 kb
Host smart-5a596118-782e-4b72-939e-1a742f4b73c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818879444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.1818879444
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.717068303
Short name T337
Test name
Test status
Simulation time 213679424 ps
CPU time 5.08 seconds
Started Aug 03 06:35:47 PM PDT 24
Finished Aug 03 06:35:52 PM PDT 24
Peak memory 241784 kb
Host smart-3b107938-3443-4ccf-b348-1bfc21206920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717068303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.717068303
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.2946822944
Short name T792
Test name
Test status
Simulation time 4064281534 ps
CPU time 11.3 seconds
Started Aug 03 06:35:49 PM PDT 24
Finished Aug 03 06:36:00 PM PDT 24
Peak memory 242004 kb
Host smart-83028d79-54f5-45b2-9d66-d39238e7f2ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2946822944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2946822944
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.1757553682
Short name T499
Test name
Test status
Simulation time 2644223943 ps
CPU time 6.55 seconds
Started Aug 03 06:35:43 PM PDT 24
Finished Aug 03 06:35:50 PM PDT 24
Peak memory 242152 kb
Host smart-0715e187-8ca6-4560-bee3-ec60b7016de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757553682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1757553682
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.310305343
Short name T390
Test name
Test status
Simulation time 7448271032 ps
CPU time 108.79 seconds
Started Aug 03 06:35:55 PM PDT 24
Finished Aug 03 06:37:43 PM PDT 24
Peak memory 246472 kb
Host smart-5e038ff1-8e92-4d24-9141-afc84c0a831b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310305343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.310305343
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.3697132638
Short name T21
Test name
Test status
Simulation time 40668770299 ps
CPU time 746.86 seconds
Started Aug 03 06:35:57 PM PDT 24
Finished Aug 03 06:48:24 PM PDT 24
Peak memory 280932 kb
Host smart-33a7cecc-52c3-4a45-8eb0-d4955eac4acc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697132638 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.3697132638
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.3675945525
Short name T380
Test name
Test status
Simulation time 1656083033 ps
CPU time 30.23 seconds
Started Aug 03 06:35:54 PM PDT 24
Finished Aug 03 06:36:24 PM PDT 24
Peak memory 242308 kb
Host smart-362c446e-b9d9-4168-806f-7f568c67c6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675945525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.3675945525
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.3606955423
Short name T226
Test name
Test status
Simulation time 428425336 ps
CPU time 4.87 seconds
Started Aug 03 06:48:21 PM PDT 24
Finished Aug 03 06:48:26 PM PDT 24
Peak memory 242056 kb
Host smart-e2425261-5aef-432d-905b-47f48b2449b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606955423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.3606955423
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.2178171495
Short name T1182
Test name
Test status
Simulation time 150703767939 ps
CPU time 2126.78 seconds
Started Aug 03 06:48:28 PM PDT 24
Finished Aug 03 07:23:55 PM PDT 24
Peak memory 284160 kb
Host smart-254c213d-c17b-4757-b202-e15740496a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178171495 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.2178171495
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.1024112458
Short name T572
Test name
Test status
Simulation time 118071374 ps
CPU time 4.52 seconds
Started Aug 03 06:48:24 PM PDT 24
Finished Aug 03 06:48:29 PM PDT 24
Peak memory 242252 kb
Host smart-e2f26740-762f-4f11-a40d-feff69d19fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024112458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.1024112458
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.2631018324
Short name T1124
Test name
Test status
Simulation time 434436893 ps
CPU time 10.77 seconds
Started Aug 03 06:48:26 PM PDT 24
Finished Aug 03 06:48:37 PM PDT 24
Peak memory 241828 kb
Host smart-669f0e95-948f-4ee8-8b18-fb24bb34a6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631018324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2631018324
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.3644486613
Short name T195
Test name
Test status
Simulation time 575308093 ps
CPU time 4.69 seconds
Started Aug 03 06:48:37 PM PDT 24
Finished Aug 03 06:48:42 PM PDT 24
Peak memory 242308 kb
Host smart-7969e35e-2f9d-4351-9e05-1c943bae015c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644486613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3644486613
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.3984903627
Short name T137
Test name
Test status
Simulation time 1325644746 ps
CPU time 28.29 seconds
Started Aug 03 06:48:39 PM PDT 24
Finished Aug 03 06:49:08 PM PDT 24
Peak memory 241896 kb
Host smart-63a92456-9391-4851-98a1-a9f7168404b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984903627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.3984903627
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.4171937170
Short name T52
Test name
Test status
Simulation time 376350648 ps
CPU time 3.55 seconds
Started Aug 03 06:48:40 PM PDT 24
Finished Aug 03 06:48:44 PM PDT 24
Peak memory 242212 kb
Host smart-112a80c1-649a-4031-a17a-f216e9e4b4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171937170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.4171937170
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.855813182
Short name T804
Test name
Test status
Simulation time 573710142 ps
CPU time 7.14 seconds
Started Aug 03 06:48:45 PM PDT 24
Finished Aug 03 06:48:52 PM PDT 24
Peak memory 242464 kb
Host smart-e36849a0-2ab9-4dc2-a166-0794d64d4479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855813182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.855813182
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.666263324
Short name T19
Test name
Test status
Simulation time 93493018245 ps
CPU time 1810.33 seconds
Started Aug 03 06:48:45 PM PDT 24
Finished Aug 03 07:18:56 PM PDT 24
Peak memory 267388 kb
Host smart-5df29be0-d7bb-40fd-a821-13198a3585f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666263324 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.666263324
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.915663744
Short name T123
Test name
Test status
Simulation time 116171565 ps
CPU time 3.22 seconds
Started Aug 03 06:48:45 PM PDT 24
Finished Aug 03 06:48:49 PM PDT 24
Peak memory 242048 kb
Host smart-acf1361b-061e-4d47-a6e9-a98ef2402c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915663744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.915663744
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.3599362872
Short name T592
Test name
Test status
Simulation time 156583628 ps
CPU time 7.01 seconds
Started Aug 03 06:48:49 PM PDT 24
Finished Aug 03 06:48:56 PM PDT 24
Peak memory 242344 kb
Host smart-2f854400-8b3b-47e6-b45e-ef0f961ed00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599362872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.3599362872
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.3646577408
Short name T1112
Test name
Test status
Simulation time 1887435560381 ps
CPU time 4076.97 seconds
Started Aug 03 06:48:54 PM PDT 24
Finished Aug 03 07:56:52 PM PDT 24
Peak memory 574040 kb
Host smart-e4f22f30-48e9-46c7-b312-a0e57c5126a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646577408 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.3646577408
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.2366152909
Short name T803
Test name
Test status
Simulation time 206000998 ps
CPU time 4.17 seconds
Started Aug 03 06:48:59 PM PDT 24
Finished Aug 03 06:49:03 PM PDT 24
Peak memory 242228 kb
Host smart-f8cd7f3d-b55d-4b3a-a1fd-2e41cbbe029d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366152909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.2366152909
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.818292126
Short name T484
Test name
Test status
Simulation time 6442057271 ps
CPU time 14.71 seconds
Started Aug 03 06:48:59 PM PDT 24
Finished Aug 03 06:49:14 PM PDT 24
Peak memory 241976 kb
Host smart-610c4133-1281-4790-b08e-ac09bc0cc9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818292126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.818292126
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.350253225
Short name T262
Test name
Test status
Simulation time 1152176402007 ps
CPU time 2693.37 seconds
Started Aug 03 06:49:01 PM PDT 24
Finished Aug 03 07:33:54 PM PDT 24
Peak memory 306128 kb
Host smart-5b0052d5-7731-47f3-8264-6ab16a4c8a69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350253225 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.350253225
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.3756227423
Short name T116
Test name
Test status
Simulation time 329856442 ps
CPU time 3.43 seconds
Started Aug 03 06:49:04 PM PDT 24
Finished Aug 03 06:49:08 PM PDT 24
Peak memory 242136 kb
Host smart-ee950939-6c76-4424-bdad-90837dfc8528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756227423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.3756227423
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.4147946709
Short name T968
Test name
Test status
Simulation time 3744731013 ps
CPU time 15.18 seconds
Started Aug 03 06:49:10 PM PDT 24
Finished Aug 03 06:49:25 PM PDT 24
Peak memory 242404 kb
Host smart-8dcee7fc-bcf0-4cc2-aafc-34d48a952025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147946709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.4147946709
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.4028783702
Short name T775
Test name
Test status
Simulation time 176740618440 ps
CPU time 3417.94 seconds
Started Aug 03 06:49:09 PM PDT 24
Finished Aug 03 07:46:08 PM PDT 24
Peak memory 286380 kb
Host smart-6220f7b2-32e7-4da5-bd78-cadc6da4dd8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028783702 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.4028783702
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.1570762632
Short name T485
Test name
Test status
Simulation time 162699265 ps
CPU time 4.37 seconds
Started Aug 03 06:49:17 PM PDT 24
Finished Aug 03 06:49:21 PM PDT 24
Peak memory 242072 kb
Host smart-875bfd55-3535-4d7b-9b50-bf0cbde1194f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570762632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.1570762632
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.1081762689
Short name T558
Test name
Test status
Simulation time 121374221 ps
CPU time 4.26 seconds
Started Aug 03 06:49:16 PM PDT 24
Finished Aug 03 06:49:20 PM PDT 24
Peak memory 241952 kb
Host smart-4acbeb1b-c00d-4c6d-b300-4ecffa4717be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081762689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.1081762689
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.943976081
Short name T697
Test name
Test status
Simulation time 283179029 ps
CPU time 4.33 seconds
Started Aug 03 06:49:20 PM PDT 24
Finished Aug 03 06:49:24 PM PDT 24
Peak memory 242400 kb
Host smart-cc0e94eb-8b1c-4de9-ae60-511b665cbdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943976081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.943976081
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.1155292279
Short name T597
Test name
Test status
Simulation time 1222108465 ps
CPU time 28.43 seconds
Started Aug 03 06:49:21 PM PDT 24
Finished Aug 03 06:49:49 PM PDT 24
Peak memory 242288 kb
Host smart-5078ccf8-612d-401a-a91c-604f9106dc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155292279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1155292279
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.3617463983
Short name T283
Test name
Test status
Simulation time 36455658326 ps
CPU time 735.42 seconds
Started Aug 03 06:49:26 PM PDT 24
Finished Aug 03 07:01:41 PM PDT 24
Peak memory 295140 kb
Host smart-0ef5c6d2-f963-4d32-8451-917aef56eac6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617463983 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.3617463983
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.2861315959
Short name T522
Test name
Test status
Simulation time 421785344 ps
CPU time 3.8 seconds
Started Aug 03 06:49:25 PM PDT 24
Finished Aug 03 06:49:29 PM PDT 24
Peak memory 241952 kb
Host smart-ee3a3f1f-c580-42e6-af38-6a2786fd976f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861315959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2861315959
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.844788402
Short name T614
Test name
Test status
Simulation time 241728803 ps
CPU time 6.16 seconds
Started Aug 03 06:49:24 PM PDT 24
Finished Aug 03 06:49:31 PM PDT 24
Peak memory 241976 kb
Host smart-a6458809-1494-4d25-9c10-9c1c15f5853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844788402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.844788402
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.3836891457
Short name T1100
Test name
Test status
Simulation time 205064763 ps
CPU time 2.64 seconds
Started Aug 03 06:36:05 PM PDT 24
Finished Aug 03 06:36:08 PM PDT 24
Peak memory 240816 kb
Host smart-42a4bf98-1064-4417-9953-ea6158519739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836891457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.3836891457
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.1519005030
Short name T585
Test name
Test status
Simulation time 1162083144 ps
CPU time 9.88 seconds
Started Aug 03 06:35:54 PM PDT 24
Finished Aug 03 06:36:03 PM PDT 24
Peak memory 248604 kb
Host smart-0a12e2f5-835d-4d1b-9dad-45a7c4d8e2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519005030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1519005030
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.2683446938
Short name T105
Test name
Test status
Simulation time 4338058697 ps
CPU time 44.31 seconds
Started Aug 03 06:36:00 PM PDT 24
Finished Aug 03 06:36:44 PM PDT 24
Peak memory 246048 kb
Host smart-2d659714-58ed-48fd-9ac5-d05990c7e8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683446938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2683446938
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.2552117590
Short name T895
Test name
Test status
Simulation time 22227364472 ps
CPU time 65.29 seconds
Started Aug 03 06:35:59 PM PDT 24
Finished Aug 03 06:37:04 PM PDT 24
Peak memory 253112 kb
Host smart-a280e893-023f-45e3-86b4-57da0437f4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552117590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.2552117590
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.1042076163
Short name T398
Test name
Test status
Simulation time 3842419379 ps
CPU time 22.2 seconds
Started Aug 03 06:36:00 PM PDT 24
Finished Aug 03 06:36:22 PM PDT 24
Peak memory 242164 kb
Host smart-90d0c06b-7418-469f-a893-281eb362159a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042076163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.1042076163
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.3661390865
Short name T583
Test name
Test status
Simulation time 448101055 ps
CPU time 4.65 seconds
Started Aug 03 06:35:53 PM PDT 24
Finished Aug 03 06:35:58 PM PDT 24
Peak memory 242156 kb
Host smart-cbf35faf-b3c7-47d6-afcb-8881a5f9e021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661390865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.3661390865
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.3368420710
Short name T1010
Test name
Test status
Simulation time 7662917309 ps
CPU time 41.19 seconds
Started Aug 03 06:36:00 PM PDT 24
Finished Aug 03 06:36:42 PM PDT 24
Peak memory 248652 kb
Host smart-6c8366b3-047f-4fb2-a211-2acf19a85a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368420710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.3368420710
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.124362684
Short name T643
Test name
Test status
Simulation time 9639544598 ps
CPU time 35.74 seconds
Started Aug 03 06:36:08 PM PDT 24
Finished Aug 03 06:36:44 PM PDT 24
Peak memory 244052 kb
Host smart-8e786c4a-c985-4bbd-9342-892898259468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124362684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.124362684
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.3917586585
Short name T203
Test name
Test status
Simulation time 249677290 ps
CPU time 6.72 seconds
Started Aug 03 06:36:03 PM PDT 24
Finished Aug 03 06:36:09 PM PDT 24
Peak memory 241932 kb
Host smart-b2f6b399-1900-4f06-b07e-fa2e52903f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917586585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.3917586585
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.2818573219
Short name T619
Test name
Test status
Simulation time 382399328 ps
CPU time 5.82 seconds
Started Aug 03 06:35:56 PM PDT 24
Finished Aug 03 06:36:02 PM PDT 24
Peak memory 247816 kb
Host smart-b391f673-cd72-4641-9480-8cd446953d41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2818573219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.2818573219
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.3759604966
Short name T863
Test name
Test status
Simulation time 422264355 ps
CPU time 3.98 seconds
Started Aug 03 06:36:05 PM PDT 24
Finished Aug 03 06:36:09 PM PDT 24
Peak memory 241924 kb
Host smart-88c6c357-c276-4bd2-81a9-1cce6ddd841c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3759604966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.3759604966
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.2100713991
Short name T990
Test name
Test status
Simulation time 402505740 ps
CPU time 6.18 seconds
Started Aug 03 06:35:56 PM PDT 24
Finished Aug 03 06:36:02 PM PDT 24
Peak memory 242028 kb
Host smart-98e60a2b-ac34-4ef4-bec7-e8062e3a3eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100713991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.2100713991
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.3567659741
Short name T300
Test name
Test status
Simulation time 102121649587 ps
CPU time 216.69 seconds
Started Aug 03 06:36:05 PM PDT 24
Finished Aug 03 06:39:41 PM PDT 24
Peak memory 259732 kb
Host smart-1ffae8fc-0a91-463e-a446-94ade1f0d7a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567659741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
3567659741
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.1512008095
Short name T135
Test name
Test status
Simulation time 437783642610 ps
CPU time 845.7 seconds
Started Aug 03 06:36:09 PM PDT 24
Finished Aug 03 06:50:15 PM PDT 24
Peak memory 379832 kb
Host smart-aa24ea7e-9a3e-423b-ab6b-75982e3e99b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512008095 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.1512008095
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.48144531
Short name T755
Test name
Test status
Simulation time 212745045 ps
CPU time 4.87 seconds
Started Aug 03 06:36:05 PM PDT 24
Finished Aug 03 06:36:10 PM PDT 24
Peak memory 242032 kb
Host smart-4345aca8-9110-43f4-b0e7-d54861d6a8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48144531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.48144531
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.3359911670
Short name T562
Test name
Test status
Simulation time 104650682 ps
CPU time 3.39 seconds
Started Aug 03 06:49:31 PM PDT 24
Finished Aug 03 06:49:35 PM PDT 24
Peak memory 241980 kb
Host smart-caccbdba-54bf-4d2e-9323-a91ba4e7ba12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359911670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3359911670
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.4182719887
Short name T1045
Test name
Test status
Simulation time 314635007 ps
CPU time 16.4 seconds
Started Aug 03 06:49:42 PM PDT 24
Finished Aug 03 06:49:58 PM PDT 24
Peak memory 242024 kb
Host smart-9719f624-760f-4eaf-9dc0-9daac1ae17b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182719887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.4182719887
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.2231836412
Short name T169
Test name
Test status
Simulation time 236684054611 ps
CPU time 2084.18 seconds
Started Aug 03 06:49:46 PM PDT 24
Finished Aug 03 07:24:31 PM PDT 24
Peak memory 284036 kb
Host smart-d802c1e8-380c-4ea6-9362-67294adb5f0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231836412 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.2231836412
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.2398185046
Short name T732
Test name
Test status
Simulation time 209633379 ps
CPU time 3.75 seconds
Started Aug 03 06:49:46 PM PDT 24
Finished Aug 03 06:49:50 PM PDT 24
Peak memory 241992 kb
Host smart-945e3a53-d0ee-46f6-b920-ed18a3143a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398185046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.2398185046
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.4280865082
Short name T240
Test name
Test status
Simulation time 1559600640 ps
CPU time 13.43 seconds
Started Aug 03 06:49:51 PM PDT 24
Finished Aug 03 06:50:04 PM PDT 24
Peak memory 242372 kb
Host smart-ef34d49d-1a61-4bbc-b327-46145191e643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280865082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.4280865082
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.3637668081
Short name T348
Test name
Test status
Simulation time 31080253240 ps
CPU time 619.35 seconds
Started Aug 03 06:49:52 PM PDT 24
Finished Aug 03 07:00:12 PM PDT 24
Peak memory 260856 kb
Host smart-11a15e2d-e9c5-45ce-968e-c4aab07df04c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637668081 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.3637668081
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.1995857034
Short name T443
Test name
Test status
Simulation time 160977190 ps
CPU time 4.12 seconds
Started Aug 03 06:49:51 PM PDT 24
Finished Aug 03 06:49:55 PM PDT 24
Peak memory 242104 kb
Host smart-bed3aaf2-523a-4744-8261-ecf569fa2232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995857034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1995857034
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.248105528
Short name T622
Test name
Test status
Simulation time 2004742347 ps
CPU time 6.83 seconds
Started Aug 03 06:49:57 PM PDT 24
Finished Aug 03 06:50:03 PM PDT 24
Peak memory 242356 kb
Host smart-ff0c385e-d992-43b0-95a5-900d00ff18b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248105528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.248105528
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.3476681104
Short name T1179
Test name
Test status
Simulation time 1110829276439 ps
CPU time 2276.57 seconds
Started Aug 03 06:49:59 PM PDT 24
Finished Aug 03 07:27:56 PM PDT 24
Peak memory 324796 kb
Host smart-05f6582a-4d98-42ab-8caf-33f17148a974
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476681104 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.3476681104
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.2907677588
Short name T735
Test name
Test status
Simulation time 2314743240 ps
CPU time 6.96 seconds
Started Aug 03 06:49:57 PM PDT 24
Finished Aug 03 06:50:04 PM PDT 24
Peak memory 242204 kb
Host smart-2270e293-3e31-4854-b2bf-2bc62ae4a3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907677588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.2907677588
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.528153387
Short name T1149
Test name
Test status
Simulation time 2048291931 ps
CPU time 15.77 seconds
Started Aug 03 06:50:01 PM PDT 24
Finished Aug 03 06:50:17 PM PDT 24
Peak memory 241940 kb
Host smart-fddb0137-54d8-46ad-bce0-6b51eaf4120e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528153387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.528153387
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.3609530057
Short name T293
Test name
Test status
Simulation time 254690676279 ps
CPU time 1597.33 seconds
Started Aug 03 06:50:01 PM PDT 24
Finished Aug 03 07:16:39 PM PDT 24
Peak memory 363316 kb
Host smart-ac37e8c4-8aed-4dd4-bbaa-8b25a8a7df3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609530057 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.3609530057
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.2299238129
Short name T926
Test name
Test status
Simulation time 711934146 ps
CPU time 5.3 seconds
Started Aug 03 06:50:07 PM PDT 24
Finished Aug 03 06:50:13 PM PDT 24
Peak memory 241984 kb
Host smart-c74f77a6-3190-42aa-8d15-abd0b12a3004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299238129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2299238129
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.1921279023
Short name T500
Test name
Test status
Simulation time 500841794 ps
CPU time 3.5 seconds
Started Aug 03 06:50:07 PM PDT 24
Finished Aug 03 06:50:10 PM PDT 24
Peak memory 242380 kb
Host smart-8fda80bc-e03a-44fb-83cc-b0dd080cbba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921279023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1921279023
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.1200876387
Short name T263
Test name
Test status
Simulation time 92709548096 ps
CPU time 1270.02 seconds
Started Aug 03 06:50:07 PM PDT 24
Finished Aug 03 07:11:18 PM PDT 24
Peak memory 302904 kb
Host smart-3150e464-b699-41ec-9c7c-2a103f314c11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200876387 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.1200876387
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.3427763845
Short name T821
Test name
Test status
Simulation time 144342141 ps
CPU time 4.49 seconds
Started Aug 03 06:50:08 PM PDT 24
Finished Aug 03 06:50:13 PM PDT 24
Peak memory 242028 kb
Host smart-c6a645ef-5348-4a9a-bb11-adfb8b82b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427763845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.3427763845
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.3390767497
Short name T184
Test name
Test status
Simulation time 141902866 ps
CPU time 4 seconds
Started Aug 03 06:50:13 PM PDT 24
Finished Aug 03 06:50:17 PM PDT 24
Peak memory 242020 kb
Host smart-d0f51593-9f0e-486e-b7b3-ffa403da2ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390767497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.3390767497
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.2403135248
Short name T295
Test name
Test status
Simulation time 661301945528 ps
CPU time 1124.23 seconds
Started Aug 03 06:50:17 PM PDT 24
Finished Aug 03 07:09:02 PM PDT 24
Peak memory 283744 kb
Host smart-fcd2c08f-9f8d-4bb6-b327-7025707cb3e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403135248 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.2403135248
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.419024744
Short name T115
Test name
Test status
Simulation time 161218904 ps
CPU time 4.06 seconds
Started Aug 03 06:50:22 PM PDT 24
Finished Aug 03 06:50:26 PM PDT 24
Peak memory 242152 kb
Host smart-2ceea643-2265-4953-8f72-df6503b8805e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419024744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.419024744
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.3166164456
Short name T418
Test name
Test status
Simulation time 6775786625 ps
CPU time 18.19 seconds
Started Aug 03 06:50:26 PM PDT 24
Finished Aug 03 06:50:44 PM PDT 24
Peak memory 241988 kb
Host smart-22bdfcb0-ff4e-4dd3-985a-3891e8bc7412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166164456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.3166164456
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.3553999548
Short name T302
Test name
Test status
Simulation time 80975224228 ps
CPU time 1445.25 seconds
Started Aug 03 06:50:28 PM PDT 24
Finished Aug 03 07:14:34 PM PDT 24
Peak memory 262484 kb
Host smart-1ea33352-e954-4e8a-a26f-776779940cd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553999548 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.3553999548
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.3235628487
Short name T844
Test name
Test status
Simulation time 1923867777 ps
CPU time 4.06 seconds
Started Aug 03 06:50:32 PM PDT 24
Finished Aug 03 06:50:37 PM PDT 24
Peak memory 242168 kb
Host smart-49e95866-b196-4caf-a509-cf15a14fa46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235628487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.3235628487
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.2779545642
Short name T817
Test name
Test status
Simulation time 316035597 ps
CPU time 3.78 seconds
Started Aug 03 06:50:38 PM PDT 24
Finished Aug 03 06:50:42 PM PDT 24
Peak memory 242288 kb
Host smart-d310d456-dfb8-4c4d-8c33-f43203c28d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779545642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.2779545642
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.2367769328
Short name T523
Test name
Test status
Simulation time 45222245725 ps
CPU time 603.17 seconds
Started Aug 03 06:50:37 PM PDT 24
Finished Aug 03 07:00:40 PM PDT 24
Peak memory 376260 kb
Host smart-59a48759-e4a0-417e-9715-a8e66f860bb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367769328 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.2367769328
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.299414964
Short name T159
Test name
Test status
Simulation time 490005570 ps
CPU time 4.11 seconds
Started Aug 03 06:50:44 PM PDT 24
Finished Aug 03 06:50:48 PM PDT 24
Peak memory 242112 kb
Host smart-d58d575b-c957-4c03-9216-ae6fa084feac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299414964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.299414964
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.405305302
Short name T446
Test name
Test status
Simulation time 402027837 ps
CPU time 3.89 seconds
Started Aug 03 06:50:42 PM PDT 24
Finished Aug 03 06:50:46 PM PDT 24
Peak memory 241872 kb
Host smart-a1277485-19d3-4a52-bb21-a4602b5f1dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405305302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.405305302
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.1270420166
Short name T748
Test name
Test status
Simulation time 17220660885 ps
CPU time 362.16 seconds
Started Aug 03 06:50:41 PM PDT 24
Finished Aug 03 06:56:43 PM PDT 24
Peak memory 248812 kb
Host smart-ad55f6bf-6caa-4a60-a5f0-df7bc8af3aea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270420166 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.1270420166
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.1245922915
Short name T1118
Test name
Test status
Simulation time 2581327103 ps
CPU time 5.33 seconds
Started Aug 03 06:50:49 PM PDT 24
Finished Aug 03 06:50:54 PM PDT 24
Peak memory 242396 kb
Host smart-8b39ba74-810c-4587-b0a8-4852a200e29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245922915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.1245922915
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.446891478
Short name T530
Test name
Test status
Simulation time 396537534 ps
CPU time 10.27 seconds
Started Aug 03 06:50:48 PM PDT 24
Finished Aug 03 06:50:58 PM PDT 24
Peak memory 242064 kb
Host smart-afe975f2-2f28-4bb6-922b-e37848bbeebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446891478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.446891478
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.2321769865
Short name T782
Test name
Test status
Simulation time 223073191 ps
CPU time 1.87 seconds
Started Aug 03 06:36:15 PM PDT 24
Finished Aug 03 06:36:17 PM PDT 24
Peak memory 240492 kb
Host smart-d8c5cd5e-90ff-4e54-85a8-44567c9b9ca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321769865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.2321769865
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.1830238110
Short name T805
Test name
Test status
Simulation time 28602272723 ps
CPU time 37.77 seconds
Started Aug 03 06:36:10 PM PDT 24
Finished Aug 03 06:36:48 PM PDT 24
Peak memory 243416 kb
Host smart-d4b96559-2cb9-48e1-9f93-6cc43ab17b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830238110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1830238110
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.2930583637
Short name T897
Test name
Test status
Simulation time 2521169710 ps
CPU time 26.63 seconds
Started Aug 03 06:36:11 PM PDT 24
Finished Aug 03 06:36:38 PM PDT 24
Peak memory 242880 kb
Host smart-75e8afb5-8fd0-43c4-9c84-6a9fb5854462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930583637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2930583637
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.4051955370
Short name T158
Test name
Test status
Simulation time 9930645312 ps
CPU time 31.53 seconds
Started Aug 03 06:36:12 PM PDT 24
Finished Aug 03 06:36:43 PM PDT 24
Peak memory 242096 kb
Host smart-7230c973-4d5d-456c-85fd-26f958c21968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051955370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.4051955370
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.3505488964
Short name T436
Test name
Test status
Simulation time 326058877 ps
CPU time 8.6 seconds
Started Aug 03 06:36:09 PM PDT 24
Finished Aug 03 06:36:18 PM PDT 24
Peak memory 242472 kb
Host smart-4eabfd44-7cb3-4594-8902-5d7d784edd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505488964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.3505488964
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.43435461
Short name T921
Test name
Test status
Simulation time 1945121331 ps
CPU time 4.54 seconds
Started Aug 03 06:36:05 PM PDT 24
Finished Aug 03 06:36:10 PM PDT 24
Peak memory 241976 kb
Host smart-59023c4e-7721-411d-8714-829eca791326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43435461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.43435461
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.4159089368
Short name T196
Test name
Test status
Simulation time 7186596638 ps
CPU time 15.19 seconds
Started Aug 03 06:36:10 PM PDT 24
Finished Aug 03 06:36:26 PM PDT 24
Peak memory 248616 kb
Host smart-4b9cabad-1f0a-4119-a94e-40a8ec58d8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159089368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.4159089368
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.1591439475
Short name T2
Test name
Test status
Simulation time 10513129748 ps
CPU time 18.83 seconds
Started Aug 03 06:36:11 PM PDT 24
Finished Aug 03 06:36:30 PM PDT 24
Peak memory 242072 kb
Host smart-58e55b8d-04f1-4f45-b5f4-7420b39d9815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591439475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.1591439475
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.1071390022
Short name T745
Test name
Test status
Simulation time 5494980104 ps
CPU time 17.33 seconds
Started Aug 03 06:36:11 PM PDT 24
Finished Aug 03 06:36:28 PM PDT 24
Peak memory 242444 kb
Host smart-1797f737-2cbe-41ba-aa48-75896242cb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071390022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.1071390022
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.3840820514
Short name T456
Test name
Test status
Simulation time 342472786 ps
CPU time 6.25 seconds
Started Aug 03 06:36:11 PM PDT 24
Finished Aug 03 06:36:17 PM PDT 24
Peak memory 248632 kb
Host smart-e49adcbd-e8c3-4d08-852a-ddb8d00cbc12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3840820514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3840820514
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.2355348930
Short name T1189
Test name
Test status
Simulation time 1186988303 ps
CPU time 8.87 seconds
Started Aug 03 06:36:12 PM PDT 24
Finished Aug 03 06:36:21 PM PDT 24
Peak memory 242088 kb
Host smart-e569f31e-64c3-4a3e-96a1-56b03c29743b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355348930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.2355348930
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.3170749947
Short name T175
Test name
Test status
Simulation time 297607943 ps
CPU time 7.5 seconds
Started Aug 03 06:36:09 PM PDT 24
Finished Aug 03 06:36:17 PM PDT 24
Peak memory 242112 kb
Host smart-78c85eb3-3bb5-4a2f-aad5-ed7319624248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170749947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.3170749947
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.2323262165
Short name T744
Test name
Test status
Simulation time 27013995860 ps
CPU time 124.22 seconds
Started Aug 03 06:36:16 PM PDT 24
Finished Aug 03 06:38:20 PM PDT 24
Peak memory 255440 kb
Host smart-0af3935b-a1c8-46e3-80c1-c4230756e8a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323262165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
2323262165
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.1852599261
Short name T497
Test name
Test status
Simulation time 106145244222 ps
CPU time 2152.04 seconds
Started Aug 03 06:36:13 PM PDT 24
Finished Aug 03 07:12:06 PM PDT 24
Peak memory 306148 kb
Host smart-a5ae587d-599c-4942-89d2-d41ca33ea00b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852599261 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.1852599261
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.2175244612
Short name T210
Test name
Test status
Simulation time 400935284 ps
CPU time 4.5 seconds
Started Aug 03 06:50:52 PM PDT 24
Finished Aug 03 06:50:56 PM PDT 24
Peak memory 241940 kb
Host smart-01493db1-1f95-4521-bbac-3607d3473ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175244612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.2175244612
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.4163125948
Short name T757
Test name
Test status
Simulation time 7822597532 ps
CPU time 18.56 seconds
Started Aug 03 06:50:52 PM PDT 24
Finished Aug 03 06:51:11 PM PDT 24
Peak memory 242368 kb
Host smart-67d283fe-b876-42aa-aa21-f06029a52ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163125948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.4163125948
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.3381896844
Short name T604
Test name
Test status
Simulation time 188951660654 ps
CPU time 938.03 seconds
Started Aug 03 06:50:59 PM PDT 24
Finished Aug 03 07:06:38 PM PDT 24
Peak memory 319032 kb
Host smart-91488048-74a9-4eb8-a262-0edd90a0726f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381896844 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.3381896844
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.3559557800
Short name T1065
Test name
Test status
Simulation time 418865715 ps
CPU time 3.47 seconds
Started Aug 03 06:51:06 PM PDT 24
Finished Aug 03 06:51:09 PM PDT 24
Peak memory 242320 kb
Host smart-ffc357d1-17ea-44ad-96c1-cb067a71b8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559557800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.3559557800
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.1648381238
Short name T1155
Test name
Test status
Simulation time 3492775064 ps
CPU time 8.17 seconds
Started Aug 03 06:51:05 PM PDT 24
Finished Aug 03 06:51:13 PM PDT 24
Peak memory 242372 kb
Host smart-14269be3-fcb5-4b54-a634-5965901a87d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648381238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1648381238
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.2738636787
Short name T1125
Test name
Test status
Simulation time 549556007073 ps
CPU time 1261.68 seconds
Started Aug 03 06:51:05 PM PDT 24
Finished Aug 03 07:12:07 PM PDT 24
Peak memory 323788 kb
Host smart-5f85ee6c-1df2-4118-8126-218f3ff89e8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738636787 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.2738636787
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.3466117623
Short name T797
Test name
Test status
Simulation time 2186269306 ps
CPU time 4.97 seconds
Started Aug 03 06:51:16 PM PDT 24
Finished Aug 03 06:51:21 PM PDT 24
Peak memory 242352 kb
Host smart-a7aeeb61-24fa-4011-b885-01ac0dbd47d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466117623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.3466117623
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.547169138
Short name T988
Test name
Test status
Simulation time 273023190 ps
CPU time 4.08 seconds
Started Aug 03 06:51:22 PM PDT 24
Finished Aug 03 06:51:27 PM PDT 24
Peak memory 242140 kb
Host smart-59aa76ef-c4e9-4d3b-8b14-9df9f69a31b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547169138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.547169138
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.379239401
Short name T334
Test name
Test status
Simulation time 112582652055 ps
CPU time 3437.62 seconds
Started Aug 03 06:51:22 PM PDT 24
Finished Aug 03 07:48:40 PM PDT 24
Peak memory 583576 kb
Host smart-778ceeab-c5af-4c23-b591-4aa9cdd615a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379239401 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.379239401
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.3937445158
Short name T620
Test name
Test status
Simulation time 306311631 ps
CPU time 3.73 seconds
Started Aug 03 06:51:27 PM PDT 24
Finished Aug 03 06:51:31 PM PDT 24
Peak memory 242184 kb
Host smart-1310e1c2-63b1-46bf-ba73-bb0a6ee9538c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937445158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.3937445158
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.426860277
Short name T605
Test name
Test status
Simulation time 451177596 ps
CPU time 6.92 seconds
Started Aug 03 06:51:27 PM PDT 24
Finished Aug 03 06:51:34 PM PDT 24
Peak memory 248472 kb
Host smart-ec19934a-858a-450d-9746-3d644aae2f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426860277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.426860277
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.2081058286
Short name T729
Test name
Test status
Simulation time 2569798769 ps
CPU time 5.99 seconds
Started Aug 03 06:51:26 PM PDT 24
Finished Aug 03 06:51:32 PM PDT 24
Peak memory 241972 kb
Host smart-029b3d3a-7f85-42c0-b6f0-29a824aa9a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081058286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.2081058286
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.2287253298
Short name T1067
Test name
Test status
Simulation time 447780870 ps
CPU time 5.5 seconds
Started Aug 03 06:51:28 PM PDT 24
Finished Aug 03 06:51:33 PM PDT 24
Peak memory 241852 kb
Host smart-74ecf0ad-612d-4e4d-a701-17f777515010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287253298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.2287253298
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2109106761
Short name T1153
Test name
Test status
Simulation time 364485800392 ps
CPU time 969.61 seconds
Started Aug 03 06:51:31 PM PDT 24
Finished Aug 03 07:07:41 PM PDT 24
Peak memory 341440 kb
Host smart-966e96ee-d29d-4717-b19a-2edae4edad4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109106761 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.2109106761
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.3016231961
Short name T182
Test name
Test status
Simulation time 481155265 ps
CPU time 3.54 seconds
Started Aug 03 06:51:32 PM PDT 24
Finished Aug 03 06:51:36 PM PDT 24
Peak memory 242228 kb
Host smart-5e48df69-3d50-460f-ac36-fcab8a148530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016231961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3016231961
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.1236160681
Short name T698
Test name
Test status
Simulation time 2166337327 ps
CPU time 5.75 seconds
Started Aug 03 06:51:32 PM PDT 24
Finished Aug 03 06:51:38 PM PDT 24
Peak memory 241952 kb
Host smart-dcfeb1ec-bdc6-4a3e-bb19-b55498b5a6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236160681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.1236160681
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.3417108655
Short name T45
Test name
Test status
Simulation time 2235204317 ps
CPU time 5.05 seconds
Started Aug 03 06:51:48 PM PDT 24
Finished Aug 03 06:51:53 PM PDT 24
Peak memory 242292 kb
Host smart-40068b6a-0b25-4cd3-8d41-5545ec815f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417108655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.3417108655
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.2364368620
Short name T1058
Test name
Test status
Simulation time 476547307 ps
CPU time 12.09 seconds
Started Aug 03 06:51:46 PM PDT 24
Finished Aug 03 06:51:59 PM PDT 24
Peak memory 242052 kb
Host smart-8d90c410-7f5e-4362-8b45-71a10eb00ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364368620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.2364368620
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.3290395489
Short name T250
Test name
Test status
Simulation time 21055346559 ps
CPU time 181.37 seconds
Started Aug 03 06:51:52 PM PDT 24
Finished Aug 03 06:54:53 PM PDT 24
Peak memory 248840 kb
Host smart-00887fef-ee24-4bd0-87e1-6b25a7dec30e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290395489 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.3290395489
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.1396833134
Short name T188
Test name
Test status
Simulation time 136408741 ps
CPU time 3.56 seconds
Started Aug 03 06:51:57 PM PDT 24
Finished Aug 03 06:52:00 PM PDT 24
Peak memory 242144 kb
Host smart-ed898e1f-2941-4aef-b882-29f50d5bf0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396833134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.1396833134
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.16061075
Short name T146
Test name
Test status
Simulation time 534854241 ps
CPU time 4.85 seconds
Started Aug 03 06:52:06 PM PDT 24
Finished Aug 03 06:52:11 PM PDT 24
Peak memory 241980 kb
Host smart-efd6a616-3a41-4594-bcdf-7186501c611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16061075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.16061075
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.935879068
Short name T299
Test name
Test status
Simulation time 36627864255 ps
CPU time 1032.11 seconds
Started Aug 03 06:52:07 PM PDT 24
Finished Aug 03 07:09:19 PM PDT 24
Peak memory 373652 kb
Host smart-0cae9aba-40ea-42c9-926a-45a3550dd2c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935879068 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.935879068
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.218979406
Short name T596
Test name
Test status
Simulation time 214098406 ps
CPU time 3.86 seconds
Started Aug 03 06:52:08 PM PDT 24
Finished Aug 03 06:52:12 PM PDT 24
Peak memory 242216 kb
Host smart-d39d105e-b7c3-4ab4-9428-2e0367e712f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218979406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.218979406
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.3241122898
Short name T655
Test name
Test status
Simulation time 186427399 ps
CPU time 4.51 seconds
Started Aug 03 06:52:09 PM PDT 24
Finished Aug 03 06:52:14 PM PDT 24
Peak memory 241872 kb
Host smart-bba14730-a00e-4a36-8367-6d77f9b789ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241122898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.3241122898
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.735448198
Short name T292
Test name
Test status
Simulation time 179434836440 ps
CPU time 820.3 seconds
Started Aug 03 06:52:11 PM PDT 24
Finished Aug 03 07:05:51 PM PDT 24
Peak memory 256844 kb
Host smart-bf6d10be-f267-4928-93a5-48fb714a328d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735448198 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.735448198
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.416310963
Short name T778
Test name
Test status
Simulation time 386648649 ps
CPU time 3.19 seconds
Started Aug 03 06:52:18 PM PDT 24
Finished Aug 03 06:52:21 PM PDT 24
Peak memory 242256 kb
Host smart-32802f00-2362-4146-a400-5d685526c246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416310963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.416310963
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.1037180401
Short name T892
Test name
Test status
Simulation time 188858243 ps
CPU time 3.81 seconds
Started Aug 03 06:52:23 PM PDT 24
Finished Aug 03 06:52:27 PM PDT 24
Peak memory 241900 kb
Host smart-c5c4bb3b-3159-4fbf-92ee-08ddcea84ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037180401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.1037180401
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.2379573667
Short name T1123
Test name
Test status
Simulation time 207773356092 ps
CPU time 1414.04 seconds
Started Aug 03 06:52:27 PM PDT 24
Finished Aug 03 07:16:01 PM PDT 24
Peak memory 506856 kb
Host smart-75c754fc-ad3b-4214-9880-ee7b210c35e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379573667 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.2379573667
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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