Unified Coverage Report :: Module :: prim_sync_reqack

Module : prim_sync_reqack

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack	95.83	100.00	83.33			100.00	100.00

---

Module Instance : tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_sync_reqack_data

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		37	37	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	1	1
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_sync_reqack

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T2,T3,T4
EVEN	0	-	Covered	T1,T2,T3
ODD	-	1	Covered	T2,T3,T4
ODD	-	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T2,T3,T4
EVEN	0	-	Covered	T1,T2,T3
ODD	-	1	Covered	T2,T3,T4
ODD	-	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	1161721693	510877	0	0
SyncReqAckHoldReq	447256694	255159	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161721693	510877	0	0
T2	17389	188	0	0
T3	92032	188	0	0
T4	145073	4998	0	0
T5	203337	4421	0	0
T6	0	1934	0	0
T7	28023	0	0	0
T8	4206	0	0	0
T9	23332	0	0	0
T10	783335	1151	0	0
T11	39929	0	0	0
T12	3494	0	0	0
T14	0	2622	0	0
T103	0	182	0	0
T104	0	274	0	0
T108	0	204	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	447256694	255159	0	0
T2	29810	94	0	0
T3	45075	94	0	0
T4	377808	2499	0	0
T5	629555	2209	0	0
T6	0	967	0	0
T7	28888	0	0	0
T8	15528	0	0	0
T9	11546	0	0	0
T10	48958	575	0	0
T11	13177	0	0	0
T12	13171	0	0	0
T14	0	1310	0	0
T103	0	91	0	0
T104	0	137	0	0
T108	0	102	0	0