Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
0.00 0.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
buf_err_code_cg_wrap[CreatorSwCfgIdx] 0.00 1 100 1 64 64
buf_err_code_cg_wrap[OwnerSwCfgIdx] 0.00 1 100 1 64 64
buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx] 0.00 1 100 1 64 64
buf_err_code_cg_wrap[RotCreatorAuthStateIdx] 0.00 1 100 1 64 64
buf_err_code_cg_wrap[VendorTestIdx] 0.00 1 100 1 64 64




Group Instance : buf_err_code_cg_wrap[CreatorSwCfgIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 6 0 0.00
Crosses 8 8 0 0.00


Variables for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
operation_type 2 2 0 0.00 100 1 1 0
read_access_locked 2 2 0 0.00 100 1 1 2
write_access_locked 2 2 0 0.00 100 1 1 2


Crosses for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
unbuf_part_access_cross 8 8 0 0.00 100 1 1 0



Group Instance : buf_err_code_cg_wrap[OwnerSwCfgIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 6 0 0.00
Crosses 8 8 0 0.00


Variables for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
operation_type 2 2 0 0.00 100 1 1 0
read_access_locked 2 2 0 0.00 100 1 1 2
write_access_locked 2 2 0 0.00 100 1 1 2


Crosses for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
unbuf_part_access_cross 8 8 0 0.00 100 1 1 0



Group Instance : buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 6 0 0.00
Crosses 8 8 0 0.00


Variables for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
operation_type 2 2 0 0.00 100 1 1 0
read_access_locked 2 2 0 0.00 100 1 1 2
write_access_locked 2 2 0 0.00 100 1 1 2


Crosses for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
unbuf_part_access_cross 8 8 0 0.00 100 1 1 0



Group Instance : buf_err_code_cg_wrap[RotCreatorAuthStateIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 6 0 0.00
Crosses 8 8 0 0.00


Variables for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
operation_type 2 2 0 0.00 100 1 1 0
read_access_locked 2 2 0 0.00 100 1 1 2
write_access_locked 2 2 0 0.00 100 1 1 2


Crosses for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
unbuf_part_access_cross 8 8 0 0.00 100 1 1 0



Group Instance : buf_err_code_cg_wrap[VendorTestIdx]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 6 0 0.00
Crosses 8 8 0 0.00


Variables for Group Instance buf_err_code_cg_wrap[VendorTestIdx]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
operation_type 2 2 0 0.00 100 1 1 0
read_access_locked 2 2 0 0.00 100 1 1 2
write_access_locked 2 2 0 0.00 100 1 1 2


Crosses for Group Instance buf_err_code_cg_wrap[VendorTestIdx]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
unbuf_part_access_cross 8 8 0 0.00 100 1 1 0


Summary for Variable operation_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for operation_type

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
read_op 0 1 1
write_op 0 1 1



Summary for Variable read_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for read_access_locked

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable write_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for write_access_locked

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 8 0 0.00 8


Automatically Generated Cross Bins for unbuf_part_access_cross

Uncovered bins
read_access_lockedwrite_access_lockedoperation_typeCOUNTAT LEASTNUMBERSTATUS
* * * -- -- 8


Summary for Variable operation_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for operation_type

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
read_op 0 1 1
write_op 0 1 1



Summary for Variable read_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for read_access_locked

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable write_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for write_access_locked

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 8 0 0.00 8


Automatically Generated Cross Bins for unbuf_part_access_cross

Uncovered bins
read_access_lockedwrite_access_lockedoperation_typeCOUNTAT LEASTNUMBERSTATUS
* * * -- -- 8


Summary for Variable operation_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for operation_type

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
read_op 0 1 1
write_op 0 1 1



Summary for Variable read_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for read_access_locked

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable write_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for write_access_locked

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 8 0 0.00 8


Automatically Generated Cross Bins for unbuf_part_access_cross

Uncovered bins
read_access_lockedwrite_access_lockedoperation_typeCOUNTAT LEASTNUMBERSTATUS
* * * -- -- 8


Summary for Variable operation_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for operation_type

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
read_op 0 1 1
write_op 0 1 1



Summary for Variable read_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for read_access_locked

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable write_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for write_access_locked

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 8 0 0.00 8


Automatically Generated Cross Bins for unbuf_part_access_cross

Uncovered bins
read_access_lockedwrite_access_lockedoperation_typeCOUNTAT LEASTNUMBERSTATUS
* * * -- -- 8


Summary for Variable operation_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for operation_type

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
read_op 0 1 1
write_op 0 1 1



Summary for Variable read_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for read_access_locked

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable write_access_locked

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for write_access_locked

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 8 0 0.00 8


Automatically Generated Cross Bins for unbuf_part_access_cross

Uncovered bins
read_access_lockedwrite_access_lockedoperation_typeCOUNTAT LEASTNUMBERSTATUS
* * * -- -- 8

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%