Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

41728

1

T1

109

T2

1

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	21408	1			T1	30		T2	1		T3	11
values[0x0]	17938	1			T1	49		T3	8		T4	241
values[0x1]	19710	1			T1	128		T3	3		T4	231

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12700	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

46356

1

T1

168

T2

1

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	209	1			T7	3		T8	4		T35	4
valid_sources[0x01]	316	1			T1	6		T8	7		T10	1
valid_sources[0x02]	253	1			T4	29		T6	11		T17	6
valid_sources[0x03]	198	1			T7	5		T8	7		T6	2
valid_sources[0x04]	206	1			T7	1		T8	3		T6	7
valid_sources[0x05]	144	1			T10	2		T6	5		T17	1
valid_sources[0x06]	177	1			T7	2		T8	2		T5	2
valid_sources[0x07]	339	1			T1	2		T6	3		T17	2
valid_sources[0x08]	245	1			T7	1		T17	4		T28	8
valid_sources[0x09]	179	1			T7	1		T5	1		T6	7
valid_sources[0x0a]	209	1			T1	1		T7	2		T8	5
valid_sources[0x0b]	252	1			T7	1		T5	1		T6	1
valid_sources[0x0c]	178	1			T7	2		T5	1		T6	6
valid_sources[0x0d]	371	1			T7	1		T5	2		T6	5
valid_sources[0x0e]	208	1			T3	2		T9	1		T8	6
valid_sources[0x0f]	195	1			T10	1		T5	3		T6	4
valid_sources[0x10]	192	1			T5	1		T6	8		T17	2
valid_sources[0x11]	269	1			T7	1		T5	1		T6	4
valid_sources[0x12]	232	1			T4	29		T7	2		T6	8
valid_sources[0x13]	298	1			T7	3		T8	6		T6	4
valid_sources[0x14]	187	1			T6	13		T17	4		T28	5
valid_sources[0x15]	179	1			T7	1		T8	2		T5	1
valid_sources[0x16]	245	1			T1	1		T4	28		T7	1
valid_sources[0x17]	246	1			T8	2		T6	3		T17	5
valid_sources[0x18]	254	1			T1	2		T7	1		T8	3
valid_sources[0x19]	681	1			T1	6		T7	2		T9	1
valid_sources[0x1a]	141	1			T7	1		T9	1		T14	1
valid_sources[0x1b]	228	1			T7	2		T9	10		T8	6
valid_sources[0x1c]	262	1			T7	1		T9	6		T8	1
valid_sources[0x1d]	227	1			T7	1		T8	1		T10	1
valid_sources[0x1e]	224	1			T7	1		T8	2		T5	1
valid_sources[0x1f]	252	1			T5	1		T6	6		T17	5
valid_sources[0x20]	285	1			T7	1		T6	8		T19	14
valid_sources[0x21]	242	1			T1	2		T7	1		T8	5
valid_sources[0x22]	159	1			T3	4		T7	1		T5	1
valid_sources[0x23]	410	1			T3	1		T7	2		T8	5
valid_sources[0x24]	324	1			T7	1		T8	1		T6	2
valid_sources[0x25]	229	1			T1	7		T7	1		T8	10
valid_sources[0x26]	235	1			T7	1		T6	2		T17	3
valid_sources[0x27]	234	1			T17	2		T28	13		T26	10
valid_sources[0x28]	244	1			T1	24		T7	5		T8	1
valid_sources[0x29]	172	1			T7	3		T10	3		T6	8
valid_sources[0x2a]	194	1			T1	1		T7	2		T5	1
valid_sources[0x2b]	193	1			T1	4		T7	2		T8	4
valid_sources[0x2c]	183	1			T1	7		T7	4		T8	2
valid_sources[0x2d]	241	1			T7	1		T8	10		T6	4
valid_sources[0x2e]	357	1			T7	2		T8	2		T6	4
valid_sources[0x2f]	251	1			T4	49		T7	4		T5	1
valid_sources[0x30]	199	1			T1	4		T7	2		T9	1
valid_sources[0x31]	231	1			T4	29		T7	1		T9	1
valid_sources[0x32]	240	1			T1	18		T7	1		T6	1
valid_sources[0x33]	252	1			T8	2		T10	1		T6	3
valid_sources[0x34]	238	1			T4	22		T7	2		T8	2
valid_sources[0x35]	159	1			T7	1		T6	5		T17	5
valid_sources[0x36]	367	1			T7	1		T8	6		T6	4
valid_sources[0x37]	181	1			T1	1		T4	21		T8	5
valid_sources[0x38]	250	1			T5	1		T6	4		T17	4
valid_sources[0x39]	221	1			T4	4		T8	3		T16	32
valid_sources[0x3a]	284	1			T7	1		T6	10		T19	3
valid_sources[0x3b]	271	1			T7	2		T8	17		T16	3
valid_sources[0x3c]	170	1			T10	3		T5	1		T6	1
valid_sources[0x3d]	267	1			T7	1		T9	2		T8	1
valid_sources[0x3e]	352	1			T8	2		T10	3		T5	1
valid_sources[0x3f]	253	1			T7	1		T5	1		T6	7
valid_sources[0x40]	171	1			T7	3		T6	3		T19	1
valid_sources[0x41]	269	1			T1	3		T7	1		T8	3
valid_sources[0x42]	322	1			T5	1		T6	4		T17	8
valid_sources[0x43]	287	1			T8	2		T5	1		T6	8
valid_sources[0x44]	180	1			T1	1		T7	1		T5	1
valid_sources[0x45]	273	1			T1	3		T9	1		T8	3
valid_sources[0x46]	295	1			T4	43		T9	1		T6	7
valid_sources[0x47]	273	1			T7	4		T8	4		T6	4
valid_sources[0x48]	206	1			T7	2		T6	3		T19	19
valid_sources[0x49]	177	1			T8	1		T5	1		T6	4
valid_sources[0x4a]	157	1			T7	2		T8	1		T10	3
valid_sources[0x4b]	249	1			T7	1		T8	1		T5	1
valid_sources[0x4c]	193	1			T7	1		T8	6		T6	7
valid_sources[0x4d]	199	1			T7	1		T6	6		T17	8
valid_sources[0x4e]	189	1			T1	2		T7	2		T8	1
valid_sources[0x4f]	229	1			T10	3		T6	1		T19	6
valid_sources[0x50]	212	1			T4	3		T7	2		T8	1
valid_sources[0x51]	254	1			T4	5		T7	2		T8	2
valid_sources[0x52]	356	1			T7	1		T8	5		T6	4
valid_sources[0x53]	188	1			T7	2		T8	14		T5	1
valid_sources[0x54]	192	1			T1	4		T9	1		T6	2
valid_sources[0x55]	225	1			T4	32		T7	2		T5	1
valid_sources[0x56]	222	1			T1	1		T7	2		T8	4
valid_sources[0x57]	252	1			T3	1		T4	43		T5	1
valid_sources[0x58]	272	1			T7	1		T6	8		T17	5
valid_sources[0x59]	286	1			T8	6		T6	2		T17	7
valid_sources[0x5a]	424	1			T4	57		T7	1		T9	1
valid_sources[0x5b]	219	1			T7	2		T8	2		T5	1
valid_sources[0x5c]	221	1			T8	1		T10	3		T14	1
valid_sources[0x5d]	208	1			T4	4		T8	9		T6	5
valid_sources[0x5e]	268	1			T7	2		T5	1		T6	7
valid_sources[0x5f]	222	1			T1	6		T7	2		T8	2
valid_sources[0x60]	230	1			T1	2		T7	3		T5	1
valid_sources[0x61]	263	1			T9	2		T8	2		T6	5
valid_sources[0x62]	330	1			T6	9		T17	9		T28	12
valid_sources[0x63]	194	1			T7	1		T6	2		T17	3
valid_sources[0x64]	188	1			T1	11		T7	1		T5	1
valid_sources[0x65]	178	1			T1	1		T7	1		T5	2
valid_sources[0x66]	235	1			T3	3		T5	2		T6	10
valid_sources[0x67]	198	1			T7	4		T8	2		T6	6
valid_sources[0x68]	368	1			T1	1		T7	1		T8	9
valid_sources[0x69]	226	1			T1	1		T7	1		T9	1
valid_sources[0x6a]	239	1			T7	2		T6	7		T17	3
valid_sources[0x6b]	296	1			T4	21		T7	1		T6	6
valid_sources[0x6c]	226	1			T4	14		T7	1		T9	1
valid_sources[0x6d]	204	1			T7	2		T8	2		T16	5
valid_sources[0x6e]	198	1			T7	2		T6	1		T17	5
valid_sources[0x6f]	255	1			T7	3		T6	3		T17	2
valid_sources[0x70]	167	1			T7	1		T8	6		T14	1
valid_sources[0x71]	277	1			T9	3		T8	10		T5	1
valid_sources[0x72]	205	1			T7	1		T8	1		T5	1
valid_sources[0x73]	126	1			T7	1		T6	5		T17	6
valid_sources[0x74]	242	1			T1	8		T7	1		T8	2
valid_sources[0x75]	214	1			T7	1		T8	2		T6	6
valid_sources[0x76]	168	1			T7	1		T8	1		T6	5
valid_sources[0x77]	251	1			T7	1		T5	1		T17	6
valid_sources[0x78]	198	1			T9	2		T8	4		T6	7
valid_sources[0x79]	165	1			T7	2		T8	3		T6	7
valid_sources[0x7a]	155	1			T6	1		T19	2		T17	8
valid_sources[0x7b]	294	1			T7	2		T8	4		T6	2
valid_sources[0x7c]	193	1			T1	3		T7	3		T8	2
valid_sources[0x7d]	260	1			T7	3		T6	6		T17	4
valid_sources[0x7e]	181	1			T1	4		T7	1		T8	2
valid_sources[0x7f]	226	1			T7	1		T8	4		T14	1
valid_sources[0x80]	263	1			T7	2		T8	1		T19	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

12527

1

T1

27

T2

1

T3

7

values[0x0]

all_enables

biggest_size

14847

1

T1

39

T3

3

T4

185

values[0x1]

all_enables

biggest_size

14354

1

T1

43

T4

173

T7

100

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13540	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

21940

1

T1

557

T4

85

T7

345

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19482	1			T1	129		T4	202		T7	95
values[0x0]	7806	1			T1	219		T4	36		T7	116
values[0x1]	8192	1			T1	232		T4	44		T7	142

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9262	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

26218

1

T1

574

T4

155

T7

350

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	100	1			T8	3		T6	2		T19	5
valid_sources[0x01]	98	1			T8	3		T5	1		T6	4
valid_sources[0x02]	122	1			T9	2		T8	3		T10	1
valid_sources[0x03]	149	1			T1	8		T7	3		T8	4
valid_sources[0x04]	130	1			T8	1		T5	1		T28	8
valid_sources[0x05]	96	1			T4	3		T5	1		T6	8
valid_sources[0x06]	163	1			T1	16		T8	4		T6	3
valid_sources[0x07]	91	1			T4	4		T6	1		T26	2
valid_sources[0x08]	117	1			T8	1		T26	4		T32	1
valid_sources[0x09]	109	1			T8	6		T28	13		T26	3
valid_sources[0x0a]	123	1			T19	16		T20	1		T21	1
valid_sources[0x0b]	171	1			T9	1		T6	14		T21	1
valid_sources[0x0c]	187	1			T9	1		T8	2		T10	1
valid_sources[0x0d]	128	1			T8	1		T6	2		T19	11
valid_sources[0x0e]	135	1			T1	7		T8	3		T19	23
valid_sources[0x0f]	129	1			T4	7		T28	4		T26	1
valid_sources[0x10]	83	1			T26	4		T27	1		T47	3
valid_sources[0x11]	184	1			T8	1		T10	1		T6	2
valid_sources[0x12]	137	1			T9	1		T8	6		T10	1
valid_sources[0x13]	117	1			T6	7		T28	11		T21	2
valid_sources[0x14]	114	1			T6	3		T19	2		T28	2
valid_sources[0x15]	180	1			T8	1		T6	2		T28	8
valid_sources[0x16]	111	1			T1	11		T8	3		T6	4
valid_sources[0x17]	178	1			T8	2		T6	3		T19	22
valid_sources[0x18]	121	1			T1	16		T7	4		T5	1
valid_sources[0x19]	112	1			T4	8		T19	6		T29	2
valid_sources[0x1a]	179	1			T4	9		T8	2		T28	1
valid_sources[0x1b]	119	1			T8	7		T6	6		T19	2
valid_sources[0x1c]	111	1			T4	5		T8	1		T10	3
valid_sources[0x1d]	119	1			T8	1		T10	1		T26	1
valid_sources[0x1e]	153	1			T8	1		T10	1		T6	4
valid_sources[0x1f]	120	1			T8	3		T6	4		T25	13
valid_sources[0x20]	150	1			T4	25		T8	2		T28	12
valid_sources[0x21]	209	1			T1	1		T8	3		T5	3
valid_sources[0x22]	92	1			T8	3		T21	1		T26	5
valid_sources[0x23]	306	1			T4	1		T5	2		T6	3
valid_sources[0x24]	169	1			T4	2		T19	21		T26	1
valid_sources[0x25]	126	1			T8	6		T5	1		T16	1
valid_sources[0x26]	158	1			T1	2		T8	1		T6	4
valid_sources[0x27]	94	1			T8	3		T26	1		T31	2
valid_sources[0x28]	116	1			T8	2		T5	5		T6	6
valid_sources[0x29]	219	1			T7	93		T10	1		T16	9
valid_sources[0x2a]	190	1			T1	37		T8	1		T5	2
valid_sources[0x2b]	126	1			T8	2		T6	3		T19	24
valid_sources[0x2c]	117	1			T1	33		T8	1		T6	4
valid_sources[0x2d]	110	1			T6	3		T26	6		T27	6
valid_sources[0x2e]	92	1			T1	4		T4	3		T8	1
valid_sources[0x2f]	113	1			T8	1		T5	1		T6	3
valid_sources[0x30]	151	1			T8	2		T6	2		T19	18
valid_sources[0x31]	138	1			T6	2		T28	8		T26	4
valid_sources[0x32]	214	1			T8	4		T6	4		T29	1
valid_sources[0x33]	105	1			T8	3		T6	5		T28	3
valid_sources[0x34]	187	1			T8	6		T6	10		T17	27
valid_sources[0x35]	88	1			T1	19		T8	2		T6	2
valid_sources[0x36]	102	1			T8	1		T26	6		T31	2
valid_sources[0x37]	130	1			T8	3		T5	1		T28	8
valid_sources[0x38]	202	1			T4	6		T8	6		T6	4
valid_sources[0x39]	103	1			T9	1		T8	1		T19	1
valid_sources[0x3a]	102	1			T9	1		T8	4		T5	2
valid_sources[0x3b]	121	1			T6	5		T21	1		T26	1
valid_sources[0x3c]	166	1			T9	1		T6	1		T57	1
valid_sources[0x3d]	151	1			T8	3		T6	10		T25	37
valid_sources[0x3e]	108	1			T8	2		T26	5		T31	1
valid_sources[0x3f]	184	1			T7	10		T8	3		T6	1
valid_sources[0x40]	143	1			T8	1		T6	3		T28	7
valid_sources[0x41]	117	1			T1	3		T8	2		T21	2
valid_sources[0x42]	139	1			T8	2		T5	2		T6	10
valid_sources[0x43]	128	1			T6	1		T19	7		T17	42
valid_sources[0x44]	171	1			T8	3		T6	5		T28	8
valid_sources[0x45]	102	1			T8	2		T21	3		T26	3
valid_sources[0x46]	90	1			T6	1		T26	5		T24	8
valid_sources[0x47]	87	1			T8	1		T6	6		T19	9
valid_sources[0x48]	121	1			T8	2		T28	18		T21	1
valid_sources[0x49]	143	1			T8	9		T6	4		T28	8
valid_sources[0x4a]	143	1			T1	4		T8	1		T6	7
valid_sources[0x4b]	107	1			T8	3		T26	2		T57	1
valid_sources[0x4c]	119	1			T8	3		T6	3		T28	2
valid_sources[0x4d]	224	1			T4	1		T8	7		T29	1
valid_sources[0x4e]	103	1			T4	7		T5	1		T6	8
valid_sources[0x4f]	226	1			T8	4		T10	1		T6	3
valid_sources[0x50]	163	1			T4	23		T6	1		T21	2
valid_sources[0x51]	143	1			T8	5		T5	4		T36	12
valid_sources[0x52]	209	1			T8	1		T6	1		T17	19
valid_sources[0x53]	145	1			T8	5		T19	7		T28	1
valid_sources[0x54]	131	1			T4	10		T8	3		T6	3
valid_sources[0x55]	112	1			T4	5		T8	7		T6	1
valid_sources[0x56]	132	1			T9	1		T28	8		T26	1
valid_sources[0x57]	150	1			T8	2		T6	2		T26	4
valid_sources[0x58]	139	1			T7	12		T9	1		T5	1
valid_sources[0x59]	98	1			T8	2		T29	1		T26	2
valid_sources[0x5a]	64	1			T8	1		T6	5		T19	1
valid_sources[0x5b]	113	1			T6	2		T17	16		T28	13
valid_sources[0x5c]	84	1			T9	1		T6	2		T21	1
valid_sources[0x5d]	124	1			T1	15		T8	1		T6	2
valid_sources[0x5e]	196	1			T1	17		T4	1		T6	3
valid_sources[0x5f]	105	1			T8	3		T6	7		T28	8
valid_sources[0x60]	126	1			T4	2		T8	2		T6	1
valid_sources[0x61]	160	1			T9	1		T8	2		T10	1
valid_sources[0x62]	205	1			T8	1		T28	16		T26	1
valid_sources[0x63]	92	1			T8	7		T10	1		T6	1
valid_sources[0x64]	131	1			T8	5		T6	10		T28	7
valid_sources[0x65]	189	1			T5	2		T26	4		T27	2
valid_sources[0x66]	143	1			T4	1		T8	4		T6	15
valid_sources[0x67]	142	1			T1	52		T8	5		T5	1
valid_sources[0x68]	137	1			T4	11		T8	2		T6	4
valid_sources[0x69]	89	1			T6	2		T28	4		T26	2
valid_sources[0x6a]	166	1			T4	8		T9	1		T8	5
valid_sources[0x6b]	621	1			T8	3		T10	1		T6	4
valid_sources[0x6c]	164	1			T1	8		T8	1		T6	4
valid_sources[0x6d]	92	1			T21	2		T26	2		T31	1
valid_sources[0x6e]	81	1			T8	2		T19	4		T21	2
valid_sources[0x6f]	128	1			T4	2		T8	2		T19	10
valid_sources[0x70]	94	1			T28	8		T26	3		T31	2
valid_sources[0x71]	177	1			T8	1		T10	1		T6	2
valid_sources[0x72]	170	1			T7	89		T8	5		T6	1
valid_sources[0x73]	115	1			T4	1		T6	1		T28	8
valid_sources[0x74]	148	1			T8	3		T19	8		T28	3
valid_sources[0x75]	119	1			T8	8		T6	1		T26	1
valid_sources[0x76]	146	1			T4	14		T8	6		T10	1
valid_sources[0x77]	96	1			T8	2		T5	1		T6	8
valid_sources[0x78]	138	1			T8	7		T6	1		T19	3
valid_sources[0x79]	170	1			T8	9		T19	2		T28	8
valid_sources[0x7a]	154	1			T4	2		T8	5		T6	4
valid_sources[0x7b]	83	1			T8	1		T6	5		T20	6
valid_sources[0x7c]	144	1			T8	2		T19	3		T17	19
valid_sources[0x7d]	165	1			T4	8		T8	1		T6	2
valid_sources[0x7e]	117	1			T8	2		T6	4		T28	3
valid_sources[0x7f]	117	1			T7	12		T8	1		T6	1
valid_sources[0x80]	134	1			T8	4		T6	3		T19	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8075

1

T1

129

T4

21

T7

95

values[0x0]

all_enables

biggest_size

7114

1

T1

217

T4

31

T7

114

values[0x1]

all_enables

biggest_size

6751

1

T1

211

T4

33

T7

136