Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter_sram	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_tlul_adapter_sram

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.74	0.00	0.00	30.95		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	0.00	0.00	0.00			0.00
u_reqfifo	0.00	0.00	0.00			0.00
u_rsp_gen	0.00	0.00
u_rspfifo	0.00	0.00	0.00			0.00
u_sram_byte	0.00	0.00
u_sramreqfifo	0.00	0.00	0.00			0.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

Line Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
TOTAL		73	0	0.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	3	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
CONT_ASSIGN	188	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	273	1	0	0.00
CONT_ASSIGN	274	1	0	0.00
ALWAYS	279	8	0	0.00
ALWAYS	299	6	0	0.00
CONT_ASSIGN	313	1	0	0.00
CONT_ASSIGN	317	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
CONT_ASSIGN	341	1	0	0.00
CONT_ASSIGN	347	1	0	0.00
CONT_ASSIGN	359	1	0	0.00
ALWAYS	362	3	0	0.00
CONT_ASSIGN	369	1	0	0.00
CONT_ASSIGN	390	1	0	0.00
CONT_ASSIGN	391	1	0	0.00
CONT_ASSIGN	392	1	0	0.00
CONT_ASSIGN	393	1	0	0.00
ALWAYS	423	6	0	0.00
ALWAYS	435	5	0	0.00
CONT_ASSIGN	450	1	0	0.00
CONT_ASSIGN	451	1	0	0.00
CONT_ASSIGN	452	1	0	0.00
CONT_ASSIGN	456	1	0	0.00
CONT_ASSIGN	457	1	0	0.00
CONT_ASSIGN	459	1	0	0.00
CONT_ASSIGN	460	1	0	0.00
CONT_ASSIGN	467	1	0	0.00
CONT_ASSIGN	470	1	0	0.00
CONT_ASSIGN	474	1	0	0.00
CONT_ASSIGN	475	1	0	0.00
CONT_ASSIGN	477	1	0	0.00
CONT_ASSIGN	479	1	0	0.00
CONT_ASSIGN	486	1	0	0.00
ALWAYS	517	3	0	0.00
CONT_ASSIGN	523	1	0	0.00
CONT_ASSIGN	526	1	0	0.00
CONT_ASSIGN	531	1	0	0.00
CONT_ASSIGN	536	1	0	0.00
CONT_ASSIGN	620	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	0	1
130	0	1
131	0	1
132		unreachable
			==> MISSING_ELSE
138	0	1
144	0	1
151	0	1
156	0	1
176	0	1
188	0	1
272	0	1
273	0	1
274	0	1
279	0	1
281	0	1
282	0	1
284	0	1
285	0	1
286	0	1
289	0	1
292	0	1
299	0	1
301	0	1
302	0	1
303	0	1
305	0	1
308	0	1
313	0	1
317	0	1
336	0	1
341	0	1
347	0	1
359	0	1
362	0	1
363	0	1
365	0	1
369	0	1
390	0	1
391	0	1
392	0	1
393	0	1
423	0	1
424	0	1
426	0	1
427	0	1
428	0	1
429	0	1
			==> MISSING_ELSE
435	0	1
436	0	1
438	0	1
439	0	1
440	0	1
			==> MISSING_ELSE
450	0	1
451	0	1
452	0	1
456	0	1
457	0	1
459	0	1
460	0	1
467	0	1
470	0	1
474	0	1
475	0	1
477	0	1
479	0	1
486	0	1
517	0	1
518	0	1
519	0	1
523	0	1
526	0	1
531	0	1
536	0	1
620	0	1

---

Cond Coverage for Module : tlul_adapter_sram

	Total	Covered	Percent
Conditions	121	0	0.00
Logical	121	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Unreachable
0	0	1	0	Unreachable
0	1	0	0	Unreachable
1	0	0	0	Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Not Covered
0	0	0	0	1	Not Covered
0	0	0	1	0	Unreachable
0	0	1	0	0	Unreachable
0	1	0	0	0	Unreachable
1	0	0	0	0	Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Not Covered
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Not Covered
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Unreachable
1	1	1	1	Not Covered

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       452
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		26	0	0.00
TERNARY	144	2	0	0.00
TERNARY	341	2	0	0.00
TERNARY	347	3	0	0.00
TERNARY	393	2	0	0.00
TERNARY	531	2	0	0.00
IF	129	2	0	0.00
IF	281	4	0	0.00
IF	301	3	0	0.00
IF	362	2	0	0.00
IF	426	2	0	0.00
IF	438	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	341	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	347	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	347	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	393	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	531	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	129	if ((!rst_ni))
-2-:	131	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Unreachable
0	0	Not Covered

	LineNo.	Expression
-1-:	281	if (reqfifo_rvalid)
-2-:	282	if (reqfifo_rdata.error)
-3-:	285	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	1	Not Covered
1	0	0	Not Covered
0	-	-	Not Covered

	LineNo.	Expression
-1-:	301	if (reqfifo_rvalid)
-2-:	302	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	362	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	426	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	438	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram

	Line No.	Total	Covered	Percent
TOTAL		72	0	0.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	3	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
CONT_ASSIGN	188	1	0	0.00
CONT_ASSIGN	272	1	0	0.00
CONT_ASSIGN	273	1	0	0.00
CONT_ASSIGN	274	1	0	0.00
ALWAYS	279	7	0	0.00
ALWAYS	299	6	0	0.00
CONT_ASSIGN	313	1	0	0.00
CONT_ASSIGN	317	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
CONT_ASSIGN	341	1	0	0.00
CONT_ASSIGN	347	1	0	0.00
CONT_ASSIGN	359	1	0	0.00
ALWAYS	362	3	0	0.00
CONT_ASSIGN	369	1	0	0.00
CONT_ASSIGN	390	1	0	0.00
CONT_ASSIGN	391	1	0	0.00
CONT_ASSIGN	392	1	0	0.00
CONT_ASSIGN	393	1	0	0.00
ALWAYS	423	6	0	0.00
ALWAYS	435	5	0	0.00
CONT_ASSIGN	450	1	0	0.00
CONT_ASSIGN	451	1	0	0.00
CONT_ASSIGN	452	1	0	0.00
CONT_ASSIGN	456	1	0	0.00
CONT_ASSIGN	457	1	0	0.00
CONT_ASSIGN	459	1	0	0.00
CONT_ASSIGN	460	1	0	0.00
CONT_ASSIGN	467	1	0	0.00
CONT_ASSIGN	470	1	0	0.00
CONT_ASSIGN	474	1	0	0.00
CONT_ASSIGN	475	1	0	0.00
CONT_ASSIGN	477	1	0	0.00
CONT_ASSIGN	479	1	0	0.00
CONT_ASSIGN	486	1	0	0.00
ALWAYS	517	3	0	0.00
CONT_ASSIGN	523	1	0	0.00
CONT_ASSIGN	526	1	0	0.00
CONT_ASSIGN	531	1	0	0.00
CONT_ASSIGN	536	1	0	0.00
CONT_ASSIGN	620	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	0	1
130	0	1
131	0	1
132		unreachable
			==> MISSING_ELSE
138	0	1
144	0	1
151	0	1
156	0	1
176	0	1
188	0	1
272	0	1
273	0	1
274	0	1
279	0	1
281	0	1
282	0	1
284	0	1
285	0	1
286	0	1
289		excluded
			Exclude Annotation: VC_COV_UNR
292	0	1
299	0	1
301	0	1
302	0	1
303	0	1
305	0	1
308	0	1
313	0	1
317	0	1
336	0	1
341	0	1
347	0	1
359	0	1
362	0	1
363	0	1
365	0	1
369	0	1
390	0	1
391	0	1
392	0	1
393	0	1
423	0	1
424	0	1
426	0	1
427	0	1
428	0	1
429	0	1
			==> MISSING_ELSE
435	0	1
436	0	1
438	0	1
439	0	1
440	0	1
			==> MISSING_ELSE
450	0	1
451	0	1
452	0	1
456	0	1
457	0	1
459	0	1
460	0	1
467	0	1
470	0	1
474	0	1
475	0	1
477	0	1
479	0	1
486	0	1
517	0	1
518	0	1
519	0	1
523	0	1
526	0	1
531	0	1
536	0	1
620	0	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram

	Total	Covered	Percent
Conditions	110	0	0.00
Logical	110	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Unreachable
0	0	1	0	Unreachable
0	1	0	0	Unreachable
1	0	0	0	Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Not Covered
0	0	0	0	1	Not Covered
0	0	0	1	0	Unreachable
0	0	1	0	0	Unreachable
0	1	0	0	0	Unreachable
1	0	0	0	0	Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests	Exclude Annotation
0	0	0	0	0	0	Not Covered
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Not Covered
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Not Covered
1	1	Not Covered

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Not Covered

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Not Covered
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Not Covered

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests	Exclude Annotation
0	Not Covered
1	Excluded		VC_COV_UNR

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Not Covered
1	1	Excluded		VC_COV_UNR

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Unreachable
1	1	1	1	Not Covered

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       452
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:i=0:vcs_gen_end:VC_COV_UNR
1	0	Not Covered
1	1	Not Covered

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Not Covered

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Not Covered

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		24	0	0.00
TERNARY	144	2	0	0.00
TERNARY	341	2	0	0.00
TERNARY	347	2	0	0.00
TERNARY	393	2	0	0.00
TERNARY	531	2	0	0.00
IF	129	2	0	0.00
IF	281	3	0	0.00
IF	301	3	0	0.00
IF	362	2	0	0.00
IF	426	2	0	0.00
IF	438	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	341	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	347	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	347	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Excluded		VC_COV_UNR
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	393	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	531	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	129	if ((!rst_ni))
-2-:	131	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Unreachable
0	0	Not Covered

	LineNo.	Expression
-1-:	281	if (reqfifo_rvalid)
-2-:	282	if (reqfifo_rdata.error)
-3-:	285	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	1	-	Not Covered
1	0	1	Not Covered
1	0	0	Excluded		VC_COV_UNR
0	-	-	Not Covered

	LineNo.	Expression
-1-:	301	if (reqfifo_rvalid)
-2-:	302	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	362	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	426	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	438	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered