Unified Coverage Report :: Module :: prim_packer_fifo

Module : prim_packer_fifo

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_edn_req.u_prim_packer_fifo	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_prim_edn_req

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_packer_fifo

	Line No.	Total	Covered	Percent
TOTAL		17	0	0.00
ALWAYS	82	7	0	0.00
CONT_ASSIGN	94	0	0
CONT_ASSIGN	96	1	0	0.00
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	102	1	0	0.00
CONT_ASSIGN	103	1	0	0.00
CONT_ASSIGN	104	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	110	1	0	0.00
CONT_ASSIGN	115	1	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	117	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
82	0	1
83	0	1
84	0	1
85	0	1
87	0	1
88	0	1
89	0	1
94		unreachable
96	0	1
101	0	1
102	0	1
103	0	1
104	0	1
106	0	1
110	0	1
115	0	1
116	0	1
117	0	1

---

Cond Coverage for Module : prim_packer_fifo

	Total	Covered	Percent
Conditions	30	0	0.00
Logical	30	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION ((rready_i && rvalid_o) || clr_q)
             -----------1----------    --2--

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       102
 SUB-EXPRESSION (rready_i && rvalid_o)
                 ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Not Covered

 LINE       103
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Unreachable

 LINE       104
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       106
 EXPRESSION (clear_status ? '0 : (load_data ? ((depth_q + DepthOne)) : depth_q))
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       106
 SUB-EXPRESSION (load_data ? ((depth_q + DepthOne)) : depth_q)
                 ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       110
 EXPRESSION (clear_data ? '0 : (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q))
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       110
 SUB-EXPRESSION (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q)
                 ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       115
 EXPRESSION (( ! (depth_q == FullDepth) ) && ((!clr_q)))
             --------------1-------------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       115
 SUB-EXPRESSION ( ! (depth_q == FullDepth) )
                    -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       115
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       117
 EXPRESSION ((depth_q == FullDepth) && ((!clr_q)))
             -----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       117
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : prim_packer_fifo

	Line No.	Total	Covered	Percent
Branches		8	0	0.00
TERNARY	106	3	0	0.00
TERNARY	110	3	0	0.00
IF	82	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	106	(clear_status) ? 
-2-:	106	(load_data) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	110	(clear_data) ? 
-2-:	110	(load_data) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo

	Line No.	Total	Covered	Percent
TOTAL		17	0	0.00
ALWAYS	82	7	0	0.00
CONT_ASSIGN	94	0	0
CONT_ASSIGN	96	1	0	0.00
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	102	1	0	0.00
CONT_ASSIGN	103	1	0	0.00
CONT_ASSIGN	104	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	110	1	0	0.00
CONT_ASSIGN	115	1	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	117	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
82	0	1
83	0	1
84	0	1
85	0	1
87	0	1
88	0	1
89	0	1
94		unreachable
96	0	1
101	0	1
102	0	1
103	0	1
104	0	1
106	0	1
110	0	1
115	0	1
116	0	1
117	0	1

---

Cond Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo

	Total	Covered	Percent
Conditions	29	0	0.00
Logical	29	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION ((rready_i && rvalid_o) || clr_q)
             -----------1----------    --2--

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       102
 SUB-EXPRESSION (rready_i && rvalid_o)
                 ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Not Covered

 LINE       103
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Unreachable

 LINE       104
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       106
 EXPRESSION (clear_status ? '0 : (load_data ? ((depth_q + DepthOne)) : depth_q))
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       106
 SUB-EXPRESSION (load_data ? ((depth_q + DepthOne)) : depth_q)
                 ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       110
 EXPRESSION (clear_data ? '0 : (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q))
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       110
 SUB-EXPRESSION (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q)
                 ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       115
 EXPRESSION (( ! (depth_q == FullDepth) ) && ((!clr_q)))
             --------------1-------------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       115
 SUB-EXPRESSION ( ! (depth_q == FullDepth) )
                    -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       115
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       117
 EXPRESSION ((depth_q == FullDepth) && ((!clr_q)))
             -----------1----------    -----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Not Covered

 LINE       117
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo

	Line No.	Total	Covered	Percent
Branches		8	0	0.00
TERNARY	106	3	0	0.00
TERNARY	110	3	0	0.00
IF	82	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	106	(clear_status) ? 
-2-:	106	(load_data) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	110	(clear_data) ? 
-2-:	110	(load_data) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered