Unified Coverage Report :: Module :: prim_ram_1p_adv

Module : prim_ram_1p_adv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv	0.00	0.00				0.00

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_mem	0.00	0.00				0.00
u_req_d_buf	0.00	0.00
u_write_d_buf	0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_ram_1p_adv

	Line No.	Total	Covered	Percent
TOTAL		38	0	0.00
CONT_ASSIGN	102	1	0	0.00
CONT_ASSIGN	103	1	0	0.00
CONT_ASSIGN	123	1	0	0.00
ALWAYS	126	3	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	135	1	0	0.00
CONT_ASSIGN	136	1	0	0.00
CONT_ASSIGN	137	1	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	147	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	248	0	0
CONT_ASSIGN	249	1	0	0.00
CONT_ASSIGN	251	1	0	0.00
CONT_ASSIGN	255	1	0	0.00
ALWAYS	288	5	0	0.00
ALWAYS	299	7	0	0.00
ALWAYS	334	3	0	0.00
ALWAYS	343	5	0	0.00
CONT_ASSIGN	359	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
102	0	1
103	0	1
123	0	1
126	0	1
127	0	1
129	0	1
133	0	1
134	0	1
135	0	1
136	0	1
137	0	1
138	0	1
147	0	1
156	0	1
248		unreachable
249	0	1
251	0	1
255	0	1
288	0	1
289	0	1
290	0	1
292	0	1
293	0	1
299	0	1
300	0	1
301	0	1
302	0	1
304	0	1
305	0	1
306	0	1
334	0	1
335	0	1
337	0	1
343	0	1
344	0	1
345	0	1
347	0	1
349	0	1
359	0	1

---

Branch Coverage for Module : prim_ram_1p_adv

	Line No.	Total	Covered	Percent
Branches		10	0	0.00
IF	126	2	0	0.00
IF	299	2	0	0.00
IF	288	2	0	0.00
IF	343	2	0	0.00
IF	334	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	126	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	343	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	334	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered