Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data	0.00	0.00

---

Module Instance : tb.dut.u_prim_edn_req.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_prim_edn_req

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	0.00	0.00	0.00			0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	0	0.00
CONT_ASSIGN	93	1	0	0.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	0	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable