Unified Coverage Report :: Module :: otp_ctrl_ecc_reg

Module : otp_ctrl_ecc_reg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	0.00	0.00				0.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	0.00	0.00				0.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	0.00	0.00				0.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	0.00	0.00				0.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	0.00	0.00				0.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	0.00	0.00				0.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	0.00	0.00				0.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	0.00	0.00				0.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	0.00	0.00				0.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	0.00	0.00				0.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[3].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[4].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[10].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=9,Aw=4,EccWidth=8 + Width=64,Depth=2,Aw=1,EccWidth=8 + Width=64,Depth=5,Aw=3,EccWidth=8 + Width=64,Depth=11,Aw=4,EccWidth=8 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	60	8	0	0.00
CONT_ASSIGN	87	1	0	0.00
ALWAYS	90	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	0	1
61	0	1
62	0	1
64	0	1
65	0	1
66	0	1
67	0	1
68	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
87	0	1
90	0	1
91	0	1
92	0	1
94	0	1
95	0	1

---

Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=1,Aw=1,EccWidth=8 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	46	8	0	0.00
CONT_ASSIGN	87	1	0	0.00
ALWAYS	90	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	0	1
47	0	1
48	0	1
50	0	1
51	0	1
52	0	1
53	0	1
54	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
87	0	1
90	0	1
91	0	1
92	0	1
94	0	1
95	0	1

---

Branch Coverage for Module : otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	90	2	0	0.00
IF	65	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	46	8	0	0.00
CONT_ASSIGN	87	1	0	0.00
ALWAYS	90	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	0	1
47	0	1
48	0	1
50	0	1
51	0	1
52	0	1
53	0	1
54	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
87	0	1
90	0	1
91	0	1
92	0	1
94	0	1
95	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	90	2	0	0.00
IF	65	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	46	8	0	0.00
CONT_ASSIGN	87	1	0	0.00
ALWAYS	90	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	0	1
47	0	1
48	0	1
50	0	1
51	0	1
52	0	1
53	0	1
54	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
87	0	1
90	0	1
91	0	1
92	0	1
94	0	1
95	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	90	2	0	0.00
IF	65	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	46	8	0	0.00
CONT_ASSIGN	87	1	0	0.00
ALWAYS	90	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	0	1
47	0	1
48	0	1
50	0	1
51	0	1
52	0	1
53	0	1
54	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
87	0	1
90	0	1
91	0	1
92	0	1
94	0	1
95	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	90	2	0	0.00
IF	65	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	46	8	0	0.00
CONT_ASSIGN	87	1	0	0.00
ALWAYS	90	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	0	1
47	0	1
48	0	1
50	0	1
51	0	1
52	0	1
53	0	1
54	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
87	0	1
90	0	1
91	0	1
92	0	1
94	0	1
95	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	90	2	0	0.00
IF	65	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	46	8	0	0.00
CONT_ASSIGN	87	1	0	0.00
ALWAYS	90	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	0	1
47	0	1
48	0	1
50	0	1
51	0	1
52	0	1
53	0	1
54	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
87	0	1
90	0	1
91	0	1
92	0	1
94	0	1
95	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	90	2	0	0.00
IF	65	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	60	8	0	0.00
CONT_ASSIGN	87	1	0	0.00
ALWAYS	90	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	0	1
61	0	1
62	0	1
64	0	1
65	0	1
66	0	1
67	0	1
68	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
87	0	1
90	0	1
91	0	1
92	0	1
94	0	1
95	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	90	2	0	0.00
IF	65	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	60	8	0	0.00
CONT_ASSIGN	87	1	0	0.00
ALWAYS	90	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	0	1
61	0	1
62	0	1
64	0	1
65	0	1
66	0	1
67	0	1
68	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
87	0	1
90	0	1
91	0	1
92	0	1
94	0	1
95	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	0	0.00
IF	90	2	0	0.00
IF	65	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	1	Not Covered
1	0	Not Covered
0	-	Excluded		VC_COV_UNR

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	60	8	0	0.00
CONT_ASSIGN	87	1	0	0.00
ALWAYS	90	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	0	1
61	0	1
62	0	1
64	0	1
65	0	1
66	0	1
67	0	1
68	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
87	0	1
90	0	1
91	0	1
92	0	1
94	0	1
95	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	90	2	0	0.00
IF	65	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	60	8	0	0.00
CONT_ASSIGN	87	1	0	0.00
ALWAYS	90	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	0	1
61	0	1
62	0	1
64	0	1
65	0	1
66	0	1
67	0	1
68	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
87	0	1
90	0	1
91	0	1
92	0	1
94	0	1
95	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	90	2	0	0.00
IF	65	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	60	8	0	0.00
CONT_ASSIGN	87	1	0	0.00
ALWAYS	90	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	0	1
61	0	1
62	0	1
64	0	1
65	0	1
66	0	1
67	0	1
68	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
87	0	1
90	0	1
91	0	1
92	0	1
94	0	1
95	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	90	2	0	0.00
IF	65	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	60	8	0	0.00
CONT_ASSIGN	87	1	0	0.00
ALWAYS	90	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	0	1
61	0	1
62	0	1
64	0	1
65	0	1
66	0	1
67	0	1
68	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
87	0	1
90	0	1
91	0	1
92	0	1
94	0	1
95	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	90	2	0	0.00
IF	65	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered