Unified Coverage Report :: Module Instance :: tb.dut.u_scrmbl_mtx

Module Instance : tb.dut.u_scrmbl_mtx

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.74	0.00	0.00	30.95		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_scrmbl_mtx

	Line No.	Total	Covered	Percent
TOTAL		192	0	0.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	128	1	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	148	0	0
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	0	0
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	160	0	0
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	164	1	0	0.00
CONT_ASSIGN	171	1	0	0.00
CONT_ASSIGN	180	1	0	0.00
CONT_ASSIGN	182	1	0	0.00
CONT_ASSIGN	183	1	0	0.00
ALWAYS	191	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	0	14
118	0	14
122	0	14
126		unreachable
128	0	14
138	0	2
148	0	14(1 unreachable)
150	0	14(1 unreachable)
151	0	14(1 unreachable)
155	0	15
156	0	15
160	0	14(1 unreachable)
161	0	15
163	0	11(4 unreachable)
164	0	15
171	0	1
180	0	1
182	0	1
183	0	1
191	0	1
192	0	1
194	0	1

---

Cond Coverage for Instance : tb.dut.u_scrmbl_mtx

	Total	Covered	Percent
Conditions	362	0	0.00
Logical	362	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR
1	1	Excluded		vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR
1	1	Excluded		vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR
1	1	Excluded		vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR
1	1	Excluded		vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR

 LINE       118
 EXPRESSION (req_i[4] & gen_normal_case.prio_mask_q[4])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR
1	1	Excluded		vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR

 LINE       118
 EXPRESSION (req_i[5] & gen_normal_case.prio_mask_q[5])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       118
 EXPRESSION (req_i[6] & gen_normal_case.prio_mask_q[6])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       118
 EXPRESSION (req_i[7] & gen_normal_case.prio_mask_q[7])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       118
 EXPRESSION (req_i[8] & gen_normal_case.prio_mask_q[8])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       118
 EXPRESSION (req_i[9] & gen_normal_case.prio_mask_q[9])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       118
 EXPRESSION (req_i[10] & gen_normal_case.prio_mask_q[10])
             ----1----   ---------------2---------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR
1	1	Excluded		vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR

 LINE       118
 EXPRESSION (req_i[11] & gen_normal_case.prio_mask_q[11])
             ----1----   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       118
 EXPRESSION (req_i[12] & gen_normal_case.prio_mask_q[12])
             ----1----   ---------------2---------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR
1	1	Excluded		vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR

 LINE       118
 EXPRESSION (req_i[13] & gen_normal_case.prio_mask_q[13])
             ----1----   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Excluded		vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR
1	1	1	Unreachable

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Excluded		vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR
1	1	1	Unreachable

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Excluded		vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR
1	1	1	Unreachable

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Excluded		vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR
1	1	1	Unreachable

 LINE       126
 EXPRESSION (req_i[4] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Excluded		vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR
1	1	1	Unreachable

 LINE       126
 EXPRESSION (req_i[5] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Not Covered
1	1	1	Unreachable

 LINE       126
 EXPRESSION (req_i[6] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Not Covered
1	1	1	Unreachable

 LINE       126
 EXPRESSION (req_i[7] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Not Covered
1	1	1	Unreachable

 LINE       126
 EXPRESSION (req_i[8] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Not Covered
1	1	1	Unreachable

 LINE       126
 EXPRESSION (req_i[9] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Not Covered
1	1	1	Unreachable

 LINE       126
 EXPRESSION (req_i[10] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ready_i)
             ----1----   -----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Excluded		vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR
1	1	1	Unreachable

 LINE       126
 EXPRESSION (req_i[11] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] & ready_i)
             ----1----   -----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Not Covered
1	1	1	Unreachable

 LINE       126
 EXPRESSION (req_i[12] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ready_i)
             ----1----   -----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Excluded		vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR
1	1	1	Unreachable

 LINE       126
 EXPRESSION (req_i[13] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ready_i)
             ----1----   -----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Not Covered
1	1	1	Unreachable

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Unreachable
1	1	Excluded		vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Unreachable
1	1	Excluded		vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Unreachable
1	1	Excluded		vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Unreachable
1	1	Excluded		vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[4])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Unreachable
1	1	Excluded		vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[5])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=4,offset=5:vcs_gen_end:VC_COV_UNR

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[6])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[7])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[8])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[9])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[10])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ((~ready_i)))
                 -----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Unreachable
1	1	Excluded		vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[11])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] & ((~ready_i)))
                 -----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[12])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ((~ready_i)))
                 -----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Unreachable
1	1	Excluded		vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[13])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR
0	1	Not Covered
1	0	Not Covered

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i)))
                 -----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
0	1	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1]))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR
0	1	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Not Covered
1	1	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1]))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1]))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1]))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR
0	1	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Not Covered
1	1	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1]))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR
0	1	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR
1	0	Not Covered
1	1	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1]))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR
0	1	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[3].C1]))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[3].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[4].C1]))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[4].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1]))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR
0	1	Excluded		vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1]))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR
0	1	Excluded		vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[7].C1]))

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Not Covered

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[7].C1])

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Not Covered

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Unreachable

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])

-1-	Status	Tests	Exclude Annotation
0	Excluded		vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR
1	Not Covered

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Not Covered

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Not Covered
1	1	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR
1	1	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR
1	1	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR
1	1	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR
1	0	Not Covered
1	1	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR
1	0	Not Covered
1	1	Excluded		vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR
1	0	Not Covered
1	1	Excluded		vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Not Covered

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
1	1	Not Covered

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR
1	1	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR
1	1	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR
1	1	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR
1	1	Not Covered

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR
1	1	Not Covered

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR
1	1	Not Covered

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Not Covered
1	0	Excluded		vcs_gen_start:level=2,offset=1:vcs_gen_end:VC_COV_UNR

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR
1	0	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR
1	0	Not Covered

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.u_scrmbl_mtx

	Line No.	Total	Covered	Percent
Branches		74	0	0.00
TERNARY	155	2	0	0.00
TERNARY	156	2	0	0.00
TERNARY	155	1	0	0.00
TERNARY	156	1	0	0.00
TERNARY	155	2	0	0.00
TERNARY	156	2	0	0.00
TERNARY	155	1	0	0.00
TERNARY	156	1	0	0.00
TERNARY	155	2	0	0.00
TERNARY	156	2	0	0.00
TERNARY	155	2	0	0.00
TERNARY	156	2	0	0.00
TERNARY	155	2	0	0.00
TERNARY	156	2	0	0.00
TERNARY	155	1	0	0.00
TERNARY	156	1	0	0.00
TERNARY	155	1	0	0.00
TERNARY	156	1	0	0.00
TERNARY	155	1	0	0.00
TERNARY	156	1	0	0.00
TERNARY	155	2	0	0.00
TERNARY	156	2	0	0.00
TERNARY	155	2	0	0.00
TERNARY	156	2	0	0.00
TERNARY	155	1	0	0.00
TERNARY	156	1	0	0.00
TERNARY	155	1	0	0.00
TERNARY	156	1	0	0.00
TERNARY	155	1	0	0.00
TERNARY	156	1	0	0.00
TERNARY	128	2	0	0.00
TERNARY	128	2	0	0.00
TERNARY	128	2	0	0.00
TERNARY	128	2	0	0.00
TERNARY	128	2	0	0.00
TERNARY	128	2	0	0.00
TERNARY	128	2	0	0.00
TERNARY	128	2	0	0.00
TERNARY	128	2	0	0.00
TERNARY	128	2	0	0.00
TERNARY	128	2	0	0.00
TERNARY	128	2	0	0.00
TERNARY	128	2	0	0.00
TERNARY	128	2	0	0.00
IF	191	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered