Unified Coverage Report :: Module :: tlul_err_resp

Module : tlul_err_resp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_lc_gate.u_tlul_err_resp	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_tlul_lc_gate.u_tlul_err_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_tlul_lc_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_err_resp

	Line No.	Total	Covered	Percent
TOTAL		21	0	0.00
ALWAYS	34	14	0	0.00
CONT_ASSIGN	51	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	53	1	0	0.00
CONT_ASSIGN	55	1	0	0.00
CONT_ASSIGN	58	1	0	0.00
CONT_ASSIGN	59	1	0	0.00
CONT_ASSIGN	65	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
35	0	1
36	0	1
37	0	1
38	0	1
39	0	1
40	0	1
41	0	1
42	0	1
43	0	1
44	0	1
45	0	1
46	0	1
47	0	1
			==> MISSING_ELSE
51	0	1
52	0	1
53	0	1
55	0	1
58	0	1
59	0	1
65	0	1

---

Cond Coverage for Module : tlul_err_resp

	Total	Covered	Percent
Conditions	10	0	0.00
Logical	10	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
             -------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       42
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : tlul_err_resp

	Line No.	Total	Covered	Percent
Branches		6	0	0.00
TERNARY	59	2	0	0.00
IF	34	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	59	((err_opcode == Get)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	34	if ((!rst_ni))
-2-:	40	if ((err_rsp_pending && tl_h_i.d_ready))
-3-:	42	if ((tl_h_i.a_valid && tl_h_o_int.a_ready))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered