Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4390063	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2484758

1

T1

7

T2

166

T3

289

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5789886	1			T1	4		T2	275		T3	749
values[0x0]	507633	1			T1	9		T2	98		T3	43
values[0x1]	577302	1			T1	6		T2	83		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3232549	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3642272

1

T1

10

T2

239

T3

444

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23330	1			T2	1		T6	7		T11	23
valid_sources[0x01]	19749	1			T2	1		T6	4		T11	31
valid_sources[0x02]	18530	1			T2	7		T6	9		T11	29
valid_sources[0x03]	48239	1			T6	9		T11	9		T13	2
valid_sources[0x04]	22612	1			T2	2		T6	5		T11	6
valid_sources[0x05]	33921	1			T2	2		T6	8		T12	4
valid_sources[0x06]	19042	1			T2	6		T3	3		T6	15
valid_sources[0x07]	22005	1			T3	1		T6	8		T11	9
valid_sources[0x08]	34591	1			T6	12		T11	15		T12	13
valid_sources[0x09]	26536	1			T2	3		T6	19		T11	19
valid_sources[0x0a]	22323	1			T6	9		T11	11		T12	21
valid_sources[0x0b]	25088	1			T6	13		T11	38		T12	18
valid_sources[0x0c]	19060	1			T6	32		T11	15		T12	17
valid_sources[0x0d]	19078	1			T2	3		T6	25		T11	9
valid_sources[0x0e]	30348	1			T2	5		T6	13		T11	27
valid_sources[0x0f]	22455	1			T6	14		T12	9		T13	1
valid_sources[0x10]	89854	1			T6	20		T11	11		T12	14
valid_sources[0x11]	19731	1			T2	1		T3	3		T6	4
valid_sources[0x12]	22251	1			T2	3		T6	5		T11	1
valid_sources[0x13]	19583	1			T2	1		T3	9		T6	6
valid_sources[0x14]	32957	1			T2	2		T3	4		T6	3
valid_sources[0x15]	20226	1			T2	5		T6	17		T11	86
valid_sources[0x16]	27470	1			T6	8		T11	8		T12	14
valid_sources[0x17]	21837	1			T6	23		T11	5		T12	20
valid_sources[0x18]	18431	1			T6	13		T11	56		T12	39
valid_sources[0x19]	29612	1			T2	1		T6	18		T12	35
valid_sources[0x1a]	23151	1			T1	19		T11	25		T12	12
valid_sources[0x1b]	18985	1			T2	7		T6	10		T11	25
valid_sources[0x1c]	29304	1			T6	16		T11	12		T12	14
valid_sources[0x1d]	19259	1			T2	5		T6	13		T11	6
valid_sources[0x1e]	22018	1			T2	2		T6	4		T11	12
valid_sources[0x1f]	38448	1			T2	2		T6	4		T11	2
valid_sources[0x20]	19622	1			T2	2		T6	5		T12	42
valid_sources[0x21]	52664	1			T6	12		T12	8		T13	3
valid_sources[0x22]	21912	1			T2	4		T6	3		T11	16
valid_sources[0x23]	66940	1			T2	2		T6	7		T11	24
valid_sources[0x24]	23569	1			T2	2		T6	1		T11	8
valid_sources[0x25]	18795	1			T2	2		T3	31		T6	11
valid_sources[0x26]	19756	1			T2	6		T6	16		T11	11
valid_sources[0x27]	21140	1			T2	2		T6	14		T11	19
valid_sources[0x28]	21507	1			T6	11		T11	49		T12	40
valid_sources[0x29]	24868	1			T6	6		T12	13		T13	3
valid_sources[0x2a]	48045	1			T2	1		T3	60		T6	6
valid_sources[0x2b]	24092	1			T2	2		T3	25		T6	5
valid_sources[0x2c]	27916	1			T2	5		T6	14		T11	17
valid_sources[0x2d]	24676	1			T6	1		T12	20		T13	2
valid_sources[0x2e]	19048	1			T6	6		T11	2		T12	28
valid_sources[0x2f]	20856	1			T6	14		T12	40		T104	5
valid_sources[0x30]	23215	1			T2	1		T6	17		T11	7
valid_sources[0x31]	83406	1			T2	5		T6	6		T11	19
valid_sources[0x32]	19558	1			T2	2		T6	9		T11	1
valid_sources[0x33]	19009	1			T2	1		T6	7		T11	58
valid_sources[0x34]	24750	1			T2	12		T6	9		T11	33
valid_sources[0x35]	20374	1			T2	1		T6	8		T11	7
valid_sources[0x36]	23204	1			T2	5		T6	2		T12	7
valid_sources[0x37]	20456	1			T2	2		T6	10		T11	54
valid_sources[0x38]	20019	1			T6	5		T12	40		T104	4
valid_sources[0x39]	28177	1			T2	5		T6	17		T12	29
valid_sources[0x3a]	32822	1			T6	18		T11	28		T12	19
valid_sources[0x3b]	21228	1			T6	9		T11	27		T12	27
valid_sources[0x3c]	21482	1			T2	2		T6	9		T11	25
valid_sources[0x3d]	22518	1			T6	15		T11	2		T12	6
valid_sources[0x3e]	75774	1			T3	54		T6	11		T12	4
valid_sources[0x3f]	32542	1			T2	4		T6	5		T11	3
valid_sources[0x40]	20217	1			T2	4		T6	5		T11	17
valid_sources[0x41]	21403	1			T6	9		T11	2		T12	22
valid_sources[0x42]	24576	1			T6	5		T11	29		T12	36
valid_sources[0x43]	19025	1			T2	1		T6	7		T12	21
valid_sources[0x44]	23904	1			T2	3		T6	3		T11	26
valid_sources[0x45]	55165	1			T6	29		T12	32		T13	2
valid_sources[0x46]	19228	1			T2	8		T6	12		T11	25
valid_sources[0x47]	22085	1			T2	2		T6	1		T11	35
valid_sources[0x48]	30670	1			T6	8		T11	7		T12	18
valid_sources[0x49]	21291	1			T3	13		T6	5		T11	61
valid_sources[0x4a]	19488	1			T6	6		T11	9		T12	35
valid_sources[0x4b]	117490	1			T6	12		T11	28		T12	16
valid_sources[0x4c]	25133	1			T2	7		T6	15		T11	23
valid_sources[0x4d]	29943	1			T2	6		T6	30		T11	7
valid_sources[0x4e]	20369	1			T6	19		T11	17		T12	7
valid_sources[0x4f]	22117	1			T2	2		T3	30		T6	3
valid_sources[0x50]	24771	1			T6	11		T12	16		T13	5
valid_sources[0x51]	19826	1			T2	4		T6	9		T11	33
valid_sources[0x52]	19309	1			T2	2		T6	16		T11	8
valid_sources[0x53]	25724	1			T2	4		T6	12		T11	40
valid_sources[0x54]	41877	1			T6	1		T11	14		T12	15
valid_sources[0x55]	21156	1			T6	15		T11	17		T12	5
valid_sources[0x56]	20195	1			T11	9		T12	31		T13	5
valid_sources[0x57]	27663	1			T2	1		T6	9		T11	19
valid_sources[0x58]	23277	1			T6	10		T12	23		T127	36
valid_sources[0x59]	34823	1			T2	1		T6	8		T11	5
valid_sources[0x5a]	19113	1			T2	3		T6	4		T11	8
valid_sources[0x5b]	19248	1			T6	10		T11	8		T12	6
valid_sources[0x5c]	19742	1			T6	6		T11	17		T12	25
valid_sources[0x5d]	21616	1			T6	2		T11	49		T12	23
valid_sources[0x5e]	19105	1			T3	54		T6	9		T11	7
valid_sources[0x5f]	19228	1			T2	2		T6	14		T12	21
valid_sources[0x60]	20931	1			T6	6		T11	6		T12	6
valid_sources[0x61]	21384	1			T2	3		T6	10		T11	3
valid_sources[0x62]	23707	1			T2	2		T3	4		T6	14
valid_sources[0x63]	30869	1			T2	3		T6	11		T11	47
valid_sources[0x64]	27515	1			T6	13		T11	16		T12	31
valid_sources[0x65]	18984	1			T2	2		T6	23		T11	3
valid_sources[0x66]	22094	1			T2	1		T6	13		T11	1
valid_sources[0x67]	21485	1			T2	1		T3	9		T6	18
valid_sources[0x68]	18838	1			T2	4		T6	2		T11	19
valid_sources[0x69]	36501	1			T2	3		T6	11		T11	19
valid_sources[0x6a]	22665	1			T2	6		T6	9		T11	27
valid_sources[0x6b]	21791	1			T2	1		T6	3		T12	2
valid_sources[0x6c]	22986	1			T6	12		T11	15		T12	21
valid_sources[0x6d]	23127	1			T2	1		T6	14		T11	36
valid_sources[0x6e]	20054	1			T6	4		T11	8		T12	35
valid_sources[0x6f]	23236	1			T6	21		T11	1		T12	7
valid_sources[0x70]	19581	1			T2	4		T6	8		T11	16
valid_sources[0x71]	21453	1			T4	2216		T6	18		T12	25
valid_sources[0x72]	31321	1			T2	2		T6	13		T11	5
valid_sources[0x73]	21003	1			T2	6		T6	9		T11	24
valid_sources[0x74]	18727	1			T2	1		T6	11		T11	5
valid_sources[0x75]	21009	1			T6	17		T11	9		T12	21
valid_sources[0x76]	24854	1			T2	1		T3	4		T6	12
valid_sources[0x77]	22275	1			T2	2		T6	6		T11	57
valid_sources[0x78]	20274	1			T2	1		T6	17		T11	33
valid_sources[0x79]	33988	1			T2	6		T6	14		T11	12
valid_sources[0x7a]	28011	1			T2	2		T6	9		T12	12
valid_sources[0x7b]	58392	1			T6	11		T11	10		T12	21
valid_sources[0x7c]	19489	1			T2	4		T3	8		T6	6
valid_sources[0x7d]	28788	1			T6	14		T11	41		T12	5
valid_sources[0x7e]	27998	1			T2	1		T6	4		T11	49
valid_sources[0x7f]	19116	1			T2	1		T3	21		T6	13
valid_sources[0x80]	19668	1			T2	3		T6	8		T11	50

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1963742

1

T2

70

T3

257

T4

402

values[0x0]

all_enables

biggest_size

291130

1

T1

5

T2

60

T3

20

values[0x1]

all_enables

biggest_size

229886

1

T1

2

T2

36

T3

12

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26722	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

552938

1

T3

20

T4

120

T5

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	181164	1			T3	10		T4	60		T5	20
values[0x0]	194693	1			T3	6		T4	33		T5	7
values[0x1]	203803	1			T3	4		T4	27		T5	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14264	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

565396

1

T3

20

T4

120

T5

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2153	1			T93	1		T120	3		T108	2
valid_sources[0x01]	2375	1			T93	1		T96	4		T108	1
valid_sources[0x02]	2105	1			T96	1		T108	2		T263	4
valid_sources[0x03]	2321	1			T93	2		T197	1		T155	1
valid_sources[0x04]	2444	1			T37	2		T96	3		T20	1
valid_sources[0x05]	3008	1			T93	1		T37	1		T263	1
valid_sources[0x06]	2088	1			T37	2		T96	1		T263	1
valid_sources[0x07]	2753	1			T37	1		T19	1		T96	1
valid_sources[0x08]	2086	1			T12	1		T37	1		T120	1
valid_sources[0x09]	2080	1			T93	4		T105	40		T37	1
valid_sources[0x0a]	2209	1			T93	3		T96	1		T120	4
valid_sources[0x0b]	2240	1			T12	7		T93	1		T37	1
valid_sources[0x0c]	2090	1			T6	1		T98	1		T19	2
valid_sources[0x0d]	1949	1			T96	2		T8	2		T170	1
valid_sources[0x0e]	2295	1			T12	1		T96	4		T120	1
valid_sources[0x0f]	2221	1			T37	1		T108	4		T263	2
valid_sources[0x10]	2749	1			T19	1		T108	1		T126	1
valid_sources[0x11]	2170	1			T37	1		T119	3		T122	2
valid_sources[0x12]	2378	1			T128	1		T93	1		T19	1
valid_sources[0x13]	2714	1			T12	1		T93	2		T19	2
valid_sources[0x14]	2291	1			T37	1		T19	2		T7	1
valid_sources[0x15]	2010	1			T126	1		T151	1		T149	3
valid_sources[0x16]	2950	1			T93	1		T19	1		T122	2
valid_sources[0x17]	2322	1			T12	1		T93	1		T37	1
valid_sources[0x18]	2264	1			T93	1		T116	1		T19	1
valid_sources[0x19]	2130	1			T120	2		T108	1		T126	2
valid_sources[0x1a]	2094	1			T12	2		T93	3		T37	2
valid_sources[0x1b]	2193	1			T37	1		T108	1		T197	4
valid_sources[0x1c]	2743	1			T93	1		T96	3		T121	1
valid_sources[0x1d]	2371	1			T128	1		T93	3		T19	2
valid_sources[0x1e]	2370	1			T12	2		T128	1		T129	20
valid_sources[0x1f]	2706	1			T93	1		T37	1		T119	2
valid_sources[0x20]	2181	1			T93	1		T122	4		T123	6
valid_sources[0x21]	2028	1			T126	1		T380	1		T156	1
valid_sources[0x22]	2399	1			T3	20		T12	2		T93	1
valid_sources[0x23]	2514	1			T98	13		T120	3		T122	1
valid_sources[0x24]	2134	1			T12	4		T19	1		T121	1
valid_sources[0x25]	2195	1			T93	2		T19	2		T120	2
valid_sources[0x26]	2262	1			T98	9		T120	1		T263	1
valid_sources[0x27]	2326	1			T12	5		T93	1		T19	1
valid_sources[0x28]	2296	1			T12	3		T93	1		T37	3
valid_sources[0x29]	2260	1			T19	1		T96	3		T120	12
valid_sources[0x2a]	2169	1			T128	1		T37	1		T122	1
valid_sources[0x2b]	2169	1			T93	1		T116	2		T108	1
valid_sources[0x2c]	2020	1			T128	1		T93	2		T37	1
valid_sources[0x2d]	2504	1			T93	1		T37	1		T108	1
valid_sources[0x2e]	2951	1			T12	1		T93	1		T37	1
valid_sources[0x2f]	1915	1			T93	4		T37	1		T19	1
valid_sources[0x30]	2086	1			T116	1		T108	2		T122	1
valid_sources[0x31]	2491	1			T122	1		T126	2		T170	1
valid_sources[0x32]	1950	1			T37	4		T155	1		T149	3
valid_sources[0x33]	2200	1			T37	1		T19	1		T123	1
valid_sources[0x34]	2117	1			T37	1		T96	2		T126	1
valid_sources[0x35]	2670	1			T93	1		T7	1		T263	2
valid_sources[0x36]	2518	1			T93	1		T37	1		T96	2
valid_sources[0x37]	1963	1			T93	1		T37	1		T263	2
valid_sources[0x38]	3433	1			T122	2		T151	1		T91	1
valid_sources[0x39]	2025	1			T128	1		T93	1		T120	1
valid_sources[0x3a]	2384	1			T12	1		T93	1		T126	1
valid_sources[0x3b]	2138	1			T93	2		T37	3		T19	2
valid_sources[0x3c]	1990	1			T93	1		T19	1		T119	3
valid_sources[0x3d]	2356	1			T98	12		T19	1		T197	2
valid_sources[0x3e]	2221	1			T37	1		T19	1		T122	1
valid_sources[0x3f]	2308	1			T19	2		T263	1		T126	2
valid_sources[0x40]	2047	1			T93	1		T116	1		T19	1
valid_sources[0x41]	2146	1			T93	2		T119	3		T122	3
valid_sources[0x42]	2768	1			T6	3		T37	2		T96	2
valid_sources[0x43]	2040	1			T37	1		T19	1		T96	2
valid_sources[0x44]	1977	1			T93	1		T20	3		T155	2
valid_sources[0x45]	2030	1			T96	1		T108	1		T197	5
valid_sources[0x46]	2405	1			T93	1		T37	1		T19	1
valid_sources[0x47]	1949	1			T19	1		T108	1		T122	1
valid_sources[0x48]	2600	1			T12	4		T37	1		T19	1
valid_sources[0x49]	1991	1			T93	1		T37	1		T20	2
valid_sources[0x4a]	2070	1			T12	4		T98	1		T96	1
valid_sources[0x4b]	2099	1			T128	1		T93	1		T37	1
valid_sources[0x4c]	2700	1			T93	1		T37	2		T19	1
valid_sources[0x4d]	2300	1			T121	1		T108	1		T122	1
valid_sources[0x4e]	2709	1			T6	1		T93	1		T37	2
valid_sources[0x4f]	2412	1			T93	4		T126	1		T155	1
valid_sources[0x50]	2106	1			T93	4		T37	1		T108	2
valid_sources[0x51]	2086	1			T93	1		T37	1		T118	100
valid_sources[0x52]	2358	1			T93	1		T37	1		T19	1
valid_sources[0x53]	2035	1			T12	4		T93	1		T197	1
valid_sources[0x54]	1818	1			T93	1		T121	1		T123	5
valid_sources[0x55]	2040	1			T37	1		T126	1		T155	1
valid_sources[0x56]	2046	1			T6	1		T12	1		T93	1
valid_sources[0x57]	2478	1			T12	1		T93	1		T122	1
valid_sources[0x58]	2072	1			T98	2		T128	1		T37	1
valid_sources[0x59]	2508	1			T37	1		T19	1		T122	3
valid_sources[0x5a]	1911	1			T37	1		T19	1		T96	1
valid_sources[0x5b]	2064	1			T12	3		T37	2		T122	1
valid_sources[0x5c]	2313	1			T12	1		T93	2		T19	1
valid_sources[0x5d]	1924	1			T93	1		T96	1		T52	8
valid_sources[0x5e]	2135	1			T12	3		T128	1		T93	1
valid_sources[0x5f]	2170	1			T98	2		T93	1		T37	1
valid_sources[0x60]	2239	1			T128	1		T93	1		T37	1
valid_sources[0x61]	2236	1			T93	1		T19	1		T120	1
valid_sources[0x62]	2303	1			T12	3		T93	2		T19	1
valid_sources[0x63]	2212	1			T93	2		T96	1		T126	1
valid_sources[0x64]	1927	1			T96	2		T120	15		T121	1
valid_sources[0x65]	2554	1			T96	3		T120	1		T122	1
valid_sources[0x66]	2038	1			T17	100		T98	7		T93	2
valid_sources[0x67]	2825	1			T93	2		T96	1		T122	1
valid_sources[0x68]	2167	1			T93	3		T37	3		T19	2
valid_sources[0x69]	2482	1			T93	2		T37	3		T263	1
valid_sources[0x6a]	2195	1			T6	2		T12	3		T93	4
valid_sources[0x6b]	2311	1			T12	4		T122	1		T263	4
valid_sources[0x6c]	2642	1			T6	1		T121	2		T108	1
valid_sources[0x6d]	2358	1			T6	1		T96	1		T120	6
valid_sources[0x6e]	2287	1			T37	1		T121	1		T108	1
valid_sources[0x6f]	2315	1			T93	1		T96	3		T120	6
valid_sources[0x70]	2056	1			T12	2		T37	2		T19	4
valid_sources[0x71]	2101	1			T91	3		T139	3		T131	1
valid_sources[0x72]	2094	1			T37	1		T19	1		T96	2
valid_sources[0x73]	1922	1			T93	1		T263	2		T126	1
valid_sources[0x74]	2849	1			T93	3		T197	3		T263	5
valid_sources[0x75]	2472	1			T93	1		T96	2		T126	2
valid_sources[0x76]	2092	1			T93	1		T37	1		T108	1
valid_sources[0x77]	2497	1			T19	1		T96	9		T108	1
valid_sources[0x78]	2342	1			T93	2		T37	1		T19	1
valid_sources[0x79]	2716	1			T93	1		T37	1		T122	2
valid_sources[0x7a]	2820	1			T19	1		T96	2		T122	1
valid_sources[0x7b]	2538	1			T6	1		T93	1		T19	2
valid_sources[0x7c]	1884	1			T128	1		T122	1		T447	1
valid_sources[0x7d]	2086	1			T93	1		T37	1		T119	2
valid_sources[0x7e]	2281	1			T93	2		T37	2		T20	2
valid_sources[0x7f]	2449	1			T37	1		T120	1		T108	1
valid_sources[0x80]	2139	1			T93	2		T37	1		T96	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

168702

1

T3

10

T4

60

T5

20

values[0x0]

all_enables

biggest_size

193081

1

T3

6

T4

33

T5

7

values[0x1]

all_enables

biggest_size

191155

1

T3

4

T4

27

T5

13