Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	91185948	396858	0	0
check_regwen_rd_A	91185948	2028	0	0
check_timeout_rd_A	91185948	1168	0	0
check_trigger_regwen_rd_A	91185948	1867	0	0
consistency_check_period_rd_A	91185948	1751	0	0
creator_sw_cfg_read_lock_rd_A	91185948	1095	0	0
direct_access_address_rd_A	91185948	381	0	0
direct_access_wdata_0_rd_A	91185948	36	0	0
direct_access_wdata_1_rd_A	91185948	24	0	0
integrity_check_period_rd_A	91185948	1948	0	0
intr_enable_rd_A	91185948	2530	0	0
owner_sw_cfg_read_lock_rd_A	91185948	1222	0	0
rot_creator_auth_codesign_read_lock_rd_A	91185948	1150	0	0
rot_creator_auth_state_read_lock_rd_A	91185948	1013	0	0
vendor_test_read_lock_rd_A	91185948	1114	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	396858	0	0
T14	313017	8687	0	0
T15	248425	3802	0	0
T16	177944	2924	0	0
T21	0	9527	0	0
T24	0	4514	0	0
T25	0	3921	0	0
T136	420783	0	0	0
T175	0	1587	0	0
T209	89398	0	0	0
T213	0	5281	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T288	0	4764	0	0
T289	0	2650	0	0
T290	78951	0	0	0
T291	38022	0	0	0
T292	4330	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	2028	0	0
T15	248425	39	0	0
T16	177944	31	0	0
T158	14324	0	0	0
T175	0	21	0	0
T209	89398	0	0	0
T214	0	10	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T288	0	28	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T332	0	9	0	0
T333	0	35	0	0
T334	0	25	0	0
T335	0	28	0	0
T336	0	19	0	0
T337	61738	0	0	0
T338	36427	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	1168	0	0
T15	248425	38	0	0
T16	177944	14	0	0
T158	14324	0	0	0
T175	0	21	0	0
T209	89398	0	0	0
T214	0	26	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T288	0	37	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T332	0	14	0	0
T333	0	26	0	0
T334	0	21	0	0
T335	0	12	0	0
T336	0	17	0	0
T337	61738	0	0	0
T338	36427	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	1867	0	0
T15	248425	28	0	0
T16	177944	25	0	0
T158	14324	0	0	0
T175	0	24	0	0
T209	89398	0	0	0
T214	0	20	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T288	0	26	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T332	0	11	0	0
T333	0	33	0	0
T334	0	25	0	0
T335	0	19	0	0
T336	0	13	0	0
T337	61738	0	0	0
T338	36427	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	1751	0	0
T15	248425	46	0	0
T16	177944	22	0	0
T158	14324	0	0	0
T175	0	25	0	0
T209	89398	0	0	0
T214	0	17	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T288	0	16	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T332	0	9	0	0
T333	0	21	0	0
T334	0	19	0	0
T335	0	5	0	0
T336	0	21	0	0
T337	61738	0	0	0
T338	36427	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	1095	0	0
T15	248425	51	0	0
T16	177944	40	0	0
T158	14324	0	0	0
T175	0	21	0	0
T209	89398	0	0	0
T214	0	32	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T288	0	17	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T332	0	20	0	0
T333	0	23	0	0
T334	0	15	0	0
T335	0	3	0	0
T336	0	21	0	0
T337	61738	0	0	0
T338	36427	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	381	0	0
T15	248425	34	0	0
T16	177944	17	0	0
T158	14324	0	0	0
T175	0	15	0	0
T209	89398	0	0	0
T214	0	21	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T288	0	21	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T332	0	11	0	0
T333	0	24	0	0
T334	0	24	0	0
T335	0	7	0	0
T336	0	23	0	0
T337	61738	0	0	0
T338	36427	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	36	0	0
T15	248425	3	0	0
T16	177944	0	0	0
T158	14324	0	0	0
T209	89398	0	0	0
T214	0	7	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T333	0	6	0	0
T334	0	6	0	0
T337	61738	0	0	0
T338	36427	0	0	0
T339	0	6	0	0
T340	0	8	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	24	0	0
T15	248425	5	0	0
T16	177944	0	0	0
T158	14324	0	0	0
T209	89398	0	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T334	0	6	0	0
T337	61738	0	0	0
T338	36427	0	0	0
T339	0	3	0	0
T341	0	10	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	1948	0	0
T15	248425	22	0	0
T16	177944	33	0	0
T158	14324	0	0	0
T175	0	36	0	0
T209	89398	0	0	0
T214	0	17	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T288	0	14	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T332	0	9	0	0
T333	0	5	0	0
T334	0	31	0	0
T335	0	10	0	0
T336	0	29	0	0
T337	61738	0	0	0
T338	36427	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	2530	0	0
T15	248425	68	0	0
T16	177944	18	0	0
T158	14324	0	0	0
T175	0	10	0	0
T209	89398	0	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T288	0	97	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T332	0	16	0	0
T337	61738	0	0	0
T338	36427	0	0	0
T342	0	15	0	0
T343	0	12	0	0
T344	0	16	0	0
T345	0	14	0	0
T346	0	31	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	1222	0	0
T15	248425	36	0	0
T16	177944	21	0	0
T158	14324	0	0	0
T175	0	25	0	0
T209	89398	0	0	0
T214	0	30	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T288	0	34	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T333	0	26	0	0
T334	0	25	0	0
T335	0	10	0	0
T336	0	18	0	0
T337	61738	0	0	0
T338	36427	0	0	0
T341	0	53	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	1150	0	0
T15	248425	45	0	0
T16	177944	33	0	0
T158	14324	0	0	0
T175	0	16	0	0
T209	89398	0	0	0
T214	0	9	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T288	0	21	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T332	0	13	0	0
T333	0	16	0	0
T334	0	32	0	0
T335	0	17	0	0
T336	0	26	0	0
T337	61738	0	0	0
T338	36427	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	1013	0	0
T15	248425	26	0	0
T16	177944	24	0	0
T158	14324	0	0	0
T175	0	21	0	0
T209	89398	0	0	0
T214	0	14	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T288	0	11	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T332	0	4	0	0
T333	0	22	0	0
T334	0	19	0	0
T335	0	8	0	0
T336	0	18	0	0
T337	61738	0	0	0
T338	36427	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91185948	1114	0	0
T15	248425	42	0	0
T16	177944	17	0	0
T158	14324	0	0	0
T175	0	18	0	0
T209	89398	0	0	0
T214	0	20	0	0
T264	26010	0	0	0
T274	43949	0	0	0
T288	0	30	0	0
T291	38022	0	0	0
T292	4330	0	0	0
T332	0	14	0	0
T333	0	38	0	0
T334	0	20	0	0
T335	0	1	0	0
T336	0	22	0	0
T337	61738	0	0	0
T338	36427	0	0	0