Module Definition
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Module : otp_ctrl_prim_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.49 100.00 97.98 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.32 91.84 99.74 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.45 97.27 100.00 100.00 100.00 100.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_chk 100.00 100.00 100.00 100.00
u_csr0_field0 100.00 100.00 100.00 100.00
u_csr0_field1 100.00 100.00 100.00 100.00
u_csr0_field2 100.00 100.00 100.00 100.00
u_csr0_field3 100.00 100.00 100.00 100.00
u_csr0_field4 100.00 100.00 100.00 100.00
u_csr1_field0 100.00 100.00 100.00 100.00
u_csr1_field1 100.00 100.00 100.00 100.00
u_csr1_field2 100.00 100.00 100.00 100.00
u_csr1_field3 100.00 100.00 100.00 100.00
u_csr1_field4 100.00 100.00 100.00 100.00
u_csr2 100.00 100.00 100.00 100.00
u_csr3_field0 100.00 100.00 100.00 100.00
u_csr3_field1 100.00 100.00 100.00 100.00
u_csr3_field2 100.00 100.00 100.00 100.00
u_csr3_field3 87.50 62.50 100.00 100.00
u_csr3_field4 87.50 62.50 100.00 100.00
u_csr3_field5 87.50 62.50 100.00 100.00
u_csr3_field6 87.50 62.50 100.00 100.00
u_csr3_field7 87.50 62.50 100.00 100.00
u_csr3_field8 87.50 62.50 100.00 100.00
u_csr4_field0 100.00 100.00 100.00 100.00
u_csr4_field1 100.00 100.00 100.00 100.00
u_csr4_field2 100.00 100.00 100.00 100.00
u_csr4_field3 100.00 100.00 100.00 100.00
u_csr5_field0 100.00 100.00 100.00 100.00
u_csr5_field1 100.00 100.00 100.00 100.00
u_csr5_field2 87.50 62.50 100.00 100.00
u_csr5_field3 87.50 62.50 100.00 100.00
u_csr5_field4 87.50 62.50 100.00 100.00
u_csr5_field5 87.50 62.50 100.00 100.00
u_csr5_field6 100.00 100.00 100.00 100.00
u_csr6_field0 100.00 100.00 100.00 100.00
u_csr6_field1 100.00 100.00 100.00 100.00
u_csr6_field2 100.00 100.00 100.00 100.00
u_csr6_field3 100.00 100.00 100.00 100.00
u_csr7_field0 87.50 62.50 100.00 100.00
u_csr7_field1 87.50 62.50 100.00 100.00
u_csr7_field2 87.50 62.50 100.00 100.00
u_csr7_field3 87.50 62.50 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.97 97.14 98.75 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00

Line Coverage for Module : otp_ctrl_prim_reg_top
Line No.TotalCoveredPercent
TOTAL104104100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
ALWAYS126899100.00
CONT_ASSIGN127911100.00
ALWAYS128311100.00
CONT_ASSIGN129511100.00
CONT_ASSIGN129711100.00
CONT_ASSIGN129911100.00
CONT_ASSIGN130111100.00
CONT_ASSIGN130311100.00
CONT_ASSIGN130511100.00
CONT_ASSIGN130611100.00
CONT_ASSIGN130811100.00
CONT_ASSIGN131011100.00
CONT_ASSIGN131211100.00
CONT_ASSIGN131411100.00
CONT_ASSIGN131611100.00
CONT_ASSIGN131711100.00
CONT_ASSIGN131911100.00
CONT_ASSIGN132011100.00
CONT_ASSIGN132211100.00
CONT_ASSIGN132411100.00
CONT_ASSIGN132611100.00
CONT_ASSIGN132711100.00
CONT_ASSIGN132911100.00
CONT_ASSIGN133111100.00
CONT_ASSIGN133311100.00
CONT_ASSIGN133511100.00
CONT_ASSIGN133611100.00
CONT_ASSIGN133811100.00
CONT_ASSIGN134011100.00
CONT_ASSIGN134211100.00
CONT_ASSIGN134311100.00
CONT_ASSIGN134511100.00
CONT_ASSIGN134711100.00
CONT_ASSIGN134911100.00
CONT_ASSIGN135111100.00
ALWAYS135599100.00
ALWAYS13684141100.00
CONT_ASSIGN144400
CONT_ASSIGN145211100.00
CONT_ASSIGN145311100.00


67                        always_ff @(posedge clk_i or negedge rst_ni) begin
68         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
69         1/1                err_q <= '0;
           Tests:       T1 T2 T3 
70         1/1              end else if (intg_err || reg_we_err) begin
           Tests:       T1 T2 T3 
71         1/1                err_q <= 1'b1;
           Tests:       T26 T27 T28 
72                          end
                        MISSING_ELSE
73                        end
74                      
75                        // integrity error output is permanent and should be used for alert generation
76                        // register errors are transactional
77         1/1            assign intg_err_o = err_q | intg_err | reg_we_err;
           Tests:       T1 T2 T3 
78                      
79                        // outgoing integrity generation
80                        tlul_pkg::tl_d2h_t tl_o_pre;
81                        tlul_rsp_intg_gen #(
82                          .EnableRspIntgGen(1),
83                          .EnableDataIntgGen(1)
84                        ) u_rsp_intg_gen (
85                          .tl_i(tl_o_pre),
86                          .tl_o(tl_o)
87                        );
88                      
89         1/1            assign tl_reg_h2d = tl_i;
           Tests:       T1 T2 T3 
90         1/1            assign tl_o_pre   = tl_reg_d2h;
           Tests:       T1 T2 T3 
91                      
92                        tlul_adapter_reg #(
93                          .RegAw(AW),
94                          .RegDw(DW),
95                          .EnableDataIntgGen(0)
96                        ) u_reg_if (
97                          .clk_i  (clk_i),
98                          .rst_ni (rst_ni),
99                      
100                         .tl_i (tl_reg_h2d),
101                         .tl_o (tl_reg_d2h),
102                     
103                         .en_ifetch_i(prim_mubi_pkg::MuBi4False),
104                         .intg_error_o(),
105                     
106                         .we_o    (reg_we),
107                         .re_o    (reg_re),
108                         .addr_o  (reg_addr),
109                         .wdata_o (reg_wdata),
110                         .be_o    (reg_be),
111                         .busy_i  (reg_busy),
112                         .rdata_i (reg_rdata),
113                         .error_i (reg_error)
114                       );
115                     
116                       // cdc oversampling signals
117                     
118        1/1            assign reg_rdata = reg_rdata_next ;
           Tests:       T1 T2 T3 
119        1/1            assign reg_error = addrmiss | wr_err | intg_err;
           Tests:       T1 T2 T3 
120                     
121                       // Define SW related signals
122                       // Format: <reg>_<field>_{wd|we|qs}
123                       //        or <reg>_{wd|we|qs} if field == 1 or 0
124                       logic csr0_we;
125                       logic csr0_field0_qs;
126                       logic csr0_field0_wd;
127                       logic csr0_field1_qs;
128                       logic csr0_field1_wd;
129                       logic csr0_field2_qs;
130                       logic csr0_field2_wd;
131                       logic [9:0] csr0_field3_qs;
132                       logic [9:0] csr0_field3_wd;
133                       logic [10:0] csr0_field4_qs;
134                       logic [10:0] csr0_field4_wd;
135                       logic csr1_we;
136                       logic [6:0] csr1_field0_qs;
137                       logic [6:0] csr1_field0_wd;
138                       logic csr1_field1_qs;
139                       logic csr1_field1_wd;
140                       logic [6:0] csr1_field2_qs;
141                       logic [6:0] csr1_field2_wd;
142                       logic csr1_field3_qs;
143                       logic csr1_field3_wd;
144                       logic [15:0] csr1_field4_qs;
145                       logic [15:0] csr1_field4_wd;
146                       logic csr2_we;
147                       logic csr2_qs;
148                       logic csr2_wd;
149                       logic csr3_we;
150                       logic [2:0] csr3_field0_qs;
151                       logic [2:0] csr3_field0_wd;
152                       logic [9:0] csr3_field1_qs;
153                       logic [9:0] csr3_field1_wd;
154                       logic csr3_field2_qs;
155                       logic csr3_field2_wd;
156                       logic csr3_field3_qs;
157                       logic csr3_field4_qs;
158                       logic csr3_field5_qs;
159                       logic csr3_field6_qs;
160                       logic csr3_field7_qs;
161                       logic csr3_field8_qs;
162                       logic csr4_we;
163                       logic [9:0] csr4_field0_qs;
164                       logic [9:0] csr4_field0_wd;
165                       logic csr4_field1_qs;
166                       logic csr4_field1_wd;
167                       logic csr4_field2_qs;
168                       logic csr4_field2_wd;
169                       logic csr4_field3_qs;
170                       logic csr4_field3_wd;
171                       logic csr5_we;
172                       logic [5:0] csr5_field0_qs;
173                       logic [5:0] csr5_field0_wd;
174                       logic [1:0] csr5_field1_qs;
175                       logic [1:0] csr5_field1_wd;
176                       logic csr5_field2_qs;
177                       logic [2:0] csr5_field3_qs;
178                       logic csr5_field4_qs;
179                       logic csr5_field5_qs;
180                       logic [15:0] csr5_field6_qs;
181                       logic [15:0] csr5_field6_wd;
182                       logic csr6_we;
183                       logic [9:0] csr6_field0_qs;
184                       logic [9:0] csr6_field0_wd;
185                       logic csr6_field1_qs;
186                       logic csr6_field1_wd;
187                       logic csr6_field2_qs;
188                       logic csr6_field2_wd;
189                       logic [15:0] csr6_field3_qs;
190                       logic [15:0] csr6_field3_wd;
191                       logic [5:0] csr7_field0_qs;
192                       logic [2:0] csr7_field1_qs;
193                       logic csr7_field2_qs;
194                       logic csr7_field3_qs;
195                     
196                       // Register instances
197                       // R[csr0]: V(False)
198                       //   F[field0]: 0:0
199                       prim_subreg #(
200                         .DW      (1),
201                         .SwAccess(prim_subreg_pkg::SwAccessRW),
202                         .RESVAL  (1'h0),
203                         .Mubi    (1'b0)
204                       ) u_csr0_field0 (
205                         .clk_i   (clk_i),
206                         .rst_ni  (rst_ni),
207                     
208                         // from register interface
209                         .we     (csr0_we),
210                         .wd     (csr0_field0_wd),
211                     
212                         // from internal hardware
213                         .de     (1'b0),
214                         .d      ('0),
215                     
216                         // to internal hardware
217                         .qe     (),
218                         .q      (reg2hw.csr0.field0.q),
219                         .ds     (),
220                     
221                         // to register interface (read)
222                         .qs     (csr0_field0_qs)
223                       );
224                     
225                       //   F[field1]: 1:1
226                       prim_subreg #(
227                         .DW      (1),
228                         .SwAccess(prim_subreg_pkg::SwAccessRW),
229                         .RESVAL  (1'h0),
230                         .Mubi    (1'b0)
231                       ) u_csr0_field1 (
232                         .clk_i   (clk_i),
233                         .rst_ni  (rst_ni),
234                     
235                         // from register interface
236                         .we     (csr0_we),
237                         .wd     (csr0_field1_wd),
238                     
239                         // from internal hardware
240                         .de     (1'b0),
241                         .d      ('0),
242                     
243                         // to internal hardware
244                         .qe     (),
245                         .q      (reg2hw.csr0.field1.q),
246                         .ds     (),
247                     
248                         // to register interface (read)
249                         .qs     (csr0_field1_qs)
250                       );
251                     
252                       //   F[field2]: 2:2
253                       prim_subreg #(
254                         .DW      (1),
255                         .SwAccess(prim_subreg_pkg::SwAccessRW),
256                         .RESVAL  (1'h0),
257                         .Mubi    (1'b0)
258                       ) u_csr0_field2 (
259                         .clk_i   (clk_i),
260                         .rst_ni  (rst_ni),
261                     
262                         // from register interface
263                         .we     (csr0_we),
264                         .wd     (csr0_field2_wd),
265                     
266                         // from internal hardware
267                         .de     (1'b0),
268                         .d      ('0),
269                     
270                         // to internal hardware
271                         .qe     (),
272                         .q      (reg2hw.csr0.field2.q),
273                         .ds     (),
274                     
275                         // to register interface (read)
276                         .qs     (csr0_field2_qs)
277                       );
278                     
279                       //   F[field3]: 13:4
280                       prim_subreg #(
281                         .DW      (10),
282                         .SwAccess(prim_subreg_pkg::SwAccessRW),
283                         .RESVAL  (10'h0),
284                         .Mubi    (1'b0)
285                       ) u_csr0_field3 (
286                         .clk_i   (clk_i),
287                         .rst_ni  (rst_ni),
288                     
289                         // from register interface
290                         .we     (csr0_we),
291                         .wd     (csr0_field3_wd),
292                     
293                         // from internal hardware
294                         .de     (1'b0),
295                         .d      ('0),
296                     
297                         // to internal hardware
298                         .qe     (),
299                         .q      (reg2hw.csr0.field3.q),
300                         .ds     (),
301                     
302                         // to register interface (read)
303                         .qs     (csr0_field3_qs)
304                       );
305                     
306                       //   F[field4]: 26:16
307                       prim_subreg #(
308                         .DW      (11),
309                         .SwAccess(prim_subreg_pkg::SwAccessRW),
310                         .RESVAL  (11'h0),
311                         .Mubi    (1'b0)
312                       ) u_csr0_field4 (
313                         .clk_i   (clk_i),
314                         .rst_ni  (rst_ni),
315                     
316                         // from register interface
317                         .we     (csr0_we),
318                         .wd     (csr0_field4_wd),
319                     
320                         // from internal hardware
321                         .de     (1'b0),
322                         .d      ('0),
323                     
324                         // to internal hardware
325                         .qe     (),
326                         .q      (reg2hw.csr0.field4.q),
327                         .ds     (),
328                     
329                         // to register interface (read)
330                         .qs     (csr0_field4_qs)
331                       );
332                     
333                     
334                       // R[csr1]: V(False)
335                       //   F[field0]: 6:0
336                       prim_subreg #(
337                         .DW      (7),
338                         .SwAccess(prim_subreg_pkg::SwAccessRW),
339                         .RESVAL  (7'h0),
340                         .Mubi    (1'b0)
341                       ) u_csr1_field0 (
342                         .clk_i   (clk_i),
343                         .rst_ni  (rst_ni),
344                     
345                         // from register interface
346                         .we     (csr1_we),
347                         .wd     (csr1_field0_wd),
348                     
349                         // from internal hardware
350                         .de     (1'b0),
351                         .d      ('0),
352                     
353                         // to internal hardware
354                         .qe     (),
355                         .q      (reg2hw.csr1.field0.q),
356                         .ds     (),
357                     
358                         // to register interface (read)
359                         .qs     (csr1_field0_qs)
360                       );
361                     
362                       //   F[field1]: 7:7
363                       prim_subreg #(
364                         .DW      (1),
365                         .SwAccess(prim_subreg_pkg::SwAccessRW),
366                         .RESVAL  (1'h0),
367                         .Mubi    (1'b0)
368                       ) u_csr1_field1 (
369                         .clk_i   (clk_i),
370                         .rst_ni  (rst_ni),
371                     
372                         // from register interface
373                         .we     (csr1_we),
374                         .wd     (csr1_field1_wd),
375                     
376                         // from internal hardware
377                         .de     (1'b0),
378                         .d      ('0),
379                     
380                         // to internal hardware
381                         .qe     (),
382                         .q      (reg2hw.csr1.field1.q),
383                         .ds     (),
384                     
385                         // to register interface (read)
386                         .qs     (csr1_field1_qs)
387                       );
388                     
389                       //   F[field2]: 14:8
390                       prim_subreg #(
391                         .DW      (7),
392                         .SwAccess(prim_subreg_pkg::SwAccessRW),
393                         .RESVAL  (7'h0),
394                         .Mubi    (1'b0)
395                       ) u_csr1_field2 (
396                         .clk_i   (clk_i),
397                         .rst_ni  (rst_ni),
398                     
399                         // from register interface
400                         .we     (csr1_we),
401                         .wd     (csr1_field2_wd),
402                     
403                         // from internal hardware
404                         .de     (1'b0),
405                         .d      ('0),
406                     
407                         // to internal hardware
408                         .qe     (),
409                         .q      (reg2hw.csr1.field2.q),
410                         .ds     (),
411                     
412                         // to register interface (read)
413                         .qs     (csr1_field2_qs)
414                       );
415                     
416                       //   F[field3]: 15:15
417                       prim_subreg #(
418                         .DW      (1),
419                         .SwAccess(prim_subreg_pkg::SwAccessRW),
420                         .RESVAL  (1'h0),
421                         .Mubi    (1'b0)
422                       ) u_csr1_field3 (
423                         .clk_i   (clk_i),
424                         .rst_ni  (rst_ni),
425                     
426                         // from register interface
427                         .we     (csr1_we),
428                         .wd     (csr1_field3_wd),
429                     
430                         // from internal hardware
431                         .de     (1'b0),
432                         .d      ('0),
433                     
434                         // to internal hardware
435                         .qe     (),
436                         .q      (reg2hw.csr1.field3.q),
437                         .ds     (),
438                     
439                         // to register interface (read)
440                         .qs     (csr1_field3_qs)
441                       );
442                     
443                       //   F[field4]: 31:16
444                       prim_subreg #(
445                         .DW      (16),
446                         .SwAccess(prim_subreg_pkg::SwAccessRW),
447                         .RESVAL  (16'h0),
448                         .Mubi    (1'b0)
449                       ) u_csr1_field4 (
450                         .clk_i   (clk_i),
451                         .rst_ni  (rst_ni),
452                     
453                         // from register interface
454                         .we     (csr1_we),
455                         .wd     (csr1_field4_wd),
456                     
457                         // from internal hardware
458                         .de     (1'b0),
459                         .d      ('0),
460                     
461                         // to internal hardware
462                         .qe     (),
463                         .q      (reg2hw.csr1.field4.q),
464                         .ds     (),
465                     
466                         // to register interface (read)
467                         .qs     (csr1_field4_qs)
468                       );
469                     
470                     
471                       // R[csr2]: V(False)
472                       prim_subreg #(
473                         .DW      (1),
474                         .SwAccess(prim_subreg_pkg::SwAccessRW),
475                         .RESVAL  (1'h0),
476                         .Mubi    (1'b0)
477                       ) u_csr2 (
478                         .clk_i   (clk_i),
479                         .rst_ni  (rst_ni),
480                     
481                         // from register interface
482                         .we     (csr2_we),
483                         .wd     (csr2_wd),
484                     
485                         // from internal hardware
486                         .de     (1'b0),
487                         .d      ('0),
488                     
489                         // to internal hardware
490                         .qe     (),
491                         .q      (reg2hw.csr2.q),
492                         .ds     (),
493                     
494                         // to register interface (read)
495                         .qs     (csr2_qs)
496                       );
497                     
498                     
499                       // R[csr3]: V(False)
500                       //   F[field0]: 2:0
501                       prim_subreg #(
502                         .DW      (3),
503                         .SwAccess(prim_subreg_pkg::SwAccessW1C),
504                         .RESVAL  (3'h0),
505                         .Mubi    (1'b0)
506                       ) u_csr3_field0 (
507                         .clk_i   (clk_i),
508                         .rst_ni  (rst_ni),
509                     
510                         // from register interface
511                         .we     (csr3_we),
512                         .wd     (csr3_field0_wd),
513                     
514                         // from internal hardware
515                         .de     (hw2reg.csr3.field0.de),
516                         .d      (hw2reg.csr3.field0.d),
517                     
518                         // to internal hardware
519                         .qe     (),
520                         .q      (reg2hw.csr3.field0.q),
521                         .ds     (),
522                     
523                         // to register interface (read)
524                         .qs     (csr3_field0_qs)
525                       );
526                     
527                       //   F[field1]: 13:4
528                       prim_subreg #(
529                         .DW      (10),
530                         .SwAccess(prim_subreg_pkg::SwAccessW1C),
531                         .RESVAL  (10'h0),
532                         .Mubi    (1'b0)
533                       ) u_csr3_field1 (
534                         .clk_i   (clk_i),
535                         .rst_ni  (rst_ni),
536                     
537                         // from register interface
538                         .we     (csr3_we),
539                         .wd     (csr3_field1_wd),
540                     
541                         // from internal hardware
542                         .de     (hw2reg.csr3.field1.de),
543                         .d      (hw2reg.csr3.field1.d),
544                     
545                         // to internal hardware
546                         .qe     (),
547                         .q      (reg2hw.csr3.field1.q),
548                         .ds     (),
549                     
550                         // to register interface (read)
551                         .qs     (csr3_field1_qs)
552                       );
553                     
554                       //   F[field2]: 16:16
555                       prim_subreg #(
556                         .DW      (1),
557                         .SwAccess(prim_subreg_pkg::SwAccessW1C),
558                         .RESVAL  (1'h0),
559                         .Mubi    (1'b0)
560                       ) u_csr3_field2 (
561                         .clk_i   (clk_i),
562                         .rst_ni  (rst_ni),
563                     
564                         // from register interface
565                         .we     (csr3_we),
566                         .wd     (csr3_field2_wd),
567                     
568                         // from internal hardware
569                         .de     (hw2reg.csr3.field2.de),
570                         .d      (hw2reg.csr3.field2.d),
571                     
572                         // to internal hardware
573                         .qe     (),
574                         .q      (reg2hw.csr3.field2.q),
575                         .ds     (),
576                     
577                         // to register interface (read)
578                         .qs     (csr3_field2_qs)
579                       );
580                     
581                       //   F[field3]: 17:17
582                       prim_subreg #(
583                         .DW      (1),
584                         .SwAccess(prim_subreg_pkg::SwAccessRO),
585                         .RESVAL  (1'h0),
586                         .Mubi    (1'b0)
587                       ) u_csr3_field3 (
588                         .clk_i   (clk_i),
589                         .rst_ni  (rst_ni),
590                     
591                         // from register interface
592                         .we     (1'b0),
593                         .wd     ('0),
594                     
595                         // from internal hardware
596                         .de     (hw2reg.csr3.field3.de),
597                         .d      (hw2reg.csr3.field3.d),
598                     
599                         // to internal hardware
600                         .qe     (),
601                         .q      (reg2hw.csr3.field3.q),
602                         .ds     (),
603                     
604                         // to register interface (read)
605                         .qs     (csr3_field3_qs)
606                       );
607                     
608                       //   F[field4]: 18:18
609                       prim_subreg #(
610                         .DW      (1),
611                         .SwAccess(prim_subreg_pkg::SwAccessRO),
612                         .RESVAL  (1'h0),
613                         .Mubi    (1'b0)
614                       ) u_csr3_field4 (
615                         .clk_i   (clk_i),
616                         .rst_ni  (rst_ni),
617                     
618                         // from register interface
619                         .we     (1'b0),
620                         .wd     ('0),
621                     
622                         // from internal hardware
623                         .de     (hw2reg.csr3.field4.de),
624                         .d      (hw2reg.csr3.field4.d),
625                     
626                         // to internal hardware
627                         .qe     (),
628                         .q      (reg2hw.csr3.field4.q),
629                         .ds     (),
630                     
631                         // to register interface (read)
632                         .qs     (csr3_field4_qs)
633                       );
634                     
635                       //   F[field5]: 19:19
636                       prim_subreg #(
637                         .DW      (1),
638                         .SwAccess(prim_subreg_pkg::SwAccessRO),
639                         .RESVAL  (1'h0),
640                         .Mubi    (1'b0)
641                       ) u_csr3_field5 (
642                         .clk_i   (clk_i),
643                         .rst_ni  (rst_ni),
644                     
645                         // from register interface
646                         .we     (1'b0),
647                         .wd     ('0),
648                     
649                         // from internal hardware
650                         .de     (hw2reg.csr3.field5.de),
651                         .d      (hw2reg.csr3.field5.d),
652                     
653                         // to internal hardware
654                         .qe     (),
655                         .q      (reg2hw.csr3.field5.q),
656                         .ds     (),
657                     
658                         // to register interface (read)
659                         .qs     (csr3_field5_qs)
660                       );
661                     
662                       //   F[field6]: 20:20
663                       prim_subreg #(
664                         .DW      (1),
665                         .SwAccess(prim_subreg_pkg::SwAccessRO),
666                         .RESVAL  (1'h0),
667                         .Mubi    (1'b0)
668                       ) u_csr3_field6 (
669                         .clk_i   (clk_i),
670                         .rst_ni  (rst_ni),
671                     
672                         // from register interface
673                         .we     (1'b0),
674                         .wd     ('0),
675                     
676                         // from internal hardware
677                         .de     (hw2reg.csr3.field6.de),
678                         .d      (hw2reg.csr3.field6.d),
679                     
680                         // to internal hardware
681                         .qe     (),
682                         .q      (reg2hw.csr3.field6.q),
683                         .ds     (),
684                     
685                         // to register interface (read)
686                         .qs     (csr3_field6_qs)
687                       );
688                     
689                       //   F[field7]: 21:21
690                       prim_subreg #(
691                         .DW      (1),
692                         .SwAccess(prim_subreg_pkg::SwAccessRO),
693                         .RESVAL  (1'h0),
694                         .Mubi    (1'b0)
695                       ) u_csr3_field7 (
696                         .clk_i   (clk_i),
697                         .rst_ni  (rst_ni),
698                     
699                         // from register interface
700                         .we     (1'b0),
701                         .wd     ('0),
702                     
703                         // from internal hardware
704                         .de     (hw2reg.csr3.field7.de),
705                         .d      (hw2reg.csr3.field7.d),
706                     
707                         // to internal hardware
708                         .qe     (),
709                         .q      (reg2hw.csr3.field7.q),
710                         .ds     (),
711                     
712                         // to register interface (read)
713                         .qs     (csr3_field7_qs)
714                       );
715                     
716                       //   F[field8]: 22:22
717                       prim_subreg #(
718                         .DW      (1),
719                         .SwAccess(prim_subreg_pkg::SwAccessRO),
720                         .RESVAL  (1'h0),
721                         .Mubi    (1'b0)
722                       ) u_csr3_field8 (
723                         .clk_i   (clk_i),
724                         .rst_ni  (rst_ni),
725                     
726                         // from register interface
727                         .we     (1'b0),
728                         .wd     ('0),
729                     
730                         // from internal hardware
731                         .de     (hw2reg.csr3.field8.de),
732                         .d      (hw2reg.csr3.field8.d),
733                     
734                         // to internal hardware
735                         .qe     (),
736                         .q      (reg2hw.csr3.field8.q),
737                         .ds     (),
738                     
739                         // to register interface (read)
740                         .qs     (csr3_field8_qs)
741                       );
742                     
743                     
744                       // R[csr4]: V(False)
745                       //   F[field0]: 9:0
746                       prim_subreg #(
747                         .DW      (10),
748                         .SwAccess(prim_subreg_pkg::SwAccessRW),
749                         .RESVAL  (10'h0),
750                         .Mubi    (1'b0)
751                       ) u_csr4_field0 (
752                         .clk_i   (clk_i),
753                         .rst_ni  (rst_ni),
754                     
755                         // from register interface
756                         .we     (csr4_we),
757                         .wd     (csr4_field0_wd),
758                     
759                         // from internal hardware
760                         .de     (1'b0),
761                         .d      ('0),
762                     
763                         // to internal hardware
764                         .qe     (),
765                         .q      (reg2hw.csr4.field0.q),
766                         .ds     (),
767                     
768                         // to register interface (read)
769                         .qs     (csr4_field0_qs)
770                       );
771                     
772                       //   F[field1]: 12:12
773                       prim_subreg #(
774                         .DW      (1),
775                         .SwAccess(prim_subreg_pkg::SwAccessRW),
776                         .RESVAL  (1'h0),
777                         .Mubi    (1'b0)
778                       ) u_csr4_field1 (
779                         .clk_i   (clk_i),
780                         .rst_ni  (rst_ni),
781                     
782                         // from register interface
783                         .we     (csr4_we),
784                         .wd     (csr4_field1_wd),
785                     
786                         // from internal hardware
787                         .de     (1'b0),
788                         .d      ('0),
789                     
790                         // to internal hardware
791                         .qe     (),
792                         .q      (reg2hw.csr4.field1.q),
793                         .ds     (),
794                     
795                         // to register interface (read)
796                         .qs     (csr4_field1_qs)
797                       );
798                     
799                       //   F[field2]: 13:13
800                       prim_subreg #(
801                         .DW      (1),
802                         .SwAccess(prim_subreg_pkg::SwAccessRW),
803                         .RESVAL  (1'h0),
804                         .Mubi    (1'b0)
805                       ) u_csr4_field2 (
806                         .clk_i   (clk_i),
807                         .rst_ni  (rst_ni),
808                     
809                         // from register interface
810                         .we     (csr4_we),
811                         .wd     (csr4_field2_wd),
812                     
813                         // from internal hardware
814                         .de     (1'b0),
815                         .d      ('0),
816                     
817                         // to internal hardware
818                         .qe     (),
819                         .q      (reg2hw.csr4.field2.q),
820                         .ds     (),
821                     
822                         // to register interface (read)
823                         .qs     (csr4_field2_qs)
824                       );
825                     
826                       //   F[field3]: 14:14
827                       prim_subreg #(
828                         .DW      (1),
829                         .SwAccess(prim_subreg_pkg::SwAccessRW),
830                         .RESVAL  (1'h0),
831                         .Mubi    (1'b0)
832                       ) u_csr4_field3 (
833                         .clk_i   (clk_i),
834                         .rst_ni  (rst_ni),
835                     
836                         // from register interface
837                         .we     (csr4_we),
838                         .wd     (csr4_field3_wd),
839                     
840                         // from internal hardware
841                         .de     (1'b0),
842                         .d      ('0),
843                     
844                         // to internal hardware
845                         .qe     (),
846                         .q      (reg2hw.csr4.field3.q),
847                         .ds     (),
848                     
849                         // to register interface (read)
850                         .qs     (csr4_field3_qs)
851                       );
852                     
853                     
854                       // R[csr5]: V(False)
855                       //   F[field0]: 5:0
856                       prim_subreg #(
857                         .DW      (6),
858                         .SwAccess(prim_subreg_pkg::SwAccessRW),
859                         .RESVAL  (6'h0),
860                         .Mubi    (1'b0)
861                       ) u_csr5_field0 (
862                         .clk_i   (clk_i),
863                         .rst_ni  (rst_ni),
864                     
865                         // from register interface
866                         .we     (csr5_we),
867                         .wd     (csr5_field0_wd),
868                     
869                         // from internal hardware
870                         .de     (hw2reg.csr5.field0.de),
871                         .d      (hw2reg.csr5.field0.d),
872                     
873                         // to internal hardware
874                         .qe     (),
875                         .q      (reg2hw.csr5.field0.q),
876                         .ds     (),
877                     
878                         // to register interface (read)
879                         .qs     (csr5_field0_qs)
880                       );
881                     
882                       //   F[field1]: 7:6
883                       prim_subreg #(
884                         .DW      (2),
885                         .SwAccess(prim_subreg_pkg::SwAccessRW),
886                         .RESVAL  (2'h0),
887                         .Mubi    (1'b0)
888                       ) u_csr5_field1 (
889                         .clk_i   (clk_i),
890                         .rst_ni  (rst_ni),
891                     
892                         // from register interface
893                         .we     (csr5_we),
894                         .wd     (csr5_field1_wd),
895                     
896                         // from internal hardware
897                         .de     (hw2reg.csr5.field1.de),
898                         .d      (hw2reg.csr5.field1.d),
899                     
900                         // to internal hardware
901                         .qe     (),
902                         .q      (reg2hw.csr5.field1.q),
903                         .ds     (),
904                     
905                         // to register interface (read)
906                         .qs     (csr5_field1_qs)
907                       );
908                     
909                       //   F[field2]: 8:8
910                       prim_subreg #(
911                         .DW      (1),
912                         .SwAccess(prim_subreg_pkg::SwAccessRO),
913                         .RESVAL  (1'h0),
914                         .Mubi    (1'b0)
915                       ) u_csr5_field2 (
916                         .clk_i   (clk_i),
917                         .rst_ni  (rst_ni),
918                     
919                         // from register interface
920                         .we     (1'b0),
921                         .wd     ('0),
922                     
923                         // from internal hardware
924                         .de     (hw2reg.csr5.field2.de),
925                         .d      (hw2reg.csr5.field2.d),
926                     
927                         // to internal hardware
928                         .qe     (),
929                         .q      (reg2hw.csr5.field2.q),
930                         .ds     (),
931                     
932                         // to register interface (read)
933                         .qs     (csr5_field2_qs)
934                       );
935                     
936                       //   F[field3]: 11:9
937                       prim_subreg #(
938                         .DW      (3),
939                         .SwAccess(prim_subreg_pkg::SwAccessRO),
940                         .RESVAL  (3'h0),
941                         .Mubi    (1'b0)
942                       ) u_csr5_field3 (
943                         .clk_i   (clk_i),
944                         .rst_ni  (rst_ni),
945                     
946                         // from register interface
947                         .we     (1'b0),
948                         .wd     ('0),
949                     
950                         // from internal hardware
951                         .de     (hw2reg.csr5.field3.de),
952                         .d      (hw2reg.csr5.field3.d),
953                     
954                         // to internal hardware
955                         .qe     (),
956                         .q      (reg2hw.csr5.field3.q),
957                         .ds     (),
958                     
959                         // to register interface (read)
960                         .qs     (csr5_field3_qs)
961                       );
962                     
963                       //   F[field4]: 12:12
964                       prim_subreg #(
965                         .DW      (1),
966                         .SwAccess(prim_subreg_pkg::SwAccessRO),
967                         .RESVAL  (1'h0),
968                         .Mubi    (1'b0)
969                       ) u_csr5_field4 (
970                         .clk_i   (clk_i),
971                         .rst_ni  (rst_ni),
972                     
973                         // from register interface
974                         .we     (1'b0),
975                         .wd     ('0),
976                     
977                         // from internal hardware
978                         .de     (hw2reg.csr5.field4.de),
979                         .d      (hw2reg.csr5.field4.d),
980                     
981                         // to internal hardware
982                         .qe     (),
983                         .q      (reg2hw.csr5.field4.q),
984                         .ds     (),
985                     
986                         // to register interface (read)
987                         .qs     (csr5_field4_qs)
988                       );
989                     
990                       //   F[field5]: 13:13
991                       prim_subreg #(
992                         .DW      (1),
993                         .SwAccess(prim_subreg_pkg::SwAccessRO),
994                         .RESVAL  (1'h0),
995                         .Mubi    (1'b0)
996                       ) u_csr5_field5 (
997                         .clk_i   (clk_i),
998                         .rst_ni  (rst_ni),
999                     
1000                        // from register interface
1001                        .we     (1'b0),
1002                        .wd     ('0),
1003                    
1004                        // from internal hardware
1005                        .de     (hw2reg.csr5.field5.de),
1006                        .d      (hw2reg.csr5.field5.d),
1007                    
1008                        // to internal hardware
1009                        .qe     (),
1010                        .q      (reg2hw.csr5.field5.q),
1011                        .ds     (),
1012                    
1013                        // to register interface (read)
1014                        .qs     (csr5_field5_qs)
1015                      );
1016                    
1017                      //   F[field6]: 31:16
1018                      prim_subreg #(
1019                        .DW      (16),
1020                        .SwAccess(prim_subreg_pkg::SwAccessRW),
1021                        .RESVAL  (16'h0),
1022                        .Mubi    (1'b0)
1023                      ) u_csr5_field6 (
1024                        .clk_i   (clk_i),
1025                        .rst_ni  (rst_ni),
1026                    
1027                        // from register interface
1028                        .we     (csr5_we),
1029                        .wd     (csr5_field6_wd),
1030                    
1031                        // from internal hardware
1032                        .de     (hw2reg.csr5.field6.de),
1033                        .d      (hw2reg.csr5.field6.d),
1034                    
1035                        // to internal hardware
1036                        .qe     (),
1037                        .q      (reg2hw.csr5.field6.q),
1038                        .ds     (),
1039                    
1040                        // to register interface (read)
1041                        .qs     (csr5_field6_qs)
1042                      );
1043                    
1044                    
1045                      // R[csr6]: V(False)
1046                      //   F[field0]: 9:0
1047                      prim_subreg #(
1048                        .DW      (10),
1049                        .SwAccess(prim_subreg_pkg::SwAccessRW),
1050                        .RESVAL  (10'h0),
1051                        .Mubi    (1'b0)
1052                      ) u_csr6_field0 (
1053                        .clk_i   (clk_i),
1054                        .rst_ni  (rst_ni),
1055                    
1056                        // from register interface
1057                        .we     (csr6_we),
1058                        .wd     (csr6_field0_wd),
1059                    
1060                        // from internal hardware
1061                        .de     (1'b0),
1062                        .d      ('0),
1063                    
1064                        // to internal hardware
1065                        .qe     (),
1066                        .q      (reg2hw.csr6.field0.q),
1067                        .ds     (),
1068                    
1069                        // to register interface (read)
1070                        .qs     (csr6_field0_qs)
1071                      );
1072                    
1073                      //   F[field1]: 11:11
1074                      prim_subreg #(
1075                        .DW      (1),
1076                        .SwAccess(prim_subreg_pkg::SwAccessRW),
1077                        .RESVAL  (1'h0),
1078                        .Mubi    (1'b0)
1079                      ) u_csr6_field1 (
1080                        .clk_i   (clk_i),
1081                        .rst_ni  (rst_ni),
1082                    
1083                        // from register interface
1084                        .we     (csr6_we),
1085                        .wd     (csr6_field1_wd),
1086                    
1087                        // from internal hardware
1088                        .de     (1'b0),
1089                        .d      ('0),
1090                    
1091                        // to internal hardware
1092                        .qe     (),
1093                        .q      (reg2hw.csr6.field1.q),
1094                        .ds     (),
1095                    
1096                        // to register interface (read)
1097                        .qs     (csr6_field1_qs)
1098                      );
1099                    
1100                      //   F[field2]: 12:12
1101                      prim_subreg #(
1102                        .DW      (1),
1103                        .SwAccess(prim_subreg_pkg::SwAccessRW),
1104                        .RESVAL  (1'h0),
1105                        .Mubi    (1'b0)
1106                      ) u_csr6_field2 (
1107                        .clk_i   (clk_i),
1108                        .rst_ni  (rst_ni),
1109                    
1110                        // from register interface
1111                        .we     (csr6_we),
1112                        .wd     (csr6_field2_wd),
1113                    
1114                        // from internal hardware
1115                        .de     (1'b0),
1116                        .d      ('0),
1117                    
1118                        // to internal hardware
1119                        .qe     (),
1120                        .q      (reg2hw.csr6.field2.q),
1121                        .ds     (),
1122                    
1123                        // to register interface (read)
1124                        .qs     (csr6_field2_qs)
1125                      );
1126                    
1127                      //   F[field3]: 31:16
1128                      prim_subreg #(
1129                        .DW      (16),
1130                        .SwAccess(prim_subreg_pkg::SwAccessRW),
1131                        .RESVAL  (16'h0),
1132                        .Mubi    (1'b0)
1133                      ) u_csr6_field3 (
1134                        .clk_i   (clk_i),
1135                        .rst_ni  (rst_ni),
1136                    
1137                        // from register interface
1138                        .we     (csr6_we),
1139                        .wd     (csr6_field3_wd),
1140                    
1141                        // from internal hardware
1142                        .de     (1'b0),
1143                        .d      ('0),
1144                    
1145                        // to internal hardware
1146                        .qe     (),
1147                        .q      (reg2hw.csr6.field3.q),
1148                        .ds     (),
1149                    
1150                        // to register interface (read)
1151                        .qs     (csr6_field3_qs)
1152                      );
1153                    
1154                    
1155                      // R[csr7]: V(False)
1156                      //   F[field0]: 5:0
1157                      prim_subreg #(
1158                        .DW      (6),
1159                        .SwAccess(prim_subreg_pkg::SwAccessRO),
1160                        .RESVAL  (6'h0),
1161                        .Mubi    (1'b0)
1162                      ) u_csr7_field0 (
1163                        .clk_i   (clk_i),
1164                        .rst_ni  (rst_ni),
1165                    
1166                        // from register interface
1167                        .we     (1'b0),
1168                        .wd     ('0),
1169                    
1170                        // from internal hardware
1171                        .de     (hw2reg.csr7.field0.de),
1172                        .d      (hw2reg.csr7.field0.d),
1173                    
1174                        // to internal hardware
1175                        .qe     (),
1176                        .q      (reg2hw.csr7.field0.q),
1177                        .ds     (),
1178                    
1179                        // to register interface (read)
1180                        .qs     (csr7_field0_qs)
1181                      );
1182                    
1183                      //   F[field1]: 10:8
1184                      prim_subreg #(
1185                        .DW      (3),
1186                        .SwAccess(prim_subreg_pkg::SwAccessRO),
1187                        .RESVAL  (3'h0),
1188                        .Mubi    (1'b0)
1189                      ) u_csr7_field1 (
1190                        .clk_i   (clk_i),
1191                        .rst_ni  (rst_ni),
1192                    
1193                        // from register interface
1194                        .we     (1'b0),
1195                        .wd     ('0),
1196                    
1197                        // from internal hardware
1198                        .de     (hw2reg.csr7.field1.de),
1199                        .d      (hw2reg.csr7.field1.d),
1200                    
1201                        // to internal hardware
1202                        .qe     (),
1203                        .q      (reg2hw.csr7.field1.q),
1204                        .ds     (),
1205                    
1206                        // to register interface (read)
1207                        .qs     (csr7_field1_qs)
1208                      );
1209                    
1210                      //   F[field2]: 14:14
1211                      prim_subreg #(
1212                        .DW      (1),
1213                        .SwAccess(prim_subreg_pkg::SwAccessRO),
1214                        .RESVAL  (1'h0),
1215                        .Mubi    (1'b0)
1216                      ) u_csr7_field2 (
1217                        .clk_i   (clk_i),
1218                        .rst_ni  (rst_ni),
1219                    
1220                        // from register interface
1221                        .we     (1'b0),
1222                        .wd     ('0),
1223                    
1224                        // from internal hardware
1225                        .de     (hw2reg.csr7.field2.de),
1226                        .d      (hw2reg.csr7.field2.d),
1227                    
1228                        // to internal hardware
1229                        .qe     (),
1230                        .q      (reg2hw.csr7.field2.q),
1231                        .ds     (),
1232                    
1233                        // to register interface (read)
1234                        .qs     (csr7_field2_qs)
1235                      );
1236                    
1237                      //   F[field3]: 15:15
1238                      prim_subreg #(
1239                        .DW      (1),
1240                        .SwAccess(prim_subreg_pkg::SwAccessRO),
1241                        .RESVAL  (1'h0),
1242                        .Mubi    (1'b0)
1243                      ) u_csr7_field3 (
1244                        .clk_i   (clk_i),
1245                        .rst_ni  (rst_ni),
1246                    
1247                        // from register interface
1248                        .we     (1'b0),
1249                        .wd     ('0),
1250                    
1251                        // from internal hardware
1252                        .de     (hw2reg.csr7.field3.de),
1253                        .d      (hw2reg.csr7.field3.d),
1254                    
1255                        // to internal hardware
1256                        .qe     (),
1257                        .q      (reg2hw.csr7.field3.q),
1258                        .ds     (),
1259                    
1260                        // to register interface (read)
1261                        .qs     (csr7_field3_qs)
1262                      );
1263                    
1264                    
1265                    
1266                      logic [7:0] addr_hit;
1267                      always_comb begin
1268       1/1              addr_hit = '0;
           Tests:       T1 T2 T3 
1269       1/1              addr_hit[0] = (reg_addr == OTP_CTRL_CSR0_OFFSET);
           Tests:       T1 T2 T3 
1270       1/1              addr_hit[1] = (reg_addr == OTP_CTRL_CSR1_OFFSET);
           Tests:       T1 T2 T3 
1271       1/1              addr_hit[2] = (reg_addr == OTP_CTRL_CSR2_OFFSET);
           Tests:       T1 T2 T3 
1272       1/1              addr_hit[3] = (reg_addr == OTP_CTRL_CSR3_OFFSET);
           Tests:       T1 T2 T3 
1273       1/1              addr_hit[4] = (reg_addr == OTP_CTRL_CSR4_OFFSET);
           Tests:       T1 T2 T3 
1274       1/1              addr_hit[5] = (reg_addr == OTP_CTRL_CSR5_OFFSET);
           Tests:       T1 T2 T3 
1275       1/1              addr_hit[6] = (reg_addr == OTP_CTRL_CSR6_OFFSET);
           Tests:       T1 T2 T3 
1276       1/1              addr_hit[7] = (reg_addr == OTP_CTRL_CSR7_OFFSET);
           Tests:       T1 T2 T3 
1277                      end
1278                    
1279       1/1            assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
           Tests:       T1 T2 T3 
1280                    
1281                      // Check sub-word write is permitted
1282                      always_comb begin
1283       1/1              wr_err = (reg_we &
           Tests:       T1 T2 T3 
1284                                  ((addr_hit[0] & (|(OTP_CTRL_PRIM_PERMIT[0] & ~reg_be))) |
1285                                   (addr_hit[1] & (|(OTP_CTRL_PRIM_PERMIT[1] & ~reg_be))) |
1286                                   (addr_hit[2] & (|(OTP_CTRL_PRIM_PERMIT[2] & ~reg_be))) |
1287                                   (addr_hit[3] & (|(OTP_CTRL_PRIM_PERMIT[3] & ~reg_be))) |
1288                                   (addr_hit[4] & (|(OTP_CTRL_PRIM_PERMIT[4] & ~reg_be))) |
1289                                   (addr_hit[5] & (|(OTP_CTRL_PRIM_PERMIT[5] & ~reg_be))) |
1290                                   (addr_hit[6] & (|(OTP_CTRL_PRIM_PERMIT[6] & ~reg_be))) |
1291                                   (addr_hit[7] & (|(OTP_CTRL_PRIM_PERMIT[7] & ~reg_be)))));
1292                      end
1293                    
1294                      // Generate write-enables
1295       1/1            assign csr0_we = addr_hit[0] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1296                    
1297       1/1            assign csr0_field0_wd = reg_wdata[0];
           Tests:       T1 T2 T3 
1298                    
1299       1/1            assign csr0_field1_wd = reg_wdata[1];
           Tests:       T1 T2 T3 
1300                    
1301       1/1            assign csr0_field2_wd = reg_wdata[2];
           Tests:       T1 T2 T3 
1302                    
1303       1/1            assign csr0_field3_wd = reg_wdata[13:4];
           Tests:       T1 T2 T3 
1304                    
1305       1/1            assign csr0_field4_wd = reg_wdata[26:16];
           Tests:       T1 T2 T3 
1306       1/1            assign csr1_we = addr_hit[1] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1307                    
1308       1/1            assign csr1_field0_wd = reg_wdata[6:0];
           Tests:       T1 T2 T3 
1309                    
1310       1/1            assign csr1_field1_wd = reg_wdata[7];
           Tests:       T1 T2 T3 
1311                    
1312       1/1            assign csr1_field2_wd = reg_wdata[14:8];
           Tests:       T1 T2 T3 
1313                    
1314       1/1            assign csr1_field3_wd = reg_wdata[15];
           Tests:       T1 T2 T3 
1315                    
1316       1/1            assign csr1_field4_wd = reg_wdata[31:16];
           Tests:       T1 T2 T3 
1317       1/1            assign csr2_we = addr_hit[2] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1318                    
1319       1/1            assign csr2_wd = reg_wdata[0];
           Tests:       T1 T2 T3 
1320       1/1            assign csr3_we = addr_hit[3] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1321                    
1322       1/1            assign csr3_field0_wd = reg_wdata[2:0];
           Tests:       T1 T2 T3 
1323                    
1324       1/1            assign csr3_field1_wd = reg_wdata[13:4];
           Tests:       T1 T2 T3 
1325                    
1326       1/1            assign csr3_field2_wd = reg_wdata[16];
           Tests:       T1 T2 T3 
1327       1/1            assign csr4_we = addr_hit[4] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1328                    
1329       1/1            assign csr4_field0_wd = reg_wdata[9:0];
           Tests:       T1 T2 T3 
1330                    
1331       1/1            assign csr4_field1_wd = reg_wdata[12];
           Tests:       T1 T2 T3 
1332                    
1333       1/1            assign csr4_field2_wd = reg_wdata[13];
           Tests:       T1 T2 T3 
1334                    
1335       1/1            assign csr4_field3_wd = reg_wdata[14];
           Tests:       T1 T2 T3 
1336       1/1            assign csr5_we = addr_hit[5] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1337                    
1338       1/1            assign csr5_field0_wd = reg_wdata[5:0];
           Tests:       T1 T2 T3 
1339                    
1340       1/1            assign csr5_field1_wd = reg_wdata[7:6];
           Tests:       T1 T2 T3 
1341                    
1342       1/1            assign csr5_field6_wd = reg_wdata[31:16];
           Tests:       T1 T2 T3 
1343       1/1            assign csr6_we = addr_hit[6] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1344                    
1345       1/1            assign csr6_field0_wd = reg_wdata[9:0];
           Tests:       T1 T2 T3 
1346                    
1347       1/1            assign csr6_field1_wd = reg_wdata[11];
           Tests:       T1 T2 T3 
1348                    
1349       1/1            assign csr6_field2_wd = reg_wdata[12];
           Tests:       T1 T2 T3 
1350                    
1351       1/1            assign csr6_field3_wd = reg_wdata[31:16];
           Tests:       T1 T2 T3 
1352                    
1353                      // Assign write-enables to checker logic vector.
1354                      always_comb begin
1355       1/1              reg_we_check = '0;
           Tests:       T1 T2 T3 
1356       1/1              reg_we_check[0] = csr0_we;
           Tests:       T1 T2 T3 
1357       1/1              reg_we_check[1] = csr1_we;
           Tests:       T1 T2 T3 
1358       1/1              reg_we_check[2] = csr2_we;
           Tests:       T1 T2 T3 
1359       1/1              reg_we_check[3] = csr3_we;
           Tests:       T1 T2 T3 
1360       1/1              reg_we_check[4] = csr4_we;
           Tests:       T1 T2 T3 
1361       1/1              reg_we_check[5] = csr5_we;
           Tests:       T1 T2 T3 
1362       1/1              reg_we_check[6] = csr6_we;
           Tests:       T1 T2 T3 
1363       1/1              reg_we_check[7] = 1'b0;
           Tests:       T1 T2 T3 
1364                      end
1365                    
1366                      // Read data return
1367                      always_comb begin
1368       1/1              reg_rdata_next = '0;
           Tests:       T1 T2 T3 
1369       1/1              unique case (1'b1)
           Tests:       T1 T2 T3 
1370                          addr_hit[0]: begin
1371       1/1                  reg_rdata_next[0] = csr0_field0_qs;
           Tests:       T1 T2 T3 
1372       1/1                  reg_rdata_next[1] = csr0_field1_qs;
           Tests:       T1 T2 T3 
1373       1/1                  reg_rdata_next[2] = csr0_field2_qs;
           Tests:       T1 T2 T3 
1374       1/1                  reg_rdata_next[13:4] = csr0_field3_qs;
           Tests:       T1 T2 T3 
1375       1/1                  reg_rdata_next[26:16] = csr0_field4_qs;
           Tests:       T1 T2 T3 
1376                          end
1377                    
1378                          addr_hit[1]: begin
1379       1/1                  reg_rdata_next[6:0] = csr1_field0_qs;
           Tests:       T10 T17 T18 
1380       1/1                  reg_rdata_next[7] = csr1_field1_qs;
           Tests:       T10 T17 T18 
1381       1/1                  reg_rdata_next[14:8] = csr1_field2_qs;
           Tests:       T10 T17 T18 
1382       1/1                  reg_rdata_next[15] = csr1_field3_qs;
           Tests:       T10 T17 T18 
1383       1/1                  reg_rdata_next[31:16] = csr1_field4_qs;
           Tests:       T10 T17 T18 
1384                          end
1385                    
1386                          addr_hit[2]: begin
1387       1/1                  reg_rdata_next[0] = csr2_qs;
           Tests:       T10 T17 T18 
1388                          end
1389                    
1390                          addr_hit[3]: begin
1391       1/1                  reg_rdata_next[2:0] = csr3_field0_qs;
           Tests:       T10 T17 T18 
1392       1/1                  reg_rdata_next[13:4] = csr3_field1_qs;
           Tests:       T10 T17 T18 
1393       1/1                  reg_rdata_next[16] = csr3_field2_qs;
           Tests:       T10 T17 T18 
1394       1/1                  reg_rdata_next[17] = csr3_field3_qs;
           Tests:       T10 T17 T18 
1395       1/1                  reg_rdata_next[18] = csr3_field4_qs;
           Tests:       T10 T17 T18 
1396       1/1                  reg_rdata_next[19] = csr3_field5_qs;
           Tests:       T10 T17 T18 
1397       1/1                  reg_rdata_next[20] = csr3_field6_qs;
           Tests:       T10 T17 T18 
1398       1/1                  reg_rdata_next[21] = csr3_field7_qs;
           Tests:       T10 T17 T18 
1399       1/1                  reg_rdata_next[22] = csr3_field8_qs;
           Tests:       T10 T17 T18 
1400                          end
1401                    
1402                          addr_hit[4]: begin
1403       1/1                  reg_rdata_next[9:0] = csr4_field0_qs;
           Tests:       T10 T17 T18 
1404       1/1                  reg_rdata_next[12] = csr4_field1_qs;
           Tests:       T10 T17 T18 
1405       1/1                  reg_rdata_next[13] = csr4_field2_qs;
           Tests:       T10 T17 T18 
1406       1/1                  reg_rdata_next[14] = csr4_field3_qs;
           Tests:       T10 T17 T18 
1407                          end
1408                    
1409                          addr_hit[5]: begin
1410       1/1                  reg_rdata_next[5:0] = csr5_field0_qs;
           Tests:       T10 T17 T18 
1411       1/1                  reg_rdata_next[7:6] = csr5_field1_qs;
           Tests:       T10 T17 T18 
1412       1/1                  reg_rdata_next[8] = csr5_field2_qs;
           Tests:       T10 T17 T18 
1413       1/1                  reg_rdata_next[11:9] = csr5_field3_qs;
           Tests:       T10 T17 T18 
1414       1/1                  reg_rdata_next[12] = csr5_field4_qs;
           Tests:       T10 T17 T18 
1415       1/1                  reg_rdata_next[13] = csr5_field5_qs;
           Tests:       T10 T17 T18 
1416       1/1                  reg_rdata_next[31:16] = csr5_field6_qs;
           Tests:       T10 T17 T18 
1417                          end
1418                    
1419                          addr_hit[6]: begin
1420       1/1                  reg_rdata_next[9:0] = csr6_field0_qs;
           Tests:       T10 T17 T18 
1421       1/1                  reg_rdata_next[11] = csr6_field1_qs;
           Tests:       T10 T17 T18 
1422       1/1                  reg_rdata_next[12] = csr6_field2_qs;
           Tests:       T10 T17 T18 
1423       1/1                  reg_rdata_next[31:16] = csr6_field3_qs;
           Tests:       T10 T17 T18 
1424                          end
1425                    
1426                          addr_hit[7]: begin
1427       1/1                  reg_rdata_next[5:0] = csr7_field0_qs;
           Tests:       T10 T17 T18 
1428       1/1                  reg_rdata_next[10:8] = csr7_field1_qs;
           Tests:       T10 T17 T18 
1429       1/1                  reg_rdata_next[14] = csr7_field2_qs;
           Tests:       T10 T17 T18 
1430       1/1                  reg_rdata_next[15] = csr7_field3_qs;
           Tests:       T10 T17 T18 
1431                          end
1432                    
1433                          default: begin
1434                            reg_rdata_next = '1;
1435                          end
1436                        endcase
1437                      end
1438                    
1439                      // shadow busy
1440                      logic shadow_busy;
1441                      assign shadow_busy = 1'b0;
1442                    
1443                      // register busy
1444       unreachable    assign reg_busy = shadow_busy;
1445                    
1446                      // Unused signal tieoff
1447                    
1448                      // wdata / byte enable are not always fully used
1449                      // add a blanket unused statement to handle lint waivers
1450                      logic unused_wdata;
1451                      logic unused_be;
1452       1/1            assign unused_wdata = ^reg_wdata;
           Tests:       T1 T2 T3 
1453       1/1            assign unused_be = ^reg_be;
           Tests:       T1 T2 T3 
Cond Coverage for Module : otp_ctrl_prim_reg_top
TotalCoveredPercent
Conditions999797.98
Logical999797.98
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT17,T19,T20 

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT26,T27,T28
10CoveredT278,T279,T280 

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT26,T27,T28
010CoveredT278,T279,T280
100CoveredT26,T27,T28 

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT278,T279,T280
010CoveredT14,T15,T16
100Not Covered 

 LINE       1269
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR0_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT10,T17,T18
1CoveredT1,T2,T3 

 LINE       1270
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR1_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1271
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR2_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1272
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR3_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1273
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR4_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1274
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR5_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1275
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR6_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1276
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR7_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1279
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1279
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T19,T20
10CoveredT17,T19,T20 

 LINE       1283
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT14,T15,T16 

 LINE       1283
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))))
-1--2--3--4--5--6--7--8-StatusTests
00000000CoveredT17,T19,T20
00000001CoveredT17,T20,T151
00000010CoveredT17,T20,T151
00000100CoveredT17,T20,T151
00001000CoveredT17,T20,T151
00010000CoveredT17,T20,T151
00100000CoveredT17,T20,T151
01000000CoveredT17,T20,T151
10000000CoveredT1,T2,T3 

 LINE       1283
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T20,T151
10CoveredT17,T19,T20
11CoveredT1,T2,T3 

 LINE       1283
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT17,T20,T151 

 LINE       1283
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT17,T20,T151 

 LINE       1283
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT17,T20,T151 

 LINE       1283
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T151
11CoveredT17,T20,T151 

 LINE       1283
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT17,T20,T151 

 LINE       1283
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT17,T20,T151 

 LINE       1283
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT17,T20,T151 

 LINE       1295
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT1,T2,T3
110CoveredT14,T15,T16
111CoveredT17,T19,T20 

 LINE       1306
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT17,T19,T20
110CoveredT15,T16,T21
111CoveredT17,T19,T20 

 LINE       1317
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT17,T19,T20
110CoveredT15,T16,T21
111CoveredT19,T20,T151 

 LINE       1320
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT17,T19,T20
110CoveredT15,T16,T24
111CoveredT17,T19,T20 

 LINE       1327
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT17,T19,T20
110CoveredT15,T16,T21
111CoveredT17,T19,T139 

 LINE       1336
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT17,T19,T20
110CoveredT15,T16,T25
111CoveredT17,T19,T20 

 LINE       1343
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT17,T19,T20
110CoveredT15,T16,T21
111CoveredT17,T19,T20
Branch Coverage for Module : otp_ctrl_prim_reg_top
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 1279 2 2 100.00
IF 68 3 3 100.00
CASE 1369 9 9 100.00 



1279         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:
-1-StatusTests
1 Covered T17,T19,T20
0 Covered T1,T2,T3 



68             if (!rst_ni) begin
               -1-  
69               err_q <= '0;
                 ==>
70             end else if (intg_err || reg_we_err) begin
                        -2-  
71               err_q <= 1'b1;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T26,T27,T28
0 0 Covered T1,T2,T3 



1369           unique case (1'b1)
                      -1-  
1370             addr_hit[0]: begin
1371               reg_rdata_next[0] = csr0_field0_qs;
                   ==>
1372               reg_rdata_next[1] = csr0_field1_qs;
1373               reg_rdata_next[2] = csr0_field2_qs;
1374               reg_rdata_next[13:4] = csr0_field3_qs;
1375               reg_rdata_next[26:16] = csr0_field4_qs;
1376             end
1377       
1378             addr_hit[1]: begin
1379               reg_rdata_next[6:0] = csr1_field0_qs;
                   ==>
1380               reg_rdata_next[7] = csr1_field1_qs;
1381               reg_rdata_next[14:8] = csr1_field2_qs;
1382               reg_rdata_next[15] = csr1_field3_qs;
1383               reg_rdata_next[31:16] = csr1_field4_qs;
1384             end
1385       
1386             addr_hit[2]: begin
1387               reg_rdata_next[0] = csr2_qs;
                   ==>
1388             end
1389       
1390             addr_hit[3]: begin
1391               reg_rdata_next[2:0] = csr3_field0_qs;
                   ==>
1392               reg_rdata_next[13:4] = csr3_field1_qs;
1393               reg_rdata_next[16] = csr3_field2_qs;
1394               reg_rdata_next[17] = csr3_field3_qs;
1395               reg_rdata_next[18] = csr3_field4_qs;
1396               reg_rdata_next[19] = csr3_field5_qs;
1397               reg_rdata_next[20] = csr3_field6_qs;
1398               reg_rdata_next[21] = csr3_field7_qs;
1399               reg_rdata_next[22] = csr3_field8_qs;
1400             end
1401       
1402             addr_hit[4]: begin
1403               reg_rdata_next[9:0] = csr4_field0_qs;
                   ==>
1404               reg_rdata_next[12] = csr4_field1_qs;
1405               reg_rdata_next[13] = csr4_field2_qs;
1406               reg_rdata_next[14] = csr4_field3_qs;
1407             end
1408       
1409             addr_hit[5]: begin
1410               reg_rdata_next[5:0] = csr5_field0_qs;
                   ==>
1411               reg_rdata_next[7:6] = csr5_field1_qs;
1412               reg_rdata_next[8] = csr5_field2_qs;
1413               reg_rdata_next[11:9] = csr5_field3_qs;
1414               reg_rdata_next[12] = csr5_field4_qs;
1415               reg_rdata_next[13] = csr5_field5_qs;
1416               reg_rdata_next[31:16] = csr5_field6_qs;
1417             end
1418       
1419             addr_hit[6]: begin
1420               reg_rdata_next[9:0] = csr6_field0_qs;
                   ==>
1421               reg_rdata_next[11] = csr6_field1_qs;
1422               reg_rdata_next[12] = csr6_field2_qs;
1423               reg_rdata_next[31:16] = csr6_field3_qs;
1424             end
1425       
1426             addr_hit[7]: begin
1427               reg_rdata_next[5:0] = csr7_field0_qs;
                   ==>
1428               reg_rdata_next[10:8] = csr7_field1_qs;
1429               reg_rdata_next[14] = csr7_field2_qs;
1430               reg_rdata_next[15] = csr7_field3_qs;
1431             end
1432       
1433             default: begin
1434               reg_rdata_next = '1;
                   ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T10,T17,T18
addr_hit[2] Covered T10,T17,T18
addr_hit[3] Covered T10,T17,T18
addr_hit[4] Covered T10,T17,T18
addr_hit[5] Covered T10,T17,T18
addr_hit[6] Covered T10,T17,T18
addr_hit[7] Covered T10,T17,T18
default Covered T10,T18,T19

Assert Coverage for Module : otp_ctrl_prim_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 91185948 36787 0 0
reAfterRv 91185948 36787 0 0
rePulse 91185948 22562 0 0
wePulse 91185948 14225 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 91185948 36787 0 0
T14 0 40 0 0
T15 0 158 0 0
T17 77151 52 0 0
T19 0 40 0 0
T20 0 34 0 0
T93 91589 0 0 0
T97 30986 0 0 0
T98 37909 0 0 0
T101 14706 0 0 0
T102 30181 0 0 0
T105 44569 0 0 0
T127 59995 0 0 0
T128 14105 0 0 0
T129 33379 0 0 0
T135 0 54 0 0
T139 0 48 0 0
T151 0 20 0 0
T192 0 36 0 0
T287 0 108 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 91185948 36787 0 0
T14 0 40 0 0
T15 0 158 0 0
T17 77151 52 0 0
T19 0 40 0 0
T20 0 34 0 0
T93 91589 0 0 0
T97 30986 0 0 0
T98 37909 0 0 0
T101 14706 0 0 0
T102 30181 0 0 0
T105 44569 0 0 0
T127 59995 0 0 0
T128 14105 0 0 0
T129 33379 0 0 0
T135 0 54 0 0
T139 0 48 0 0
T151 0 20 0 0
T192 0 36 0 0
T287 0 108 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 91185948 22562 0 0
T14 0 39 0 0
T15 0 85 0 0
T17 77151 26 0 0
T19 0 20 0 0
T20 0 17 0 0
T93 91589 0 0 0
T97 30986 0 0 0
T98 37909 0 0 0
T101 14706 0 0 0
T102 30181 0 0 0
T105 44569 0 0 0
T127 59995 0 0 0
T128 14105 0 0 0
T129 33379 0 0 0
T135 0 27 0 0
T139 0 24 0 0
T151 0 10 0 0
T192 0 18 0 0
T287 0 54 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 91185948 14225 0 0
T14 0 1 0 0
T15 0 73 0 0
T17 77151 26 0 0
T19 0 20 0 0
T20 0 17 0 0
T93 91589 0 0 0
T97 30986 0 0 0
T98 37909 0 0 0
T101 14706 0 0 0
T102 30181 0 0 0
T105 44569 0 0 0
T127 59995 0 0 0
T128 14105 0 0 0
T129 33379 0 0 0
T135 0 27 0 0
T139 0 24 0 0
T151 0 10 0 0
T192 0 18 0 0
T287 0 54 0 0

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top
Line No.TotalCoveredPercent
TOTAL104104100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
ALWAYS126899100.00
CONT_ASSIGN127911100.00
ALWAYS128311100.00
CONT_ASSIGN129511100.00
CONT_ASSIGN129711100.00
CONT_ASSIGN129911100.00
CONT_ASSIGN130111100.00
CONT_ASSIGN130311100.00
CONT_ASSIGN130511100.00
CONT_ASSIGN130611100.00
CONT_ASSIGN130811100.00
CONT_ASSIGN131011100.00
CONT_ASSIGN131211100.00
CONT_ASSIGN131411100.00
CONT_ASSIGN131611100.00
CONT_ASSIGN131711100.00
CONT_ASSIGN131911100.00
CONT_ASSIGN132011100.00
CONT_ASSIGN132211100.00
CONT_ASSIGN132411100.00
CONT_ASSIGN132611100.00
CONT_ASSIGN132711100.00
CONT_ASSIGN132911100.00
CONT_ASSIGN133111100.00
CONT_ASSIGN133311100.00
CONT_ASSIGN133511100.00
CONT_ASSIGN133611100.00
CONT_ASSIGN133811100.00
CONT_ASSIGN134011100.00
CONT_ASSIGN134211100.00
CONT_ASSIGN134311100.00
CONT_ASSIGN134511100.00
CONT_ASSIGN134711100.00
CONT_ASSIGN134911100.00
CONT_ASSIGN135111100.00
ALWAYS135599100.00
ALWAYS13684141100.00
CONT_ASSIGN144400
CONT_ASSIGN145211100.00
CONT_ASSIGN145311100.00


67                        always_ff @(posedge clk_i or negedge rst_ni) begin
68         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
69         1/1                err_q <= '0;
           Tests:       T1 T2 T3 
70         1/1              end else if (intg_err || reg_we_err) begin
           Tests:       T1 T2 T3 
71         1/1                err_q <= 1'b1;
           Tests:       T26 T27 T28 
72                          end
                        MISSING_ELSE
73                        end
74                      
75                        // integrity error output is permanent and should be used for alert generation
76                        // register errors are transactional
77         1/1            assign intg_err_o = err_q | intg_err | reg_we_err;
           Tests:       T1 T2 T3 
78                      
79                        // outgoing integrity generation
80                        tlul_pkg::tl_d2h_t tl_o_pre;
81                        tlul_rsp_intg_gen #(
82                          .EnableRspIntgGen(1),
83                          .EnableDataIntgGen(1)
84                        ) u_rsp_intg_gen (
85                          .tl_i(tl_o_pre),
86                          .tl_o(tl_o)
87                        );
88                      
89         1/1            assign tl_reg_h2d = tl_i;
           Tests:       T1 T2 T3 
90         1/1            assign tl_o_pre   = tl_reg_d2h;
           Tests:       T1 T2 T3 
91                      
92                        tlul_adapter_reg #(
93                          .RegAw(AW),
94                          .RegDw(DW),
95                          .EnableDataIntgGen(0)
96                        ) u_reg_if (
97                          .clk_i  (clk_i),
98                          .rst_ni (rst_ni),
99                      
100                         .tl_i (tl_reg_h2d),
101                         .tl_o (tl_reg_d2h),
102                     
103                         .en_ifetch_i(prim_mubi_pkg::MuBi4False),
104                         .intg_error_o(),
105                     
106                         .we_o    (reg_we),
107                         .re_o    (reg_re),
108                         .addr_o  (reg_addr),
109                         .wdata_o (reg_wdata),
110                         .be_o    (reg_be),
111                         .busy_i  (reg_busy),
112                         .rdata_i (reg_rdata),
113                         .error_i (reg_error)
114                       );
115                     
116                       // cdc oversampling signals
117                     
118        1/1            assign reg_rdata = reg_rdata_next ;
           Tests:       T1 T2 T3 
119        1/1            assign reg_error = addrmiss | wr_err | intg_err;
           Tests:       T1 T2 T3 
120                     
121                       // Define SW related signals
122                       // Format: <reg>_<field>_{wd|we|qs}
123                       //        or <reg>_{wd|we|qs} if field == 1 or 0
124                       logic csr0_we;
125                       logic csr0_field0_qs;
126                       logic csr0_field0_wd;
127                       logic csr0_field1_qs;
128                       logic csr0_field1_wd;
129                       logic csr0_field2_qs;
130                       logic csr0_field2_wd;
131                       logic [9:0] csr0_field3_qs;
132                       logic [9:0] csr0_field3_wd;
133                       logic [10:0] csr0_field4_qs;
134                       logic [10:0] csr0_field4_wd;
135                       logic csr1_we;
136                       logic [6:0] csr1_field0_qs;
137                       logic [6:0] csr1_field0_wd;
138                       logic csr1_field1_qs;
139                       logic csr1_field1_wd;
140                       logic [6:0] csr1_field2_qs;
141                       logic [6:0] csr1_field2_wd;
142                       logic csr1_field3_qs;
143                       logic csr1_field3_wd;
144                       logic [15:0] csr1_field4_qs;
145                       logic [15:0] csr1_field4_wd;
146                       logic csr2_we;
147                       logic csr2_qs;
148                       logic csr2_wd;
149                       logic csr3_we;
150                       logic [2:0] csr3_field0_qs;
151                       logic [2:0] csr3_field0_wd;
152                       logic [9:0] csr3_field1_qs;
153                       logic [9:0] csr3_field1_wd;
154                       logic csr3_field2_qs;
155                       logic csr3_field2_wd;
156                       logic csr3_field3_qs;
157                       logic csr3_field4_qs;
158                       logic csr3_field5_qs;
159                       logic csr3_field6_qs;
160                       logic csr3_field7_qs;
161                       logic csr3_field8_qs;
162                       logic csr4_we;
163                       logic [9:0] csr4_field0_qs;
164                       logic [9:0] csr4_field0_wd;
165                       logic csr4_field1_qs;
166                       logic csr4_field1_wd;
167                       logic csr4_field2_qs;
168                       logic csr4_field2_wd;
169                       logic csr4_field3_qs;
170                       logic csr4_field3_wd;
171                       logic csr5_we;
172                       logic [5:0] csr5_field0_qs;
173                       logic [5:0] csr5_field0_wd;
174                       logic [1:0] csr5_field1_qs;
175                       logic [1:0] csr5_field1_wd;
176                       logic csr5_field2_qs;
177                       logic [2:0] csr5_field3_qs;
178                       logic csr5_field4_qs;
179                       logic csr5_field5_qs;
180                       logic [15:0] csr5_field6_qs;
181                       logic [15:0] csr5_field6_wd;
182                       logic csr6_we;
183                       logic [9:0] csr6_field0_qs;
184                       logic [9:0] csr6_field0_wd;
185                       logic csr6_field1_qs;
186                       logic csr6_field1_wd;
187                       logic csr6_field2_qs;
188                       logic csr6_field2_wd;
189                       logic [15:0] csr6_field3_qs;
190                       logic [15:0] csr6_field3_wd;
191                       logic [5:0] csr7_field0_qs;
192                       logic [2:0] csr7_field1_qs;
193                       logic csr7_field2_qs;
194                       logic csr7_field3_qs;
195                     
196                       // Register instances
197                       // R[csr0]: V(False)
198                       //   F[field0]: 0:0
199                       prim_subreg #(
200                         .DW      (1),
201                         .SwAccess(prim_subreg_pkg::SwAccessRW),
202                         .RESVAL  (1'h0),
203                         .Mubi    (1'b0)
204                       ) u_csr0_field0 (
205                         .clk_i   (clk_i),
206                         .rst_ni  (rst_ni),
207                     
208                         // from register interface
209                         .we     (csr0_we),
210                         .wd     (csr0_field0_wd),
211                     
212                         // from internal hardware
213                         .de     (1'b0),
214                         .d      ('0),
215                     
216                         // to internal hardware
217                         .qe     (),
218                         .q      (reg2hw.csr0.field0.q),
219                         .ds     (),
220                     
221                         // to register interface (read)
222                         .qs     (csr0_field0_qs)
223                       );
224                     
225                       //   F[field1]: 1:1
226                       prim_subreg #(
227                         .DW      (1),
228                         .SwAccess(prim_subreg_pkg::SwAccessRW),
229                         .RESVAL  (1'h0),
230                         .Mubi    (1'b0)
231                       ) u_csr0_field1 (
232                         .clk_i   (clk_i),
233                         .rst_ni  (rst_ni),
234                     
235                         // from register interface
236                         .we     (csr0_we),
237                         .wd     (csr0_field1_wd),
238                     
239                         // from internal hardware
240                         .de     (1'b0),
241                         .d      ('0),
242                     
243                         // to internal hardware
244                         .qe     (),
245                         .q      (reg2hw.csr0.field1.q),
246                         .ds     (),
247                     
248                         // to register interface (read)
249                         .qs     (csr0_field1_qs)
250                       );
251                     
252                       //   F[field2]: 2:2
253                       prim_subreg #(
254                         .DW      (1),
255                         .SwAccess(prim_subreg_pkg::SwAccessRW),
256                         .RESVAL  (1'h0),
257                         .Mubi    (1'b0)
258                       ) u_csr0_field2 (
259                         .clk_i   (clk_i),
260                         .rst_ni  (rst_ni),
261                     
262                         // from register interface
263                         .we     (csr0_we),
264                         .wd     (csr0_field2_wd),
265                     
266                         // from internal hardware
267                         .de     (1'b0),
268                         .d      ('0),
269                     
270                         // to internal hardware
271                         .qe     (),
272                         .q      (reg2hw.csr0.field2.q),
273                         .ds     (),
274                     
275                         // to register interface (read)
276                         .qs     (csr0_field2_qs)
277                       );
278                     
279                       //   F[field3]: 13:4
280                       prim_subreg #(
281                         .DW      (10),
282                         .SwAccess(prim_subreg_pkg::SwAccessRW),
283                         .RESVAL  (10'h0),
284                         .Mubi    (1'b0)
285                       ) u_csr0_field3 (
286                         .clk_i   (clk_i),
287                         .rst_ni  (rst_ni),
288                     
289                         // from register interface
290                         .we     (csr0_we),
291                         .wd     (csr0_field3_wd),
292                     
293                         // from internal hardware
294                         .de     (1'b0),
295                         .d      ('0),
296                     
297                         // to internal hardware
298                         .qe     (),
299                         .q      (reg2hw.csr0.field3.q),
300                         .ds     (),
301                     
302                         // to register interface (read)
303                         .qs     (csr0_field3_qs)
304                       );
305                     
306                       //   F[field4]: 26:16
307                       prim_subreg #(
308                         .DW      (11),
309                         .SwAccess(prim_subreg_pkg::SwAccessRW),
310                         .RESVAL  (11'h0),
311                         .Mubi    (1'b0)
312                       ) u_csr0_field4 (
313                         .clk_i   (clk_i),
314                         .rst_ni  (rst_ni),
315                     
316                         // from register interface
317                         .we     (csr0_we),
318                         .wd     (csr0_field4_wd),
319                     
320                         // from internal hardware
321                         .de     (1'b0),
322                         .d      ('0),
323                     
324                         // to internal hardware
325                         .qe     (),
326                         .q      (reg2hw.csr0.field4.q),
327                         .ds     (),
328                     
329                         // to register interface (read)
330                         .qs     (csr0_field4_qs)
331                       );
332                     
333                     
334                       // R[csr1]: V(False)
335                       //   F[field0]: 6:0
336                       prim_subreg #(
337                         .DW      (7),
338                         .SwAccess(prim_subreg_pkg::SwAccessRW),
339                         .RESVAL  (7'h0),
340                         .Mubi    (1'b0)
341                       ) u_csr1_field0 (
342                         .clk_i   (clk_i),
343                         .rst_ni  (rst_ni),
344                     
345                         // from register interface
346                         .we     (csr1_we),
347                         .wd     (csr1_field0_wd),
348                     
349                         // from internal hardware
350                         .de     (1'b0),
351                         .d      ('0),
352                     
353                         // to internal hardware
354                         .qe     (),
355                         .q      (reg2hw.csr1.field0.q),
356                         .ds     (),
357                     
358                         // to register interface (read)
359                         .qs     (csr1_field0_qs)
360                       );
361                     
362                       //   F[field1]: 7:7
363                       prim_subreg #(
364                         .DW      (1),
365                         .SwAccess(prim_subreg_pkg::SwAccessRW),
366                         .RESVAL  (1'h0),
367                         .Mubi    (1'b0)
368                       ) u_csr1_field1 (
369                         .clk_i   (clk_i),
370                         .rst_ni  (rst_ni),
371                     
372                         // from register interface
373                         .we     (csr1_we),
374                         .wd     (csr1_field1_wd),
375                     
376                         // from internal hardware
377                         .de     (1'b0),
378                         .d      ('0),
379                     
380                         // to internal hardware
381                         .qe     (),
382                         .q      (reg2hw.csr1.field1.q),
383                         .ds     (),
384                     
385                         // to register interface (read)
386                         .qs     (csr1_field1_qs)
387                       );
388                     
389                       //   F[field2]: 14:8
390                       prim_subreg #(
391                         .DW      (7),
392                         .SwAccess(prim_subreg_pkg::SwAccessRW),
393                         .RESVAL  (7'h0),
394                         .Mubi    (1'b0)
395                       ) u_csr1_field2 (
396                         .clk_i   (clk_i),
397                         .rst_ni  (rst_ni),
398                     
399                         // from register interface
400                         .we     (csr1_we),
401                         .wd     (csr1_field2_wd),
402                     
403                         // from internal hardware
404                         .de     (1'b0),
405                         .d      ('0),
406                     
407                         // to internal hardware
408                         .qe     (),
409                         .q      (reg2hw.csr1.field2.q),
410                         .ds     (),
411                     
412                         // to register interface (read)
413                         .qs     (csr1_field2_qs)
414                       );
415                     
416                       //   F[field3]: 15:15
417                       prim_subreg #(
418                         .DW      (1),
419                         .SwAccess(prim_subreg_pkg::SwAccessRW),
420                         .RESVAL  (1'h0),
421                         .Mubi    (1'b0)
422                       ) u_csr1_field3 (
423                         .clk_i   (clk_i),
424                         .rst_ni  (rst_ni),
425                     
426                         // from register interface
427                         .we     (csr1_we),
428                         .wd     (csr1_field3_wd),
429                     
430                         // from internal hardware
431                         .de     (1'b0),
432                         .d      ('0),
433                     
434                         // to internal hardware
435                         .qe     (),
436                         .q      (reg2hw.csr1.field3.q),
437                         .ds     (),
438                     
439                         // to register interface (read)
440                         .qs     (csr1_field3_qs)
441                       );
442                     
443                       //   F[field4]: 31:16
444                       prim_subreg #(
445                         .DW      (16),
446                         .SwAccess(prim_subreg_pkg::SwAccessRW),
447                         .RESVAL  (16'h0),
448                         .Mubi    (1'b0)
449                       ) u_csr1_field4 (
450                         .clk_i   (clk_i),
451                         .rst_ni  (rst_ni),
452                     
453                         // from register interface
454                         .we     (csr1_we),
455                         .wd     (csr1_field4_wd),
456                     
457                         // from internal hardware
458                         .de     (1'b0),
459                         .d      ('0),
460                     
461                         // to internal hardware
462                         .qe     (),
463                         .q      (reg2hw.csr1.field4.q),
464                         .ds     (),
465                     
466                         // to register interface (read)
467                         .qs     (csr1_field4_qs)
468                       );
469                     
470                     
471                       // R[csr2]: V(False)
472                       prim_subreg #(
473                         .DW      (1),
474                         .SwAccess(prim_subreg_pkg::SwAccessRW),
475                         .RESVAL  (1'h0),
476                         .Mubi    (1'b0)
477                       ) u_csr2 (
478                         .clk_i   (clk_i),
479                         .rst_ni  (rst_ni),
480                     
481                         // from register interface
482                         .we     (csr2_we),
483                         .wd     (csr2_wd),
484                     
485                         // from internal hardware
486                         .de     (1'b0),
487                         .d      ('0),
488                     
489                         // to internal hardware
490                         .qe     (),
491                         .q      (reg2hw.csr2.q),
492                         .ds     (),
493                     
494                         // to register interface (read)
495                         .qs     (csr2_qs)
496                       );
497                     
498                     
499                       // R[csr3]: V(False)
500                       //   F[field0]: 2:0
501                       prim_subreg #(
502                         .DW      (3),
503                         .SwAccess(prim_subreg_pkg::SwAccessW1C),
504                         .RESVAL  (3'h0),
505                         .Mubi    (1'b0)
506                       ) u_csr3_field0 (
507                         .clk_i   (clk_i),
508                         .rst_ni  (rst_ni),
509                     
510                         // from register interface
511                         .we     (csr3_we),
512                         .wd     (csr3_field0_wd),
513                     
514                         // from internal hardware
515                         .de     (hw2reg.csr3.field0.de),
516                         .d      (hw2reg.csr3.field0.d),
517                     
518                         // to internal hardware
519                         .qe     (),
520                         .q      (reg2hw.csr3.field0.q),
521                         .ds     (),
522                     
523                         // to register interface (read)
524                         .qs     (csr3_field0_qs)
525                       );
526                     
527                       //   F[field1]: 13:4
528                       prim_subreg #(
529                         .DW      (10),
530                         .SwAccess(prim_subreg_pkg::SwAccessW1C),
531                         .RESVAL  (10'h0),
532                         .Mubi    (1'b0)
533                       ) u_csr3_field1 (
534                         .clk_i   (clk_i),
535                         .rst_ni  (rst_ni),
536                     
537                         // from register interface
538                         .we     (csr3_we),
539                         .wd     (csr3_field1_wd),
540                     
541                         // from internal hardware
542                         .de     (hw2reg.csr3.field1.de),
543                         .d      (hw2reg.csr3.field1.d),
544                     
545                         // to internal hardware
546                         .qe     (),
547                         .q      (reg2hw.csr3.field1.q),
548                         .ds     (),
549                     
550                         // to register interface (read)
551                         .qs     (csr3_field1_qs)
552                       );
553                     
554                       //   F[field2]: 16:16
555                       prim_subreg #(
556                         .DW      (1),
557                         .SwAccess(prim_subreg_pkg::SwAccessW1C),
558                         .RESVAL  (1'h0),
559                         .Mubi    (1'b0)
560                       ) u_csr3_field2 (
561                         .clk_i   (clk_i),
562                         .rst_ni  (rst_ni),
563                     
564                         // from register interface
565                         .we     (csr3_we),
566                         .wd     (csr3_field2_wd),
567                     
568                         // from internal hardware
569                         .de     (hw2reg.csr3.field2.de),
570                         .d      (hw2reg.csr3.field2.d),
571                     
572                         // to internal hardware
573                         .qe     (),
574                         .q      (reg2hw.csr3.field2.q),
575                         .ds     (),
576                     
577                         // to register interface (read)
578                         .qs     (csr3_field2_qs)
579                       );
580                     
581                       //   F[field3]: 17:17
582                       prim_subreg #(
583                         .DW      (1),
584                         .SwAccess(prim_subreg_pkg::SwAccessRO),
585                         .RESVAL  (1'h0),
586                         .Mubi    (1'b0)
587                       ) u_csr3_field3 (
588                         .clk_i   (clk_i),
589                         .rst_ni  (rst_ni),
590                     
591                         // from register interface
592                         .we     (1'b0),
593                         .wd     ('0),
594                     
595                         // from internal hardware
596                         .de     (hw2reg.csr3.field3.de),
597                         .d      (hw2reg.csr3.field3.d),
598                     
599                         // to internal hardware
600                         .qe     (),
601                         .q      (reg2hw.csr3.field3.q),
602                         .ds     (),
603                     
604                         // to register interface (read)
605                         .qs     (csr3_field3_qs)
606                       );
607                     
608                       //   F[field4]: 18:18
609                       prim_subreg #(
610                         .DW      (1),
611                         .SwAccess(prim_subreg_pkg::SwAccessRO),
612                         .RESVAL  (1'h0),
613                         .Mubi    (1'b0)
614                       ) u_csr3_field4 (
615                         .clk_i   (clk_i),
616                         .rst_ni  (rst_ni),
617                     
618                         // from register interface
619                         .we     (1'b0),
620                         .wd     ('0),
621                     
622                         // from internal hardware
623                         .de     (hw2reg.csr3.field4.de),
624                         .d      (hw2reg.csr3.field4.d),
625                     
626                         // to internal hardware
627                         .qe     (),
628                         .q      (reg2hw.csr3.field4.q),
629                         .ds     (),
630                     
631                         // to register interface (read)
632                         .qs     (csr3_field4_qs)
633                       );
634                     
635                       //   F[field5]: 19:19
636                       prim_subreg #(
637                         .DW      (1),
638                         .SwAccess(prim_subreg_pkg::SwAccessRO),
639                         .RESVAL  (1'h0),
640                         .Mubi    (1'b0)
641                       ) u_csr3_field5 (
642                         .clk_i   (clk_i),
643                         .rst_ni  (rst_ni),
644                     
645                         // from register interface
646                         .we     (1'b0),
647                         .wd     ('0),
648                     
649                         // from internal hardware
650                         .de     (hw2reg.csr3.field5.de),
651                         .d      (hw2reg.csr3.field5.d),
652                     
653                         // to internal hardware
654                         .qe     (),
655                         .q      (reg2hw.csr3.field5.q),
656                         .ds     (),
657                     
658                         // to register interface (read)
659                         .qs     (csr3_field5_qs)
660                       );
661                     
662                       //   F[field6]: 20:20
663                       prim_subreg #(
664                         .DW      (1),
665                         .SwAccess(prim_subreg_pkg::SwAccessRO),
666                         .RESVAL  (1'h0),
667                         .Mubi    (1'b0)
668                       ) u_csr3_field6 (
669                         .clk_i   (clk_i),
670                         .rst_ni  (rst_ni),
671                     
672                         // from register interface
673                         .we     (1'b0),
674                         .wd     ('0),
675                     
676                         // from internal hardware
677                         .de     (hw2reg.csr3.field6.de),
678                         .d      (hw2reg.csr3.field6.d),
679                     
680                         // to internal hardware
681                         .qe     (),
682                         .q      (reg2hw.csr3.field6.q),
683                         .ds     (),
684                     
685                         // to register interface (read)
686                         .qs     (csr3_field6_qs)
687                       );
688                     
689                       //   F[field7]: 21:21
690                       prim_subreg #(
691                         .DW      (1),
692                         .SwAccess(prim_subreg_pkg::SwAccessRO),
693                         .RESVAL  (1'h0),
694                         .Mubi    (1'b0)
695                       ) u_csr3_field7 (
696                         .clk_i   (clk_i),
697                         .rst_ni  (rst_ni),
698                     
699                         // from register interface
700                         .we     (1'b0),
701                         .wd     ('0),
702                     
703                         // from internal hardware
704                         .de     (hw2reg.csr3.field7.de),
705                         .d      (hw2reg.csr3.field7.d),
706                     
707                         // to internal hardware
708                         .qe     (),
709                         .q      (reg2hw.csr3.field7.q),
710                         .ds     (),
711                     
712                         // to register interface (read)
713                         .qs     (csr3_field7_qs)
714                       );
715                     
716                       //   F[field8]: 22:22
717                       prim_subreg #(
718                         .DW      (1),
719                         .SwAccess(prim_subreg_pkg::SwAccessRO),
720                         .RESVAL  (1'h0),
721                         .Mubi    (1'b0)
722                       ) u_csr3_field8 (
723                         .clk_i   (clk_i),
724                         .rst_ni  (rst_ni),
725                     
726                         // from register interface
727                         .we     (1'b0),
728                         .wd     ('0),
729                     
730                         // from internal hardware
731                         .de     (hw2reg.csr3.field8.de),
732                         .d      (hw2reg.csr3.field8.d),
733                     
734                         // to internal hardware
735                         .qe     (),
736                         .q      (reg2hw.csr3.field8.q),
737                         .ds     (),
738                     
739                         // to register interface (read)
740                         .qs     (csr3_field8_qs)
741                       );
742                     
743                     
744                       // R[csr4]: V(False)
745                       //   F[field0]: 9:0
746                       prim_subreg #(
747                         .DW      (10),
748                         .SwAccess(prim_subreg_pkg::SwAccessRW),
749                         .RESVAL  (10'h0),
750                         .Mubi    (1'b0)
751                       ) u_csr4_field0 (
752                         .clk_i   (clk_i),
753                         .rst_ni  (rst_ni),
754                     
755                         // from register interface
756                         .we     (csr4_we),
757                         .wd     (csr4_field0_wd),
758                     
759                         // from internal hardware
760                         .de     (1'b0),
761                         .d      ('0),
762                     
763                         // to internal hardware
764                         .qe     (),
765                         .q      (reg2hw.csr4.field0.q),
766                         .ds     (),
767                     
768                         // to register interface (read)
769                         .qs     (csr4_field0_qs)
770                       );
771                     
772                       //   F[field1]: 12:12
773                       prim_subreg #(
774                         .DW      (1),
775                         .SwAccess(prim_subreg_pkg::SwAccessRW),
776                         .RESVAL  (1'h0),
777                         .Mubi    (1'b0)
778                       ) u_csr4_field1 (
779                         .clk_i   (clk_i),
780                         .rst_ni  (rst_ni),
781                     
782                         // from register interface
783                         .we     (csr4_we),
784                         .wd     (csr4_field1_wd),
785                     
786                         // from internal hardware
787                         .de     (1'b0),
788                         .d      ('0),
789                     
790                         // to internal hardware
791                         .qe     (),
792                         .q      (reg2hw.csr4.field1.q),
793                         .ds     (),
794                     
795                         // to register interface (read)
796                         .qs     (csr4_field1_qs)
797                       );
798                     
799                       //   F[field2]: 13:13
800                       prim_subreg #(
801                         .DW      (1),
802                         .SwAccess(prim_subreg_pkg::SwAccessRW),
803                         .RESVAL  (1'h0),
804                         .Mubi    (1'b0)
805                       ) u_csr4_field2 (
806                         .clk_i   (clk_i),
807                         .rst_ni  (rst_ni),
808                     
809                         // from register interface
810                         .we     (csr4_we),
811                         .wd     (csr4_field2_wd),
812                     
813                         // from internal hardware
814                         .de     (1'b0),
815                         .d      ('0),
816                     
817                         // to internal hardware
818                         .qe     (),
819                         .q      (reg2hw.csr4.field2.q),
820                         .ds     (),
821                     
822                         // to register interface (read)
823                         .qs     (csr4_field2_qs)
824                       );
825                     
826                       //   F[field3]: 14:14
827                       prim_subreg #(
828                         .DW      (1),
829                         .SwAccess(prim_subreg_pkg::SwAccessRW),
830                         .RESVAL  (1'h0),
831                         .Mubi    (1'b0)
832                       ) u_csr4_field3 (
833                         .clk_i   (clk_i),
834                         .rst_ni  (rst_ni),
835                     
836                         // from register interface
837                         .we     (csr4_we),
838                         .wd     (csr4_field3_wd),
839                     
840                         // from internal hardware
841                         .de     (1'b0),
842                         .d      ('0),
843                     
844                         // to internal hardware
845                         .qe     (),
846                         .q      (reg2hw.csr4.field3.q),
847                         .ds     (),
848                     
849                         // to register interface (read)
850                         .qs     (csr4_field3_qs)
851                       );
852                     
853                     
854                       // R[csr5]: V(False)
855                       //   F[field0]: 5:0
856                       prim_subreg #(
857                         .DW      (6),
858                         .SwAccess(prim_subreg_pkg::SwAccessRW),
859                         .RESVAL  (6'h0),
860                         .Mubi    (1'b0)
861                       ) u_csr5_field0 (
862                         .clk_i   (clk_i),
863                         .rst_ni  (rst_ni),
864                     
865                         // from register interface
866                         .we     (csr5_we),
867                         .wd     (csr5_field0_wd),
868                     
869                         // from internal hardware
870                         .de     (hw2reg.csr5.field0.de),
871                         .d      (hw2reg.csr5.field0.d),
872                     
873                         // to internal hardware
874                         .qe     (),
875                         .q      (reg2hw.csr5.field0.q),
876                         .ds     (),
877                     
878                         // to register interface (read)
879                         .qs     (csr5_field0_qs)
880                       );
881                     
882                       //   F[field1]: 7:6
883                       prim_subreg #(
884                         .DW      (2),
885                         .SwAccess(prim_subreg_pkg::SwAccessRW),
886                         .RESVAL  (2'h0),
887                         .Mubi    (1'b0)
888                       ) u_csr5_field1 (
889                         .clk_i   (clk_i),
890                         .rst_ni  (rst_ni),
891                     
892                         // from register interface
893                         .we     (csr5_we),
894                         .wd     (csr5_field1_wd),
895                     
896                         // from internal hardware
897                         .de     (hw2reg.csr5.field1.de),
898                         .d      (hw2reg.csr5.field1.d),
899                     
900                         // to internal hardware
901                         .qe     (),
902                         .q      (reg2hw.csr5.field1.q),
903                         .ds     (),
904                     
905                         // to register interface (read)
906                         .qs     (csr5_field1_qs)
907                       );
908                     
909                       //   F[field2]: 8:8
910                       prim_subreg #(
911                         .DW      (1),
912                         .SwAccess(prim_subreg_pkg::SwAccessRO),
913                         .RESVAL  (1'h0),
914                         .Mubi    (1'b0)
915                       ) u_csr5_field2 (
916                         .clk_i   (clk_i),
917                         .rst_ni  (rst_ni),
918                     
919                         // from register interface
920                         .we     (1'b0),
921                         .wd     ('0),
922                     
923                         // from internal hardware
924                         .de     (hw2reg.csr5.field2.de),
925                         .d      (hw2reg.csr5.field2.d),
926                     
927                         // to internal hardware
928                         .qe     (),
929                         .q      (reg2hw.csr5.field2.q),
930                         .ds     (),
931                     
932                         // to register interface (read)
933                         .qs     (csr5_field2_qs)
934                       );
935                     
936                       //   F[field3]: 11:9
937                       prim_subreg #(
938                         .DW      (3),
939                         .SwAccess(prim_subreg_pkg::SwAccessRO),
940                         .RESVAL  (3'h0),
941                         .Mubi    (1'b0)
942                       ) u_csr5_field3 (
943                         .clk_i   (clk_i),
944                         .rst_ni  (rst_ni),
945                     
946                         // from register interface
947                         .we     (1'b0),
948                         .wd     ('0),
949                     
950                         // from internal hardware
951                         .de     (hw2reg.csr5.field3.de),
952                         .d      (hw2reg.csr5.field3.d),
953                     
954                         // to internal hardware
955                         .qe     (),
956                         .q      (reg2hw.csr5.field3.q),
957                         .ds     (),
958                     
959                         // to register interface (read)
960                         .qs     (csr5_field3_qs)
961                       );
962                     
963                       //   F[field4]: 12:12
964                       prim_subreg #(
965                         .DW      (1),
966                         .SwAccess(prim_subreg_pkg::SwAccessRO),
967                         .RESVAL  (1'h0),
968                         .Mubi    (1'b0)
969                       ) u_csr5_field4 (
970                         .clk_i   (clk_i),
971                         .rst_ni  (rst_ni),
972                     
973                         // from register interface
974                         .we     (1'b0),
975                         .wd     ('0),
976                     
977                         // from internal hardware
978                         .de     (hw2reg.csr5.field4.de),
979                         .d      (hw2reg.csr5.field4.d),
980                     
981                         // to internal hardware
982                         .qe     (),
983                         .q      (reg2hw.csr5.field4.q),
984                         .ds     (),
985                     
986                         // to register interface (read)
987                         .qs     (csr5_field4_qs)
988                       );
989                     
990                       //   F[field5]: 13:13
991                       prim_subreg #(
992                         .DW      (1),
993                         .SwAccess(prim_subreg_pkg::SwAccessRO),
994                         .RESVAL  (1'h0),
995                         .Mubi    (1'b0)
996                       ) u_csr5_field5 (
997                         .clk_i   (clk_i),
998                         .rst_ni  (rst_ni),
999                     
1000                        // from register interface
1001                        .we     (1'b0),
1002                        .wd     ('0),
1003                    
1004                        // from internal hardware
1005                        .de     (hw2reg.csr5.field5.de),
1006                        .d      (hw2reg.csr5.field5.d),
1007                    
1008                        // to internal hardware
1009                        .qe     (),
1010                        .q      (reg2hw.csr5.field5.q),
1011                        .ds     (),
1012                    
1013                        // to register interface (read)
1014                        .qs     (csr5_field5_qs)
1015                      );
1016                    
1017                      //   F[field6]: 31:16
1018                      prim_subreg #(
1019                        .DW      (16),
1020                        .SwAccess(prim_subreg_pkg::SwAccessRW),
1021                        .RESVAL  (16'h0),
1022                        .Mubi    (1'b0)
1023                      ) u_csr5_field6 (
1024                        .clk_i   (clk_i),
1025                        .rst_ni  (rst_ni),
1026                    
1027                        // from register interface
1028                        .we     (csr5_we),
1029                        .wd     (csr5_field6_wd),
1030                    
1031                        // from internal hardware
1032                        .de     (hw2reg.csr5.field6.de),
1033                        .d      (hw2reg.csr5.field6.d),
1034                    
1035                        // to internal hardware
1036                        .qe     (),
1037                        .q      (reg2hw.csr5.field6.q),
1038                        .ds     (),
1039                    
1040                        // to register interface (read)
1041                        .qs     (csr5_field6_qs)
1042                      );
1043                    
1044                    
1045                      // R[csr6]: V(False)
1046                      //   F[field0]: 9:0
1047                      prim_subreg #(
1048                        .DW      (10),
1049                        .SwAccess(prim_subreg_pkg::SwAccessRW),
1050                        .RESVAL  (10'h0),
1051                        .Mubi    (1'b0)
1052                      ) u_csr6_field0 (
1053                        .clk_i   (clk_i),
1054                        .rst_ni  (rst_ni),
1055                    
1056                        // from register interface
1057                        .we     (csr6_we),
1058                        .wd     (csr6_field0_wd),
1059                    
1060                        // from internal hardware
1061                        .de     (1'b0),
1062                        .d      ('0),
1063                    
1064                        // to internal hardware
1065                        .qe     (),
1066                        .q      (reg2hw.csr6.field0.q),
1067                        .ds     (),
1068                    
1069                        // to register interface (read)
1070                        .qs     (csr6_field0_qs)
1071                      );
1072                    
1073                      //   F[field1]: 11:11
1074                      prim_subreg #(
1075                        .DW      (1),
1076                        .SwAccess(prim_subreg_pkg::SwAccessRW),
1077                        .RESVAL  (1'h0),
1078                        .Mubi    (1'b0)
1079                      ) u_csr6_field1 (
1080                        .clk_i   (clk_i),
1081                        .rst_ni  (rst_ni),
1082                    
1083                        // from register interface
1084                        .we     (csr6_we),
1085                        .wd     (csr6_field1_wd),
1086                    
1087                        // from internal hardware
1088                        .de     (1'b0),
1089                        .d      ('0),
1090                    
1091                        // to internal hardware
1092                        .qe     (),
1093                        .q      (reg2hw.csr6.field1.q),
1094                        .ds     (),
1095                    
1096                        // to register interface (read)
1097                        .qs     (csr6_field1_qs)
1098                      );
1099                    
1100                      //   F[field2]: 12:12
1101                      prim_subreg #(
1102                        .DW      (1),
1103                        .SwAccess(prim_subreg_pkg::SwAccessRW),
1104                        .RESVAL  (1'h0),
1105                        .Mubi    (1'b0)
1106                      ) u_csr6_field2 (
1107                        .clk_i   (clk_i),
1108                        .rst_ni  (rst_ni),
1109                    
1110                        // from register interface
1111                        .we     (csr6_we),
1112                        .wd     (csr6_field2_wd),
1113                    
1114                        // from internal hardware
1115                        .de     (1'b0),
1116                        .d      ('0),
1117                    
1118                        // to internal hardware
1119                        .qe     (),
1120                        .q      (reg2hw.csr6.field2.q),
1121                        .ds     (),
1122                    
1123                        // to register interface (read)
1124                        .qs     (csr6_field2_qs)
1125                      );
1126                    
1127                      //   F[field3]: 31:16
1128                      prim_subreg #(
1129                        .DW      (16),
1130                        .SwAccess(prim_subreg_pkg::SwAccessRW),
1131                        .RESVAL  (16'h0),
1132                        .Mubi    (1'b0)
1133                      ) u_csr6_field3 (
1134                        .clk_i   (clk_i),
1135                        .rst_ni  (rst_ni),
1136                    
1137                        // from register interface
1138                        .we     (csr6_we),
1139                        .wd     (csr6_field3_wd),
1140                    
1141                        // from internal hardware
1142                        .de     (1'b0),
1143                        .d      ('0),
1144                    
1145                        // to internal hardware
1146                        .qe     (),
1147                        .q      (reg2hw.csr6.field3.q),
1148                        .ds     (),
1149                    
1150                        // to register interface (read)
1151                        .qs     (csr6_field3_qs)
1152                      );
1153                    
1154                    
1155                      // R[csr7]: V(False)
1156                      //   F[field0]: 5:0
1157                      prim_subreg #(
1158                        .DW      (6),
1159                        .SwAccess(prim_subreg_pkg::SwAccessRO),
1160                        .RESVAL  (6'h0),
1161                        .Mubi    (1'b0)
1162                      ) u_csr7_field0 (
1163                        .clk_i   (clk_i),
1164                        .rst_ni  (rst_ni),
1165                    
1166                        // from register interface
1167                        .we     (1'b0),
1168                        .wd     ('0),
1169                    
1170                        // from internal hardware
1171                        .de     (hw2reg.csr7.field0.de),
1172                        .d      (hw2reg.csr7.field0.d),
1173                    
1174                        // to internal hardware
1175                        .qe     (),
1176                        .q      (reg2hw.csr7.field0.q),
1177                        .ds     (),
1178                    
1179                        // to register interface (read)
1180                        .qs     (csr7_field0_qs)
1181                      );
1182                    
1183                      //   F[field1]: 10:8
1184                      prim_subreg #(
1185                        .DW      (3),
1186                        .SwAccess(prim_subreg_pkg::SwAccessRO),
1187                        .RESVAL  (3'h0),
1188                        .Mubi    (1'b0)
1189                      ) u_csr7_field1 (
1190                        .clk_i   (clk_i),
1191                        .rst_ni  (rst_ni),
1192                    
1193                        // from register interface
1194                        .we     (1'b0),
1195                        .wd     ('0),
1196                    
1197                        // from internal hardware
1198                        .de     (hw2reg.csr7.field1.de),
1199                        .d      (hw2reg.csr7.field1.d),
1200                    
1201                        // to internal hardware
1202                        .qe     (),
1203                        .q      (reg2hw.csr7.field1.q),
1204                        .ds     (),
1205                    
1206                        // to register interface (read)
1207                        .qs     (csr7_field1_qs)
1208                      );
1209                    
1210                      //   F[field2]: 14:14
1211                      prim_subreg #(
1212                        .DW      (1),
1213                        .SwAccess(prim_subreg_pkg::SwAccessRO),
1214                        .RESVAL  (1'h0),
1215                        .Mubi    (1'b0)
1216                      ) u_csr7_field2 (
1217                        .clk_i   (clk_i),
1218                        .rst_ni  (rst_ni),
1219                    
1220                        // from register interface
1221                        .we     (1'b0),
1222                        .wd     ('0),
1223                    
1224                        // from internal hardware
1225                        .de     (hw2reg.csr7.field2.de),
1226                        .d      (hw2reg.csr7.field2.d),
1227                    
1228                        // to internal hardware
1229                        .qe     (),
1230                        .q      (reg2hw.csr7.field2.q),
1231                        .ds     (),
1232                    
1233                        // to register interface (read)
1234                        .qs     (csr7_field2_qs)
1235                      );
1236                    
1237                      //   F[field3]: 15:15
1238                      prim_subreg #(
1239                        .DW      (1),
1240                        .SwAccess(prim_subreg_pkg::SwAccessRO),
1241                        .RESVAL  (1'h0),
1242                        .Mubi    (1'b0)
1243                      ) u_csr7_field3 (
1244                        .clk_i   (clk_i),
1245                        .rst_ni  (rst_ni),
1246                    
1247                        // from register interface
1248                        .we     (1'b0),
1249                        .wd     ('0),
1250                    
1251                        // from internal hardware
1252                        .de     (hw2reg.csr7.field3.de),
1253                        .d      (hw2reg.csr7.field3.d),
1254                    
1255                        // to internal hardware
1256                        .qe     (),
1257                        .q      (reg2hw.csr7.field3.q),
1258                        .ds     (),
1259                    
1260                        // to register interface (read)
1261                        .qs     (csr7_field3_qs)
1262                      );
1263                    
1264                    
1265                    
1266                      logic [7:0] addr_hit;
1267                      always_comb begin
1268       1/1              addr_hit = '0;
           Tests:       T1 T2 T3 
1269       1/1              addr_hit[0] = (reg_addr == OTP_CTRL_CSR0_OFFSET);
           Tests:       T1 T2 T3 
1270       1/1              addr_hit[1] = (reg_addr == OTP_CTRL_CSR1_OFFSET);
           Tests:       T1 T2 T3 
1271       1/1              addr_hit[2] = (reg_addr == OTP_CTRL_CSR2_OFFSET);
           Tests:       T1 T2 T3 
1272       1/1              addr_hit[3] = (reg_addr == OTP_CTRL_CSR3_OFFSET);
           Tests:       T1 T2 T3 
1273       1/1              addr_hit[4] = (reg_addr == OTP_CTRL_CSR4_OFFSET);
           Tests:       T1 T2 T3 
1274       1/1              addr_hit[5] = (reg_addr == OTP_CTRL_CSR5_OFFSET);
           Tests:       T1 T2 T3 
1275       1/1              addr_hit[6] = (reg_addr == OTP_CTRL_CSR6_OFFSET);
           Tests:       T1 T2 T3 
1276       1/1              addr_hit[7] = (reg_addr == OTP_CTRL_CSR7_OFFSET);
           Tests:       T1 T2 T3 
1277                      end
1278                    
1279       1/1            assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
           Tests:       T1 T2 T3 
1280                    
1281                      // Check sub-word write is permitted
1282                      always_comb begin
1283       1/1              wr_err = (reg_we &
           Tests:       T1 T2 T3 
1284                                  ((addr_hit[0] & (|(OTP_CTRL_PRIM_PERMIT[0] & ~reg_be))) |
1285                                   (addr_hit[1] & (|(OTP_CTRL_PRIM_PERMIT[1] & ~reg_be))) |
1286                                   (addr_hit[2] & (|(OTP_CTRL_PRIM_PERMIT[2] & ~reg_be))) |
1287                                   (addr_hit[3] & (|(OTP_CTRL_PRIM_PERMIT[3] & ~reg_be))) |
1288                                   (addr_hit[4] & (|(OTP_CTRL_PRIM_PERMIT[4] & ~reg_be))) |
1289                                   (addr_hit[5] & (|(OTP_CTRL_PRIM_PERMIT[5] & ~reg_be))) |
1290                                   (addr_hit[6] & (|(OTP_CTRL_PRIM_PERMIT[6] & ~reg_be))) |
1291                                   (addr_hit[7] & (|(OTP_CTRL_PRIM_PERMIT[7] & ~reg_be)))));
1292                      end
1293                    
1294                      // Generate write-enables
1295       1/1            assign csr0_we = addr_hit[0] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1296                    
1297       1/1            assign csr0_field0_wd = reg_wdata[0];
           Tests:       T1 T2 T3 
1298                    
1299       1/1            assign csr0_field1_wd = reg_wdata[1];
           Tests:       T1 T2 T3 
1300                    
1301       1/1            assign csr0_field2_wd = reg_wdata[2];
           Tests:       T1 T2 T3 
1302                    
1303       1/1            assign csr0_field3_wd = reg_wdata[13:4];
           Tests:       T1 T2 T3 
1304                    
1305       1/1            assign csr0_field4_wd = reg_wdata[26:16];
           Tests:       T1 T2 T3 
1306       1/1            assign csr1_we = addr_hit[1] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1307                    
1308       1/1            assign csr1_field0_wd = reg_wdata[6:0];
           Tests:       T1 T2 T3 
1309                    
1310       1/1            assign csr1_field1_wd = reg_wdata[7];
           Tests:       T1 T2 T3 
1311                    
1312       1/1            assign csr1_field2_wd = reg_wdata[14:8];
           Tests:       T1 T2 T3 
1313                    
1314       1/1            assign csr1_field3_wd = reg_wdata[15];
           Tests:       T1 T2 T3 
1315                    
1316       1/1            assign csr1_field4_wd = reg_wdata[31:16];
           Tests:       T1 T2 T3 
1317       1/1            assign csr2_we = addr_hit[2] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1318                    
1319       1/1            assign csr2_wd = reg_wdata[0];
           Tests:       T1 T2 T3 
1320       1/1            assign csr3_we = addr_hit[3] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1321                    
1322       1/1            assign csr3_field0_wd = reg_wdata[2:0];
           Tests:       T1 T2 T3 
1323                    
1324       1/1            assign csr3_field1_wd = reg_wdata[13:4];
           Tests:       T1 T2 T3 
1325                    
1326       1/1            assign csr3_field2_wd = reg_wdata[16];
           Tests:       T1 T2 T3 
1327       1/1            assign csr4_we = addr_hit[4] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1328                    
1329       1/1            assign csr4_field0_wd = reg_wdata[9:0];
           Tests:       T1 T2 T3 
1330                    
1331       1/1            assign csr4_field1_wd = reg_wdata[12];
           Tests:       T1 T2 T3 
1332                    
1333       1/1            assign csr4_field2_wd = reg_wdata[13];
           Tests:       T1 T2 T3 
1334                    
1335       1/1            assign csr4_field3_wd = reg_wdata[14];
           Tests:       T1 T2 T3 
1336       1/1            assign csr5_we = addr_hit[5] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1337                    
1338       1/1            assign csr5_field0_wd = reg_wdata[5:0];
           Tests:       T1 T2 T3 
1339                    
1340       1/1            assign csr5_field1_wd = reg_wdata[7:6];
           Tests:       T1 T2 T3 
1341                    
1342       1/1            assign csr5_field6_wd = reg_wdata[31:16];
           Tests:       T1 T2 T3 
1343       1/1            assign csr6_we = addr_hit[6] & reg_we & !reg_error;
           Tests:       T1 T2 T3 
1344                    
1345       1/1            assign csr6_field0_wd = reg_wdata[9:0];
           Tests:       T1 T2 T3 
1346                    
1347       1/1            assign csr6_field1_wd = reg_wdata[11];
           Tests:       T1 T2 T3 
1348                    
1349       1/1            assign csr6_field2_wd = reg_wdata[12];
           Tests:       T1 T2 T3 
1350                    
1351       1/1            assign csr6_field3_wd = reg_wdata[31:16];
           Tests:       T1 T2 T3 
1352                    
1353                      // Assign write-enables to checker logic vector.
1354                      always_comb begin
1355       1/1              reg_we_check = '0;
           Tests:       T1 T2 T3 
1356       1/1              reg_we_check[0] = csr0_we;
           Tests:       T1 T2 T3 
1357       1/1              reg_we_check[1] = csr1_we;
           Tests:       T1 T2 T3 
1358       1/1              reg_we_check[2] = csr2_we;
           Tests:       T1 T2 T3 
1359       1/1              reg_we_check[3] = csr3_we;
           Tests:       T1 T2 T3 
1360       1/1              reg_we_check[4] = csr4_we;
           Tests:       T1 T2 T3 
1361       1/1              reg_we_check[5] = csr5_we;
           Tests:       T1 T2 T3 
1362       1/1              reg_we_check[6] = csr6_we;
           Tests:       T1 T2 T3 
1363       1/1              reg_we_check[7] = 1'b0;
           Tests:       T1 T2 T3 
1364                      end
1365                    
1366                      // Read data return
1367                      always_comb begin
1368       1/1              reg_rdata_next = '0;
           Tests:       T1 T2 T3 
1369       1/1              unique case (1'b1)
           Tests:       T1 T2 T3 
1370                          addr_hit[0]: begin
1371       1/1                  reg_rdata_next[0] = csr0_field0_qs;
           Tests:       T1 T2 T3 
1372       1/1                  reg_rdata_next[1] = csr0_field1_qs;
           Tests:       T1 T2 T3 
1373       1/1                  reg_rdata_next[2] = csr0_field2_qs;
           Tests:       T1 T2 T3 
1374       1/1                  reg_rdata_next[13:4] = csr0_field3_qs;
           Tests:       T1 T2 T3 
1375       1/1                  reg_rdata_next[26:16] = csr0_field4_qs;
           Tests:       T1 T2 T3 
1376                          end
1377                    
1378                          addr_hit[1]: begin
1379       1/1                  reg_rdata_next[6:0] = csr1_field0_qs;
           Tests:       T10 T17 T18 
1380       1/1                  reg_rdata_next[7] = csr1_field1_qs;
           Tests:       T10 T17 T18 
1381       1/1                  reg_rdata_next[14:8] = csr1_field2_qs;
           Tests:       T10 T17 T18 
1382       1/1                  reg_rdata_next[15] = csr1_field3_qs;
           Tests:       T10 T17 T18 
1383       1/1                  reg_rdata_next[31:16] = csr1_field4_qs;
           Tests:       T10 T17 T18 
1384                          end
1385                    
1386                          addr_hit[2]: begin
1387       1/1                  reg_rdata_next[0] = csr2_qs;
           Tests:       T10 T17 T18 
1388                          end
1389                    
1390                          addr_hit[3]: begin
1391       1/1                  reg_rdata_next[2:0] = csr3_field0_qs;
           Tests:       T10 T17 T18 
1392       1/1                  reg_rdata_next[13:4] = csr3_field1_qs;
           Tests:       T10 T17 T18 
1393       1/1                  reg_rdata_next[16] = csr3_field2_qs;
           Tests:       T10 T17 T18 
1394       1/1                  reg_rdata_next[17] = csr3_field3_qs;
           Tests:       T10 T17 T18 
1395       1/1                  reg_rdata_next[18] = csr3_field4_qs;
           Tests:       T10 T17 T18 
1396       1/1                  reg_rdata_next[19] = csr3_field5_qs;
           Tests:       T10 T17 T18 
1397       1/1                  reg_rdata_next[20] = csr3_field6_qs;
           Tests:       T10 T17 T18 
1398       1/1                  reg_rdata_next[21] = csr3_field7_qs;
           Tests:       T10 T17 T18 
1399       1/1                  reg_rdata_next[22] = csr3_field8_qs;
           Tests:       T10 T17 T18 
1400                          end
1401                    
1402                          addr_hit[4]: begin
1403       1/1                  reg_rdata_next[9:0] = csr4_field0_qs;
           Tests:       T10 T17 T18 
1404       1/1                  reg_rdata_next[12] = csr4_field1_qs;
           Tests:       T10 T17 T18 
1405       1/1                  reg_rdata_next[13] = csr4_field2_qs;
           Tests:       T10 T17 T18 
1406       1/1                  reg_rdata_next[14] = csr4_field3_qs;
           Tests:       T10 T17 T18 
1407                          end
1408                    
1409                          addr_hit[5]: begin
1410       1/1                  reg_rdata_next[5:0] = csr5_field0_qs;
           Tests:       T10 T17 T18 
1411       1/1                  reg_rdata_next[7:6] = csr5_field1_qs;
           Tests:       T10 T17 T18 
1412       1/1                  reg_rdata_next[8] = csr5_field2_qs;
           Tests:       T10 T17 T18 
1413       1/1                  reg_rdata_next[11:9] = csr5_field3_qs;
           Tests:       T10 T17 T18 
1414       1/1                  reg_rdata_next[12] = csr5_field4_qs;
           Tests:       T10 T17 T18 
1415       1/1                  reg_rdata_next[13] = csr5_field5_qs;
           Tests:       T10 T17 T18 
1416       1/1                  reg_rdata_next[31:16] = csr5_field6_qs;
           Tests:       T10 T17 T18 
1417                          end
1418                    
1419                          addr_hit[6]: begin
1420       1/1                  reg_rdata_next[9:0] = csr6_field0_qs;
           Tests:       T10 T17 T18 
1421       1/1                  reg_rdata_next[11] = csr6_field1_qs;
           Tests:       T10 T17 T18 
1422       1/1                  reg_rdata_next[12] = csr6_field2_qs;
           Tests:       T10 T17 T18 
1423       1/1                  reg_rdata_next[31:16] = csr6_field3_qs;
           Tests:       T10 T17 T18 
1424                          end
1425                    
1426                          addr_hit[7]: begin
1427       1/1                  reg_rdata_next[5:0] = csr7_field0_qs;
           Tests:       T10 T17 T18 
1428       1/1                  reg_rdata_next[10:8] = csr7_field1_qs;
           Tests:       T10 T17 T18 
1429       1/1                  reg_rdata_next[14] = csr7_field2_qs;
           Tests:       T10 T17 T18 
1430       1/1                  reg_rdata_next[15] = csr7_field3_qs;
           Tests:       T10 T17 T18 
1431                          end
1432                    
1433                          default: begin
1434                            reg_rdata_next = '1;
1435                          end
1436                        endcase
1437                      end
1438                    
1439                      // shadow busy
1440                      logic shadow_busy;
1441                      assign shadow_busy = 1'b0;
1442                    
1443                      // register busy
1444       unreachable    assign reg_busy = shadow_busy;
1445                    
1446                      // Unused signal tieoff
1447                    
1448                      // wdata / byte enable are not always fully used
1449                      // add a blanket unused statement to handle lint waivers
1450                      logic unused_wdata;
1451                      logic unused_be;
1452       1/1            assign unused_wdata = ^reg_wdata;
           Tests:       T1 T2 T3 
1453       1/1            assign unused_be = ^reg_be;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top
TotalCoveredPercent
Conditions9797100.00
Logical9797100.00
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT17,T19,T20 

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT26,T27,T28
10CoveredT278,T279,T280 

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT26,T27,T28
010CoveredT278,T279,T280
100CoveredT26,T27,T28 

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTestsExclude Annotation
000CoveredT1,T2,T3
001CoveredT278,T279,T280
010CoveredT14,T15,T16
100Excluded VC_COV_UNR 

 LINE       1269
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR0_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT10,T17,T18
1CoveredT1,T2,T3 

 LINE       1270
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR1_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1271
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR2_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1272
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR3_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1273
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR4_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1274
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR5_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1275
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR6_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1276
 EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR7_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1279
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T19,T20 

 LINE       1279
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T19,T20
10CoveredT17,T19,T20 

 LINE       1283
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT14,T15,T16 

 LINE       1283
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))))
-1--2--3--4--5--6--7--8-StatusTests
00000000CoveredT17,T19,T20
00000001CoveredT17,T20,T151
00000010CoveredT17,T20,T151
00000100CoveredT17,T20,T151
00001000CoveredT17,T20,T151
00010000CoveredT17,T20,T151
00100000CoveredT17,T20,T151
01000000CoveredT17,T20,T151
10000000CoveredT1,T2,T3 

 LINE       1283
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T20,T151
10CoveredT17,T19,T20
11CoveredT1,T2,T3 

 LINE       1283
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT17,T20,T151 

 LINE       1283
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT17,T20,T151 

 LINE       1283
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT17,T20,T151 

 LINE       1283
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T151
11CoveredT17,T20,T151 

 LINE       1283
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT17,T20,T151 

 LINE       1283
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT17,T20,T151 

 LINE       1283
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T19,T20
11CoveredT17,T20,T151 

 LINE       1295
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT1,T2,T3
110CoveredT14,T15,T16
111CoveredT17,T19,T20 

 LINE       1306
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT17,T19,T20
110CoveredT15,T16,T21
111CoveredT17,T19,T20 

 LINE       1317
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT17,T19,T20
110CoveredT15,T16,T21
111CoveredT19,T20,T151 

 LINE       1320
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT17,T19,T20
110CoveredT15,T16,T24
111CoveredT17,T19,T20 

 LINE       1327
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT17,T19,T20
110CoveredT15,T16,T21
111CoveredT17,T19,T139 

 LINE       1336
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT17,T19,T20
110CoveredT15,T16,T25
111CoveredT17,T19,T20 

 LINE       1343
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT17,T19,T20
101CoveredT17,T19,T20
110CoveredT15,T16,T21
111CoveredT17,T19,T20
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 1279 2 2 100.00
IF 68 3 3 100.00
CASE 1369 9 9 100.00 



1279         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:
-1-StatusTests
1 Covered T17,T19,T20
0 Covered T1,T2,T3 



68             if (!rst_ni) begin
               -1-  
69               err_q <= '0;
                 ==>
70             end else if (intg_err || reg_we_err) begin
                        -2-  
71               err_q <= 1'b1;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T26,T27,T28
0 0 Covered T1,T2,T3 



1369           unique case (1'b1)
                      -1-  
1370             addr_hit[0]: begin
1371               reg_rdata_next[0] = csr0_field0_qs;
                   ==>
1372               reg_rdata_next[1] = csr0_field1_qs;
1373               reg_rdata_next[2] = csr0_field2_qs;
1374               reg_rdata_next[13:4] = csr0_field3_qs;
1375               reg_rdata_next[26:16] = csr0_field4_qs;
1376             end
1377       
1378             addr_hit[1]: begin
1379               reg_rdata_next[6:0] = csr1_field0_qs;
                   ==>
1380               reg_rdata_next[7] = csr1_field1_qs;
1381               reg_rdata_next[14:8] = csr1_field2_qs;
1382               reg_rdata_next[15] = csr1_field3_qs;
1383               reg_rdata_next[31:16] = csr1_field4_qs;
1384             end
1385       
1386             addr_hit[2]: begin
1387               reg_rdata_next[0] = csr2_qs;
                   ==>
1388             end
1389       
1390             addr_hit[3]: begin
1391               reg_rdata_next[2:0] = csr3_field0_qs;
                   ==>
1392               reg_rdata_next[13:4] = csr3_field1_qs;
1393               reg_rdata_next[16] = csr3_field2_qs;
1394               reg_rdata_next[17] = csr3_field3_qs;
1395               reg_rdata_next[18] = csr3_field4_qs;
1396               reg_rdata_next[19] = csr3_field5_qs;
1397               reg_rdata_next[20] = csr3_field6_qs;
1398               reg_rdata_next[21] = csr3_field7_qs;
1399               reg_rdata_next[22] = csr3_field8_qs;
1400             end
1401       
1402             addr_hit[4]: begin
1403               reg_rdata_next[9:0] = csr4_field0_qs;
                   ==>
1404               reg_rdata_next[12] = csr4_field1_qs;
1405               reg_rdata_next[13] = csr4_field2_qs;
1406               reg_rdata_next[14] = csr4_field3_qs;
1407             end
1408       
1409             addr_hit[5]: begin
1410               reg_rdata_next[5:0] = csr5_field0_qs;
                   ==>
1411               reg_rdata_next[7:6] = csr5_field1_qs;
1412               reg_rdata_next[8] = csr5_field2_qs;
1413               reg_rdata_next[11:9] = csr5_field3_qs;
1414               reg_rdata_next[12] = csr5_field4_qs;
1415               reg_rdata_next[13] = csr5_field5_qs;
1416               reg_rdata_next[31:16] = csr5_field6_qs;
1417             end
1418       
1419             addr_hit[6]: begin
1420               reg_rdata_next[9:0] = csr6_field0_qs;
                   ==>
1421               reg_rdata_next[11] = csr6_field1_qs;
1422               reg_rdata_next[12] = csr6_field2_qs;
1423               reg_rdata_next[31:16] = csr6_field3_qs;
1424             end
1425       
1426             addr_hit[7]: begin
1427               reg_rdata_next[5:0] = csr7_field0_qs;
                   ==>
1428               reg_rdata_next[10:8] = csr7_field1_qs;
1429               reg_rdata_next[14] = csr7_field2_qs;
1430               reg_rdata_next[15] = csr7_field3_qs;
1431             end
1432       
1433             default: begin
1434               reg_rdata_next = '1;
                   ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T10,T17,T18
addr_hit[2] Covered T10,T17,T18
addr_hit[3] Covered T10,T17,T18
addr_hit[4] Covered T10,T17,T18
addr_hit[5] Covered T10,T17,T18
addr_hit[6] Covered T10,T17,T18
addr_hit[7] Covered T10,T17,T18
default Covered T10,T18,T19

Assert Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 91185948 36787 0 0
reAfterRv 91185948 36787 0 0
rePulse 91185948 22562 0 0
wePulse 91185948 14225 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 91185948 36787 0 0
T14 0 40 0 0
T15 0 158 0 0
T17 77151 52 0 0
T19 0 40 0 0
T20 0 34 0 0
T93 91589 0 0 0
T97 30986 0 0 0
T98 37909 0 0 0
T101 14706 0 0 0
T102 30181 0 0 0
T105 44569 0 0 0
T127 59995 0 0 0
T128 14105 0 0 0
T129 33379 0 0 0
T135 0 54 0 0
T139 0 48 0 0
T151 0 20 0 0
T192 0 36 0 0
T287 0 108 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 91185948 36787 0 0
T14 0 40 0 0
T15 0 158 0 0
T17 77151 52 0 0
T19 0 40 0 0
T20 0 34 0 0
T93 91589 0 0 0
T97 30986 0 0 0
T98 37909 0 0 0
T101 14706 0 0 0
T102 30181 0 0 0
T105 44569 0 0 0
T127 59995 0 0 0
T128 14105 0 0 0
T129 33379 0 0 0
T135 0 54 0 0
T139 0 48 0 0
T151 0 20 0 0
T192 0 36 0 0
T287 0 108 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 91185948 22562 0 0
T14 0 39 0 0
T15 0 85 0 0
T17 77151 26 0 0
T19 0 20 0 0
T20 0 17 0 0
T93 91589 0 0 0
T97 30986 0 0 0
T98 37909 0 0 0
T101 14706 0 0 0
T102 30181 0 0 0
T105 44569 0 0 0
T127 59995 0 0 0
T128 14105 0 0 0
T129 33379 0 0 0
T135 0 27 0 0
T139 0 24 0 0
T151 0 10 0 0
T192 0 18 0 0
T287 0 54 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 91185948 14225 0 0
T14 0 1 0 0
T15 0 73 0 0
T17 77151 26 0 0
T19 0 20 0 0
T20 0 17 0 0
T93 91589 0 0 0
T97 30986 0 0 0
T98 37909 0 0 0
T101 14706 0 0 0
T102 30181 0 0 0
T105 44569 0 0 0
T127 59995 0 0 0
T128 14105 0 0 0
T129 33379 0 0 0
T135 0 27 0 0
T139 0 24 0 0
T151 0 10 0 0
T192 0 18 0 0
T287 0 54 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%