Module Definition
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Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :
SCORELINE
91.41 96.51
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
TOTAL938389.25
CONT_ASSIGN13811100.00
ALWAYS15333100.00
ALWAYS164685885.29
CONT_ASSIGN33411100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN45411100.00
ALWAYS46133100.00
ALWAYS46488100.00

137 // Output partition error state. 138 1/1 assign error_o = error_q; Tests: T1 T2 T3  139 140 // This partition cannot do any write accesses, hence we tie this 141 // constantly off. 142 assign otp_wdata_o = '0; 143 // Depending on the partition configuration, the wrapper is instructed to ignore integrity 144 // calculations and checks. To be on the safe side, the partition filters error responses at this 145 // point and does not report any integrity errors if integrity is disabled. 146 otp_err_e otp_err; 147 if (Info.integrity) begin : gen_integrity 148 assign otp_cmd_o = prim_otp_pkg::Read; 149 assign otp_err = otp_err_e'(otp_err_i); 150 end else begin : gen_no_integrity 151 assign otp_cmd_o = prim_otp_pkg::ReadRaw; 152 always_comb begin 153 1/1 if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin Tests: T1 T2 T3  154 1/1 otp_err = NoError; Tests: T3 T99 T94  155 end else begin 156 1/1 otp_err = otp_err_e'(otp_err_i); Tests: T1 T2 T3  157 end 158 end 159 end 160 161 `ASSERT_KNOWN(FsmStateKnown_A, state_q) 162 always_comb begin : p_fsm 163 // Default assignments 164 1/1 state_d = state_q; Tests: T1 T2 T3  165 166 // Response to init request 167 1/1 init_done_o = 1'b0; Tests: T1 T2 T3  168 169 // OTP signals 170 1/1 otp_req_o = 1'b0; Tests: T1 T2 T3  171 1/1 otp_addr_sel = DigestAddrSel; Tests: T1 T2 T3  172 173 // TL-UL signals 174 1/1 tlul_gnt_o = 1'b0; Tests: T1 T2 T3  175 1/1 tlul_rvalid_o = 1'b0; Tests: T1 T2 T3  176 1/1 tlul_rerror_o = '0; Tests: T1 T2 T3  177 178 // Enable for buffered digest register 179 1/1 digest_reg_en = 1'b0; Tests: T1 T2 T3  180 181 // Error Register 182 1/1 error_d = error_q; Tests: T1 T2 T3  183 1/1 pending_tlul_error_d = 1'b0; Tests: T1 T2 T3  184 1/1 fsm_err_o = 1'b0; Tests: T1 T2 T3  185 186 1/1 unique case (state_q) Tests: T1 T2 T3  187 /////////////////////////////////////////////////////////////////// 188 // State right after reset. Wait here until we get a an 189 // initialization request. 190 ResetSt: begin 191 1/1 if (init_req_i) begin Tests: T1 T2 T3  192 // If the partition does not have a digest, no initialization is necessary. 193 1/1 if (Info.sw_digest) begin Tests: T1 T2 T3  194 1/1 state_d = InitSt; Tests: T1 T2 T3  195 end else begin 196 unreachable state_d = IdleSt; 197 end 198 end MISSING_ELSE 199 end 200 /////////////////////////////////////////////////////////////////// 201 // Initialization reads out the digest only in unbuffered 202 // partitions. Wait here until the OTP request has been granted. 203 // And then wait until the OTP word comes back. 204 InitSt: begin 205 1/1 otp_req_o = 1'b1; Tests: T1 T2 T3  206 1/1 if (otp_gnt_i) begin Tests: T1 T2 T3  207 1/1 state_d = InitWaitSt; Tests: T1 T2 T3  208 end ==> MISSING_ELSE 209 end 210 /////////////////////////////////////////////////////////////////// 211 // Wait for OTP response and write to digest buffer register. In 212 // case an OTP transaction fails, latch the OTP error code and 213 // jump to a terminal error state. 214 InitWaitSt: begin 215 1/1 if (otp_rvalid_i) begin Tests: T1 T2 T3  216 1/1 digest_reg_en = 1'b1; Tests: T1 T2 T3  217 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin Tests: T1 T2 T3  218 1/1 state_d = IdleSt; Tests: T1 T2 T3  219 // At this point the only error that we could have gotten are correctable ECC errors. 220 1/1 if (otp_err != NoError) begin Tests: T1 T2 T3  221 0/1 ==> error_d = MacroEccCorrError; 222 end MISSING_ELSE 223 end else begin 224 0/1 ==> state_d = ErrorSt; 225 0/1 ==> error_d = otp_err; 226 end 227 end MISSING_ELSE 228 end 229 /////////////////////////////////////////////////////////////////// 230 // Wait for TL-UL requests coming in. 231 // Then latch address and go to readout state. 232 IdleSt: begin 233 1/1 init_done_o = 1'b1; Tests: T1 T2 T3  234 1/1 if (tlul_req_i) begin Tests: T1 T2 T3  235 1/1 error_d = NoError; // clear recoverable soft errors. Tests: T2 T3 T6  236 1/1 state_d = ReadSt; Tests: T2 T3 T6  237 1/1 tlul_gnt_o = 1'b1; Tests: T2 T3 T6  238 end MISSING_ELSE 239 end 240 /////////////////////////////////////////////////////////////////// 241 // If the address is out of bounds, or if the partition is 242 // locked, signal back a bus error. Note that such an error does 243 // not cause the partition to go into error state. Otherwise if 244 // these checks pass, an OTP word is requested. 245 ReadSt: begin 246 1/1 init_done_o = 1'b1; Tests: T2 T3 T6  247 // Double check the address range. 248 1/1 if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin Tests: T2 T3 T6  249 1/1 otp_req_o = 1'b1; Tests: T2 T3 T6  250 1/1 otp_addr_sel = DataAddrSel; Tests: T2 T3 T6  251 1/1 if (otp_gnt_i) begin Tests: T2 T3 T6  252 1/1 state_d = ReadWaitSt; Tests: T2 T3 T6  253 end MISSING_ELSE 254 end else begin 255 1/1 state_d = IdleSt; Tests: T94 T95 T148  256 1/1 error_d = AccessError; // Signal this error, but do not go into terminal error state. Tests: T94 T95 T148  257 1/1 tlul_rvalid_o = 1'b1; Tests: T94 T95 T148  258 1/1 tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error. Tests: T94 T95 T148  259 end 260 end 261 /////////////////////////////////////////////////////////////////// 262 // Wait for OTP response and release the TL-UL response. In 263 // case an OTP transaction fails, latch the OTP error code, 264 // signal a TL-Ul bus error and jump to a terminal error state. 265 ReadWaitSt: begin 266 1/1 init_done_o = 1'b1; Tests: T2 T3 T6  267 1/1 if (otp_rvalid_i) begin Tests: T2 T3 T6  268 1/1 tlul_rvalid_o = 1'b1; Tests: T2 T3 T6  269 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin Tests: T2 T3 T6  270 1/1 state_d = IdleSt; Tests: T2 T3 T6  271 // At this point the only error that we could have gotten are correctable ECC errors. 272 1/1 if (otp_err != NoError) begin Tests: T2 T3 T6  273 0/1 ==> error_d = MacroEccCorrError; 274 end MISSING_ELSE 275 end else begin 276 0/1 ==> state_d = ErrorSt; 277 0/1 ==> error_d = otp_err; 278 // This causes the TL-UL adapter to return a bus error. 279 0/1 ==> tlul_rerror_o = 2'b11; 280 end 281 end MISSING_ELSE 282 end 283 /////////////////////////////////////////////////////////////////// 284 // Terminal Error State. This locks access to the partition. 285 // Make sure the partition signals an error state if no error 286 // code has been latched so far. 287 ErrorSt: begin 288 1/1 if (error_q == NoError) begin Tests: T3 T4 T7  289 1/1 error_d = FsmStateError; Tests: T25 T26 T27  290 end MISSING_ELSE 291 292 // Return bus errors if there are pending TL-UL requests. 293 1/1 if (pending_tlul_error_q) begin Tests: T3 T4 T7  294 1/1 tlul_rerror_o = 2'b11; Tests: T94 T98 T9  295 1/1 tlul_rvalid_o = 1'b1; Tests: T94 T98 T9  296 1/1 end else if (tlul_req_i) begin Tests: T3 T4 T7  297 1/1 tlul_gnt_o = 1'b1; Tests: T94 T98 T9  298 1/1 pending_tlul_error_d = 1'b1; Tests: T94 T98 T9  299 end MISSING_ELSE 300 end 301 /////////////////////////////////////////////////////////////////// 302 // We should never get here. If we do (e.g. via a malicious 303 // glitch), error out immediately. 304 default: begin 305 state_d = ErrorSt; 306 fsm_err_o = 1'b1; 307 end 308 /////////////////////////////////////////////////////////////////// 309 endcase // state_q 310 311 // Unconditionally jump into the terminal error state in case of 312 // an ECC error or escalation, and lock access to the partition down. 313 // SEC_CM: PART.FSM.LOCAL_ESC 314 1/1 if (ecc_err) begin Tests: T1 T2 T3  315 0/1 ==> state_d = ErrorSt; 316 0/1 ==> if (state_q != ErrorSt) begin 317 0/1 ==> error_d = CheckFailError; 318 end ==> MISSING_ELSE 319 end MISSING_ELSE 320 // SEC_CM: PART.FSM.GLOBAL_ESC 321 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin Tests: T1 T2 T3  322 1/1 state_d = ErrorSt; Tests: T3 T4 T7  323 1/1 fsm_err_o = 1'b1; Tests: T3 T4 T7  324 1/1 if (state_q != ErrorSt) begin Tests: T3 T4 T7  325 1/1 error_d = FsmStateError; Tests: T3 T4 T7  326 end MISSING_ELSE 327 end MISSING_ELSE 328 end 329 330 /////////////////////////////////// 331 // Signals to/from TL-UL Adapter // 332 /////////////////////////////////// 333 334 1/1 assign tlul_addr_d = tlul_addr_i; Tests: T1 T2 T3  335 // Do not forward data in case of an error. 336 1/1 assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0; Tests: T1 T2 T3  337 338 if (Info.offset == 0) begin : gen_zero_offset 339 1/1 assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd; Tests: T1 T2 T3  340 341 end else begin : gen_nonzero_offset 342 assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset && 343 {1'b0, tlul_addr_q, 2'b00} < PartEnd; 344 end 345 346 // Note that OTP works on halfword (16bit) addresses, hence need to 347 // shift the addresses appropriately. 348 logic [OtpByteAddrWidth-1:0] addr_calc; 349 1/1 assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00}; Tests: T1 T2 T3  350 1/1 assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift]; Tests: T1 T2 T3  351 352 if (OtpAddrShift > 0) begin : gen_unused 353 logic unused_bits; 354 1/1 assign unused_bits = ^addr_calc[OtpAddrShift-1:0]; Tests: T1 T2 T3  355 end 356 357 // Request 32bit except in case of the digest. 358 1/1 assign otp_size_o = (otp_addr_sel == DigestAddrSel) ? Tests: T1 T2 T3  359 OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) : 360 OtpSizeWidth'(unsigned'(32 / OtpWidth - 1)); 361 362 //////////////// 363 // Digest Reg // 364 //////////////// 365 366 if (Info.sw_digest) begin : gen_ecc_reg 367 // SEC_CM: PART.DATA_REG.INTEGRITY 368 otp_ctrl_ecc_reg #( 369 .Width ( ScrmblBlockWidth ), 370 .Depth ( 1 ) 371 ) u_otp_ctrl_ecc_reg ( 372 .clk_i, 373 .rst_ni, 374 .wren_i ( digest_reg_en ), 375 .addr_i ( '0 ), 376 .wdata_i ( otp_rdata_i ), 377 .rdata_o ( ), 378 .data_o ( digest_o ), 379 .ecc_err_o ( ecc_err ) 380 ); 381 end else begin : gen_no_ecc_reg 382 logic unused_digest_reg_en; 383 logic unused_rdata; 384 assign unused_digest_reg_en = digest_reg_en; 385 assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case. 386 assign digest_o = '0; 387 assign ecc_err = 1'b0; 388 end 389 390 //////////////////////// 391 // DAI Access Control // 392 //////////////////////// 393 394 mubi8_t init_locked; 395 1/1 assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False; Tests: T1 T2 T3  396 397 // Aggregate all possible DAI write locks. The partition is also locked when uninitialized. 398 // Note that the locks are redundantly encoded values. 399 part_access_t access_pre; 400 prim_mubi8_sender #( 401 .AsyncOn(0) 402 ) u_prim_mubi8_sender_write_lock_pre ( 403 .clk_i, 404 .rst_ni, 405 .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)), 406 .mubi_o(access_pre.write_lock) 407 ); 408 prim_mubi8_sender #( 409 .AsyncOn(0) 410 ) u_prim_mubi8_sender_read_lock_pre ( 411 .clk_i, 412 .rst_ni, 413 .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)), 414 .mubi_o(access_pre.read_lock) 415 ); 416 417 // SEC_CM: PART.MEM.SW_UNWRITABLE 418 if (Info.write_lock) begin : gen_digest_write_lock 419 mubi8_t digest_locked; 420 1/1 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; Tests: T1 T2 T3  421 422 // This prevents the synthesis tool from optimizing the multibit signal. 423 prim_mubi8_sender #( 424 .AsyncOn(0) 425 ) u_prim_mubi8_sender_write_lock ( 426 .clk_i, 427 .rst_ni, 428 .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)), 429 .mubi_o(access_o.write_lock) 430 ); 431 432 `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock)) 433 end else begin : gen_no_digest_write_lock 434 assign access_o.write_lock = access_pre.write_lock; 435 end 436 437 // SEC_CM: PART.MEM.SW_UNREADABLE 438 if (Info.read_lock) begin : gen_digest_read_lock 439 mubi8_t digest_locked; 440 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; 441 442 // This prevents the synthesis tool from optimizing the multibit signal. 443 prim_mubi8_sender #( 444 .AsyncOn(0) 445 ) u_prim_mubi8_sender_read_lock ( 446 .clk_i, 447 .rst_ni, 448 .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)), 449 .mubi_o(access_o.read_lock) 450 ); 451 452 `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock)) 453 end else begin : gen_no_digest_read_lock 454 1/1 assign access_o.read_lock = access_pre.read_lock; Tests: T1 T2 T3  455 end 456 457 /////////////// 458 // Registers // 459 /////////////// 460 461 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt): 461.1 `ifdef SIMULATION 461.2 prim_sparse_fsm_flop #( 461.3 .StateEnumT(state_e), 461.4 .Width($bits(state_e)), 461.5 .ResetValue($bits(state_e)'(ResetSt)), 461.6 .EnableAlertTriggerSVA(1), 461.7 .CustomForceName("state_q") 461.8 ) u_state_regs ( 461.9 .clk_i ( clk_i ), 461.10 .rst_ni ( rst_ni ), 461.11 .state_i ( state_d ), 461.12 .state_o ( ) 461.13 ); 461.14 always_ff @(posedge clk_i or negedge rst_ni) begin 461.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  461.16 1/1 state_q <= ResetSt; Tests: T1 T2 T3  461.17 end else begin 461.18 1/1 state_q <= state_d; Tests: T1 T2 T3  461.19 end 461.20 end 461.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 461.22 else begin 461.23 `ifdef UVM 461.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 461.25 "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1); 461.26 `else 461.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 461.28 `PRIM_STRINGIFY(u_state_regs_A)); 461.29 `endif 461.30 end 461.31 `else 461.32 prim_sparse_fsm_flop #( 461.33 .StateEnumT(state_e), 461.34 .Width($bits(state_e)), 461.35 .ResetValue($bits(state_e)'(ResetSt)), 461.36 .EnableAlertTriggerSVA(1) 461.37 ) u_state_regs ( 461.38 .clk_i ( `PRIM_FLOP_CLK ), 461.39 .rst_ni ( `PRIM_FLOP_RST ), 461.40 .state_i ( state_d ), 461.41 .state_o ( state_q ) 461.42 ); 461.43 `endif462 463 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 464 1/1 if (!rst_ni) begin Tests: T1 T2 T3  465 1/1 error_q <= NoError; Tests: T1 T2 T3  466 1/1 tlul_addr_q <= '0; Tests: T1 T2 T3  467 1/1 pending_tlul_error_q <= 1'b0; Tests: T1 T2 T3  468 end else begin 469 1/1 error_q <= error_d; Tests: T1 T2 T3  470 1/1 pending_tlul_error_q <= pending_tlul_error_d; Tests: T1 T2 T3  471 1/1 if (tlul_gnt_o) begin Tests: T1 T2 T3  472 1/1 tlul_addr_q <= tlul_addr_d; Tests: T2 T3 T6  473 end MISSING_ELSE

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134594644,DigestOffset=424,StateWidth=10 )
Line Coverage for Module self-instances :
SCORELINE
98.33 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
TOTAL9191100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14911100.00
ALWAYS1646868100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN45411100.00
ALWAYS46133100.00
ALWAYS46488100.00

137 // Output partition error state. 138 1/1 assign error_o = error_q; Tests: T1 T2 T3  139 140 // This partition cannot do any write accesses, hence we tie this 141 // constantly off. 142 assign otp_wdata_o = '0; 143 // Depending on the partition configuration, the wrapper is instructed to ignore integrity 144 // calculations and checks. To be on the safe side, the partition filters error responses at this 145 // point and does not report any integrity errors if integrity is disabled. 146 otp_err_e otp_err; 147 if (Info.integrity) begin : gen_integrity 148 assign otp_cmd_o = prim_otp_pkg::Read; 149 1/1 assign otp_err = otp_err_e'(otp_err_i); Tests: T1 T2 T3  150 end else begin : gen_no_integrity 151 assign otp_cmd_o = prim_otp_pkg::ReadRaw; 152 always_comb begin 153 if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin 154 otp_err = NoError; 155 end else begin 156 otp_err = otp_err_e'(otp_err_i); 157 end 158 end 159 end 160 161 `ASSERT_KNOWN(FsmStateKnown_A, state_q) 162 always_comb begin : p_fsm 163 // Default assignments 164 1/1 state_d = state_q; Tests: T1 T2 T3  165 166 // Response to init request 167 1/1 init_done_o = 1'b0; Tests: T1 T2 T3  168 169 // OTP signals 170 1/1 otp_req_o = 1'b0; Tests: T1 T2 T3  171 1/1 otp_addr_sel = DigestAddrSel; Tests: T1 T2 T3  172 173 // TL-UL signals 174 1/1 tlul_gnt_o = 1'b0; Tests: T1 T2 T3  175 1/1 tlul_rvalid_o = 1'b0; Tests: T1 T2 T3  176 1/1 tlul_rerror_o = '0; Tests: T1 T2 T3  177 178 // Enable for buffered digest register 179 1/1 digest_reg_en = 1'b0; Tests: T1 T2 T3  180 181 // Error Register 182 1/1 error_d = error_q; Tests: T1 T2 T3  183 1/1 pending_tlul_error_d = 1'b0; Tests: T1 T2 T3  184 1/1 fsm_err_o = 1'b0; Tests: T1 T2 T3  185 186 1/1 unique case (state_q) Tests: T1 T2 T3  187 /////////////////////////////////////////////////////////////////// 188 // State right after reset. Wait here until we get a an 189 // initialization request. 190 ResetSt: begin 191 1/1 if (init_req_i) begin Tests: T1 T2 T3  192 // If the partition does not have a digest, no initialization is necessary. 193 1/1 if (Info.sw_digest) begin Tests: T1 T2 T3  194 1/1 state_d = InitSt; Tests: T1 T2 T3  195 end else begin 196 unreachable state_d = IdleSt; 197 end 198 end MISSING_ELSE 199 end 200 /////////////////////////////////////////////////////////////////// 201 // Initialization reads out the digest only in unbuffered 202 // partitions. Wait here until the OTP request has been granted. 203 // And then wait until the OTP word comes back. 204 InitSt: begin 205 1/1 otp_req_o = 1'b1; Tests: T1 T2 T3  206 1/1 if (otp_gnt_i) begin Tests: T1 T2 T3  207 1/1 state_d = InitWaitSt; Tests: T1 T2 T3  208 end MISSING_ELSE 209 end 210 /////////////////////////////////////////////////////////////////// 211 // Wait for OTP response and write to digest buffer register. In 212 // case an OTP transaction fails, latch the OTP error code and 213 // jump to a terminal error state. 214 InitWaitSt: begin 215 1/1 if (otp_rvalid_i) begin Tests: T1 T2 T3  216 1/1 digest_reg_en = 1'b1; Tests: T1 T2 T3  217 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin Tests: T1 T2 T3  218 1/1 state_d = IdleSt; Tests: T1 T2 T3  219 // At this point the only error that we could have gotten are correctable ECC errors. 220 1/1 if (otp_err != NoError) begin Tests: T1 T2 T3  221 1/1 error_d = MacroEccCorrError; Tests: T149 T150 T42  222 end MISSING_ELSE 223 end else begin 224 1/1 state_d = ErrorSt; Tests: T3 T117 T151  225 1/1 error_d = otp_err; Tests: T3 T117 T151  226 end 227 end MISSING_ELSE 228 end 229 /////////////////////////////////////////////////////////////////// 230 // Wait for TL-UL requests coming in. 231 // Then latch address and go to readout state. 232 IdleSt: begin 233 1/1 init_done_o = 1'b1; Tests: T1 T2 T3  234 1/1 if (tlul_req_i) begin Tests: T1 T2 T3  235 1/1 error_d = NoError; // clear recoverable soft errors. Tests: T2 T3 T6  236 1/1 state_d = ReadSt; Tests: T2 T3 T6  237 1/1 tlul_gnt_o = 1'b1; Tests: T2 T3 T6  238 end MISSING_ELSE 239 end 240 /////////////////////////////////////////////////////////////////// 241 // If the address is out of bounds, or if the partition is 242 // locked, signal back a bus error. Note that such an error does 243 // not cause the partition to go into error state. Otherwise if 244 // these checks pass, an OTP word is requested. 245 ReadSt: begin 246 1/1 init_done_o = 1'b1; Tests: T2 T3 T6  247 // Double check the address range. 248 1/1 if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin Tests: T2 T3 T6  249 1/1 otp_req_o = 1'b1; Tests: T2 T3 T6  250 1/1 otp_addr_sel = DataAddrSel; Tests: T2 T3 T6  251 1/1 if (otp_gnt_i) begin Tests: T2 T3 T6  252 1/1 state_d = ReadWaitSt; Tests: T2 T3 T6  253 end MISSING_ELSE 254 end else begin 255 1/1 state_d = IdleSt; Tests: T94 T121 T18  256 1/1 error_d = AccessError; // Signal this error, but do not go into terminal error state. Tests: T94 T121 T18  257 1/1 tlul_rvalid_o = 1'b1; Tests: T94 T121 T18  258 1/1 tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error. Tests: T94 T121 T18  259 end 260 end 261 /////////////////////////////////////////////////////////////////// 262 // Wait for OTP response and release the TL-UL response. In 263 // case an OTP transaction fails, latch the OTP error code, 264 // signal a TL-Ul bus error and jump to a terminal error state. 265 ReadWaitSt: begin 266 1/1 init_done_o = 1'b1; Tests: T2 T3 T6  267 1/1 if (otp_rvalid_i) begin Tests: T2 T3 T6  268 1/1 tlul_rvalid_o = 1'b1; Tests: T2 T3 T6  269 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin Tests: T2 T3 T6  270 1/1 state_d = IdleSt; Tests: T2 T3 T6  271 // At this point the only error that we could have gotten are correctable ECC errors. 272 1/1 if (otp_err != NoError) begin Tests: T2 T3 T6  273 1/1 error_d = MacroEccCorrError; Tests: T94 T81 T61  274 end MISSING_ELSE 275 end else begin 276 1/1 state_d = ErrorSt; Tests: T98 T115 T152  277 1/1 error_d = otp_err; Tests: T98 T115 T152  278 // This causes the TL-UL adapter to return a bus error. 279 1/1 tlul_rerror_o = 2'b11; Tests: T98 T115 T152  280 end 281 end MISSING_ELSE 282 end 283 /////////////////////////////////////////////////////////////////// 284 // Terminal Error State. This locks access to the partition. 285 // Make sure the partition signals an error state if no error 286 // code has been latched so far. 287 ErrorSt: begin 288 1/1 if (error_q == NoError) begin Tests: T3 T4 T7  289 1/1 error_d = FsmStateError; Tests: T25 T26 T27  290 end MISSING_ELSE 291 292 // Return bus errors if there are pending TL-UL requests. 293 1/1 if (pending_tlul_error_q) begin Tests: T3 T4 T7  294 1/1 tlul_rerror_o = 2'b11; Tests: T94 T98 T125  295 1/1 tlul_rvalid_o = 1'b1; Tests: T94 T98 T125  296 1/1 end else if (tlul_req_i) begin Tests: T3 T4 T7  297 1/1 tlul_gnt_o = 1'b1; Tests: T94 T98 T125  298 1/1 pending_tlul_error_d = 1'b1; Tests: T94 T98 T125  299 end MISSING_ELSE 300 end 301 /////////////////////////////////////////////////////////////////// 302 // We should never get here. If we do (e.g. via a malicious 303 // glitch), error out immediately. 304 default: begin 305 state_d = ErrorSt; 306 fsm_err_o = 1'b1; 307 end 308 /////////////////////////////////////////////////////////////////// 309 endcase // state_q 310 311 // Unconditionally jump into the terminal error state in case of 312 // an ECC error or escalation, and lock access to the partition down. 313 // SEC_CM: PART.FSM.LOCAL_ESC 314 1/1 if (ecc_err) begin Tests: T1 T2 T3  315 1/1 state_d = ErrorSt; Tests: T105  316 1/1 if (state_q != ErrorSt) begin Tests: T105  317 1/1 error_d = CheckFailError; Tests: T105  318 end MISSING_ELSE 319 end MISSING_ELSE 320 // SEC_CM: PART.FSM.GLOBAL_ESC 321 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin Tests: T1 T2 T3  322 1/1 state_d = ErrorSt; Tests: T3 T4 T7  323 1/1 fsm_err_o = 1'b1; Tests: T3 T4 T7  324 1/1 if (state_q != ErrorSt) begin Tests: T3 T4 T7  325 1/1 error_d = FsmStateError; Tests: T4 T7 T99  326 end MISSING_ELSE 327 end MISSING_ELSE 328 end 329 330 /////////////////////////////////// 331 // Signals to/from TL-UL Adapter // 332 /////////////////////////////////// 333 334 1/1 assign tlul_addr_d = tlul_addr_i; Tests: T1 T2 T3  335 // Do not forward data in case of an error. 336 1/1 assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0; Tests: T1 T2 T3  337 338 if (Info.offset == 0) begin : gen_zero_offset 339 assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd; 340 341 end else begin : gen_nonzero_offset 342 1/1 assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset && Tests: T1 T2 T3  343 {1'b0, tlul_addr_q, 2'b00} < PartEnd; 344 end 345 346 // Note that OTP works on halfword (16bit) addresses, hence need to 347 // shift the addresses appropriately. 348 logic [OtpByteAddrWidth-1:0] addr_calc; 349 1/1 assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00}; Tests: T1 T2 T3  350 1/1 assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift]; Tests: T1 T2 T3  351 352 if (OtpAddrShift > 0) begin : gen_unused 353 logic unused_bits; 354 1/1 assign unused_bits = ^addr_calc[OtpAddrShift-1:0]; Tests: T1 T2 T3  355 end 356 357 // Request 32bit except in case of the digest. 358 1/1 assign otp_size_o = (otp_addr_sel == DigestAddrSel) ? Tests: T1 T2 T3  359 OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) : 360 OtpSizeWidth'(unsigned'(32 / OtpWidth - 1)); 361 362 //////////////// 363 // Digest Reg // 364 //////////////// 365 366 if (Info.sw_digest) begin : gen_ecc_reg 367 // SEC_CM: PART.DATA_REG.INTEGRITY 368 otp_ctrl_ecc_reg #( 369 .Width ( ScrmblBlockWidth ), 370 .Depth ( 1 ) 371 ) u_otp_ctrl_ecc_reg ( 372 .clk_i, 373 .rst_ni, 374 .wren_i ( digest_reg_en ), 375 .addr_i ( '0 ), 376 .wdata_i ( otp_rdata_i ), 377 .rdata_o ( ), 378 .data_o ( digest_o ), 379 .ecc_err_o ( ecc_err ) 380 ); 381 end else begin : gen_no_ecc_reg 382 logic unused_digest_reg_en; 383 logic unused_rdata; 384 assign unused_digest_reg_en = digest_reg_en; 385 assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case. 386 assign digest_o = '0; 387 assign ecc_err = 1'b0; 388 end 389 390 //////////////////////// 391 // DAI Access Control // 392 //////////////////////// 393 394 mubi8_t init_locked; 395 1/1 assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False; Tests: T1 T2 T3  396 397 // Aggregate all possible DAI write locks. The partition is also locked when uninitialized. 398 // Note that the locks are redundantly encoded values. 399 part_access_t access_pre; 400 prim_mubi8_sender #( 401 .AsyncOn(0) 402 ) u_prim_mubi8_sender_write_lock_pre ( 403 .clk_i, 404 .rst_ni, 405 .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)), 406 .mubi_o(access_pre.write_lock) 407 ); 408 prim_mubi8_sender #( 409 .AsyncOn(0) 410 ) u_prim_mubi8_sender_read_lock_pre ( 411 .clk_i, 412 .rst_ni, 413 .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)), 414 .mubi_o(access_pre.read_lock) 415 ); 416 417 // SEC_CM: PART.MEM.SW_UNWRITABLE 418 if (Info.write_lock) begin : gen_digest_write_lock 419 mubi8_t digest_locked; 420 1/1 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; Tests: T1 T2 T3  421 422 // This prevents the synthesis tool from optimizing the multibit signal. 423 prim_mubi8_sender #( 424 .AsyncOn(0) 425 ) u_prim_mubi8_sender_write_lock ( 426 .clk_i, 427 .rst_ni, 428 .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)), 429 .mubi_o(access_o.write_lock) 430 ); 431 432 `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock)) 433 end else begin : gen_no_digest_write_lock 434 assign access_o.write_lock = access_pre.write_lock; 435 end 436 437 // SEC_CM: PART.MEM.SW_UNREADABLE 438 if (Info.read_lock) begin : gen_digest_read_lock 439 mubi8_t digest_locked; 440 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; 441 442 // This prevents the synthesis tool from optimizing the multibit signal. 443 prim_mubi8_sender #( 444 .AsyncOn(0) 445 ) u_prim_mubi8_sender_read_lock ( 446 .clk_i, 447 .rst_ni, 448 .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)), 449 .mubi_o(access_o.read_lock) 450 ); 451 452 `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock)) 453 end else begin : gen_no_digest_read_lock 454 1/1 assign access_o.read_lock = access_pre.read_lock; Tests: T1 T2 T3  455 end 456 457 /////////////// 458 // Registers // 459 /////////////// 460 461 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt): 461.1 `ifdef SIMULATION 461.2 prim_sparse_fsm_flop #( 461.3 .StateEnumT(state_e), 461.4 .Width($bits(state_e)), 461.5 .ResetValue($bits(state_e)'(ResetSt)), 461.6 .EnableAlertTriggerSVA(1), 461.7 .CustomForceName("state_q") 461.8 ) u_state_regs ( 461.9 .clk_i ( clk_i ), 461.10 .rst_ni ( rst_ni ), 461.11 .state_i ( state_d ), 461.12 .state_o ( ) 461.13 ); 461.14 always_ff @(posedge clk_i or negedge rst_ni) begin 461.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  461.16 1/1 state_q <= ResetSt; Tests: T1 T2 T3  461.17 end else begin 461.18 1/1 state_q <= state_d; Tests: T1 T2 T3  461.19 end 461.20 end 461.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 461.22 else begin 461.23 `ifdef UVM 461.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 461.25 "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1); 461.26 `else 461.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 461.28 `PRIM_STRINGIFY(u_state_regs_A)); 461.29 `endif 461.30 end 461.31 `else 461.32 prim_sparse_fsm_flop #( 461.33 .StateEnumT(state_e), 461.34 .Width($bits(state_e)), 461.35 .ResetValue($bits(state_e)'(ResetSt)), 461.36 .EnableAlertTriggerSVA(1) 461.37 ) u_state_regs ( 461.38 .clk_i ( `PRIM_FLOP_CLK ), 461.39 .rst_ni ( `PRIM_FLOP_RST ), 461.40 .state_i ( state_d ), 461.41 .state_o ( state_q ) 461.42 ); 461.43 `endif462 463 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 464 1/1 if (!rst_ni) begin Tests: T1 T2 T3  465 1/1 error_q <= NoError; Tests: T1 T2 T3  466 1/1 tlul_addr_q <= '0; Tests: T1 T2 T3  467 1/1 pending_tlul_error_q <= 1'b0; Tests: T1 T2 T3  468 end else begin 469 1/1 error_q <= error_d; Tests: T1 T2 T3  470 1/1 pending_tlul_error_q <= pending_tlul_error_d; Tests: T1 T2 T3  471 1/1 if (tlul_gnt_o) begin Tests: T1 T2 T3  472 1/1 tlul_addr_q <= tlul_addr_d; Tests: T2 T3 T6  473 end MISSING_ELSE

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=906698836,DigestOffset=1136,StateWidth=10 )
Line Coverage for Module self-instances :
SCORELINE
97.75 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
TOTAL9191100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14911100.00
ALWAYS1646868100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN45411100.00
ALWAYS46133100.00
ALWAYS46488100.00

137 // Output partition error state. 138 1/1 assign error_o = error_q; Tests: T1 T2 T3  139 140 // This partition cannot do any write accesses, hence we tie this 141 // constantly off. 142 assign otp_wdata_o = '0; 143 // Depending on the partition configuration, the wrapper is instructed to ignore integrity 144 // calculations and checks. To be on the safe side, the partition filters error responses at this 145 // point and does not report any integrity errors if integrity is disabled. 146 otp_err_e otp_err; 147 if (Info.integrity) begin : gen_integrity 148 assign otp_cmd_o = prim_otp_pkg::Read; 149 1/1 assign otp_err = otp_err_e'(otp_err_i); Tests: T1 T2 T3  150 end else begin : gen_no_integrity 151 assign otp_cmd_o = prim_otp_pkg::ReadRaw; 152 always_comb begin 153 if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin 154 otp_err = NoError; 155 end else begin 156 otp_err = otp_err_e'(otp_err_i); 157 end 158 end 159 end 160 161 `ASSERT_KNOWN(FsmStateKnown_A, state_q) 162 always_comb begin : p_fsm 163 // Default assignments 164 1/1 state_d = state_q; Tests: T1 T2 T3  165 166 // Response to init request 167 1/1 init_done_o = 1'b0; Tests: T1 T2 T3  168 169 // OTP signals 170 1/1 otp_req_o = 1'b0; Tests: T1 T2 T3  171 1/1 otp_addr_sel = DigestAddrSel; Tests: T1 T2 T3  172 173 // TL-UL signals 174 1/1 tlul_gnt_o = 1'b0; Tests: T1 T2 T3  175 1/1 tlul_rvalid_o = 1'b0; Tests: T1 T2 T3  176 1/1 tlul_rerror_o = '0; Tests: T1 T2 T3  177 178 // Enable for buffered digest register 179 1/1 digest_reg_en = 1'b0; Tests: T1 T2 T3  180 181 // Error Register 182 1/1 error_d = error_q; Tests: T1 T2 T3  183 1/1 pending_tlul_error_d = 1'b0; Tests: T1 T2 T3  184 1/1 fsm_err_o = 1'b0; Tests: T1 T2 T3  185 186 1/1 unique case (state_q) Tests: T1 T2 T3  187 /////////////////////////////////////////////////////////////////// 188 // State right after reset. Wait here until we get a an 189 // initialization request. 190 ResetSt: begin 191 1/1 if (init_req_i) begin Tests: T1 T2 T3  192 // If the partition does not have a digest, no initialization is necessary. 193 1/1 if (Info.sw_digest) begin Tests: T1 T2 T3  194 1/1 state_d = InitSt; Tests: T1 T2 T3  195 end else begin 196 unreachable state_d = IdleSt; 197 end 198 end MISSING_ELSE 199 end 200 /////////////////////////////////////////////////////////////////// 201 // Initialization reads out the digest only in unbuffered 202 // partitions. Wait here until the OTP request has been granted. 203 // And then wait until the OTP word comes back. 204 InitSt: begin 205 1/1 otp_req_o = 1'b1; Tests: T1 T2 T3  206 1/1 if (otp_gnt_i) begin Tests: T1 T2 T3  207 1/1 state_d = InitWaitSt; Tests: T1 T2 T3  208 end MISSING_ELSE 209 end 210 /////////////////////////////////////////////////////////////////// 211 // Wait for OTP response and write to digest buffer register. In 212 // case an OTP transaction fails, latch the OTP error code and 213 // jump to a terminal error state. 214 InitWaitSt: begin 215 1/1 if (otp_rvalid_i) begin Tests: T1 T2 T3  216 1/1 digest_reg_en = 1'b1; Tests: T1 T2 T3  217 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin Tests: T1 T2 T3  218 1/1 state_d = IdleSt; Tests: T1 T2 T3  219 // At this point the only error that we could have gotten are correctable ECC errors. 220 1/1 if (otp_err != NoError) begin Tests: T1 T2 T3  221 1/1 error_d = MacroEccCorrError; Tests: T99 T44 T153  222 end MISSING_ELSE 223 end else begin 224 1/1 state_d = ErrorSt; Tests: T133 T149 T154  225 1/1 error_d = otp_err; Tests: T133 T149 T154  226 end 227 end MISSING_ELSE 228 end 229 /////////////////////////////////////////////////////////////////// 230 // Wait for TL-UL requests coming in. 231 // Then latch address and go to readout state. 232 IdleSt: begin 233 1/1 init_done_o = 1'b1; Tests: T1 T2 T3  234 1/1 if (tlul_req_i) begin Tests: T1 T2 T3  235 1/1 error_d = NoError; // clear recoverable soft errors. Tests: T2 T3 T6  236 1/1 state_d = ReadSt; Tests: T2 T3 T6  237 1/1 tlul_gnt_o = 1'b1; Tests: T2 T3 T6  238 end MISSING_ELSE 239 end 240 /////////////////////////////////////////////////////////////////// 241 // If the address is out of bounds, or if the partition is 242 // locked, signal back a bus error. Note that such an error does 243 // not cause the partition to go into error state. Otherwise if 244 // these checks pass, an OTP word is requested. 245 ReadSt: begin 246 1/1 init_done_o = 1'b1; Tests: T2 T3 T6  247 // Double check the address range. 248 1/1 if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin Tests: T2 T3 T6  249 1/1 otp_req_o = 1'b1; Tests: T2 T3 T6  250 1/1 otp_addr_sel = DataAddrSel; Tests: T2 T3 T6  251 1/1 if (otp_gnt_i) begin Tests: T2 T3 T6  252 1/1 state_d = ReadWaitSt; Tests: T2 T3 T6  253 end MISSING_ELSE 254 end else begin 255 1/1 state_d = IdleSt; Tests: T94 T95 T121  256 1/1 error_d = AccessError; // Signal this error, but do not go into terminal error state. Tests: T94 T95 T121  257 1/1 tlul_rvalid_o = 1'b1; Tests: T94 T95 T121  258 1/1 tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error. Tests: T94 T95 T121  259 end 260 end 261 /////////////////////////////////////////////////////////////////// 262 // Wait for OTP response and release the TL-UL response. In 263 // case an OTP transaction fails, latch the OTP error code, 264 // signal a TL-Ul bus error and jump to a terminal error state. 265 ReadWaitSt: begin 266 1/1 init_done_o = 1'b1; Tests: T2 T3 T6  267 1/1 if (otp_rvalid_i) begin Tests: T2 T3 T6  268 1/1 tlul_rvalid_o = 1'b1; Tests: T2 T3 T6  269 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin Tests: T2 T3 T6  270 1/1 state_d = IdleSt; Tests: T2 T3 T6  271 // At this point the only error that we could have gotten are correctable ECC errors. 272 1/1 if (otp_err != NoError) begin Tests: T2 T3 T6  273 1/1 error_d = MacroEccCorrError; Tests: T94 T81 T155  274 end MISSING_ELSE 275 end else begin 276 1/1 state_d = ErrorSt; Tests: T98 T155 T156  277 1/1 error_d = otp_err; Tests: T98 T155 T156  278 // This causes the TL-UL adapter to return a bus error. 279 1/1 tlul_rerror_o = 2'b11; Tests: T98 T155 T156  280 end 281 end MISSING_ELSE 282 end 283 /////////////////////////////////////////////////////////////////// 284 // Terminal Error State. This locks access to the partition. 285 // Make sure the partition signals an error state if no error 286 // code has been latched so far. 287 ErrorSt: begin 288 1/1 if (error_q == NoError) begin Tests: T3 T4 T7  289 1/1 error_d = FsmStateError; Tests: T25 T26 T27  290 end MISSING_ELSE 291 292 // Return bus errors if there are pending TL-UL requests. 293 1/1 if (pending_tlul_error_q) begin Tests: T3 T4 T7  294 1/1 tlul_rerror_o = 2'b11; Tests: T4 T94 T98  295 1/1 tlul_rvalid_o = 1'b1; Tests: T4 T94 T98  296 1/1 end else if (tlul_req_i) begin Tests: T3 T4 T7  297 1/1 tlul_gnt_o = 1'b1; Tests: T4 T94 T98  298 1/1 pending_tlul_error_d = 1'b1; Tests: T4 T94 T98  299 end MISSING_ELSE 300 end 301 /////////////////////////////////////////////////////////////////// 302 // We should never get here. If we do (e.g. via a malicious 303 // glitch), error out immediately. 304 default: begin 305 state_d = ErrorSt; 306 fsm_err_o = 1'b1; 307 end 308 /////////////////////////////////////////////////////////////////// 309 endcase // state_q 310 311 // Unconditionally jump into the terminal error state in case of 312 // an ECC error or escalation, and lock access to the partition down. 313 // SEC_CM: PART.FSM.LOCAL_ESC 314 1/1 if (ecc_err) begin Tests: T1 T2 T3  315 1/1 state_d = ErrorSt; Tests: T105 T157 T158  316 1/1 if (state_q != ErrorSt) begin Tests: T105 T157 T158  317 1/1 error_d = CheckFailError; Tests: T105 T157 T158  318 end MISSING_ELSE 319 end MISSING_ELSE 320 // SEC_CM: PART.FSM.GLOBAL_ESC 321 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin Tests: T1 T2 T3  322 1/1 state_d = ErrorSt; Tests: T3 T4 T7  323 1/1 fsm_err_o = 1'b1; Tests: T3 T4 T7  324 1/1 if (state_q != ErrorSt) begin Tests: T3 T4 T7  325 1/1 error_d = FsmStateError; Tests: T3 T4 T7  326 end MISSING_ELSE 327 end MISSING_ELSE 328 end 329 330 /////////////////////////////////// 331 // Signals to/from TL-UL Adapter // 332 /////////////////////////////////// 333 334 1/1 assign tlul_addr_d = tlul_addr_i; Tests: T1 T2 T3  335 // Do not forward data in case of an error. 336 1/1 assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0; Tests: T1 T2 T3  337 338 if (Info.offset == 0) begin : gen_zero_offset 339 assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd; 340 341 end else begin : gen_nonzero_offset 342 1/1 assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset && Tests: T1 T2 T3  343 {1'b0, tlul_addr_q, 2'b00} < PartEnd; 344 end 345 346 // Note that OTP works on halfword (16bit) addresses, hence need to 347 // shift the addresses appropriately. 348 logic [OtpByteAddrWidth-1:0] addr_calc; 349 1/1 assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00}; Tests: T1 T2 T3  350 1/1 assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift]; Tests: T1 T2 T3  351 352 if (OtpAddrShift > 0) begin : gen_unused 353 logic unused_bits; 354 1/1 assign unused_bits = ^addr_calc[OtpAddrShift-1:0]; Tests: T1 T2 T3  355 end 356 357 // Request 32bit except in case of the digest. 358 1/1 assign otp_size_o = (otp_addr_sel == DigestAddrSel) ? Tests: T1 T2 T3  359 OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) : 360 OtpSizeWidth'(unsigned'(32 / OtpWidth - 1)); 361 362 //////////////// 363 // Digest Reg // 364 //////////////// 365 366 if (Info.sw_digest) begin : gen_ecc_reg 367 // SEC_CM: PART.DATA_REG.INTEGRITY 368 otp_ctrl_ecc_reg #( 369 .Width ( ScrmblBlockWidth ), 370 .Depth ( 1 ) 371 ) u_otp_ctrl_ecc_reg ( 372 .clk_i, 373 .rst_ni, 374 .wren_i ( digest_reg_en ), 375 .addr_i ( '0 ), 376 .wdata_i ( otp_rdata_i ), 377 .rdata_o ( ), 378 .data_o ( digest_o ), 379 .ecc_err_o ( ecc_err ) 380 ); 381 end else begin : gen_no_ecc_reg 382 logic unused_digest_reg_en; 383 logic unused_rdata; 384 assign unused_digest_reg_en = digest_reg_en; 385 assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case. 386 assign digest_o = '0; 387 assign ecc_err = 1'b0; 388 end 389 390 //////////////////////// 391 // DAI Access Control // 392 //////////////////////// 393 394 mubi8_t init_locked; 395 1/1 assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False; Tests: T1 T2 T3  396 397 // Aggregate all possible DAI write locks. The partition is also locked when uninitialized. 398 // Note that the locks are redundantly encoded values. 399 part_access_t access_pre; 400 prim_mubi8_sender #( 401 .AsyncOn(0) 402 ) u_prim_mubi8_sender_write_lock_pre ( 403 .clk_i, 404 .rst_ni, 405 .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)), 406 .mubi_o(access_pre.write_lock) 407 ); 408 prim_mubi8_sender #( 409 .AsyncOn(0) 410 ) u_prim_mubi8_sender_read_lock_pre ( 411 .clk_i, 412 .rst_ni, 413 .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)), 414 .mubi_o(access_pre.read_lock) 415 ); 416 417 // SEC_CM: PART.MEM.SW_UNWRITABLE 418 if (Info.write_lock) begin : gen_digest_write_lock 419 mubi8_t digest_locked; 420 1/1 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; Tests: T1 T2 T3  421 422 // This prevents the synthesis tool from optimizing the multibit signal. 423 prim_mubi8_sender #( 424 .AsyncOn(0) 425 ) u_prim_mubi8_sender_write_lock ( 426 .clk_i, 427 .rst_ni, 428 .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)), 429 .mubi_o(access_o.write_lock) 430 ); 431 432 `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock)) 433 end else begin : gen_no_digest_write_lock 434 assign access_o.write_lock = access_pre.write_lock; 435 end 436 437 // SEC_CM: PART.MEM.SW_UNREADABLE 438 if (Info.read_lock) begin : gen_digest_read_lock 439 mubi8_t digest_locked; 440 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; 441 442 // This prevents the synthesis tool from optimizing the multibit signal. 443 prim_mubi8_sender #( 444 .AsyncOn(0) 445 ) u_prim_mubi8_sender_read_lock ( 446 .clk_i, 447 .rst_ni, 448 .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)), 449 .mubi_o(access_o.read_lock) 450 ); 451 452 `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock)) 453 end else begin : gen_no_digest_read_lock 454 1/1 assign access_o.read_lock = access_pre.read_lock; Tests: T1 T2 T3  455 end 456 457 /////////////// 458 // Registers // 459 /////////////// 460 461 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt): 461.1 `ifdef SIMULATION 461.2 prim_sparse_fsm_flop #( 461.3 .StateEnumT(state_e), 461.4 .Width($bits(state_e)), 461.5 .ResetValue($bits(state_e)'(ResetSt)), 461.6 .EnableAlertTriggerSVA(1), 461.7 .CustomForceName("state_q") 461.8 ) u_state_regs ( 461.9 .clk_i ( clk_i ), 461.10 .rst_ni ( rst_ni ), 461.11 .state_i ( state_d ), 461.12 .state_o ( ) 461.13 ); 461.14 always_ff @(posedge clk_i or negedge rst_ni) begin 461.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  461.16 1/1 state_q <= ResetSt; Tests: T1 T2 T3  461.17 end else begin 461.18 1/1 state_q <= state_d; Tests: T1 T2 T3  461.19 end 461.20 end 461.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 461.22 else begin 461.23 `ifdef UVM 461.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 461.25 "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1); 461.26 `else 461.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 461.28 `PRIM_STRINGIFY(u_state_regs_A)); 461.29 `endif 461.30 end 461.31 `else 461.32 prim_sparse_fsm_flop #( 461.33 .StateEnumT(state_e), 461.34 .Width($bits(state_e)), 461.35 .ResetValue($bits(state_e)'(ResetSt)), 461.36 .EnableAlertTriggerSVA(1) 461.37 ) u_state_regs ( 461.38 .clk_i ( `PRIM_FLOP_CLK ), 461.39 .rst_ni ( `PRIM_FLOP_RST ), 461.40 .state_i ( state_d ), 461.41 .state_o ( state_q ) 461.42 ); 461.43 `endif462 463 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 464 1/1 if (!rst_ni) begin Tests: T1 T2 T3  465 1/1 error_q <= NoError; Tests: T1 T2 T3  466 1/1 tlul_addr_q <= '0; Tests: T1 T2 T3  467 1/1 pending_tlul_error_q <= 1'b0; Tests: T1 T2 T3  468 end else begin 469 1/1 error_q <= error_d; Tests: T1 T2 T3  470 1/1 pending_tlul_error_q <= pending_tlul_error_d; Tests: T1 T2 T3  471 1/1 if (tlul_gnt_o) begin Tests: T1 T2 T3  472 1/1 tlul_addr_q <= tlul_addr_d; Tests: T2 T3 T6  473 end MISSING_ELSE

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Line Coverage for Module self-instances :
SCORELINE
98.33 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
TOTAL9191100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14911100.00
ALWAYS1646868100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN45411100.00
ALWAYS46133100.00
ALWAYS46488100.00

137 // Output partition error state. 138 1/1 assign error_o = error_q; Tests: T1 T2 T3  139 140 // This partition cannot do any write accesses, hence we tie this 141 // constantly off. 142 assign otp_wdata_o = '0; 143 // Depending on the partition configuration, the wrapper is instructed to ignore integrity 144 // calculations and checks. To be on the safe side, the partition filters error responses at this 145 // point and does not report any integrity errors if integrity is disabled. 146 otp_err_e otp_err; 147 if (Info.integrity) begin : gen_integrity 148 assign otp_cmd_o = prim_otp_pkg::Read; 149 1/1 assign otp_err = otp_err_e'(otp_err_i); Tests: T1 T2 T3  150 end else begin : gen_no_integrity 151 assign otp_cmd_o = prim_otp_pkg::ReadRaw; 152 always_comb begin 153 if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin 154 otp_err = NoError; 155 end else begin 156 otp_err = otp_err_e'(otp_err_i); 157 end 158 end 159 end 160 161 `ASSERT_KNOWN(FsmStateKnown_A, state_q) 162 always_comb begin : p_fsm 163 // Default assignments 164 1/1 state_d = state_q; Tests: T1 T2 T3  165 166 // Response to init request 167 1/1 init_done_o = 1'b0; Tests: T1 T2 T3  168 169 // OTP signals 170 1/1 otp_req_o = 1'b0; Tests: T1 T2 T3  171 1/1 otp_addr_sel = DigestAddrSel; Tests: T1 T2 T3  172 173 // TL-UL signals 174 1/1 tlul_gnt_o = 1'b0; Tests: T1 T2 T3  175 1/1 tlul_rvalid_o = 1'b0; Tests: T1 T2 T3  176 1/1 tlul_rerror_o = '0; Tests: T1 T2 T3  177 178 // Enable for buffered digest register 179 1/1 digest_reg_en = 1'b0; Tests: T1 T2 T3  180 181 // Error Register 182 1/1 error_d = error_q; Tests: T1 T2 T3  183 1/1 pending_tlul_error_d = 1'b0; Tests: T1 T2 T3  184 1/1 fsm_err_o = 1'b0; Tests: T1 T2 T3  185 186 1/1 unique case (state_q) Tests: T1 T2 T3  187 /////////////////////////////////////////////////////////////////// 188 // State right after reset. Wait here until we get a an 189 // initialization request. 190 ResetSt: begin 191 1/1 if (init_req_i) begin Tests: T1 T2 T3  192 // If the partition does not have a digest, no initialization is necessary. 193 1/1 if (Info.sw_digest) begin Tests: T1 T2 T3  194 1/1 state_d = InitSt; Tests: T1 T2 T3  195 end else begin 196 unreachable state_d = IdleSt; 197 end 198 end MISSING_ELSE 199 end 200 /////////////////////////////////////////////////////////////////// 201 // Initialization reads out the digest only in unbuffered 202 // partitions. Wait here until the OTP request has been granted. 203 // And then wait until the OTP word comes back. 204 InitSt: begin 205 1/1 otp_req_o = 1'b1; Tests: T1 T2 T3  206 1/1 if (otp_gnt_i) begin Tests: T1 T2 T3  207 1/1 state_d = InitWaitSt; Tests: T1 T2 T3  208 end MISSING_ELSE 209 end 210 /////////////////////////////////////////////////////////////////// 211 // Wait for OTP response and write to digest buffer register. In 212 // case an OTP transaction fails, latch the OTP error code and 213 // jump to a terminal error state. 214 InitWaitSt: begin 215 1/1 if (otp_rvalid_i) begin Tests: T1 T2 T3  216 1/1 digest_reg_en = 1'b1; Tests: T1 T2 T3  217 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin Tests: T1 T2 T3  218 1/1 state_d = IdleSt; Tests: T1 T2 T3  219 // At this point the only error that we could have gotten are correctable ECC errors. 220 1/1 if (otp_err != NoError) begin Tests: T1 T2 T3  221 1/1 error_d = MacroEccCorrError; Tests: T66 T43 T159  222 end MISSING_ELSE 223 end else begin 224 1/1 state_d = ErrorSt; Tests: T132 T160 T161  225 1/1 error_d = otp_err; Tests: T132 T160 T161  226 end 227 end MISSING_ELSE 228 end 229 /////////////////////////////////////////////////////////////////// 230 // Wait for TL-UL requests coming in. 231 // Then latch address and go to readout state. 232 IdleSt: begin 233 1/1 init_done_o = 1'b1; Tests: T1 T2 T3  234 1/1 if (tlul_req_i) begin Tests: T1 T2 T3  235 1/1 error_d = NoError; // clear recoverable soft errors. Tests: T2 T3 T6  236 1/1 state_d = ReadSt; Tests: T2 T3 T6  237 1/1 tlul_gnt_o = 1'b1; Tests: T2 T3 T6  238 end MISSING_ELSE 239 end 240 /////////////////////////////////////////////////////////////////// 241 // If the address is out of bounds, or if the partition is 242 // locked, signal back a bus error. Note that such an error does 243 // not cause the partition to go into error state. Otherwise if 244 // these checks pass, an OTP word is requested. 245 ReadSt: begin 246 1/1 init_done_o = 1'b1; Tests: T2 T3 T6  247 // Double check the address range. 248 1/1 if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin Tests: T2 T3 T6  249 1/1 otp_req_o = 1'b1; Tests: T2 T3 T6  250 1/1 otp_addr_sel = DataAddrSel; Tests: T2 T3 T6  251 1/1 if (otp_gnt_i) begin Tests: T2 T3 T6  252 1/1 state_d = ReadWaitSt; Tests: T2 T3 T6  253 end MISSING_ELSE 254 end else begin 255 1/1 state_d = IdleSt; Tests: T94 T95 T121  256 1/1 error_d = AccessError; // Signal this error, but do not go into terminal error state. Tests: T94 T95 T121  257 1/1 tlul_rvalid_o = 1'b1; Tests: T94 T95 T121  258 1/1 tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error. Tests: T94 T95 T121  259 end 260 end 261 /////////////////////////////////////////////////////////////////// 262 // Wait for OTP response and release the TL-UL response. In 263 // case an OTP transaction fails, latch the OTP error code, 264 // signal a TL-Ul bus error and jump to a terminal error state. 265 ReadWaitSt: begin 266 1/1 init_done_o = 1'b1; Tests: T2 T3 T6  267 1/1 if (otp_rvalid_i) begin Tests: T2 T3 T6  268 1/1 tlul_rvalid_o = 1'b1; Tests: T2 T3 T6  269 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin Tests: T2 T3 T6  270 1/1 state_d = IdleSt; Tests: T2 T3 T6  271 // At this point the only error that we could have gotten are correctable ECC errors. 272 1/1 if (otp_err != NoError) begin Tests: T2 T3 T6  273 1/1 error_d = MacroEccCorrError; Tests: T94 T81 T156  274 end MISSING_ELSE 275 end else begin 276 1/1 state_d = ErrorSt; Tests: T162 T163 T164  277 1/1 error_d = otp_err; Tests: T162 T163 T164  278 // This causes the TL-UL adapter to return a bus error. 279 1/1 tlul_rerror_o = 2'b11; Tests: T162 T163 T164  280 end 281 end MISSING_ELSE 282 end 283 /////////////////////////////////////////////////////////////////// 284 // Terminal Error State. This locks access to the partition. 285 // Make sure the partition signals an error state if no error 286 // code has been latched so far. 287 ErrorSt: begin 288 1/1 if (error_q == NoError) begin Tests: T3 T4 T7  289 1/1 error_d = FsmStateError; Tests: T25 T26 T27  290 end MISSING_ELSE 291 292 // Return bus errors if there are pending TL-UL requests. 293 1/1 if (pending_tlul_error_q) begin Tests: T3 T4 T7  294 1/1 tlul_rerror_o = 2'b11; Tests: T4 T94 T98  295 1/1 tlul_rvalid_o = 1'b1; Tests: T4 T94 T98  296 1/1 end else if (tlul_req_i) begin Tests: T3 T4 T7  297 1/1 tlul_gnt_o = 1'b1; Tests: T4 T94 T98  298 1/1 pending_tlul_error_d = 1'b1; Tests: T4 T94 T98  299 end MISSING_ELSE 300 end 301 /////////////////////////////////////////////////////////////////// 302 // We should never get here. If we do (e.g. via a malicious 303 // glitch), error out immediately. 304 default: begin 305 state_d = ErrorSt; 306 fsm_err_o = 1'b1; 307 end 308 /////////////////////////////////////////////////////////////////// 309 endcase // state_q 310 311 // Unconditionally jump into the terminal error state in case of 312 // an ECC error or escalation, and lock access to the partition down. 313 // SEC_CM: PART.FSM.LOCAL_ESC 314 1/1 if (ecc_err) begin Tests: T1 T2 T3  315 1/1 state_d = ErrorSt; Tests: T105 T165 T166  316 1/1 if (state_q != ErrorSt) begin Tests: T105 T165 T166  317 1/1 error_d = CheckFailError; Tests: T105 T165 T166  318 end MISSING_ELSE 319 end MISSING_ELSE 320 // SEC_CM: PART.FSM.GLOBAL_ESC 321 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin Tests: T1 T2 T3  322 1/1 state_d = ErrorSt; Tests: T3 T4 T7  323 1/1 fsm_err_o = 1'b1; Tests: T3 T4 T7  324 1/1 if (state_q != ErrorSt) begin Tests: T3 T4 T7  325 1/1 error_d = FsmStateError; Tests: T3 T4 T7  326 end MISSING_ELSE 327 end MISSING_ELSE 328 end 329 330 /////////////////////////////////// 331 // Signals to/from TL-UL Adapter // 332 /////////////////////////////////// 333 334 1/1 assign tlul_addr_d = tlul_addr_i; Tests: T1 T2 T3  335 // Do not forward data in case of an error. 336 1/1 assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0; Tests: T1 T2 T3  337 338 if (Info.offset == 0) begin : gen_zero_offset 339 assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd; 340 341 end else begin : gen_nonzero_offset 342 1/1 assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset && Tests: T1 T2 T3  343 {1'b0, tlul_addr_q, 2'b00} < PartEnd; 344 end 345 346 // Note that OTP works on halfword (16bit) addresses, hence need to 347 // shift the addresses appropriately. 348 logic [OtpByteAddrWidth-1:0] addr_calc; 349 1/1 assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00}; Tests: T1 T2 T3  350 1/1 assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift]; Tests: T1 T2 T3  351 352 if (OtpAddrShift > 0) begin : gen_unused 353 logic unused_bits; 354 1/1 assign unused_bits = ^addr_calc[OtpAddrShift-1:0]; Tests: T1 T2 T3  355 end 356 357 // Request 32bit except in case of the digest. 358 1/1 assign otp_size_o = (otp_addr_sel == DigestAddrSel) ? Tests: T1 T2 T3  359 OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) : 360 OtpSizeWidth'(unsigned'(32 / OtpWidth - 1)); 361 362 //////////////// 363 // Digest Reg // 364 //////////////// 365 366 if (Info.sw_digest) begin : gen_ecc_reg 367 // SEC_CM: PART.DATA_REG.INTEGRITY 368 otp_ctrl_ecc_reg #( 369 .Width ( ScrmblBlockWidth ), 370 .Depth ( 1 ) 371 ) u_otp_ctrl_ecc_reg ( 372 .clk_i, 373 .rst_ni, 374 .wren_i ( digest_reg_en ), 375 .addr_i ( '0 ), 376 .wdata_i ( otp_rdata_i ), 377 .rdata_o ( ), 378 .data_o ( digest_o ), 379 .ecc_err_o ( ecc_err ) 380 ); 381 end else begin : gen_no_ecc_reg 382 logic unused_digest_reg_en; 383 logic unused_rdata; 384 assign unused_digest_reg_en = digest_reg_en; 385 assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case. 386 assign digest_o = '0; 387 assign ecc_err = 1'b0; 388 end 389 390 //////////////////////// 391 // DAI Access Control // 392 //////////////////////// 393 394 mubi8_t init_locked; 395 1/1 assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False; Tests: T1 T2 T3  396 397 // Aggregate all possible DAI write locks. The partition is also locked when uninitialized. 398 // Note that the locks are redundantly encoded values. 399 part_access_t access_pre; 400 prim_mubi8_sender #( 401 .AsyncOn(0) 402 ) u_prim_mubi8_sender_write_lock_pre ( 403 .clk_i, 404 .rst_ni, 405 .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)), 406 .mubi_o(access_pre.write_lock) 407 ); 408 prim_mubi8_sender #( 409 .AsyncOn(0) 410 ) u_prim_mubi8_sender_read_lock_pre ( 411 .clk_i, 412 .rst_ni, 413 .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)), 414 .mubi_o(access_pre.read_lock) 415 ); 416 417 // SEC_CM: PART.MEM.SW_UNWRITABLE 418 if (Info.write_lock) begin : gen_digest_write_lock 419 mubi8_t digest_locked; 420 1/1 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; Tests: T1 T2 T3  421 422 // This prevents the synthesis tool from optimizing the multibit signal. 423 prim_mubi8_sender #( 424 .AsyncOn(0) 425 ) u_prim_mubi8_sender_write_lock ( 426 .clk_i, 427 .rst_ni, 428 .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)), 429 .mubi_o(access_o.write_lock) 430 ); 431 432 `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock)) 433 end else begin : gen_no_digest_write_lock 434 assign access_o.write_lock = access_pre.write_lock; 435 end 436 437 // SEC_CM: PART.MEM.SW_UNREADABLE 438 if (Info.read_lock) begin : gen_digest_read_lock 439 mubi8_t digest_locked; 440 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; 441 442 // This prevents the synthesis tool from optimizing the multibit signal. 443 prim_mubi8_sender #( 444 .AsyncOn(0) 445 ) u_prim_mubi8_sender_read_lock ( 446 .clk_i, 447 .rst_ni, 448 .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)), 449 .mubi_o(access_o.read_lock) 450 ); 451 452 `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock)) 453 end else begin : gen_no_digest_read_lock 454 1/1 assign access_o.read_lock = access_pre.read_lock; Tests: T1 T2 T3  455 end 456 457 /////////////// 458 // Registers // 459 /////////////// 460 461 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt): 461.1 `ifdef SIMULATION 461.2 prim_sparse_fsm_flop #( 461.3 .StateEnumT(state_e), 461.4 .Width($bits(state_e)), 461.5 .ResetValue($bits(state_e)'(ResetSt)), 461.6 .EnableAlertTriggerSVA(1), 461.7 .CustomForceName("state_q") 461.8 ) u_state_regs ( 461.9 .clk_i ( clk_i ), 461.10 .rst_ni ( rst_ni ), 461.11 .state_i ( state_d ), 461.12 .state_o ( ) 461.13 ); 461.14 always_ff @(posedge clk_i or negedge rst_ni) begin 461.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  461.16 1/1 state_q <= ResetSt; Tests: T1 T2 T3  461.17 end else begin 461.18 1/1 state_q <= state_d; Tests: T1 T2 T3  461.19 end 461.20 end 461.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 461.22 else begin 461.23 `ifdef UVM 461.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 461.25 "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1); 461.26 `else 461.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 461.28 `PRIM_STRINGIFY(u_state_regs_A)); 461.29 `endif 461.30 end 461.31 `else 461.32 prim_sparse_fsm_flop #( 461.33 .StateEnumT(state_e), 461.34 .Width($bits(state_e)), 461.35 .ResetValue($bits(state_e)'(ResetSt)), 461.36 .EnableAlertTriggerSVA(1) 461.37 ) u_state_regs ( 461.38 .clk_i ( `PRIM_FLOP_CLK ), 461.39 .rst_ni ( `PRIM_FLOP_RST ), 461.40 .state_i ( state_d ), 461.41 .state_o ( state_q ) 461.42 ); 461.43 `endif462 463 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 464 1/1 if (!rst_ni) begin Tests: T1 T2 T3  465 1/1 error_q <= NoError; Tests: T1 T2 T3  466 1/1 tlul_addr_q <= '0; Tests: T1 T2 T3  467 1/1 pending_tlul_error_q <= 1'b0; Tests: T1 T2 T3  468 end else begin 469 1/1 error_q <= error_d; Tests: T1 T2 T3  470 1/1 pending_tlul_error_q <= pending_tlul_error_d; Tests: T1 T2 T3  471 1/1 if (tlul_gnt_o) begin Tests: T1 T2 T3  472 1/1 tlul_addr_q <= tlul_addr_d; Tests: T2 T3 T6  473 end MISSING_ELSE

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Line Coverage for Module self-instances :
SCORELINE
98.33 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
TOTAL9191100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14911100.00
ALWAYS1646868100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN45411100.00
ALWAYS46133100.00
ALWAYS46488100.00

137 // Output partition error state. 138 1/1 assign error_o = error_q; Tests: T1 T2 T3  139 140 // This partition cannot do any write accesses, hence we tie this 141 // constantly off. 142 assign otp_wdata_o = '0; 143 // Depending on the partition configuration, the wrapper is instructed to ignore integrity 144 // calculations and checks. To be on the safe side, the partition filters error responses at this 145 // point and does not report any integrity errors if integrity is disabled. 146 otp_err_e otp_err; 147 if (Info.integrity) begin : gen_integrity 148 assign otp_cmd_o = prim_otp_pkg::Read; 149 1/1 assign otp_err = otp_err_e'(otp_err_i); Tests: T1 T2 T3  150 end else begin : gen_no_integrity 151 assign otp_cmd_o = prim_otp_pkg::ReadRaw; 152 always_comb begin 153 if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin 154 otp_err = NoError; 155 end else begin 156 otp_err = otp_err_e'(otp_err_i); 157 end 158 end 159 end 160 161 `ASSERT_KNOWN(FsmStateKnown_A, state_q) 162 always_comb begin : p_fsm 163 // Default assignments 164 1/1 state_d = state_q; Tests: T1 T2 T3  165 166 // Response to init request 167 1/1 init_done_o = 1'b0; Tests: T1 T2 T3  168 169 // OTP signals 170 1/1 otp_req_o = 1'b0; Tests: T1 T2 T3  171 1/1 otp_addr_sel = DigestAddrSel; Tests: T1 T2 T3  172 173 // TL-UL signals 174 1/1 tlul_gnt_o = 1'b0; Tests: T1 T2 T3  175 1/1 tlul_rvalid_o = 1'b0; Tests: T1 T2 T3  176 1/1 tlul_rerror_o = '0; Tests: T1 T2 T3  177 178 // Enable for buffered digest register 179 1/1 digest_reg_en = 1'b0; Tests: T1 T2 T3  180 181 // Error Register 182 1/1 error_d = error_q; Tests: T1 T2 T3  183 1/1 pending_tlul_error_d = 1'b0; Tests: T1 T2 T3  184 1/1 fsm_err_o = 1'b0; Tests: T1 T2 T3  185 186 1/1 unique case (state_q) Tests: T1 T2 T3  187 /////////////////////////////////////////////////////////////////// 188 // State right after reset. Wait here until we get a an 189 // initialization request. 190 ResetSt: begin 191 1/1 if (init_req_i) begin Tests: T1 T2 T3  192 // If the partition does not have a digest, no initialization is necessary. 193 1/1 if (Info.sw_digest) begin Tests: T1 T2 T3  194 1/1 state_d = InitSt; Tests: T1 T2 T3  195 end else begin 196 unreachable state_d = IdleSt; 197 end 198 end MISSING_ELSE 199 end 200 /////////////////////////////////////////////////////////////////// 201 // Initialization reads out the digest only in unbuffered 202 // partitions. Wait here until the OTP request has been granted. 203 // And then wait until the OTP word comes back. 204 InitSt: begin 205 1/1 otp_req_o = 1'b1; Tests: T1 T2 T3  206 1/1 if (otp_gnt_i) begin Tests: T1 T2 T3  207 1/1 state_d = InitWaitSt; Tests: T1 T2 T3  208 end MISSING_ELSE 209 end 210 /////////////////////////////////////////////////////////////////// 211 // Wait for OTP response and write to digest buffer register. In 212 // case an OTP transaction fails, latch the OTP error code and 213 // jump to a terminal error state. 214 InitWaitSt: begin 215 1/1 if (otp_rvalid_i) begin Tests: T1 T2 T3  216 1/1 digest_reg_en = 1'b1; Tests: T1 T2 T3  217 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin Tests: T1 T2 T3  218 1/1 state_d = IdleSt; Tests: T1 T2 T3  219 // At this point the only error that we could have gotten are correctable ECC errors. 220 1/1 if (otp_err != NoError) begin Tests: T1 T2 T3  221 1/1 error_d = MacroEccCorrError; Tests: T45 T66 T87  222 end MISSING_ELSE 223 end else begin 224 1/1 state_d = ErrorSt; Tests: T99 T150 T167  225 1/1 error_d = otp_err; Tests: T99 T150 T167  226 end 227 end MISSING_ELSE 228 end 229 /////////////////////////////////////////////////////////////////// 230 // Wait for TL-UL requests coming in. 231 // Then latch address and go to readout state. 232 IdleSt: begin 233 1/1 init_done_o = 1'b1; Tests: T1 T2 T3  234 1/1 if (tlul_req_i) begin Tests: T1 T2 T3  235 1/1 error_d = NoError; // clear recoverable soft errors. Tests: T2 T3 T6  236 1/1 state_d = ReadSt; Tests: T2 T3 T6  237 1/1 tlul_gnt_o = 1'b1; Tests: T2 T3 T6  238 end MISSING_ELSE 239 end 240 /////////////////////////////////////////////////////////////////// 241 // If the address is out of bounds, or if the partition is 242 // locked, signal back a bus error. Note that such an error does 243 // not cause the partition to go into error state. Otherwise if 244 // these checks pass, an OTP word is requested. 245 ReadSt: begin 246 1/1 init_done_o = 1'b1; Tests: T2 T3 T6  247 // Double check the address range. 248 1/1 if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin Tests: T2 T3 T6  249 1/1 otp_req_o = 1'b1; Tests: T2 T3 T6  250 1/1 otp_addr_sel = DataAddrSel; Tests: T2 T3 T6  251 1/1 if (otp_gnt_i) begin Tests: T2 T3 T6  252 1/1 state_d = ReadWaitSt; Tests: T2 T3 T6  253 end MISSING_ELSE 254 end else begin 255 1/1 state_d = IdleSt; Tests: T94 T95 T120  256 1/1 error_d = AccessError; // Signal this error, but do not go into terminal error state. Tests: T94 T95 T120  257 1/1 tlul_rvalid_o = 1'b1; Tests: T94 T95 T120  258 1/1 tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error. Tests: T94 T95 T120  259 end 260 end 261 /////////////////////////////////////////////////////////////////// 262 // Wait for OTP response and release the TL-UL response. In 263 // case an OTP transaction fails, latch the OTP error code, 264 // signal a TL-Ul bus error and jump to a terminal error state. 265 ReadWaitSt: begin 266 1/1 init_done_o = 1'b1; Tests: T2 T3 T6  267 1/1 if (otp_rvalid_i) begin Tests: T2 T3 T6  268 1/1 tlul_rvalid_o = 1'b1; Tests: T2 T3 T6  269 1/1 if (otp_err inside {NoError, MacroEccCorrError}) begin Tests: T2 T3 T6  270 1/1 state_d = IdleSt; Tests: T2 T3 T6  271 // At this point the only error that we could have gotten are correctable ECC errors. 272 1/1 if (otp_err != NoError) begin Tests: T2 T3 T6  273 1/1 error_d = MacroEccCorrError; Tests: T94 T71 T162  274 end MISSING_ELSE 275 end else begin 276 1/1 state_d = ErrorSt; Tests: T115 T168 T169  277 1/1 error_d = otp_err; Tests: T115 T168 T169  278 // This causes the TL-UL adapter to return a bus error. 279 1/1 tlul_rerror_o = 2'b11; Tests: T115 T168 T169  280 end 281 end MISSING_ELSE 282 end 283 /////////////////////////////////////////////////////////////////// 284 // Terminal Error State. This locks access to the partition. 285 // Make sure the partition signals an error state if no error 286 // code has been latched so far. 287 ErrorSt: begin 288 1/1 if (error_q == NoError) begin Tests: T3 T4 T7  289 1/1 error_d = FsmStateError; Tests: T25 T26 T27  290 end MISSING_ELSE 291 292 // Return bus errors if there are pending TL-UL requests. 293 1/1 if (pending_tlul_error_q) begin Tests: T3 T4 T7  294 1/1 tlul_rerror_o = 2'b11; Tests: T4 T94 T98  295 1/1 tlul_rvalid_o = 1'b1; Tests: T4 T94 T98  296 1/1 end else if (tlul_req_i) begin Tests: T3 T4 T7  297 1/1 tlul_gnt_o = 1'b1; Tests: T4 T94 T98  298 1/1 pending_tlul_error_d = 1'b1; Tests: T4 T94 T98  299 end MISSING_ELSE 300 end 301 /////////////////////////////////////////////////////////////////// 302 // We should never get here. If we do (e.g. via a malicious 303 // glitch), error out immediately. 304 default: begin 305 state_d = ErrorSt; 306 fsm_err_o = 1'b1; 307 end 308 /////////////////////////////////////////////////////////////////// 309 endcase // state_q 310 311 // Unconditionally jump into the terminal error state in case of 312 // an ECC error or escalation, and lock access to the partition down. 313 // SEC_CM: PART.FSM.LOCAL_ESC 314 1/1 if (ecc_err) begin Tests: T1 T2 T3  315 1/1 state_d = ErrorSt; Tests: T105 T165 T157  316 1/1 if (state_q != ErrorSt) begin Tests: T105 T165 T157  317 1/1 error_d = CheckFailError; Tests: T105 T165 T157  318 end MISSING_ELSE 319 end MISSING_ELSE 320 // SEC_CM: PART.FSM.GLOBAL_ESC 321 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin Tests: T1 T2 T3  322 1/1 state_d = ErrorSt; Tests: T3 T4 T7  323 1/1 fsm_err_o = 1'b1; Tests: T3 T4 T7  324 1/1 if (state_q != ErrorSt) begin Tests: T3 T4 T7  325 1/1 error_d = FsmStateError; Tests: T3 T4 T7  326 end MISSING_ELSE 327 end MISSING_ELSE 328 end 329 330 /////////////////////////////////// 331 // Signals to/from TL-UL Adapter // 332 /////////////////////////////////// 333 334 1/1 assign tlul_addr_d = tlul_addr_i; Tests: T1 T2 T3  335 // Do not forward data in case of an error. 336 1/1 assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0; Tests: T1 T2 T3  337 338 if (Info.offset == 0) begin : gen_zero_offset 339 assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd; 340 341 end else begin : gen_nonzero_offset 342 1/1 assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset && Tests: T1 T2 T3  343 {1'b0, tlul_addr_q, 2'b00} < PartEnd; 344 end 345 346 // Note that OTP works on halfword (16bit) addresses, hence need to 347 // shift the addresses appropriately. 348 logic [OtpByteAddrWidth-1:0] addr_calc; 349 1/1 assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00}; Tests: T1 T2 T3  350 1/1 assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift]; Tests: T1 T2 T3  351 352 if (OtpAddrShift > 0) begin : gen_unused 353 logic unused_bits; 354 1/1 assign unused_bits = ^addr_calc[OtpAddrShift-1:0]; Tests: T1 T2 T3  355 end 356 357 // Request 32bit except in case of the digest. 358 1/1 assign otp_size_o = (otp_addr_sel == DigestAddrSel) ? Tests: T1 T2 T3  359 OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) : 360 OtpSizeWidth'(unsigned'(32 / OtpWidth - 1)); 361 362 //////////////// 363 // Digest Reg // 364 //////////////// 365 366 if (Info.sw_digest) begin : gen_ecc_reg 367 // SEC_CM: PART.DATA_REG.INTEGRITY 368 otp_ctrl_ecc_reg #( 369 .Width ( ScrmblBlockWidth ), 370 .Depth ( 1 ) 371 ) u_otp_ctrl_ecc_reg ( 372 .clk_i, 373 .rst_ni, 374 .wren_i ( digest_reg_en ), 375 .addr_i ( '0 ), 376 .wdata_i ( otp_rdata_i ), 377 .rdata_o ( ), 378 .data_o ( digest_o ), 379 .ecc_err_o ( ecc_err ) 380 ); 381 end else begin : gen_no_ecc_reg 382 logic unused_digest_reg_en; 383 logic unused_rdata; 384 assign unused_digest_reg_en = digest_reg_en; 385 assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case. 386 assign digest_o = '0; 387 assign ecc_err = 1'b0; 388 end 389 390 //////////////////////// 391 // DAI Access Control // 392 //////////////////////// 393 394 mubi8_t init_locked; 395 1/1 assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False; Tests: T1 T2 T3  396 397 // Aggregate all possible DAI write locks. The partition is also locked when uninitialized. 398 // Note that the locks are redundantly encoded values. 399 part_access_t access_pre; 400 prim_mubi8_sender #( 401 .AsyncOn(0) 402 ) u_prim_mubi8_sender_write_lock_pre ( 403 .clk_i, 404 .rst_ni, 405 .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)), 406 .mubi_o(access_pre.write_lock) 407 ); 408 prim_mubi8_sender #( 409 .AsyncOn(0) 410 ) u_prim_mubi8_sender_read_lock_pre ( 411 .clk_i, 412 .rst_ni, 413 .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)), 414 .mubi_o(access_pre.read_lock) 415 ); 416 417 // SEC_CM: PART.MEM.SW_UNWRITABLE 418 if (Info.write_lock) begin : gen_digest_write_lock 419 mubi8_t digest_locked; 420 1/1 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; Tests: T1 T2 T3  421 422 // This prevents the synthesis tool from optimizing the multibit signal. 423 prim_mubi8_sender #( 424 .AsyncOn(0) 425 ) u_prim_mubi8_sender_write_lock ( 426 .clk_i, 427 .rst_ni, 428 .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)), 429 .mubi_o(access_o.write_lock) 430 ); 431 432 `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock)) 433 end else begin : gen_no_digest_write_lock 434 assign access_o.write_lock = access_pre.write_lock; 435 end 436 437 // SEC_CM: PART.MEM.SW_UNREADABLE 438 if (Info.read_lock) begin : gen_digest_read_lock 439 mubi8_t digest_locked; 440 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; 441 442 // This prevents the synthesis tool from optimizing the multibit signal. 443 prim_mubi8_sender #( 444 .AsyncOn(0) 445 ) u_prim_mubi8_sender_read_lock ( 446 .clk_i, 447 .rst_ni, 448 .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)), 449 .mubi_o(access_o.read_lock) 450 ); 451 452 `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock)) 453 end else begin : gen_no_digest_read_lock 454 1/1 assign access_o.read_lock = access_pre.read_lock; Tests: T1 T2 T3  455 end 456 457 /////////////// 458 // Registers // 459 /////////////// 460 461 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt): 461.1 `ifdef SIMULATION 461.2 prim_sparse_fsm_flop #( 461.3 .StateEnumT(state_e), 461.4 .Width($bits(state_e)), 461.5 .ResetValue($bits(state_e)'(ResetSt)), 461.6 .EnableAlertTriggerSVA(1), 461.7 .CustomForceName("state_q") 461.8 ) u_state_regs ( 461.9 .clk_i ( clk_i ), 461.10 .rst_ni ( rst_ni ), 461.11 .state_i ( state_d ), 461.12 .state_o ( ) 461.13 ); 461.14 always_ff @(posedge clk_i or negedge rst_ni) begin 461.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  461.16 1/1 state_q <= ResetSt; Tests: T1 T2 T3  461.17 end else begin 461.18 1/1 state_q <= state_d; Tests: T1 T2 T3  461.19 end 461.20 end 461.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 461.22 else begin 461.23 `ifdef UVM 461.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 461.25 "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1); 461.26 `else 461.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 461.28 `PRIM_STRINGIFY(u_state_regs_A)); 461.29 `endif 461.30 end 461.31 `else 461.32 prim_sparse_fsm_flop #( 461.33 .StateEnumT(state_e), 461.34 .Width($bits(state_e)), 461.35 .ResetValue($bits(state_e)'(ResetSt)), 461.36 .EnableAlertTriggerSVA(1) 461.37 ) u_state_regs ( 461.38 .clk_i ( `PRIM_FLOP_CLK ), 461.39 .rst_ni ( `PRIM_FLOP_RST ), 461.40 .state_i ( state_d ), 461.41 .state_o ( state_q ) 461.42 ); 461.43 `endif462 463 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 464 1/1 if (!rst_ni) begin Tests: T1 T2 T3  465 1/1 error_q <= NoError; Tests: T1 T2 T3  466 1/1 tlul_addr_q <= '0; Tests: T1 T2 T3  467 1/1 pending_tlul_error_q <= 1'b0; Tests: T1 T2 T3  468 end else begin 469 1/1 error_q <= error_d; Tests: T1 T2 T3  470 1/1 pending_tlul_error_q <= pending_tlul_error_d; Tests: T1 T2 T3  471 1/1 if (tlul_gnt_o) begin Tests: T1 T2 T3  472 1/1 tlul_addr_q <= tlul_addr_d; Tests: T2 T3 T6  473 end MISSING_ELSE

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Cond Coverage for Module self-instances :
SCORECOND
98.33 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

TotalCoveredPercent
Conditions343397.06
Logical343397.06
Non-Logical00
Event00

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT66,T43,T159

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT94,T81,T156

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT3,T4,T7
1CoveredT25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT105,T165,T166
1CoveredT105,T165,T166

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT3,T4,T7
1CoveredT3,T4,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T94,T98
11CoveredT2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T6

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T94,T95

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T94,T95

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :
SCORECOND
91.41 93.10
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

TotalCoveredPercent
Conditions312787.10
Logical312787.10
Non-Logical00
Event00

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T6
1Not Covered

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT3,T4,T7
1CoveredT25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT3,T4,T7
1CoveredT3,T4,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT94,T98,T9
11CoveredT2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T94

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T94

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134594644,DigestOffset=424,StateWidth=10 )
Cond Coverage for Module self-instances :
SCORECOND
98.33 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

TotalCoveredPercent
Conditions343397.06
Logical343397.06
Non-Logical00
Event00

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT149,T150,T42

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT94,T81,T61

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT3,T4,T7
1CoveredT25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT105
1CoveredT105

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT3,T4,T7
1CoveredT4,T7,T99

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT94,T98,T125
11CoveredT2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T6

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=906698836,DigestOffset=1136,StateWidth=10 )
Cond Coverage for Module self-instances :
SCORECOND
97.75 97.06
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

TotalCoveredPercent
Conditions343397.06
Logical343397.06
Non-Logical00
Event00

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT99,T44,T153

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT94,T81,T155

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT3,T4,T7
1CoveredT25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT105,T157,T158
1CoveredT105,T157,T158

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT3,T4,T7
1CoveredT3,T4,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T94,T98
11CoveredT2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T6

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T94,T95

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T94,T95

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Cond Coverage for Module self-instances :
SCORECOND
98.33 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

TotalCoveredPercent
Conditions343397.06
Logical343397.06
Non-Logical00
Event00

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT45,T66,T87

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT94,T71,T162

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------
-1-StatusTests
0CoveredT3,T4,T7
1CoveredT25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT105,T165,T157
1CoveredT105,T165,T157

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------
-1-StatusTests
0CoveredT3,T4,T7
1CoveredT3,T4,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T94,T98
11CoveredT2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T6

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1-StatusTests
0CoveredT2,T3,T6
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T12,T120

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T12,T120

FSM Coverage for Module : otp_ctrl_part_unbuf
Summary for FSM :: state_q
TotalCoveredPercent
States 7 7 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
ErrorSt 224 Covered T3,T4,T7
IdleSt 196 Covered T1,T2,T3
InitSt 194 Covered T1,T2,T3
InitWaitSt 207 Covered T1,T2,T3
ReadSt 236 Covered T2,T3,T6
ReadWaitSt 252 Covered T2,T3,T6
ResetSt 190 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
IdleSt->ErrorSt 315 Covered T3,T4,T7
IdleSt->ReadSt 236 Covered T2,T3,T6
InitSt->ErrorSt 315 Covered T3,T170,T117
InitSt->InitWaitSt 207 Covered T1,T2,T3
InitWaitSt->ErrorSt 224 Covered T3,T133,T170
InitWaitSt->IdleSt 218 Covered T1,T2,T3
ReadSt->ErrorSt 315 Not Covered
ReadSt->IdleSt 255 Covered T94,T95,T120
ReadSt->ReadWaitSt 252 Covered T2,T3,T6
ReadWaitSt->ErrorSt 276 Covered T98,T155,T156
ReadWaitSt->IdleSt 270 Covered T2,T3,T6
ResetSt->ErrorSt 315 Covered T105,T106,T107
ResetSt->IdleSt 196 Not Covered
ResetSt->InitSt 194 Covered T1,T2,T3


Summary for FSM :: error_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 20 10 50.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: error_q
states   Line No.   Covered   Tests   
AccessError 256 Covered T94,T95,T120
CheckFailError 317 Covered T105,T165,T157
FsmStateError 289 Covered T3,T4,T7
MacroEccCorrError 221 Covered T99,T94,T81
NoError 235 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AccessError->CheckFailError 317 Not Covered
AccessError->FsmStateError 325 Covered T148,T171,T10
AccessError->MacroEccCorrError 221 Not Covered
AccessError->NoError 235 Covered T94,T95,T120
CheckFailError->AccessError 256 Not Covered
CheckFailError->FsmStateError 325 Not Covered
CheckFailError->MacroEccCorrError 221 Not Covered
CheckFailError->NoError 235 Covered T105,T165,T157
FsmStateError->AccessError 256 Not Covered
FsmStateError->CheckFailError 317 Not Covered
FsmStateError->MacroEccCorrError 221 Not Covered
FsmStateError->NoError 235 Covered T3,T4,T7
MacroEccCorrError->AccessError 256 Not Covered
MacroEccCorrError->CheckFailError 317 Not Covered
MacroEccCorrError->FsmStateError 325 Covered T99,T155,T156
MacroEccCorrError->NoError 235 Covered T94,T81,T71
NoError->AccessError 256 Covered T94,T95,T120
NoError->CheckFailError 317 Covered T105,T165,T157
NoError->FsmStateError 289 Covered T3,T4,T7
NoError->MacroEccCorrError 221 Covered T99,T94,T81



Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :
SCOREBRANCH
91.41 95.12
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
Branches 46 39 84.78
TERNARY 336 2 2 100.00
TERNARY 349 2 2 100.00
TERNARY 358 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 420 2 2 100.00
CASE 186 23 18 78.26
IF 314 3 1 33.33
IF 321 3 3 100.00
IF 461 2 2 100.00
IF 464 3 3 100.00
IF 153 2 2 100.00


336 assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T6
0 Covered T1,T2,T3


349 assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00}; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T6


358 assign otp_size_o = (otp_addr_sel == DigestAddrSel) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T6


395 assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


420 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T7,T94
0 Covered T1,T2,T3


186 unique case (state_q) -1- 187 /////////////////////////////////////////////////////////////////// 188 // State right after reset. Wait here until we get a an 189 // initialization request. 190 ResetSt: begin 191 if (init_req_i) begin -2- 192 // If the partition does not have a digest, no initialization is necessary. 193 if (Info.sw_digest) begin -3- 194 state_d = InitSt; ==> 195 end else begin 196 state_d = IdleSt; ==> (Unreachable) 197 end 198 end MISSING_ELSE ==> 199 end 200 /////////////////////////////////////////////////////////////////// 201 // Initialization reads out the digest only in unbuffered 202 // partitions. Wait here until the OTP request has been granted. 203 // And then wait until the OTP word comes back. 204 InitSt: begin 205 otp_req_o = 1'b1; 206 if (otp_gnt_i) begin -4- 207 state_d = InitWaitSt; ==> 208 end MISSING_ELSE ==> 209 end 210 /////////////////////////////////////////////////////////////////// 211 // Wait for OTP response and write to digest buffer register. In 212 // case an OTP transaction fails, latch the OTP error code and 213 // jump to a terminal error state. 214 InitWaitSt: begin 215 if (otp_rvalid_i) begin -5- 216 digest_reg_en = 1'b1; 217 if (otp_err inside {NoError, MacroEccCorrError}) begin -6- 218 state_d = IdleSt; 219 // At this point the only error that we could have gotten are correctable ECC errors. 220 if (otp_err != NoError) begin -7- 221 error_d = MacroEccCorrError; ==> 222 end MISSING_ELSE ==> 223 end else begin 224 state_d = ErrorSt; ==> 225 error_d = otp_err; 226 end 227 end MISSING_ELSE ==> 228 end 229 /////////////////////////////////////////////////////////////////// 230 // Wait for TL-UL requests coming in. 231 // Then latch address and go to readout state. 232 IdleSt: begin 233 init_done_o = 1'b1; 234 if (tlul_req_i) begin -8- 235 error_d = NoError; // clear recoverable soft errors. ==> 236 state_d = ReadSt; 237 tlul_gnt_o = 1'b1; 238 end MISSING_ELSE ==> 239 end 240 /////////////////////////////////////////////////////////////////// 241 // If the address is out of bounds, or if the partition is 242 // locked, signal back a bus error. Note that such an error does 243 // not cause the partition to go into error state. Otherwise if 244 // these checks pass, an OTP word is requested. 245 ReadSt: begin 246 init_done_o = 1'b1; 247 // Double check the address range. 248 if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin -9- 249 otp_req_o = 1'b1; 250 otp_addr_sel = DataAddrSel; 251 if (otp_gnt_i) begin -10- 252 state_d = ReadWaitSt; ==> 253 end MISSING_ELSE ==> 254 end else begin 255 state_d = IdleSt; ==> 256 error_d = AccessError; // Signal this error, but do not go into terminal error state. 257 tlul_rvalid_o = 1'b1; 258 tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error. 259 end 260 end 261 /////////////////////////////////////////////////////////////////// 262 // Wait for OTP response and release the TL-UL response. In 263 // case an OTP transaction fails, latch the OTP error code, 264 // signal a TL-Ul bus error and jump to a terminal error state. 265 ReadWaitSt: begin 266 init_done_o = 1'b1; 267 if (otp_rvalid_i) begin -11- 268 tlul_rvalid_o = 1'b1; 269 if (otp_err inside {NoError, MacroEccCorrError}) begin -12- 270 state_d = IdleSt; 271 // At this point the only error that we could have gotten are correctable ECC errors. 272 if (otp_err != NoError) begin -13- 273 error_d = MacroEccCorrError; ==> 274 end MISSING_ELSE ==> 275 end else begin 276 state_d = ErrorSt; ==> 277 error_d = otp_err; 278 // This causes the TL-UL adapter to return a bus error. 279 tlul_rerror_o = 2'b11; 280 end 281 end MISSING_ELSE ==> 282 end 283 /////////////////////////////////////////////////////////////////// 284 // Terminal Error State. This locks access to the partition. 285 // Make sure the partition signals an error state if no error 286 // code has been latched so far. 287 ErrorSt: begin 288 if (error_q == NoError) begin -14- 289 error_d = FsmStateError; ==> 290 end MISSING_ELSE ==> 291 292 // Return bus errors if there are pending TL-UL requests. 293 if (pending_tlul_error_q) begin -15- 294 tlul_rerror_o = 2'b11; ==> 295 tlul_rvalid_o = 1'b1; 296 end else if (tlul_req_i) begin -16- 297 tlul_gnt_o = 1'b1; ==> 298 pending_tlul_error_d = 1'b1; 299 end MISSING_ELSE ==> 300 end 301 /////////////////////////////////////////////////////////////////// 302 // We should never get here. If we do (e.g. via a malicious 303 // glitch), error out immediately. 304 default: begin 305 state_d = ErrorSt; ==>

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16-StatusTests
ResetSt 1 1 - - - - - - - - - - - - - Covered T1,T2,T3
ResetSt 1 0 - - - - - - - - - - - - - Unreachable
ResetSt 0 - - - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 1 - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 0 - - - - - - - - - - - - Not Covered
InitWaitSt - - - 1 1 1 - - - - - - - - - Not Covered
InitWaitSt - - - 1 1 0 - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - - 1 0 - - - - - - - - - - Not Covered
InitWaitSt - - - 0 - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - - 1 - - - - - - - - Covered T2,T3,T6
IdleSt - - - - - - 0 - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - 1 1 - - - - - - Covered T2,T3,T6
ReadSt - - - - - - - 1 0 - - - - - - Covered T12,T127,T123
ReadSt - - - - - - - 0 - - - - - - - Covered T94,T95,T148
ReadWaitSt - - - - - - - - - 1 1 1 - - - Not Covered
ReadWaitSt - - - - - - - - - 1 1 0 - - - Covered T2,T3,T6
ReadWaitSt - - - - - - - - - 1 0 - - - - Not Covered
ReadWaitSt - - - - - - - - - 0 - - - - - Covered T2,T3,T6
ErrorSt - - - - - - - - - - - - 1 - - Covered T25,T26,T27
ErrorSt - - - - - - - - - - - - 0 - - Covered T3,T4,T7
ErrorSt - - - - - - - - - - - - - 1 - Covered T94,T98,T9
ErrorSt - - - - - - - - - - - - - 0 1 Covered T94,T98,T9
ErrorSt - - - - - - - - - - - - - 0 0 Covered T3,T4,T7
default - - - - - - - - - - - - - - - Covered T25,T26,T27


314 if (ecc_err) begin -1- 315 state_d = ErrorSt; 316 if (state_q != ErrorSt) begin -2- 317 error_d = CheckFailError; ==> 318 end MISSING_ELSE ==> 319 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin -1- 322 state_d = ErrorSt; 323 fsm_err_o = 1'b1; 324 if (state_q != ErrorSt) begin -2- 325 error_d = FsmStateError; ==> 326 end MISSING_ELSE ==> 327 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 1 Covered T3,T4,T7
1 0 Covered T3,T4,T7
0 - Covered T1,T2,T3


461 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


464 if (!rst_ni) begin -1- 465 error_q <= NoError; ==> 466 tlul_addr_q <= '0; 467 pending_tlul_error_q <= 1'b0; 468 end else begin 469 error_q <= error_d; 470 pending_tlul_error_q <= pending_tlul_error_d; 471 if (tlul_gnt_o) begin -2- 472 tlul_addr_q <= tlul_addr_d; ==> 473 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T6
0 0 Covered T1,T2,T3


153 if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin -1- 154 otp_err = NoError; ==> 155 end else begin 156 otp_err = otp_err_e'(otp_err_i); ==>

Branches:
-1-StatusTests
1 Covered T3,T99,T94
0 Covered T1,T2,T3


Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134594644,DigestOffset=424,StateWidth=10 + Info=906698836,DigestOffset=1136,StateWidth=10 + Info=-1,DigestOffset=1608,StateWidth=10 + Info=-1,DigestOffset=1648,StateWidth=10 )
Branch Coverage for Module self-instances :
SCOREBRANCH
98.33 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

SCOREBRANCH
97.75 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

SCOREBRANCH
98.33 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

SCOREBRANCH
98.33 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Line No.TotalCoveredPercent
Branches 44 44 100.00
TERNARY 336 2 2 100.00
TERNARY 349 2 2 100.00
TERNARY 358 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 420 2 2 100.00
CASE 186 23 23 100.00
IF 314 3 3 100.00
IF 321 3 3 100.00
IF 461 2 2 100.00
IF 464 3 3 100.00


336 assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T6
0 Covered T1,T2,T3


349 assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00}; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T6


358 assign otp_size_o = (otp_addr_sel == DigestAddrSel) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T6


395 assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


420 assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


186 unique case (state_q) -1- 187 /////////////////////////////////////////////////////////////////// 188 // State right after reset. Wait here until we get a an 189 // initialization request. 190 ResetSt: begin 191 if (init_req_i) begin -2- 192 // If the partition does not have a digest, no initialization is necessary. 193 if (Info.sw_digest) begin -3- 194 state_d = InitSt; ==> 195 end else begin 196 state_d = IdleSt; ==> (Unreachable) 197 end 198 end MISSING_ELSE ==> 199 end 200 /////////////////////////////////////////////////////////////////// 201 // Initialization reads out the digest only in unbuffered 202 // partitions. Wait here until the OTP request has been granted. 203 // And then wait until the OTP word comes back. 204 InitSt: begin 205 otp_req_o = 1'b1; 206 if (otp_gnt_i) begin -4- 207 state_d = InitWaitSt; ==> 208 end MISSING_ELSE ==> 209 end 210 /////////////////////////////////////////////////////////////////// 211 // Wait for OTP response and write to digest buffer register. In 212 // case an OTP transaction fails, latch the OTP error code and 213 // jump to a terminal error state. 214 InitWaitSt: begin 215 if (otp_rvalid_i) begin -5- 216 digest_reg_en = 1'b1; 217 if (otp_err inside {NoError, MacroEccCorrError}) begin -6- 218 state_d = IdleSt; 219 // At this point the only error that we could have gotten are correctable ECC errors. 220 if (otp_err != NoError) begin -7- 221 error_d = MacroEccCorrError; ==> 222 end MISSING_ELSE ==> 223 end else begin 224 state_d = ErrorSt; ==> 225 error_d = otp_err; 226 end 227 end MISSING_ELSE ==> 228 end 229 /////////////////////////////////////////////////////////////////// 230 // Wait for TL-UL requests coming in. 231 // Then latch address and go to readout state. 232 IdleSt: begin 233 init_done_o = 1'b1; 234 if (tlul_req_i) begin -8- 235 error_d = NoError; // clear recoverable soft errors. ==> 236 state_d = ReadSt; 237 tlul_gnt_o = 1'b1; 238 end MISSING_ELSE ==> 239 end 240 /////////////////////////////////////////////////////////////////// 241 // If the address is out of bounds, or if the partition is 242 // locked, signal back a bus error. Note that such an error does 243 // not cause the partition to go into error state. Otherwise if 244 // these checks pass, an OTP word is requested. 245 ReadSt: begin 246 init_done_o = 1'b1; 247 // Double check the address range. 248 if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin -9- 249 otp_req_o = 1'b1; 250 otp_addr_sel = DataAddrSel; 251 if (otp_gnt_i) begin -10- 252 state_d = ReadWaitSt; ==> 253 end MISSING_ELSE ==> 254 end else begin 255 state_d = IdleSt; ==> 256 error_d = AccessError; // Signal this error, but do not go into terminal error state. 257 tlul_rvalid_o = 1'b1; 258 tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error. 259 end 260 end 261 /////////////////////////////////////////////////////////////////// 262 // Wait for OTP response and release the TL-UL response. In 263 // case an OTP transaction fails, latch the OTP error code, 264 // signal a TL-Ul bus error and jump to a terminal error state. 265 ReadWaitSt: begin 266 init_done_o = 1'b1; 267 if (otp_rvalid_i) begin -11- 268 tlul_rvalid_o = 1'b1; 269 if (otp_err inside {NoError, MacroEccCorrError}) begin -12- 270 state_d = IdleSt; 271 // At this point the only error that we could have gotten are correctable ECC errors. 272 if (otp_err != NoError) begin -13- 273 error_d = MacroEccCorrError; ==> 274 end MISSING_ELSE ==> 275 end else begin 276 state_d = ErrorSt; ==> 277 error_d = otp_err; 278 // This causes the TL-UL adapter to return a bus error. 279 tlul_rerror_o = 2'b11; 280 end 281 end MISSING_ELSE ==> 282 end 283 /////////////////////////////////////////////////////////////////// 284 // Terminal Error State. This locks access to the partition. 285 // Make sure the partition signals an error state if no error 286 // code has been latched so far. 287 ErrorSt: begin 288 if (error_q == NoError) begin -14- 289 error_d = FsmStateError; ==> 290 end MISSING_ELSE ==> 291 292 // Return bus errors if there are pending TL-UL requests. 293 if (pending_tlul_error_q) begin -15- 294 tlul_rerror_o = 2'b11; ==> 295 tlul_rvalid_o = 1'b1; 296 end else if (tlul_req_i) begin -16- 297 tlul_gnt_o = 1'b1; ==> 298 pending_tlul_error_d = 1'b1; 299 end MISSING_ELSE ==> 300 end 301 /////////////////////////////////////////////////////////////////// 302 // We should never get here. If we do (e.g. via a malicious 303 // glitch), error out immediately. 304 default: begin 305 state_d = ErrorSt; ==>

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16-StatusTests
ResetSt 1 1 - - - - - - - - - - - - - Covered T1,T2,T3
ResetSt 1 0 - - - - - - - - - - - - - Unreachable
ResetSt 0 - - - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 1 - - - - - - - - - - - - Covered T1,T2,T3
InitSt - - 0 - - - - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - - 1 1 1 - - - - - - - - - Covered T99,T149,T44
InitWaitSt - - - 1 1 0 - - - - - - - - - Covered T1,T2,T3
InitWaitSt - - - 1 0 - - - - - - - - - - Covered T3,T132,T133
InitWaitSt - - - 0 - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - - - - - 1 - - - - - - - - Covered T2,T3,T6
IdleSt - - - - - - 0 - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - 1 1 - - - - - - Covered T2,T3,T6
ReadSt - - - - - - - 1 0 - - - - - - Covered T120,T127,T123
ReadSt - - - - - - - 0 - - - - - - - Covered T94,T95,T120
ReadWaitSt - - - - - - - - - 1 1 1 - - - Covered T94,T81,T155
ReadWaitSt - - - - - - - - - 1 1 0 - - - Covered T2,T3,T6
ReadWaitSt - - - - - - - - - 1 0 - - - - Covered T98,T155,T156
ReadWaitSt - - - - - - - - - 0 - - - - - Covered T2,T3,T6
ErrorSt - - - - - - - - - - - - 1 - - Covered T25,T26,T27
ErrorSt - - - - - - - - - - - - 0 - - Covered T3,T4,T7
ErrorSt - - - - - - - - - - - - - 1 - Covered T4,T94,T98
ErrorSt - - - - - - - - - - - - - 0 1 Covered T4,T94,T98
ErrorSt - - - - - - - - - - - - - 0 0 Covered T3,T4,T7
default - - - - - - - - - - - - - - - Covered T25,T26,T27


314 if (ecc_err) begin -1- 315 state_d = ErrorSt; 316 if (state_q != ErrorSt) begin -2- 317 error_d = CheckFailError; ==> 318 end MISSING_ELSE ==> 319 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 1 Covered T105,T165,T157
1 0 Covered T105,T165,T157
0 - Covered T1,T2,T3


321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin -1- 322 state_d = ErrorSt; 323 fsm_err_o = 1'b1; 324 if (state_q != ErrorSt) begin -2- 325 error_d = FsmStateError; ==> 326 end MISSING_ELSE ==> 327 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 1 Covered T3,T4,T7
1 0 Covered T3,T4,T7
0 - Covered T1,T2,T3


461 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


464 if (!rst_ni) begin -1- 465 error_q <= NoError; ==> 466 tlul_addr_q <= '0; 467 pending_tlul_error_q <= 1'b0; 468 end else begin 469 error_q <= error_d; 470 pending_tlul_error_q <= pending_tlul_error_d; 471 if (tlul_gnt_o) begin -2- 472 tlul_addr_q <= tlul_addr_d; ==> 473 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T6
0 0 Covered T1,T2,T3


Assert Coverage for Module : otp_ctrl_part_unbuf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 26 26 100.00 26 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 26 26 100.00 26 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AccessKnown_A 447204215 442849415 0 0
DigestKnown_A 447204215 442849415 0 0
DigestOffsetMustBeRepresentable_A 5605 5605 0 0
EccErrorState_A 447204215 37703 0 0
ErrorKnown_A 447204215 442849415 0 0
FsmStateKnown_A 447204215 442849415 0 0
InitDoneKnown_A 447204215 442849415 0 0
InitReadLocksPartition_A 447204215 84190133 0 0
InitWriteLocksPartition_A 447204215 84190133 0 0
OffsetMustBeBlockAligned_A 5605 5605 0 0
OtpAddrKnown_A 447204215 442849415 0 0
OtpCmdKnown_A 447204215 442849415 0 0
OtpErrorState_A 447204215 209 0 0
OtpReqKnown_A 447204215 442849415 0 0
OtpSizeKnown_A 447204215 442849415 0 0
OtpWdataKnown_A 447204215 442849415 0 0
ReadLockPropagation_A 447204215 85260434 0 0
SizeMustBeBlockAligned_A 5605 5605 0 0
TlulGntKnown_A 447204215 442849415 0 0
TlulRdataKnown_A 447204215 442849415 0 0
TlulReadOnReadLock_A 447204215 32828 0 0
TlulRerrorKnown_A 447204215 442849415 0 0
TlulRvalidKnown_A 447204215 442849415 0 0
WriteLockPropagation_A 447204215 9631553 0 0
gen_digest_write_lock.DigestWriteLocksPartition_A 447204215 110649337 0 0
u_state_regs_A 447204215 442849415 0 0


AccessKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

DigestKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

DigestOffsetMustBeRepresentable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5605 5605 0 0
T1 5 5 0 0
T2 5 5 0 0
T3 5 5 0 0
T4 5 5 0 0
T5 5 5 0 0
T6 5 5 0 0
T7 5 5 0 0
T8 5 5 0 0
T12 5 5 0 0
T13 5 5 0 0

EccErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 37703 0 0
T50 253148 0 0 0
T105 41124 14552 0 0
T157 0 4320 0 0
T158 0 6732 0 0
T165 0 5722 0 0
T166 0 3668 0 0
T172 0 2709 0 0
T173 118688 0 0 0
T174 640228 0 0 0
T175 502656 0 0 0
T176 193620 0 0 0
T177 131404 0 0 0
T178 122796 0 0 0
T179 330232 0 0 0
T180 20160 0 0 0

ErrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

FsmStateKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

InitDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

InitReadLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 84190133 0 0
T1 24935 805 0 0
T2 252910 3020 0 0
T3 62975 21563 0 0
T4 109150 62305 0 0
T5 102945 655 0 0
T6 353845 440 0 0
T7 457685 9600 0 0
T8 211740 3320 0 0
T12 195005 4755 0 0
T13 34640 370 0 0

InitWriteLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 84190133 0 0
T1 24935 805 0 0
T2 252910 3020 0 0
T3 62975 21563 0 0
T4 109150 62305 0 0
T5 102945 655 0 0
T6 353845 440 0 0
T7 457685 9600 0 0
T8 211740 3320 0 0
T12 195005 4755 0 0
T13 34640 370 0 0

OffsetMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5605 5605 0 0
T1 5 5 0 0
T2 5 5 0 0
T3 5 5 0 0
T4 5 5 0 0
T5 5 5 0 0
T6 5 5 0 0
T7 5 5 0 0
T8 5 5 0 0
T12 5 5 0 0
T13 5 5 0 0

OtpAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

OtpCmdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

OtpErrorState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 209 0 0
T3 12595 1 0 0
T4 21830 0 0 0
T5 20589 0 0 0
T6 70769 0 0 0
T7 91537 0 0 0
T8 42348 0 0 0
T9 122227 0 0 0
T12 39001 0 0 0
T13 6928 0 0 0
T17 12922 0 0 0
T91 27645 0 0 0
T95 99431 0 0 0
T98 110226 2 0 0
T99 12681 0 0 0
T115 0 1 0 0
T117 0 1 0 0
T120 49388 0 0 0
T121 33364 0 0 0
T125 15414 0 0 0
T126 51273 0 0 0
T128 14898 0 0 0
T132 12982 1 0 0
T133 0 1 0 0
T148 46781 0 0 0
T149 0 1 0 0
T151 0 1 0 0
T152 0 2 0 0
T154 0 1 0 0
T155 0 1 0 0
T156 0 1 0 0
T160 0 1 0 0
T162 0 2 0 0
T163 0 1 0 0
T181 0 3 0 0
T182 0 1 0 0
T183 0 2 0 0
T184 0 1 0 0
T185 0 3 0 0
T186 0 1 0 0

OtpReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

OtpSizeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

OtpWdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

ReadLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 85260434 0 0
T4 65490 35737 0 0
T7 457685 9451 0 0
T8 211740 8865 0 0
T12 195005 715 0 0
T13 34640 0 0 0
T18 0 13673 0 0
T91 138225 0 0 0
T94 556005 111152 0 0
T95 0 87711 0 0
T98 551130 45790 0 0
T99 63405 0 0 0
T120 0 2763 0 0
T121 0 17288 0 0
T122 0 5877 0 0
T125 77070 24968 0 0
T126 102546 0 0 0
T148 0 161656 0 0

SizeMustBeBlockAligned_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5605 5605 0 0
T1 5 5 0 0
T2 5 5 0 0
T3 5 5 0 0
T4 5 5 0 0
T5 5 5 0 0
T6 5 5 0 0
T7 5 5 0 0
T8 5 5 0 0
T12 5 5 0 0
T13 5 5 0 0

TlulGntKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

TlulRdataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

TlulReadOnReadLock_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 32828 0 0
T4 65490 5 0 0
T7 274611 0 0 0
T8 127044 0 0 0
T9 244454 82 0 0
T12 117003 0 0 0
T13 20784 0 0 0
T17 25844 0 0 0
T18 0 9 0 0
T19 0 39 0 0
T81 0 3 0 0
T91 82935 0 0 0
T94 556005 39 0 0
T95 198862 6 0 0
T96 0 63 0 0
T98 551130 43 0 0
T99 38043 0 0 0
T100 0 1 0 0
T120 98776 1 0 0
T121 66728 11 0 0
T125 77070 2 0 0
T126 102546 0 0 0
T128 29796 0 0 0
T148 0 50 0 0
T187 0 2 0 0

TlulRerrorKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

TlulRvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0

WriteLockPropagation_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 9631553 0 0
T7 274611 20127 0 0
T8 211740 13042 0 0
T9 244454 0 0 0
T12 195005 1985 0 0
T13 34640 0 0 0
T19 0 80245 0 0
T81 0 14241 0 0
T91 138225 0 0 0
T94 556005 57647 0 0
T95 0 23298 0 0
T96 0 34169 0 0
T98 551130 0 0 0
T99 63405 0 0 0
T104 0 17001 0 0
T120 0 9969 0 0
T121 0 3839 0 0
T123 0 17978 0 0
T124 0 34624 0 0
T125 77070 0 0 0
T126 256365 0 0 0
T127 0 9321 0 0
T142 0 19908 0 0
T146 0 29683 0 0
T188 0 9512 0 0
T189 0 1470 0 0
T190 0 2472 0 0
T191 0 25906 0 0
T192 0 6553 0 0

gen_digest_write_lock.DigestWriteLocksPartition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 110649337 0 0
T3 25190 7089 0 0
T4 43660 0 0 0
T5 41178 0 0 0
T6 141538 0 0 0
T7 366148 257193 0 0
T8 211740 63697 0 0
T9 122227 0 0 0
T12 195005 15404 0 0
T13 34640 0 0 0
T18 0 112548 0 0
T19 0 364439 0 0
T20 0 29660 0 0
T81 0 183670 0 0
T91 138225 0 0 0
T94 333603 364304 0 0
T95 0 329048 0 0
T96 0 301304 0 0
T98 330678 0 0 0
T99 63405 0 0 0
T104 0 58720 0 0
T120 0 103143 0 0
T121 0 92063 0 0
T123 0 51323 0 0
T125 46242 0 0 0
T126 153819 0 0 0
T127 0 59358 0 0
T156 0 15732 0 0
T187 0 11402 0 0
T189 0 13976 0 0
T190 0 31423 0 0
T193 0 3049 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 447204215 442849415 0 0
T1 24935 24620 0 0
T2 252910 250130 0 0
T3 62975 61500 0 0
T4 109150 107850 0 0
T5 102945 102665 0 0
T6 353845 353520 0 0
T7 457685 450175 0 0
T8 211740 208195 0 0
T12 195005 189895 0 0
T13 34640 34275 0 0