Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

137                       // Output partition error state.
138        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
139                     
140                       // This partition cannot do any write accesses, hence we tie this
141                       // constantly off.
142                       assign otp_wdata_o = '0;
143                       // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144                       // calculations and checks. To be on the safe side, the partition filters error responses at this
145                       // point and does not report any integrity errors if integrity is disabled.
146                       otp_err_e otp_err;
147                       if (Info.integrity) begin : gen_integrity
148                         assign otp_cmd_o = prim_otp_pkg::Read;
149        1/1              assign otp_err = otp_err_e'(otp_err_i);
           Tests:       T1 T2 T3 
150                       end else begin : gen_no_integrity
151                         assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152                         always_comb begin
153                           if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
154                             otp_err = NoError;
155                           end else begin
156                             otp_err = otp_err_e'(otp_err_i);
157                           end
158                         end
159                       end
160                     
161                       `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162                       always_comb begin : p_fsm
163                         // Default assignments
164        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
165                     
166                         // Response to init request
167        1/1              init_done_o = 1'b0;
           Tests:       T1 T2 T3 
168                     
169                         // OTP signals
170        1/1              otp_req_o   = 1'b0;
           Tests:       T1 T2 T3 
171        1/1              otp_addr_sel = DigestAddrSel;
           Tests:       T1 T2 T3 
172                     
173                         // TL-UL signals
174        1/1              tlul_gnt_o      = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              tlul_rvalid_o   = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              tlul_rerror_o   = '0;
           Tests:       T1 T2 T3 
177                     
178                         // Enable for buffered digest register
179        1/1              digest_reg_en = 1'b0;
           Tests:       T1 T2 T3 
180                     
181                         // Error Register
182        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
183        1/1              pending_tlul_error_d = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           ///////////////////////////////////////////////////////////////////
188                           // State right after reset. Wait here until we get a an
189                           // initialization request.
190                           ResetSt: begin
191        1/1                  if (init_req_i) begin
           Tests:       T1 T2 T3 
192                               // If the partition does not have a digest, no initialization is necessary.
193        1/1                    if (Info.sw_digest) begin
           Tests:       T1 T2 T3 
194        1/1                      state_d = InitSt;
           Tests:       T1 T2 T3 
195                               end else begin
196        unreachable              state_d = IdleSt;
197                               end
198                             end
                        MISSING_ELSE
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Initialization reads out the digest only in unbuffered
202                           // partitions. Wait here until the OTP request has been granted.
203                           // And then wait until the OTP word comes back.
204                           InitSt: begin
205        1/1                  otp_req_o = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  if (otp_gnt_i) begin
           Tests:       T1 T2 T3 
207        1/1                    state_d = InitWaitSt;
           Tests:       T1 T2 T3 
208                             end
                        MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // Wait for OTP response and write to digest buffer register. In
212                           // case an OTP transaction fails, latch the  OTP error code and
213                           // jump to a terminal error state.
214                           InitWaitSt: begin
215        1/1                  if (otp_rvalid_i) begin
           Tests:       T1 T2 T3 
216        1/1                    digest_reg_en = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T1 T2 T3 
218        1/1                      state_d = IdleSt;
           Tests:       T1 T2 T3 
219                                 // At this point the only error that we could have gotten are correctable ECC errors.
220        1/1                      if (otp_err != NoError) begin
           Tests:       T1 T2 T3 
221        1/1                        error_d = MacroEccCorrError;
           Tests:       T66 T43 T159 
222                                 end
                        MISSING_ELSE
223                               end else begin
224        1/1                      state_d = ErrorSt;
           Tests:       T132 T160 T161 
225        1/1                      error_d = otp_err;
           Tests:       T132 T160 T161 
226                               end
227                             end
                        MISSING_ELSE
228                           end
229                           ///////////////////////////////////////////////////////////////////
230                           // Wait for TL-UL requests coming in.
231                           // Then latch address and go to readout state.
232                           IdleSt: begin
233        1/1                  init_done_o = 1'b1;
           Tests:       T1 T2 T3 
234        1/1                  if (tlul_req_i) begin
           Tests:       T1 T2 T3 
235        1/1                    error_d = NoError; // clear recoverable soft errors.
           Tests:       T2 T3 T6 
236        1/1                    state_d = ReadSt;
           Tests:       T2 T3 T6 
237        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T2 T3 T6 
238                             end
                        MISSING_ELSE
239                           end
240                           ///////////////////////////////////////////////////////////////////
241                           // If the address is out of bounds, or if the partition is
242                           // locked, signal back a bus error. Note that such an error does
243                           // not cause the partition to go into error state. Otherwise if
244                           // these checks pass, an OTP word is requested.
245                           ReadSt: begin
246        1/1                  init_done_o = 1'b1;
           Tests:       T2 T3 T6 
247                             // Double check the address range.
248        1/1                  if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
           Tests:       T2 T3 T6 
249        1/1                    otp_req_o = 1'b1;
           Tests:       T2 T3 T6 
250        1/1                    otp_addr_sel = DataAddrSel;
           Tests:       T2 T3 T6 
251        1/1                    if (otp_gnt_i) begin
           Tests:       T2 T3 T6 
252        1/1                      state_d = ReadWaitSt;
           Tests:       T2 T3 T6 
253                               end
                        MISSING_ELSE
254                             end else begin
255        1/1                    state_d = IdleSt;
           Tests:       T94 T95 T121 
256        1/1                    error_d = AccessError; // Signal this error, but do not go into terminal error state.
           Tests:       T94 T95 T121 
257        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T94 T95 T121 
258        1/1                    tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
           Tests:       T94 T95 T121 
259                             end
260                           end
261                           ///////////////////////////////////////////////////////////////////
262                           // Wait for OTP response and release the TL-UL response. In
263                           // case an OTP transaction fails, latch the OTP error code,
264                           // signal a TL-Ul bus error and jump to a terminal error state.
265                           ReadWaitSt: begin
266        1/1                  init_done_o = 1'b1;
           Tests:       T2 T3 T6 
267        1/1                  if (otp_rvalid_i) begin
           Tests:       T2 T3 T6 
268        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T2 T3 T6 
269        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T2 T3 T6 
270        1/1                      state_d = IdleSt;
           Tests:       T2 T3 T6 
271                                 // At this point the only error that we could have gotten are correctable ECC errors.
272        1/1                      if (otp_err != NoError) begin
           Tests:       T2 T3 T6 
273        1/1                        error_d = MacroEccCorrError;
           Tests:       T94 T81 T156 
274                                 end
                        MISSING_ELSE
275                               end else begin
276        1/1                      state_d = ErrorSt;
           Tests:       T162 T163 T164 
277        1/1                      error_d = otp_err;
           Tests:       T162 T163 T164 
278                                 // This causes the TL-UL adapter to return a bus error.
279        1/1                      tlul_rerror_o = 2'b11;
           Tests:       T162 T163 T164 
280                               end
281                             end
                        MISSING_ELSE
282                           end
283                           ///////////////////////////////////////////////////////////////////
284                           // Terminal Error State. This locks access to the partition.
285                           // Make sure the partition signals an error state if no error
286                           // code has been latched so far.
287                           ErrorSt: begin
288        1/1                  if (error_q == NoError) begin
           Tests:       T3 T4 T7 
289        1/1                    error_d = FsmStateError;
           Tests:       T25 T26 T27 
290                             end
                        MISSING_ELSE
291                     
292                             // Return bus errors if there are pending TL-UL requests.
293        1/1                  if (pending_tlul_error_q) begin
           Tests:       T3 T4 T7 
294        1/1                    tlul_rerror_o = 2'b11;
           Tests:       T4 T94 T98 
295        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T4 T94 T98 
296        1/1                  end else if (tlul_req_i) begin
           Tests:       T3 T4 T7 
297        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T4 T94 T98 
298        1/1                    pending_tlul_error_d = 1'b1;
           Tests:       T4 T94 T98 
299                             end
                        MISSING_ELSE
300                           end
301                           ///////////////////////////////////////////////////////////////////
302                           // We should never get here. If we do (e.g. via a malicious
303                           // glitch), error out immediately.
304                           default: begin
305                             state_d = ErrorSt;
306                             fsm_err_o = 1'b1;
307                           end
308                           ///////////////////////////////////////////////////////////////////
309                         endcase // state_q
310                     
311                         // Unconditionally jump into the terminal error state in case of
312                         // an ECC error or escalation, and lock access to the partition down.
313                         // SEC_CM: PART.FSM.LOCAL_ESC
314        1/1              if (ecc_err) begin
           Tests:       T1 T2 T3 
315        1/1                state_d = ErrorSt;
           Tests:       T105 T165 T166 
316        1/1                if (state_q != ErrorSt) begin
           Tests:       T105 T165 T166 
317        1/1                  error_d = CheckFailError;
           Tests:       T105 T165 T166 
318                           end
                        MISSING_ELSE
319                         end
                        MISSING_ELSE
320                         // SEC_CM: PART.FSM.GLOBAL_ESC
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                state_d = ErrorSt;
           Tests:       T3 T4 T7 
323        1/1                fsm_err_o = 1'b1;
           Tests:       T3 T4 T7 
324        1/1                if (state_q != ErrorSt) begin
           Tests:       T3 T4 T7 
325        1/1                  error_d = FsmStateError;
           Tests:       T3 T4 T7 
326                           end
                        MISSING_ELSE
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       ///////////////////////////////////
331                       // Signals to/from TL-UL Adapter //
332                       ///////////////////////////////////
333                     
334        1/1            assign tlul_addr_d  = tlul_addr_i;
           Tests:       T1 T2 T3 
335                       // Do not forward data in case of an error.
336        1/1            assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
           Tests:       T1 T2 T3 
337                     
338                       if (Info.offset == 0) begin : gen_zero_offset
339                         assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
340                     
341                       end else begin : gen_nonzero_offset
342        1/1              assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
           Tests:       T1 T2 T3 
343                                                     {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344                       end
345                     
346                       // Note that OTP works on halfword (16bit) addresses, hence need to
347                       // shift the addresses appropriately.
348                       logic [OtpByteAddrWidth-1:0] addr_calc;
349        1/1            assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
           Tests:       T1 T2 T3 
350        1/1            assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
           Tests:       T1 T2 T3 
351                     
352                       if (OtpAddrShift > 0) begin : gen_unused
353                         logic unused_bits;
354        1/1              assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
           Tests:       T1 T2 T3 
355                       end
356                     
357                       // Request 32bit except in case of the digest.
358        1/1            assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
           Tests:       T1 T2 T3 
359                                           OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360                                           OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361                     
362                       ////////////////
363                       // Digest Reg //
364                       ////////////////
365                     
366                       if (Info.sw_digest) begin : gen_ecc_reg
367                         // SEC_CM: PART.DATA_REG.INTEGRITY
368                         otp_ctrl_ecc_reg #(
369                           .Width ( ScrmblBlockWidth ),
370                           .Depth ( 1                )
371                         ) u_otp_ctrl_ecc_reg (
372                           .clk_i,
373                           .rst_ni,
374                           .wren_i    ( digest_reg_en ),
375                           .addr_i    ( '0            ),
376                           .wdata_i   ( otp_rdata_i   ),
377                           .rdata_o   (               ),
378                           .data_o    ( digest_o      ),
379                           .ecc_err_o ( ecc_err       )
380                         );
381                       end else begin : gen_no_ecc_reg
382                         logic unused_digest_reg_en;
383                         logic unused_rdata;
384                         assign unused_digest_reg_en = digest_reg_en;
385                         assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386                         assign digest_o = '0;
387                         assign ecc_err = 1'b0;
388                       end
389                     
390                       ////////////////////////
391                       // DAI Access Control //
392                       ////////////////////////
393                     
394                       mubi8_t init_locked;
395        1/1            assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
396                     
397                       // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398                       // Note that the locks are redundantly encoded values.
399                       part_access_t access_pre;
400                       prim_mubi8_sender #(
401                         .AsyncOn(0)
402                       ) u_prim_mubi8_sender_write_lock_pre (
403                         .clk_i,
404                         .rst_ni,
405                         .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406                         .mubi_o(access_pre.write_lock)
407                       );
408                       prim_mubi8_sender #(
409                         .AsyncOn(0)
410                       ) u_prim_mubi8_sender_read_lock_pre (
411                         .clk_i,
412                         .rst_ni,
413                         .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414                         .mubi_o(access_pre.read_lock)
415                       );
416                     
417                       // SEC_CM: PART.MEM.SW_UNWRITABLE
418                       if (Info.write_lock) begin : gen_digest_write_lock
419                         mubi8_t digest_locked;
420        1/1              assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
421                     
422                         // This prevents the synthesis tool from optimizing the multibit signal.
423                         prim_mubi8_sender #(
424                           .AsyncOn(0)
425                         ) u_prim_mubi8_sender_write_lock (
426                           .clk_i,
427                           .rst_ni,
428                           .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429                           .mubi_o(access_o.write_lock)
430                         );
431                     
432                         `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433                       end else begin : gen_no_digest_write_lock
434                         assign access_o.write_lock = access_pre.write_lock;
435                       end
436                     
437                       // SEC_CM: PART.MEM.SW_UNREADABLE
438                       if (Info.read_lock) begin : gen_digest_read_lock
439                         mubi8_t digest_locked;
440                         assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441                     
442                         // This prevents the synthesis tool from optimizing the multibit signal.
443                         prim_mubi8_sender #(
444                           .AsyncOn(0)
445                         ) u_prim_mubi8_sender_read_lock (
446                           .clk_i,
447                           .rst_ni,
448                           .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449                           .mubi_o(access_o.read_lock)
450                         );
451                     
452                         `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453                       end else begin : gen_no_digest_read_lock
454        1/1              assign access_o.read_lock = access_pre.read_lock;
           Tests:       T1 T2 T3 
455                       end
456                     
457                       ///////////////
458                       // Registers //
459                       ///////////////
460                     
461        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1                   `ifdef SIMULATION                                   
461.2                       prim_sparse_fsm_flop #(                           
461.3                         .StateEnumT(state_e),                            
461.4                         .Width($bits(state_e)),                          
461.5                         .ResetValue($bits(state_e)'(ResetSt)),          
461.6                         .EnableAlertTriggerSVA(1), 
461.7                         .CustomForceName("state_q")          
461.8                       ) u_state_regs (                                        
461.9                         .clk_i   ( clk_i   ),                           
461.10                        .rst_ni  ( rst_ni ),                           
461.11                        .state_i ( state_d     ),                           
461.12                        .state_o (         )                            
461.13                      );                                                
461.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
461.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
461.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
461.17                      end else begin                                    
461.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
461.19                      end                                               
461.20                    end  
461.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
461.22                      else begin                                                                           
461.23                        `ifdef UVM                                                                               
461.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
461.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);                                
461.26                  `else                                                                                    
461.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
461.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
461.29                  `endif                                                              
461.30                      end 
461.31                    `else                                               
461.32                      prim_sparse_fsm_flop #(                           
461.33                        .StateEnumT(state_e),                            
461.34                        .Width($bits(state_e)),                          
461.35                        .ResetValue($bits(state_e)'(ResetSt)),          
461.36                        .EnableAlertTriggerSVA(1)  
461.37                      ) u_state_regs (                                        
461.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
461.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
461.40                        .state_i ( state_d     ),                           
461.41                        .state_o ( state_q     )                            
461.42                      );                                                
461.43                    `endif462                     
463                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
465        1/1                error_q              <= NoError;
           Tests:       T1 T2 T3 
466        1/1                tlul_addr_q          <= '0;
           Tests:       T1 T2 T3 
467        1/1                pending_tlul_error_q <= 1'b0;
           Tests:       T1 T2 T3 
468                         end else begin
469        1/1                error_q              <= error_d;
           Tests:       T1 T2 T3 
470        1/1                pending_tlul_error_q <= pending_tlul_error_d;
           Tests:       T1 T2 T3 
471        1/1                if (tlul_gnt_o) begin
           Tests:       T1 T2 T3 
472        1/1                  tlul_addr_q <= tlul_addr_d;
           Tests:       T2 T3 T6 
473                           end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T66,T43,T159

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T94,T81,T156

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T105,T165,T166
1	Covered	T105,T165,T166

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T3,T4,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T94,T98
1	1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T6

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T94,T95

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T94,T95

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T4,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T6
ReadWaitSt	252	Covered	T2,T3,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T4,T7,T99
IdleSt->ReadSt	236	Covered	T2,T3,T6
InitSt->ErrorSt	315	Covered	T3,T170,T117
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T132,T133,T149
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T94,T95,T121
ReadSt->ReadWaitSt	252	Covered	T2,T3,T6
ReadWaitSt->ErrorSt	276	Covered	T162,T163,T164
ReadWaitSt->IdleSt	270	Covered	T2,T3,T6
ResetSt->ErrorSt	315	Covered	T105,T106,T107
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T94,T95,T121
CheckFailError	317	Covered	T105,T165,T166
FsmStateError	289	Covered	T3,T4,T7
MacroEccCorrError	221	Covered	T94,T81,T156
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T162,T198,T21
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T94,T95,T121
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T105,T165,T166
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T4,T7
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T156,T162,T115
MacroEccCorrError->NoError	235	Covered	T94,T81,T71
NoError->AccessError	256	Covered	T94,T95,T121
NoError->CheckFailError	317	Covered	T105,T165,T166
NoError->FsmStateError	289	Covered	T3,T4,T7
NoError->MacroEccCorrError	221	Covered	T94,T81,T156

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

336          assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
                                                                          -1-  
                                                                          ==>  
                                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

349          assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

358          assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

395          assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

420            assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T94,T95
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              ///////////////////////////////////////////////////////////////////
188              // State right after reset. Wait here until we get a an
189              // initialization request.
190              ResetSt: begin
191                if (init_req_i) begin
                   -2-  
192                  // If the partition does not have a digest, no initialization is necessary.
193                  if (Info.sw_digest) begin
                     -3-  
194                    state_d = InitSt;
                       ==>
195                  end else begin
196                    state_d = IdleSt;
                       ==> (Unreachable)
197                  end
198                end
                   MISSING_ELSE
                   ==>
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Initialization reads out the digest only in unbuffered
202              // partitions. Wait here until the OTP request has been granted.
203              // And then wait until the OTP word comes back.
204              InitSt: begin
205                otp_req_o = 1'b1;
206                if (otp_gnt_i) begin
                   -4-  
207                  state_d = InitWaitSt;
                     ==>
208                end
                   MISSING_ELSE
                   ==>
209              end
210              ///////////////////////////////////////////////////////////////////
211              // Wait for OTP response and write to digest buffer register. In
212              // case an OTP transaction fails, latch the  OTP error code and
213              // jump to a terminal error state.
214              InitWaitSt: begin
215                if (otp_rvalid_i) begin
                   -5-  
216                  digest_reg_en = 1'b1;
217                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -6-  
218                    state_d = IdleSt;
219                    // At this point the only error that we could have gotten are correctable ECC errors.
220                    if (otp_err != NoError) begin
                       -7-  
221                      error_d = MacroEccCorrError;
                         ==>
222                    end
                       MISSING_ELSE
                       ==>
223                  end else begin
224                    state_d = ErrorSt;
                       ==>
225                    error_d = otp_err;
226                  end
227                end
                   MISSING_ELSE
                   ==>
228              end
229              ///////////////////////////////////////////////////////////////////
230              // Wait for TL-UL requests coming in.
231              // Then latch address and go to readout state.
232              IdleSt: begin
233                init_done_o = 1'b1;
234                if (tlul_req_i) begin
                   -8-  
235                  error_d = NoError; // clear recoverable soft errors.
                     ==>
236                  state_d = ReadSt;
237                  tlul_gnt_o = 1'b1;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              ///////////////////////////////////////////////////////////////////
241              // If the address is out of bounds, or if the partition is
242              // locked, signal back a bus error. Note that such an error does
243              // not cause the partition to go into error state. Otherwise if
244              // these checks pass, an OTP word is requested.
245              ReadSt: begin
246                init_done_o = 1'b1;
247                // Double check the address range.
248                if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
                   -9-  
249                  otp_req_o = 1'b1;
250                  otp_addr_sel = DataAddrSel;
251                  if (otp_gnt_i) begin
                     -10-  
252                    state_d = ReadWaitSt;
                       ==>
253                  end
                     MISSING_ELSE
                     ==>
254                end else begin
255                  state_d = IdleSt;
                     ==>
256                  error_d = AccessError; // Signal this error, but do not go into terminal error state.
257                  tlul_rvalid_o = 1'b1;
258                  tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259                end
260              end
261              ///////////////////////////////////////////////////////////////////
262              // Wait for OTP response and release the TL-UL response. In
263              // case an OTP transaction fails, latch the OTP error code,
264              // signal a TL-Ul bus error and jump to a terminal error state.
265              ReadWaitSt: begin
266                init_done_o = 1'b1;
267                if (otp_rvalid_i) begin
                   -11-  
268                  tlul_rvalid_o = 1'b1;
269                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -12-  
270                    state_d = IdleSt;
271                    // At this point the only error that we could have gotten are correctable ECC errors.
272                    if (otp_err != NoError) begin
                       -13-  
273                      error_d = MacroEccCorrError;
                         ==>
274                    end
                       MISSING_ELSE
                       ==>
275                  end else begin
276                    state_d = ErrorSt;
                       ==>
277                    error_d = otp_err;
278                    // This causes the TL-UL adapter to return a bus error.
279                    tlul_rerror_o = 2'b11;
280                  end
281                end
                   MISSING_ELSE
                   ==>
282              end
283              ///////////////////////////////////////////////////////////////////
284              // Terminal Error State. This locks access to the partition.
285              // Make sure the partition signals an error state if no error
286              // code has been latched so far.
287              ErrorSt: begin
288                if (error_q == NoError) begin
                   -14-  
289                  error_d = FsmStateError;
                     ==>
290                end
                   MISSING_ELSE
                   ==>
291        
292                // Return bus errors if there are pending TL-UL requests.
293                if (pending_tlul_error_q) begin
                   -15-  
294                  tlul_rerror_o = 2'b11;
                     ==>
295                  tlul_rvalid_o = 1'b1;
296                end else if (tlul_req_i) begin
                            -16-  
297                  tlul_gnt_o = 1'b1;
                     ==>
298                  pending_tlul_error_d = 1'b1;
299                end
                   MISSING_ELSE
                   ==>
300              end
301              ///////////////////////////////////////////////////////////////////
302              // We should never get here. If we do (e.g. via a malicious
303              // glitch), error out immediately.
304              default: begin
305                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T66,T43,T159
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T132,T160,T161
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T127,T123,T190
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T94,T95,T121
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T94,T81,T156
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T162,T163,T164
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T4,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T94,T98
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T94,T98
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T4,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

314            if (ecc_err) begin
               -1-  
315              state_d = ErrorSt;
316              if (state_q != ErrorSt) begin
                 -2-  
317                error_d = CheckFailError;
                   ==>
318              end
                 MISSING_ELSE
                 ==>
319            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T105,T165,T166
1	0	Covered	T105,T165,T166
0	-	Covered	T1,T2,T3

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
               -1-  
322              state_d = ErrorSt;
323              fsm_err_o = 1'b1;
324              if (state_q != ErrorSt) begin
                 -2-  
325                error_d = FsmStateError;
                   ==>
326              end
                 MISSING_ELSE
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T4,T7
1	0	Covered	T3,T4,T7
0	-	Covered	T1,T2,T3

461          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

464            if (!rst_ni) begin
               -1-  
465              error_q              <= NoError;
                 ==>
466              tlul_addr_q          <= '0;
467              pending_tlul_error_q <= 1'b0;
468            end else begin
469              error_q              <= error_d;
470              pending_tlul_error_q <= pending_tlul_error_d;
471              if (tlul_gnt_o) begin
                 -2-  
472                tlul_addr_q <= tlul_addr_d;
                   ==>
473              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	89440843	88569883	0	0
DigestKnown_A	89440843	88569883	0	0
DigestOffsetMustBeRepresentable_A	1121	1121	0	0
EccErrorState_A	89440843	10167	0	0
ErrorKnown_A	89440843	88569883	0	0
FsmStateKnown_A	89440843	88569883	0	0
InitDoneKnown_A	89440843	88569883	0	0
InitReadLocksPartition_A	89440843	17018306	0	0
InitWriteLocksPartition_A	89440843	17018306	0	0
OffsetMustBeBlockAligned_A	1121	1121	0	0
OtpAddrKnown_A	89440843	88569883	0	0
OtpCmdKnown_A	89440843	88569883	0	0
OtpErrorState_A	89440843	50	0	0
OtpReqKnown_A	89440843	88569883	0	0
OtpSizeKnown_A	89440843	88569883	0	0
OtpWdataKnown_A	89440843	88569883	0	0
ReadLockPropagation_A	89440843	16800327	0	0
SizeMustBeBlockAligned_A	1121	1121	0	0
TlulGntKnown_A	89440843	88569883	0	0
TlulRdataKnown_A	89440843	88569883	0	0
TlulReadOnReadLock_A	89440843	6724	0	0
TlulRerrorKnown_A	89440843	88569883	0	0
TlulRvalidKnown_A	89440843	88569883	0	0
WriteLockPropagation_A	89440843	2429998	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	89440843	26882403	0	0
u_state_regs_A	89440843	88569883	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	10167	0	0
T50	63287	0	0	0
T105	10281	3638	0	0
T165	0	2861	0	0
T166	0	3668	0	0
T173	29672	0	0	0
T174	160057	0	0	0
T175	125664	0	0	0
T176	48405	0	0	0
T177	32851	0	0	0
T178	30699	0	0	0
T179	82558	0	0	0
T180	5040	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	17018306	0	0
T1	4987	178	0	0
T2	50582	723	0	0
T3	12595	4348	0	0
T4	21830	12512	0	0
T5	20589	148	0	0
T6	70769	105	0	0
T7	91537	2243	0	0
T8	42348	800	0	0
T12	39001	1138	0	0
T13	6928	91	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	17018306	0	0
T1	4987	178	0	0
T2	50582	723	0	0
T3	12595	4348	0	0
T4	21830	12512	0	0
T5	20589	148	0	0
T6	70769	105	0	0
T7	91537	2243	0	0
T8	42348	800	0	0
T12	39001	1138	0	0
T13	6928	91	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	50	0	0
T20	50788	0	0	0
T104	71862	0	0	0
T132	12982	1	0	0
T156	80163	0	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T168	0	2	0	0
T171	109742	0	0	0
T185	0	2	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	22869	0	0	0
T204	8242	0	0	0
T205	81882	0	0	0
T206	15606	0	0	0
T207	4521	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	16800327	0	0
T7	91537	1488	0	0
T8	42348	2125	0	0
T12	39001	0	0	0
T13	6928	0	0	0
T18	0	3847	0	0
T91	27645	0	0	0
T94	111201	24924	0	0
T95	0	23015	0	0
T98	110226	9150	0	0
T99	12681	0	0	0
T120	0	247	0	0
T121	0	2985	0	0
T122	0	1174	0	0
T125	15414	5918	0	0
T126	51273	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	6724	0	0
T4	21830	1	0	0
T7	91537	0	0	0
T8	42348	0	0	0
T9	0	17	0	0
T12	39001	0	0	0
T13	6928	0	0	0
T18	0	2	0	0
T19	0	12	0	0
T91	27645	0	0	0
T94	111201	7	0	0
T95	0	1	0	0
T96	0	19	0	0
T98	110226	8	0	0
T99	12681	0	0	0
T121	0	1	0	0
T125	15414	0	0	0
T148	0	10	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	2429998	0	0
T7	91537	6078	0	0
T8	42348	0	0	0
T12	39001	0	0	0
T13	6928	0	0	0
T19	0	28398	0	0
T91	27645	0	0	0
T94	111201	21084	0	0
T96	0	10638	0	0
T98	110226	0	0	0
T99	12681	0	0	0
T123	0	1155	0	0
T124	0	28310	0	0
T125	15414	0	0	0
T126	51273	0	0	0
T142	0	3244	0	0
T146	0	8581	0	0
T190	0	2472	0	0
T192	0	3365	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	26882403	0	0
T7	91537	78364	0	0
T8	42348	0	0	0
T12	39001	0	0	0
T13	6928	0	0	0
T18	0	28086	0	0
T19	0	121355	0	0
T81	0	61042	0	0
T91	27645	0	0	0
T94	111201	90872	0	0
T95	0	81956	0	0
T96	0	75020	0	0
T98	110226	0	0	0
T99	12681	0	0	0
T121	0	16980	0	0
T125	15414	0	0	0
T126	51273	0	0	0
T127	0	29594	0	0
T187	0	3795	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

137                       // Output partition error state.
138        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
139                     
140                       // This partition cannot do any write accesses, hence we tie this
141                       // constantly off.
142                       assign otp_wdata_o = '0;
143                       // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144                       // calculations and checks. To be on the safe side, the partition filters error responses at this
145                       // point and does not report any integrity errors if integrity is disabled.
146                       otp_err_e otp_err;
147                       if (Info.integrity) begin : gen_integrity
148                         assign otp_cmd_o = prim_otp_pkg::Read;
149        1/1              assign otp_err = otp_err_e'(otp_err_i);
           Tests:       T1 T2 T3 
150                       end else begin : gen_no_integrity
151                         assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152                         always_comb begin
153                           if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
154                             otp_err = NoError;
155                           end else begin
156                             otp_err = otp_err_e'(otp_err_i);
157                           end
158                         end
159                       end
160                     
161                       `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162                       always_comb begin : p_fsm
163                         // Default assignments
164        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
165                     
166                         // Response to init request
167        1/1              init_done_o = 1'b0;
           Tests:       T1 T2 T3 
168                     
169                         // OTP signals
170        1/1              otp_req_o   = 1'b0;
           Tests:       T1 T2 T3 
171        1/1              otp_addr_sel = DigestAddrSel;
           Tests:       T1 T2 T3 
172                     
173                         // TL-UL signals
174        1/1              tlul_gnt_o      = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              tlul_rvalid_o   = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              tlul_rerror_o   = '0;
           Tests:       T1 T2 T3 
177                     
178                         // Enable for buffered digest register
179        1/1              digest_reg_en = 1'b0;
           Tests:       T1 T2 T3 
180                     
181                         // Error Register
182        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
183        1/1              pending_tlul_error_d = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           ///////////////////////////////////////////////////////////////////
188                           // State right after reset. Wait here until we get a an
189                           // initialization request.
190                           ResetSt: begin
191        1/1                  if (init_req_i) begin
           Tests:       T1 T2 T3 
192                               // If the partition does not have a digest, no initialization is necessary.
193        1/1                    if (Info.sw_digest) begin
           Tests:       T1 T2 T3 
194        1/1                      state_d = InitSt;
           Tests:       T1 T2 T3 
195                               end else begin
196        unreachable              state_d = IdleSt;
197                               end
198                             end
                        MISSING_ELSE
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Initialization reads out the digest only in unbuffered
202                           // partitions. Wait here until the OTP request has been granted.
203                           // And then wait until the OTP word comes back.
204                           InitSt: begin
205        1/1                  otp_req_o = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  if (otp_gnt_i) begin
           Tests:       T1 T2 T3 
207        1/1                    state_d = InitWaitSt;
           Tests:       T1 T2 T3 
208                             end
                        MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // Wait for OTP response and write to digest buffer register. In
212                           // case an OTP transaction fails, latch the  OTP error code and
213                           // jump to a terminal error state.
214                           InitWaitSt: begin
215        1/1                  if (otp_rvalid_i) begin
           Tests:       T1 T2 T3 
216        1/1                    digest_reg_en = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T1 T2 T3 
218        1/1                      state_d = IdleSt;
           Tests:       T1 T2 T3 
219                                 // At this point the only error that we could have gotten are correctable ECC errors.
220        1/1                      if (otp_err != NoError) begin
           Tests:       T1 T2 T3 
221        1/1                        error_d = MacroEccCorrError;
           Tests:       T45 T66 T87 
222                                 end
                        MISSING_ELSE
223                               end else begin
224        1/1                      state_d = ErrorSt;
           Tests:       T99 T150 T167 
225        1/1                      error_d = otp_err;
           Tests:       T99 T150 T167 
226                               end
227                             end
                        MISSING_ELSE
228                           end
229                           ///////////////////////////////////////////////////////////////////
230                           // Wait for TL-UL requests coming in.
231                           // Then latch address and go to readout state.
232                           IdleSt: begin
233        1/1                  init_done_o = 1'b1;
           Tests:       T1 T2 T3 
234        1/1                  if (tlul_req_i) begin
           Tests:       T1 T2 T3 
235        1/1                    error_d = NoError; // clear recoverable soft errors.
           Tests:       T2 T3 T6 
236        1/1                    state_d = ReadSt;
           Tests:       T2 T3 T6 
237        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T2 T3 T6 
238                             end
                        MISSING_ELSE
239                           end
240                           ///////////////////////////////////////////////////////////////////
241                           // If the address is out of bounds, or if the partition is
242                           // locked, signal back a bus error. Note that such an error does
243                           // not cause the partition to go into error state. Otherwise if
244                           // these checks pass, an OTP word is requested.
245                           ReadSt: begin
246        1/1                  init_done_o = 1'b1;
           Tests:       T2 T3 T6 
247                             // Double check the address range.
248        1/1                  if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
           Tests:       T2 T3 T6 
249        1/1                    otp_req_o = 1'b1;
           Tests:       T2 T3 T6 
250        1/1                    otp_addr_sel = DataAddrSel;
           Tests:       T2 T3 T6 
251        1/1                    if (otp_gnt_i) begin
           Tests:       T2 T3 T6 
252        1/1                      state_d = ReadWaitSt;
           Tests:       T2 T3 T6 
253                               end
                        MISSING_ELSE
254                             end else begin
255        1/1                    state_d = IdleSt;
           Tests:       T94 T95 T120 
256        1/1                    error_d = AccessError; // Signal this error, but do not go into terminal error state.
           Tests:       T94 T95 T120 
257        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T94 T95 T120 
258        1/1                    tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
           Tests:       T94 T95 T120 
259                             end
260                           end
261                           ///////////////////////////////////////////////////////////////////
262                           // Wait for OTP response and release the TL-UL response. In
263                           // case an OTP transaction fails, latch the OTP error code,
264                           // signal a TL-Ul bus error and jump to a terminal error state.
265                           ReadWaitSt: begin
266        1/1                  init_done_o = 1'b1;
           Tests:       T2 T3 T6 
267        1/1                  if (otp_rvalid_i) begin
           Tests:       T2 T3 T6 
268        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T2 T3 T6 
269        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T2 T3 T6 
270        1/1                      state_d = IdleSt;
           Tests:       T2 T3 T6 
271                                 // At this point the only error that we could have gotten are correctable ECC errors.
272        1/1                      if (otp_err != NoError) begin
           Tests:       T2 T3 T6 
273        1/1                        error_d = MacroEccCorrError;
           Tests:       T94 T71 T162 
274                                 end
                        MISSING_ELSE
275                               end else begin
276        1/1                      state_d = ErrorSt;
           Tests:       T115 T168 T169 
277        1/1                      error_d = otp_err;
           Tests:       T115 T168 T169 
278                                 // This causes the TL-UL adapter to return a bus error.
279        1/1                      tlul_rerror_o = 2'b11;
           Tests:       T115 T168 T169 
280                               end
281                             end
                        MISSING_ELSE
282                           end
283                           ///////////////////////////////////////////////////////////////////
284                           // Terminal Error State. This locks access to the partition.
285                           // Make sure the partition signals an error state if no error
286                           // code has been latched so far.
287                           ErrorSt: begin
288        1/1                  if (error_q == NoError) begin
           Tests:       T3 T4 T7 
289        1/1                    error_d = FsmStateError;
           Tests:       T25 T26 T27 
290                             end
                        MISSING_ELSE
291                     
292                             // Return bus errors if there are pending TL-UL requests.
293        1/1                  if (pending_tlul_error_q) begin
           Tests:       T3 T4 T7 
294        1/1                    tlul_rerror_o = 2'b11;
           Tests:       T4 T94 T98 
295        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T4 T94 T98 
296        1/1                  end else if (tlul_req_i) begin
           Tests:       T3 T4 T7 
297        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T4 T94 T98 
298        1/1                    pending_tlul_error_d = 1'b1;
           Tests:       T4 T94 T98 
299                             end
                        MISSING_ELSE
300                           end
301                           ///////////////////////////////////////////////////////////////////
302                           // We should never get here. If we do (e.g. via a malicious
303                           // glitch), error out immediately.
304                           default: begin
305                             state_d = ErrorSt;
306                             fsm_err_o = 1'b1;
307                           end
308                           ///////////////////////////////////////////////////////////////////
309                         endcase // state_q
310                     
311                         // Unconditionally jump into the terminal error state in case of
312                         // an ECC error or escalation, and lock access to the partition down.
313                         // SEC_CM: PART.FSM.LOCAL_ESC
314        1/1              if (ecc_err) begin
           Tests:       T1 T2 T3 
315        1/1                state_d = ErrorSt;
           Tests:       T105 T165 T157 
316        1/1                if (state_q != ErrorSt) begin
           Tests:       T105 T165 T157 
317        1/1                  error_d = CheckFailError;
           Tests:       T105 T165 T157 
318                           end
                        MISSING_ELSE
319                         end
                        MISSING_ELSE
320                         // SEC_CM: PART.FSM.GLOBAL_ESC
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                state_d = ErrorSt;
           Tests:       T3 T4 T7 
323        1/1                fsm_err_o = 1'b1;
           Tests:       T3 T4 T7 
324        1/1                if (state_q != ErrorSt) begin
           Tests:       T3 T4 T7 
325        1/1                  error_d = FsmStateError;
           Tests:       T3 T4 T7 
326                           end
                        MISSING_ELSE
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       ///////////////////////////////////
331                       // Signals to/from TL-UL Adapter //
332                       ///////////////////////////////////
333                     
334        1/1            assign tlul_addr_d  = tlul_addr_i;
           Tests:       T1 T2 T3 
335                       // Do not forward data in case of an error.
336        1/1            assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
           Tests:       T1 T2 T3 
337                     
338                       if (Info.offset == 0) begin : gen_zero_offset
339                         assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
340                     
341                       end else begin : gen_nonzero_offset
342        1/1              assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
           Tests:       T1 T2 T3 
343                                                     {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344                       end
345                     
346                       // Note that OTP works on halfword (16bit) addresses, hence need to
347                       // shift the addresses appropriately.
348                       logic [OtpByteAddrWidth-1:0] addr_calc;
349        1/1            assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
           Tests:       T1 T2 T3 
350        1/1            assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
           Tests:       T1 T2 T3 
351                     
352                       if (OtpAddrShift > 0) begin : gen_unused
353                         logic unused_bits;
354        1/1              assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
           Tests:       T1 T2 T3 
355                       end
356                     
357                       // Request 32bit except in case of the digest.
358        1/1            assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
           Tests:       T1 T2 T3 
359                                           OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360                                           OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361                     
362                       ////////////////
363                       // Digest Reg //
364                       ////////////////
365                     
366                       if (Info.sw_digest) begin : gen_ecc_reg
367                         // SEC_CM: PART.DATA_REG.INTEGRITY
368                         otp_ctrl_ecc_reg #(
369                           .Width ( ScrmblBlockWidth ),
370                           .Depth ( 1                )
371                         ) u_otp_ctrl_ecc_reg (
372                           .clk_i,
373                           .rst_ni,
374                           .wren_i    ( digest_reg_en ),
375                           .addr_i    ( '0            ),
376                           .wdata_i   ( otp_rdata_i   ),
377                           .rdata_o   (               ),
378                           .data_o    ( digest_o      ),
379                           .ecc_err_o ( ecc_err       )
380                         );
381                       end else begin : gen_no_ecc_reg
382                         logic unused_digest_reg_en;
383                         logic unused_rdata;
384                         assign unused_digest_reg_en = digest_reg_en;
385                         assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386                         assign digest_o = '0;
387                         assign ecc_err = 1'b0;
388                       end
389                     
390                       ////////////////////////
391                       // DAI Access Control //
392                       ////////////////////////
393                     
394                       mubi8_t init_locked;
395        1/1            assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
396                     
397                       // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398                       // Note that the locks are redundantly encoded values.
399                       part_access_t access_pre;
400                       prim_mubi8_sender #(
401                         .AsyncOn(0)
402                       ) u_prim_mubi8_sender_write_lock_pre (
403                         .clk_i,
404                         .rst_ni,
405                         .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406                         .mubi_o(access_pre.write_lock)
407                       );
408                       prim_mubi8_sender #(
409                         .AsyncOn(0)
410                       ) u_prim_mubi8_sender_read_lock_pre (
411                         .clk_i,
412                         .rst_ni,
413                         .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414                         .mubi_o(access_pre.read_lock)
415                       );
416                     
417                       // SEC_CM: PART.MEM.SW_UNWRITABLE
418                       if (Info.write_lock) begin : gen_digest_write_lock
419                         mubi8_t digest_locked;
420        1/1              assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
421                     
422                         // This prevents the synthesis tool from optimizing the multibit signal.
423                         prim_mubi8_sender #(
424                           .AsyncOn(0)
425                         ) u_prim_mubi8_sender_write_lock (
426                           .clk_i,
427                           .rst_ni,
428                           .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429                           .mubi_o(access_o.write_lock)
430                         );
431                     
432                         `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433                       end else begin : gen_no_digest_write_lock
434                         assign access_o.write_lock = access_pre.write_lock;
435                       end
436                     
437                       // SEC_CM: PART.MEM.SW_UNREADABLE
438                       if (Info.read_lock) begin : gen_digest_read_lock
439                         mubi8_t digest_locked;
440                         assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441                     
442                         // This prevents the synthesis tool from optimizing the multibit signal.
443                         prim_mubi8_sender #(
444                           .AsyncOn(0)
445                         ) u_prim_mubi8_sender_read_lock (
446                           .clk_i,
447                           .rst_ni,
448                           .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449                           .mubi_o(access_o.read_lock)
450                         );
451                     
452                         `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453                       end else begin : gen_no_digest_read_lock
454        1/1              assign access_o.read_lock = access_pre.read_lock;
           Tests:       T1 T2 T3 
455                       end
456                     
457                       ///////////////
458                       // Registers //
459                       ///////////////
460                     
461        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1                   `ifdef SIMULATION                                   
461.2                       prim_sparse_fsm_flop #(                           
461.3                         .StateEnumT(state_e),                            
461.4                         .Width($bits(state_e)),                          
461.5                         .ResetValue($bits(state_e)'(ResetSt)),          
461.6                         .EnableAlertTriggerSVA(1), 
461.7                         .CustomForceName("state_q")          
461.8                       ) u_state_regs (                                        
461.9                         .clk_i   ( clk_i   ),                           
461.10                        .rst_ni  ( rst_ni ),                           
461.11                        .state_i ( state_d     ),                           
461.12                        .state_o (         )                            
461.13                      );                                                
461.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
461.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
461.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
461.17                      end else begin                                    
461.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
461.19                      end                                               
461.20                    end  
461.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
461.22                      else begin                                                                           
461.23                        `ifdef UVM                                                                               
461.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
461.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);                                
461.26                  `else                                                                                    
461.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
461.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
461.29                  `endif                                                              
461.30                      end 
461.31                    `else                                               
461.32                      prim_sparse_fsm_flop #(                           
461.33                        .StateEnumT(state_e),                            
461.34                        .Width($bits(state_e)),                          
461.35                        .ResetValue($bits(state_e)'(ResetSt)),          
461.36                        .EnableAlertTriggerSVA(1)  
461.37                      ) u_state_regs (                                        
461.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
461.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
461.40                        .state_i ( state_d     ),                           
461.41                        .state_o ( state_q     )                            
461.42                      );                                                
461.43                    `endif462                     
463                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
465        1/1                error_q              <= NoError;
           Tests:       T1 T2 T3 
466        1/1                tlul_addr_q          <= '0;
           Tests:       T1 T2 T3 
467        1/1                pending_tlul_error_q <= 1'b0;
           Tests:       T1 T2 T3 
468                         end else begin
469        1/1                error_q              <= error_d;
           Tests:       T1 T2 T3 
470        1/1                pending_tlul_error_q <= pending_tlul_error_d;
           Tests:       T1 T2 T3 
471        1/1                if (tlul_gnt_o) begin
           Tests:       T1 T2 T3 
472        1/1                  tlul_addr_q <= tlul_addr_d;
           Tests:       T2 T3 T6 
473                           end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T45,T66,T87

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T94,T71,T162

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T105,T165,T157
1	Covered	T105,T165,T157

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T3,T4,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T94,T98
1	1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T6

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T12,T120

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T12,T120

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T4,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T6
ReadWaitSt	252	Covered	T2,T3,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T4,T7,T94
IdleSt->ReadSt	236	Covered	T2,T3,T6
InitSt->ErrorSt	315	Covered	T3,T133,T170
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T99,T132,T160
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T94,T95,T120
ReadSt->ReadWaitSt	252	Covered	T2,T3,T6
ReadWaitSt->ErrorSt	276	Covered	T115,T168,T169
ReadWaitSt->IdleSt	270	Covered	T2,T3,T6
ResetSt->ErrorSt	315	Covered	T105,T106,T107
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T94,T95,T120
CheckFailError	317	Covered	T105,T165,T157
FsmStateError	289	Covered	T3,T4,T7
MacroEccCorrError	221	Covered	T94,T71,T162
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T152,T197,T198
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T94,T95,T120
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T105,T165,T157
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T4,T7
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T162,T208,T163
MacroEccCorrError->NoError	235	Covered	T94,T71,T61
NoError->AccessError	256	Covered	T94,T95,T120
NoError->CheckFailError	317	Covered	T105,T165,T157
NoError->FsmStateError	289	Covered	T3,T4,T7
NoError->MacroEccCorrError	221	Covered	T94,T71,T162

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

336          assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
                                                                          -1-  
                                                                          ==>  
                                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

349          assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

358          assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

395          assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

420            assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T120
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              ///////////////////////////////////////////////////////////////////
188              // State right after reset. Wait here until we get a an
189              // initialization request.
190              ResetSt: begin
191                if (init_req_i) begin
                   -2-  
192                  // If the partition does not have a digest, no initialization is necessary.
193                  if (Info.sw_digest) begin
                     -3-  
194                    state_d = InitSt;
                       ==>
195                  end else begin
196                    state_d = IdleSt;
                       ==> (Unreachable)
197                  end
198                end
                   MISSING_ELSE
                   ==>
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Initialization reads out the digest only in unbuffered
202              // partitions. Wait here until the OTP request has been granted.
203              // And then wait until the OTP word comes back.
204              InitSt: begin
205                otp_req_o = 1'b1;
206                if (otp_gnt_i) begin
                   -4-  
207                  state_d = InitWaitSt;
                     ==>
208                end
                   MISSING_ELSE
                   ==>
209              end
210              ///////////////////////////////////////////////////////////////////
211              // Wait for OTP response and write to digest buffer register. In
212              // case an OTP transaction fails, latch the  OTP error code and
213              // jump to a terminal error state.
214              InitWaitSt: begin
215                if (otp_rvalid_i) begin
                   -5-  
216                  digest_reg_en = 1'b1;
217                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -6-  
218                    state_d = IdleSt;
219                    // At this point the only error that we could have gotten are correctable ECC errors.
220                    if (otp_err != NoError) begin
                       -7-  
221                      error_d = MacroEccCorrError;
                         ==>
222                    end
                       MISSING_ELSE
                       ==>
223                  end else begin
224                    state_d = ErrorSt;
                       ==>
225                    error_d = otp_err;
226                  end
227                end
                   MISSING_ELSE
                   ==>
228              end
229              ///////////////////////////////////////////////////////////////////
230              // Wait for TL-UL requests coming in.
231              // Then latch address and go to readout state.
232              IdleSt: begin
233                init_done_o = 1'b1;
234                if (tlul_req_i) begin
                   -8-  
235                  error_d = NoError; // clear recoverable soft errors.
                     ==>
236                  state_d = ReadSt;
237                  tlul_gnt_o = 1'b1;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              ///////////////////////////////////////////////////////////////////
241              // If the address is out of bounds, or if the partition is
242              // locked, signal back a bus error. Note that such an error does
243              // not cause the partition to go into error state. Otherwise if
244              // these checks pass, an OTP word is requested.
245              ReadSt: begin
246                init_done_o = 1'b1;
247                // Double check the address range.
248                if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
                   -9-  
249                  otp_req_o = 1'b1;
250                  otp_addr_sel = DataAddrSel;
251                  if (otp_gnt_i) begin
                     -10-  
252                    state_d = ReadWaitSt;
                       ==>
253                  end
                     MISSING_ELSE
                     ==>
254                end else begin
255                  state_d = IdleSt;
                     ==>
256                  error_d = AccessError; // Signal this error, but do not go into terminal error state.
257                  tlul_rvalid_o = 1'b1;
258                  tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259                end
260              end
261              ///////////////////////////////////////////////////////////////////
262              // Wait for OTP response and release the TL-UL response. In
263              // case an OTP transaction fails, latch the OTP error code,
264              // signal a TL-Ul bus error and jump to a terminal error state.
265              ReadWaitSt: begin
266                init_done_o = 1'b1;
267                if (otp_rvalid_i) begin
                   -11-  
268                  tlul_rvalid_o = 1'b1;
269                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -12-  
270                    state_d = IdleSt;
271                    // At this point the only error that we could have gotten are correctable ECC errors.
272                    if (otp_err != NoError) begin
                       -13-  
273                      error_d = MacroEccCorrError;
                         ==>
274                    end
                       MISSING_ELSE
                       ==>
275                  end else begin
276                    state_d = ErrorSt;
                       ==>
277                    error_d = otp_err;
278                    // This causes the TL-UL adapter to return a bus error.
279                    tlul_rerror_o = 2'b11;
280                  end
281                end
                   MISSING_ELSE
                   ==>
282              end
283              ///////////////////////////////////////////////////////////////////
284              // Terminal Error State. This locks access to the partition.
285              // Make sure the partition signals an error state if no error
286              // code has been latched so far.
287              ErrorSt: begin
288                if (error_q == NoError) begin
                   -14-  
289                  error_d = FsmStateError;
                     ==>
290                end
                   MISSING_ELSE
                   ==>
291        
292                // Return bus errors if there are pending TL-UL requests.
293                if (pending_tlul_error_q) begin
                   -15-  
294                  tlul_rerror_o = 2'b11;
                     ==>
295                  tlul_rvalid_o = 1'b1;
296                end else if (tlul_req_i) begin
                            -16-  
297                  tlul_gnt_o = 1'b1;
                     ==>
298                  pending_tlul_error_d = 1'b1;
299                end
                   MISSING_ELSE
                   ==>
300              end
301              ///////////////////////////////////////////////////////////////////
302              // We should never get here. If we do (e.g. via a malicious
303              // glitch), error out immediately.
304              default: begin
305                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T45,T66,T87
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T99,T150,T167
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T120,T127,T123
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T94,T95,T120
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T94,T71,T162
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T115,T168,T169
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T4,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T94,T98
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T94,T98
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T4,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

314            if (ecc_err) begin
               -1-  
315              state_d = ErrorSt;
316              if (state_q != ErrorSt) begin
                 -2-  
317                error_d = CheckFailError;
                   ==>
318              end
                 MISSING_ELSE
                 ==>
319            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T105,T165,T157
1	0	Covered	T105,T165,T157
0	-	Covered	T1,T2,T3

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
               -1-  
322              state_d = ErrorSt;
323              fsm_err_o = 1'b1;
324              if (state_q != ErrorSt) begin
                 -2-  
325                error_d = FsmStateError;
                   ==>
326              end
                 MISSING_ELSE
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T4,T7
1	0	Covered	T3,T4,T7
0	-	Covered	T1,T2,T3

461          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

464            if (!rst_ni) begin
               -1-  
465              error_q              <= NoError;
                 ==>
466              tlul_addr_q          <= '0;
467              pending_tlul_error_q <= 1'b0;
468            end else begin
469              error_q              <= error_d;
470              pending_tlul_error_q <= pending_tlul_error_d;
471              if (tlul_gnt_o) begin
                 -2-  
472                tlul_addr_q <= tlul_addr_d;
                   ==>
473              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	89440843	88569883	0	0
DigestKnown_A	89440843	88569883	0	0
DigestOffsetMustBeRepresentable_A	1121	1121	0	0
EccErrorState_A	89440843	14734	0	0
ErrorKnown_A	89440843	88569883	0	0
FsmStateKnown_A	89440843	88569883	0	0
InitDoneKnown_A	89440843	88569883	0	0
InitReadLocksPartition_A	89440843	17196689	0	0
InitWriteLocksPartition_A	89440843	17196689	0	0
OffsetMustBeBlockAligned_A	1121	1121	0	0
OtpAddrKnown_A	89440843	88569883	0	0
OtpCmdKnown_A	89440843	88569883	0	0
OtpErrorState_A	89440843	41	0	0
OtpReqKnown_A	89440843	88569883	0	0
OtpSizeKnown_A	89440843	88569883	0	0
OtpWdataKnown_A	89440843	88569883	0	0
ReadLockPropagation_A	89440843	17080350	0	0
SizeMustBeBlockAligned_A	1121	1121	0	0
TlulGntKnown_A	89440843	88569883	0	0
TlulRdataKnown_A	89440843	88569883	0	0
TlulReadOnReadLock_A	89440843	6339	0	0
TlulRerrorKnown_A	89440843	88569883	0	0
TlulRvalidKnown_A	89440843	88569883	0	0
WriteLockPropagation_A	89440843	1076738	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	89440843	11163785	0	0
u_state_regs_A	89440843	88569883	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	14734	0	0
T50	63287	0	0	0
T105	10281	3638	0	0
T157	0	2160	0	0
T158	0	3366	0	0
T165	0	2861	0	0
T172	0	2709	0	0
T173	29672	0	0	0
T174	160057	0	0	0
T175	125664	0	0	0
T176	48405	0	0	0
T177	32851	0	0	0
T178	30699	0	0	0
T179	82558	0	0	0
T180	5040	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	17196689	0	0
T1	4987	195	0	0
T2	50582	842	0	0
T3	12595	4382	0	0
T4	21830	12563	0	0
T5	20589	165	0	0
T6	70769	122	0	0
T7	91537	2566	0	0
T8	42348	936	0	0
T12	39001	1325	0	0
T13	6928	108	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	17196689	0	0
T1	4987	195	0	0
T2	50582	842	0	0
T3	12595	4382	0	0
T4	21830	12563	0	0
T5	20589	165	0	0
T6	70769	122	0	0
T7	91537	2566	0	0
T8	42348	936	0	0
T12	39001	1325	0	0
T13	6928	108	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	41	0	0
T9	122227	0	0	0
T91	27645	0	0	0
T94	111201	0	0	0
T95	99431	0	0	0
T98	110226	0	0	0
T99	12681	1	0	0
T115	0	2	0	0
T120	49388	0	0	0
T125	15414	0	0	0
T126	51273	0	0	0
T128	14898	0	0	0
T150	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	17080350	0	0
T4	21830	11907	0	0
T7	91537	2519	0	0
T8	42348	821	0	0
T12	39001	0	0	0
T13	6928	0	0	0
T91	27645	0	0	0
T94	111201	15151	0	0
T95	0	27749	0	0
T98	110226	9137	0	0
T99	12681	0	0	0
T120	0	846	0	0
T121	0	3894	0	0
T125	15414	5912	0	0
T148	0	40947	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121	1121	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	6339	0	0
T4	21830	2	0	0
T7	91537	0	0	0
T8	42348	0	0	0
T9	0	15	0	0
T12	39001	0	0	0
T13	6928	0	0	0
T18	0	2	0	0
T91	27645	0	0	0
T94	111201	6	0	0
T95	0	3	0	0
T98	110226	7	0	0
T99	12681	0	0	0
T120	0	1	0	0
T121	0	2	0	0
T125	15414	1	0	0
T148	0	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	1076738	0	0
T7	91537	1802	0	0
T8	42348	0	0	0
T12	39001	1985	0	0
T13	6928	0	0	0
T19	0	8983	0	0
T91	27645	0	0	0
T94	111201	0	0	0
T98	110226	0	0	0
T99	12681	0	0	0
T111	0	4258	0	0
T120	0	4771	0	0
T121	0	1775	0	0
T123	0	9573	0	0
T125	15414	0	0	0
T126	51273	0	0	0
T189	0	1470	0	0
T191	0	25906	0	0
T192	0	3188	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	11163785	0	0
T7	91537	78075	0	0
T8	42348	0	0	0
T12	39001	15404	0	0
T13	6928	0	0	0
T19	0	121168	0	0
T91	27645	0	0	0
T94	111201	0	0	0
T98	110226	0	0	0
T99	12681	0	0	0
T120	0	34024	0	0
T121	0	24750	0	0
T123	0	51323	0	0
T125	15414	0	0	0
T126	51273	0	0	0
T187	0	3778	0	0
T189	0	13976	0	0
T190	0	31423	0	0
T193	0	3049	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89440843	88569883	0	0
T1	4987	4924	0	0
T2	50582	50026	0	0
T3	12595	12300	0	0
T4	21830	21570	0	0
T5	20589	20533	0	0
T6	70769	70704	0	0
T7	91537	90035	0	0
T8	42348	41639	0	0
T12	39001	37979	0	0
T13	6928	6855	0	0