Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4395113	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2548716

1

T1

6

T2

301

T3

250

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5847711	1			T1	4		T2	2078		T3	644
values[0x0]	518972	1			T1	9		T2	45		T3	155
values[0x1]	577146	1			T1	6		T2	49		T3	142

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3255062	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3688767

1

T1

7

T2

853

T3

435

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24978	1			T2	10		T3	2		T4	14
valid_sources[0x01]	28172	1			T2	13		T3	4		T4	6
valid_sources[0x02]	28336	1			T2	9		T3	1		T4	9
valid_sources[0x03]	20684	1			T2	8		T3	3		T4	14
valid_sources[0x04]	21094	1			T2	8		T3	4		T4	10
valid_sources[0x05]	33684	1			T2	13		T3	4		T4	14
valid_sources[0x06]	28322	1			T2	7		T3	7		T4	11
valid_sources[0x07]	32486	1			T2	5		T3	1		T4	12
valid_sources[0x08]	36007	1			T2	5		T3	4		T4	8
valid_sources[0x09]	39467	1			T2	7		T3	4		T4	18
valid_sources[0x0a]	30893	1			T2	12		T3	5		T4	15
valid_sources[0x0b]	21234	1			T2	9		T3	2		T4	21
valid_sources[0x0c]	19978	1			T2	7		T3	5		T4	8
valid_sources[0x0d]	21006	1			T2	12		T3	3		T4	7
valid_sources[0x0e]	20500	1			T2	11		T3	3		T4	15
valid_sources[0x0f]	21489	1			T2	15		T3	6		T4	10
valid_sources[0x10]	29394	1			T2	8		T3	6		T4	14
valid_sources[0x11]	21983	1			T2	7		T3	2		T4	15
valid_sources[0x12]	20857	1			T2	12		T3	2		T4	6
valid_sources[0x13]	25090	1			T2	6		T3	10		T4	8
valid_sources[0x14]	31647	1			T2	9		T3	1		T4	14
valid_sources[0x15]	20390	1			T2	13		T3	5		T4	11
valid_sources[0x16]	20269	1			T2	6		T3	3		T4	8
valid_sources[0x17]	21192	1			T2	12		T3	4		T4	15
valid_sources[0x18]	20260	1			T2	6		T3	4		T4	11
valid_sources[0x19]	29519	1			T2	12		T3	5		T4	9
valid_sources[0x1a]	22312	1			T2	8		T3	6		T4	11
valid_sources[0x1b]	40350	1			T2	13		T3	4		T4	14
valid_sources[0x1c]	22984	1			T2	5		T3	2		T4	10
valid_sources[0x1d]	20721	1			T2	5		T3	2		T4	11
valid_sources[0x1e]	21959	1			T2	7		T3	7		T4	12
valid_sources[0x1f]	20571	1			T2	13		T3	3		T4	8
valid_sources[0x20]	19696	1			T2	6		T3	5		T4	12
valid_sources[0x21]	21396	1			T2	11		T3	4		T4	9
valid_sources[0x22]	27469	1			T2	5		T3	7		T4	6
valid_sources[0x23]	21295	1			T2	12		T3	3		T4	14
valid_sources[0x24]	25759	1			T2	6		T3	2		T4	10
valid_sources[0x25]	19882	1			T2	12		T3	4		T4	13
valid_sources[0x26]	25661	1			T2	9		T4	15		T5	15
valid_sources[0x27]	19612	1			T2	9		T3	3		T4	10
valid_sources[0x28]	20021	1			T2	6		T3	2		T4	7
valid_sources[0x29]	77358	1			T2	14		T3	5		T4	6
valid_sources[0x2a]	64142	1			T2	10		T3	7		T4	21
valid_sources[0x2b]	24927	1			T2	13		T3	3		T4	17
valid_sources[0x2c]	24887	1			T2	6		T3	4		T4	8
valid_sources[0x2d]	20188	1			T2	11		T3	2		T4	13
valid_sources[0x2e]	53490	1			T2	7		T3	3		T4	10
valid_sources[0x2f]	22733	1			T2	7		T3	4		T4	9
valid_sources[0x30]	24607	1			T2	13		T3	3		T4	8
valid_sources[0x31]	26110	1			T2	14		T3	4		T4	12
valid_sources[0x32]	37680	1			T2	9		T3	4		T4	12
valid_sources[0x33]	30358	1			T2	4		T3	4		T4	14
valid_sources[0x34]	20296	1			T2	9		T3	3		T4	11
valid_sources[0x35]	72711	1			T2	11		T3	2		T4	11
valid_sources[0x36]	21926	1			T2	5		T3	2		T4	10
valid_sources[0x37]	28009	1			T2	10		T3	4		T4	12
valid_sources[0x38]	23300	1			T2	6		T3	9		T4	11
valid_sources[0x39]	22004	1			T2	10		T3	4		T4	20
valid_sources[0x3a]	22181	1			T2	2		T3	4		T4	15
valid_sources[0x3b]	21372	1			T2	9		T3	4		T4	9
valid_sources[0x3c]	24237	1			T2	14		T3	4		T4	11
valid_sources[0x3d]	20279	1			T2	13		T3	2		T4	14
valid_sources[0x3e]	22722	1			T2	7		T3	8		T4	11
valid_sources[0x3f]	29205	1			T2	11		T3	1		T4	14
valid_sources[0x40]	35327	1			T2	9		T3	8		T4	9
valid_sources[0x41]	21041	1			T2	9		T3	1		T4	14
valid_sources[0x42]	22722	1			T2	8		T3	4		T4	16
valid_sources[0x43]	27252	1			T2	10		T3	3		T4	14
valid_sources[0x44]	20076	1			T2	11		T3	3		T4	16
valid_sources[0x45]	20143	1			T2	15		T3	3		T4	14
valid_sources[0x46]	26190	1			T2	9		T3	4		T4	7
valid_sources[0x47]	20200	1			T2	8		T3	4		T4	14
valid_sources[0x48]	22610	1			T2	9		T3	2		T4	13
valid_sources[0x49]	27395	1			T2	7		T3	4		T4	16
valid_sources[0x4a]	26642	1			T2	10		T3	10		T4	10
valid_sources[0x4b]	24437	1			T2	10		T3	5		T4	17
valid_sources[0x4c]	20766	1			T2	5		T3	4		T4	8
valid_sources[0x4d]	21320	1			T2	10		T3	4		T4	14
valid_sources[0x4e]	21461	1			T2	5		T3	5		T4	10
valid_sources[0x4f]	31714	1			T2	8		T3	2		T4	13
valid_sources[0x50]	40882	1			T2	9		T3	5		T4	17
valid_sources[0x51]	31399	1			T2	9		T3	7		T4	14
valid_sources[0x52]	25318	1			T2	9		T3	2		T4	12
valid_sources[0x53]	22937	1			T2	3		T3	4		T4	11
valid_sources[0x54]	35779	1			T1	6		T2	7		T4	10
valid_sources[0x55]	22591	1			T2	11		T3	4		T4	13
valid_sources[0x56]	25240	1			T2	5		T3	5		T4	13
valid_sources[0x57]	21919	1			T2	9		T3	4		T4	12
valid_sources[0x58]	21296	1			T2	10		T3	4		T4	9
valid_sources[0x59]	19961	1			T2	7		T4	16		T5	16
valid_sources[0x5a]	25320	1			T2	9		T3	9		T4	10
valid_sources[0x5b]	23069	1			T2	5		T3	1		T4	17
valid_sources[0x5c]	24840	1			T2	8		T3	3		T4	10
valid_sources[0x5d]	27501	1			T2	6		T3	2		T4	13
valid_sources[0x5e]	31473	1			T2	7		T3	2		T4	14
valid_sources[0x5f]	22926	1			T2	11		T3	2		T4	17
valid_sources[0x60]	23054	1			T2	10		T3	4		T4	17
valid_sources[0x61]	22745	1			T2	5		T3	4		T4	11
valid_sources[0x62]	21363	1			T2	10		T3	8		T4	5
valid_sources[0x63]	21625	1			T2	6		T3	3		T4	17
valid_sources[0x64]	22387	1			T2	7		T3	1		T4	5
valid_sources[0x65]	24124	1			T2	6		T3	3		T4	13
valid_sources[0x66]	29266	1			T2	11		T3	5		T4	6
valid_sources[0x67]	37390	1			T2	5		T3	5		T4	9
valid_sources[0x68]	20161	1			T2	9		T3	2		T4	8
valid_sources[0x69]	23256	1			T2	3		T3	5		T4	8
valid_sources[0x6a]	35742	1			T2	8		T3	2		T4	15
valid_sources[0x6b]	22282	1			T2	6		T3	2		T4	8
valid_sources[0x6c]	21384	1			T2	7		T3	4		T4	22
valid_sources[0x6d]	26779	1			T2	8		T4	12		T5	14
valid_sources[0x6e]	26029	1			T2	6		T3	4		T4	8
valid_sources[0x6f]	21375	1			T2	10		T3	3		T4	10
valid_sources[0x70]	20491	1			T2	12		T3	1		T4	17
valid_sources[0x71]	25108	1			T2	10		T3	8		T4	10
valid_sources[0x72]	35937	1			T2	11		T3	3		T4	7
valid_sources[0x73]	67835	1			T2	20		T3	7		T4	17
valid_sources[0x74]	22581	1			T2	5		T3	2		T4	10
valid_sources[0x75]	23293	1			T2	5		T3	7		T4	12
valid_sources[0x76]	33938	1			T2	8		T3	5		T4	10
valid_sources[0x77]	20935	1			T2	6		T3	3		T4	7
valid_sources[0x78]	23624	1			T2	4		T3	6		T4	13
valid_sources[0x79]	19869	1			T2	9		T3	5		T4	11
valid_sources[0x7a]	19684	1			T2	9		T3	2		T4	7
valid_sources[0x7b]	23483	1			T2	6		T3	2		T4	16
valid_sources[0x7c]	20257	1			T2	4		T3	4		T4	17
valid_sources[0x7d]	34437	1			T2	10		T3	6		T4	9
valid_sources[0x7e]	24629	1			T1	2		T2	10		T3	5
valid_sources[0x7f]	34086	1			T2	13		T3	4		T4	11
valid_sources[0x80]	20154	1			T2	8		T3	2		T4	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2036964

1

T1

1

T2

257

T3

128

values[0x0]

all_enables

biggest_size

288688

1

T1

3

T2

22

T3

70

values[0x1]

all_enables

biggest_size

223064

1

T1

2

T2

22

T3

52

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25351	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

486731

1

T2

40

T4

40

T5

60

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	166858	1			T2	20		T4	20		T5	30
values[0x0]	167991	1			T2	5		T4	12		T5	11
values[0x1]	177233	1			T2	15		T4	8		T5	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

497972

1

T2

40

T4

40

T5

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1748	1			T105	7		T93	1		T20	1
valid_sources[0x01]	1859	1			T2	1		T106	1		T90	20
valid_sources[0x02]	1533	1			T108	4		T195	1		T112	1
valid_sources[0x03]	1962	1			T106	1		T110	1		T107	1
valid_sources[0x04]	1693	1			T105	1		T106	1		T20	2
valid_sources[0x05]	1978	1			T93	1		T110	1		T108	1
valid_sources[0x06]	1883	1			T2	1		T93	1		T106	1
valid_sources[0x07]	2195	1			T5	1		T93	1		T106	1
valid_sources[0x08]	1833	1			T105	1		T93	1		T106	3
valid_sources[0x09]	2089	1			T110	2		T107	2		T124	2
valid_sources[0x0a]	2357	1			T106	2		T107	2		T20	5
valid_sources[0x0b]	2114	1			T7	1		T93	1		T107	2
valid_sources[0x0c]	1715	1			T7	1		T93	1		T106	1
valid_sources[0x0d]	1946	1			T20	3		T108	5		T125	3
valid_sources[0x0e]	2202	1			T106	1		T110	1		T108	2
valid_sources[0x0f]	2374	1			T93	1		T106	2		T110	1
valid_sources[0x10]	2002	1			T112	1		T196	2		T109	4
valid_sources[0x11]	1658	1			T5	1		T93	2		T106	2
valid_sources[0x12]	2125	1			T93	1		T107	1		T20	1
valid_sources[0x13]	1751	1			T20	1		T126	1		T162	1
valid_sources[0x14]	1699	1			T106	4		T108	1		T124	2
valid_sources[0x15]	1893	1			T125	1		T9	2		T162	1
valid_sources[0x16]	1633	1			T20	3		T108	1		T91	1
valid_sources[0x17]	2156	1			T2	2		T110	6		T107	1
valid_sources[0x18]	1737	1			T105	3		T124	1		T112	1
valid_sources[0x19]	2080	1			T93	1		T106	1		T110	6
valid_sources[0x1a]	2142	1			T61	3		T125	1		T162	3
valid_sources[0x1b]	2034	1			T105	5		T106	1		T107	1
valid_sources[0x1c]	1940	1			T5	1		T105	1		T93	1
valid_sources[0x1d]	2102	1			T106	1		T110	2		T137	2
valid_sources[0x1e]	2264	1			T111	21		T108	2		T162	2
valid_sources[0x1f]	1914	1			T7	1		T93	1		T111	2
valid_sources[0x20]	1851	1			T18	120		T115	1		T107	1
valid_sources[0x21]	2042	1			T110	1		T137	2		T107	1
valid_sources[0x22]	1688	1			T108	1		T91	2		T109	3
valid_sources[0x23]	1832	1			T110	1		T107	1		T124	2
valid_sources[0x24]	1507	1			T93	1		T106	1		T107	3
valid_sources[0x25]	1585	1			T5	3		T106	1		T110	2
valid_sources[0x26]	2497	1			T105	2		T110	2		T107	1
valid_sources[0x27]	1684	1			T93	1		T106	1		T115	1
valid_sources[0x28]	1952	1			T106	1		T110	2		T115	1
valid_sources[0x29]	1586	1			T106	1		T110	2		T115	1
valid_sources[0x2a]	1859	1			T2	2		T5	1		T106	1
valid_sources[0x2b]	1990	1			T93	2		T106	1		T110	5
valid_sources[0x2c]	2156	1			T106	2		T108	4		T109	4
valid_sources[0x2d]	1872	1			T105	1		T110	1		T111	3
valid_sources[0x2e]	2069	1			T110	6		T91	2		T61	2
valid_sources[0x2f]	2232	1			T5	1		T9	1		T109	2
valid_sources[0x30]	2417	1			T107	3		T124	2		T109	2
valid_sources[0x31]	1699	1			T93	2		T107	1		T20	2
valid_sources[0x32]	2463	1			T105	2		T107	2		T91	1
valid_sources[0x33]	2008	1			T106	3		T112	1		T109	3
valid_sources[0x34]	1968	1			T107	1		T20	2		T108	2
valid_sources[0x35]	2012	1			T5	1		T106	2		T107	2
valid_sources[0x36]	2121	1			T106	1		T107	1		T108	2
valid_sources[0x37]	1841	1			T5	1		T107	2		T91	1
valid_sources[0x38]	2209	1			T2	1		T105	1		T115	1
valid_sources[0x39]	1799	1			T2	1		T5	3		T106	1
valid_sources[0x3a]	2952	1			T93	2		T116	11		T107	1
valid_sources[0x3b]	2481	1			T7	1		T105	3		T106	1
valid_sources[0x3c]	1927	1			T5	1		T107	1		T124	1
valid_sources[0x3d]	1509	1			T5	1		T105	4		T93	2
valid_sources[0x3e]	1726	1			T5	2		T110	1		T115	1
valid_sources[0x3f]	1981	1			T7	1		T93	1		T110	4
valid_sources[0x40]	1660	1			T5	1		T105	3		T116	5
valid_sources[0x41]	1859	1			T5	1		T105	3		T106	1
valid_sources[0x42]	1747	1			T5	1		T105	2		T93	1
valid_sources[0x43]	1717	1			T106	1		T110	3		T108	1
valid_sources[0x44]	2043	1			T5	2		T20	5		T109	2
valid_sources[0x45]	2234	1			T105	1		T106	2		T20	1
valid_sources[0x46]	2957	1			T5	2		T7	1		T109	2
valid_sources[0x47]	2160	1			T106	1		T107	2		T108	2
valid_sources[0x48]	1955	1			T2	1		T5	2		T20	4
valid_sources[0x49]	1432	1			T5	1		T93	1		T61	2
valid_sources[0x4a]	3924	1			T105	2		T106	2		T110	4
valid_sources[0x4b]	1779	1			T110	4		T109	8		T113	9
valid_sources[0x4c]	2408	1			T115	2		T107	2		T91	4
valid_sources[0x4d]	1722	1			T105	3		T106	2		T110	5
valid_sources[0x4e]	2395	1			T2	2		T106	1		T110	1
valid_sources[0x4f]	2633	1			T106	1		T110	4		T124	1
valid_sources[0x50]	1711	1			T2	1		T105	1		T93	1
valid_sources[0x51]	1973	1			T93	1		T61	1		T109	3
valid_sources[0x52]	1741	1			T20	1		T108	2		T61	1
valid_sources[0x53]	1940	1			T106	1		T115	1		T107	1
valid_sources[0x54]	2061	1			T107	2		T108	1		T124	1
valid_sources[0x55]	2759	1			T5	1		T102	20		T106	1
valid_sources[0x56]	1907	1			T105	7		T115	1		T107	1
valid_sources[0x57]	2365	1			T107	1		T91	4		T8	628
valid_sources[0x58]	1871	1			T5	1		T110	2		T107	1
valid_sources[0x59]	1709	1			T93	1		T91	2		T109	4
valid_sources[0x5a]	2136	1			T5	1		T108	2		T61	1
valid_sources[0x5b]	2175	1			T93	1		T107	3		T8	580
valid_sources[0x5c]	2594	1			T110	1		T20	3		T61	2
valid_sources[0x5d]	1788	1			T106	1		T107	1		T125	1
valid_sources[0x5e]	1930	1			T137	1		T107	2		T91	2
valid_sources[0x5f]	1846	1			T4	27		T5	1		T7	1
valid_sources[0x60]	2281	1			T93	1		T106	1		T115	1
valid_sources[0x61]	1995	1			T5	1		T105	4		T110	2
valid_sources[0x62]	1656	1			T109	3		T14	12		T114	2
valid_sources[0x63]	1977	1			T110	4		T20	2		T91	1
valid_sources[0x64]	1895	1			T105	4		T106	1		T110	1
valid_sources[0x65]	1944	1			T107	1		T61	1		T109	1
valid_sources[0x66]	1819	1			T93	1		T107	1		T20	1
valid_sources[0x67]	1810	1			T5	2		T111	4		T115	1
valid_sources[0x68]	1840	1			T110	1		T115	1		T20	2
valid_sources[0x69]	1624	1			T106	1		T110	1		T124	1
valid_sources[0x6a]	2670	1			T7	1		T106	1		T107	1
valid_sources[0x6b]	1800	1			T5	1		T107	1		T91	4
valid_sources[0x6c]	1768	1			T106	1		T107	1		T20	2
valid_sources[0x6d]	2091	1			T5	1		T107	1		T20	1
valid_sources[0x6e]	2223	1			T2	4		T107	1		T20	1
valid_sources[0x6f]	2269	1			T110	1		T115	1		T91	3
valid_sources[0x70]	1902	1			T107	1		T20	5		T125	2
valid_sources[0x71]	2007	1			T5	1		T106	2		T107	3
valid_sources[0x72]	2536	1			T2	1		T20	1		T124	2
valid_sources[0x73]	2207	1			T108	2		T109	3		T113	4
valid_sources[0x74]	1978	1			T105	7		T93	1		T106	1
valid_sources[0x75]	1865	1			T61	1		T126	1		T162	1
valid_sources[0x76]	2123	1			T2	4		T106	4		T91	2
valid_sources[0x77]	1678	1			T105	2		T106	2		T115	1
valid_sources[0x78]	2877	1			T106	1		T110	3		T115	1
valid_sources[0x79]	2177	1			T106	1		T20	1		T126	3
valid_sources[0x7a]	1626	1			T106	1		T20	1		T109	5
valid_sources[0x7b]	1635	1			T108	2		T91	3		T126	1
valid_sources[0x7c]	1446	1			T2	1		T20	2		T125	3
valid_sources[0x7d]	2355	1			T20	1		T108	1		T8	457
valid_sources[0x7e]	2018	1			T2	1		T105	3		T112	1
valid_sources[0x7f]	2416	1			T109	2		T113	7		T14	14
valid_sources[0x80]	1481	1			T106	2		T20	1		T108	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

153594

1

T2

20

T4

20

T5

30

values[0x0]

all_enables

biggest_size

166570

1

T2

5

T4

12

T5

11

values[0x1]

all_enables

biggest_size

166567

1

T2

15

T4

8

T5

19