Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5101683

1

T1

13

T2

1871

T3

691

full_word

2591394

1

T1

6

T2

301

T3

250

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7692767	1			T1	19		T2	2172		T3	941
auto[TlIntgErrCmd]	115	1			T258	6		T259	4		T260	8
auto[TlIntgErrData]	88	1			T258	2		T259	2		T260	3
auto[TlIntgErrBoth]	107	1			T258	2		T259	4		T260	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5899077

1

T1

4

T2

2078

T3

644

auto[1]

1794000

1

T1

15

T2

94

T3

297

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3856840	1			T1	3		T2	1821		T3	516
auto[TlIntgErrNone]	partial	auto[1]	1244567	1			T1	10		T2	50		T3	175
auto[TlIntgErrNone]	full_word	auto[0]	2042100	1			T1	1		T2	257		T3	128
auto[TlIntgErrNone]	full_word	auto[1]	549260	1			T1	5		T2	44		T3	122
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T258	3		T259	1		T260	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T258	3		T259	2		T260	6
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T271	1		T350	2		T346	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T259	1		T350	1		T347	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T258	2		T259	1		T260	3
auto[TlIntgErrData]	partial	auto[1]	41	1			T271	1		T350	3		T352	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T259	1		T349	1		T353	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T270	1		T347	1		T351	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T258	1		T259	1		T260	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T258	1		T259	2		T260	6
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T270	1		T350	1		T346	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T259	1		T260	2		T347	1