Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	94.16	96.15	96.81		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	99015688	323127	0	0
check_regwen_rd_A	99015688	2090	0	0
check_timeout_rd_A	99015688	1250	0	0
check_trigger_regwen_rd_A	99015688	2112	0	0
consistency_check_period_rd_A	99015688	2129	0	0
creator_sw_cfg_read_lock_rd_A	99015688	1407	0	0
direct_access_address_rd_A	99015688	346	0	0
direct_access_wdata_0_rd_A	99015688	31	0	0
direct_access_wdata_1_rd_A	99015688	66	0	0
integrity_check_period_rd_A	99015688	1892	0	0
intr_enable_rd_A	99015688	2769	0	0
owner_sw_cfg_read_lock_rd_A	99015688	1337	0	0
rot_creator_auth_codesign_read_lock_rd_A	99015688	1207	0	0
rot_creator_auth_state_read_lock_rd_A	99015688	1315	0	0
vendor_test_read_lock_rd_A	99015688	1351	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	323127	0	0
T8	179696	3819	0	0
T9	104867	0	0	0
T14	0	4755	0	0
T15	0	3685	0	0
T21	0	2494	0	0
T89	0	5012	0	0
T92	9178	0	0	0
T112	45775	0	0	0
T126	36065	0	0	0
T141	0	8906	0	0
T146	0	9997	0	0
T160	21431	0	0	0
T193	15974	0	0	0
T194	11208	0	0	0
T195	19956	0	0	0
T211	12493	0	0	0
T249	0	6444	0	0
T251	0	1174	0	0
T272	0	2723	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	2090	0	0
T25	991192	0	0	0
T173	11736	0	0	0
T227	112233	0	0	0
T251	85082	13	0	0
T252	0	27	0	0
T253	0	16	0	0
T305	0	54	0	0
T307	0	48	0	0
T308	0	25	0	0
T309	0	20	0	0
T310	0	22	0	0
T311	0	9	0	0
T312	0	35	0	0
T313	106072	0	0	0
T314	105892	0	0	0
T315	63492	0	0	0
T316	26531	0	0	0
T317	29405	0	0	0
T318	68954	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	1250	0	0
T25	991192	0	0	0
T173	11736	0	0	0
T227	112233	0	0	0
T251	85082	26	0	0
T252	0	41	0	0
T253	0	17	0	0
T305	0	44	0	0
T307	0	33	0	0
T308	0	36	0	0
T309	0	18	0	0
T310	0	14	0	0
T311	0	10	0	0
T312	0	65	0	0
T313	106072	0	0	0
T314	105892	0	0	0
T315	63492	0	0	0
T316	26531	0	0	0
T317	29405	0	0	0
T318	68954	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	2112	0	0
T25	991192	0	0	0
T173	11736	0	0	0
T227	112233	0	0	0
T251	85082	21	0	0
T252	0	24	0	0
T253	0	32	0	0
T305	0	37	0	0
T307	0	32	0	0
T308	0	30	0	0
T309	0	1	0	0
T310	0	15	0	0
T311	0	18	0	0
T312	0	46	0	0
T313	106072	0	0	0
T314	105892	0	0	0
T315	63492	0	0	0
T316	26531	0	0	0
T317	29405	0	0	0
T318	68954	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	2129	0	0
T25	991192	0	0	0
T173	11736	0	0	0
T227	112233	0	0	0
T251	85082	6	0	0
T252	0	17	0	0
T253	0	24	0	0
T305	0	42	0	0
T307	0	51	0	0
T308	0	29	0	0
T309	0	9	0	0
T310	0	36	0	0
T311	0	23	0	0
T312	0	50	0	0
T313	106072	0	0	0
T314	105892	0	0	0
T315	63492	0	0	0
T316	26531	0	0	0
T317	29405	0	0	0
T318	68954	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	1407	0	0
T25	991192	0	0	0
T173	11736	0	0	0
T227	112233	0	0	0
T251	85082	18	0	0
T252	0	28	0	0
T253	0	32	0	0
T305	0	51	0	0
T307	0	52	0	0
T308	0	29	0	0
T309	0	23	0	0
T310	0	50	0	0
T311	0	5	0	0
T312	0	59	0	0
T313	106072	0	0	0
T314	105892	0	0	0
T315	63492	0	0	0
T316	26531	0	0	0
T317	29405	0	0	0
T318	68954	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	346	0	0
T25	991192	0	0	0
T173	11736	0	0	0
T227	112233	0	0	0
T251	85082	30	0	0
T252	0	14	0	0
T253	0	20	0	0
T305	0	67	0	0
T307	0	39	0	0
T308	0	52	0	0
T309	0	4	0	0
T310	0	26	0	0
T311	0	17	0	0
T312	0	43	0	0
T313	106072	0	0	0
T314	105892	0	0	0
T315	63492	0	0	0
T316	26531	0	0	0
T317	29405	0	0	0
T318	68954	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	31	0	0
T121	575941	0	0	0
T252	246944	4	0	0
T305	0	1	0	0
T309	0	6	0	0
T311	0	11	0	0
T312	0	9	0	0
T319	118497	0	0	0
T320	23411	0	0	0
T321	123657	0	0	0
T322	7070	0	0	0
T323	11215	0	0	0
T324	22518	0	0	0
T325	67813	0	0	0
T326	75898	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	66	0	0
T25	991192	0	0	0
T173	11736	0	0	0
T227	112233	0	0	0
T251	85082	1	0	0
T252	0	15	0	0
T307	0	5	0	0
T308	0	7	0	0
T309	0	1	0	0
T310	0	8	0	0
T312	0	29	0	0
T313	106072	0	0	0
T314	105892	0	0	0
T315	63492	0	0	0
T316	26531	0	0	0
T317	29405	0	0	0
T318	68954	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	1892	0	0
T25	991192	0	0	0
T173	11736	0	0	0
T227	112233	0	0	0
T251	85082	30	0	0
T252	0	19	0	0
T253	0	3	0	0
T305	0	37	0	0
T307	0	51	0	0
T308	0	21	0	0
T309	0	3	0	0
T310	0	17	0	0
T311	0	11	0	0
T312	0	32	0	0
T313	106072	0	0	0
T314	105892	0	0	0
T315	63492	0	0	0
T316	26531	0	0	0
T317	29405	0	0	0
T318	68954	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	2769	0	0
T25	991192	0	0	0
T173	11736	0	0	0
T227	112233	0	0	0
T242	0	17	0	0
T251	85082	18	0	0
T252	0	39	0	0
T253	0	60	0	0
T307	0	89	0	0
T313	106072	0	0	0
T314	105892	0	0	0
T315	63492	0	0	0
T316	26531	0	0	0
T317	29405	0	0	0
T318	68954	0	0	0
T327	0	13	0	0
T328	0	3	0	0
T329	0	10	0	0
T330	0	34	0	0
T331	0	9	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	1337	0	0
T25	991192	0	0	0
T173	11736	0	0	0
T227	112233	0	0	0
T251	85082	33	0	0
T252	0	22	0	0
T253	0	28	0	0
T305	0	31	0	0
T307	0	47	0	0
T308	0	37	0	0
T309	0	8	0	0
T310	0	40	0	0
T311	0	9	0	0
T312	0	50	0	0
T313	106072	0	0	0
T314	105892	0	0	0
T315	63492	0	0	0
T316	26531	0	0	0
T317	29405	0	0	0
T318	68954	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	1207	0	0
T25	991192	0	0	0
T173	11736	0	0	0
T227	112233	0	0	0
T251	85082	23	0	0
T252	0	28	0	0
T253	0	16	0	0
T305	0	55	0	0
T307	0	39	0	0
T308	0	22	0	0
T309	0	6	0	0
T310	0	33	0	0
T311	0	3	0	0
T312	0	59	0	0
T313	106072	0	0	0
T314	105892	0	0	0
T315	63492	0	0	0
T316	26531	0	0	0
T317	29405	0	0	0
T318	68954	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	1315	0	0
T25	991192	0	0	0
T173	11736	0	0	0
T227	112233	0	0	0
T251	85082	14	0	0
T252	0	20	0	0
T253	0	21	0	0
T305	0	50	0	0
T307	0	59	0	0
T308	0	18	0	0
T309	0	5	0	0
T310	0	16	0	0
T311	0	5	0	0
T312	0	48	0	0
T313	106072	0	0	0
T314	105892	0	0	0
T315	63492	0	0	0
T316	26531	0	0	0
T317	29405	0	0	0
T318	68954	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99015688	1351	0	0
T25	991192	0	0	0
T173	11736	0	0	0
T227	112233	0	0	0
T251	85082	21	0	0
T252	0	28	0	0
T253	0	17	0	0
T305	0	41	0	0
T307	0	59	0	0
T308	0	15	0	0
T309	0	26	0	0
T310	0	46	0	0
T311	0	3	0	0
T312	0	52	0	0
T313	106072	0	0	0
T314	105892	0	0	0
T315	63492	0	0	0
T316	26531	0	0	0
T317	29405	0	0	0
T318	68954	0	0	0