Line Coverage for Module :
otp_ctrl_kdi
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 148 | 146 | 98.65 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
| ALWAYS | 259 | 9 | 9 | 100.00 |
| CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 290 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 293 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 293 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 293 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 293 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 305 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
| ALWAYS | 357 | 88 | 86 | 97.73 |
| ALWAYS | 573 | 3 | 3 | 100.00 |
| ALWAYS | 576 | 7 | 7 | 100.00 |
112
113 1/1 assign req[0] = flash_otp_key_i.data_req;
Tests: T2 T4 T5
114 1/1 assign req[1] = flash_otp_key_i.addr_req;
Tests: T2 T4 T5
115 1/1 assign req[2] = otbn_otp_key_i.req;
Tests: T2 T4 T5
116
117 1/1 assign flash_otp_key_o.data_ack = gnt[0];
Tests: T2 T4 T5
118 1/1 assign flash_otp_key_o.addr_ack = gnt[1];
Tests: T2 T4 T5
119 1/1 assign otbn_otp_key_o.ack = gnt[2];
Tests: T2 T4 T5
120
121 // anchored seeds
122 logic [FlashKeySeedWidth-1:0] flash_data_key_seed;
123 logic [FlashKeySeedWidth-1:0] flash_addr_key_seed;
124 logic [SramKeySeedWidth-1:0] sram_data_key_seed;
125
126 prim_sec_anchor_buf #(
127 .Width(FlashKeySeedWidth)
128 ) u_flash_data_key_anchor (
129 .in_i(flash_data_key_seed_i),
130 .out_o(flash_data_key_seed)
131 );
132
133 prim_sec_anchor_buf #(
134 .Width(FlashKeySeedWidth)
135 ) u_flash_addr_key_anchor (
136 .in_i(flash_addr_key_seed_i),
137 .out_o(flash_addr_key_seed)
138 );
139
140 prim_sec_anchor_buf #(
141 .Width(SramKeySeedWidth)
142 ) u_sram_data_key_anchor (
143 .in_i(sram_data_key_seed_i),
144 .out_o(sram_data_key_seed)
145 );
146
147 // Flash data key
148 1/1 assign req_bundles[0] = '{ingest_entropy: 1'b0, // no random entropy added
Tests: T1 T2 T3
149 chained_digest: 1'b0, // revert to netlist IV between blocks
150 digest_sel: FlashDataKey,
151 fetch_nonce: 1'b1,
152 nonce_size: 2'(FlashKeyWidth/EdnDataWidth-1),
153 seed_valid: scrmbl_key_seed_valid_i,
154 seed: flash_data_key_seed}; // 2x128bit
155 // Flash addr key
156 1/1 assign req_bundles[1] = '{ingest_entropy: 1'b0, // no random entropy added
Tests: T1 T2 T3
157 chained_digest: 1'b0, // revert to netlist IV between blocks
158 digest_sel: FlashAddrKey,
159 fetch_nonce: 1'b1,
160 nonce_size: '0,
161 seed_valid: scrmbl_key_seed_valid_i,
162 seed: flash_addr_key_seed}; // 2x128bit
163 // OTBN key
164 1/1 assign req_bundles[2] = '{ingest_entropy: 1'b1, // ingest random data
Tests: T1 T2 T3
165 chained_digest: 1'b0, // revert to netlist IV between blocks
166 digest_sel: SramDataKey,
167 fetch_nonce: 1'b1, // fetch nonce
168 nonce_size: 2'(OtbnNonceWidth/EdnDataWidth-1),
169 seed_valid: scrmbl_key_seed_valid_i,
170 seed: {sram_data_key_seed, // reuse same seed
171 sram_data_key_seed}};
172
173 // SRAM keys
174 for (genvar k = 3; k < NumReq; k++) begin : gen_req_assign
175 4/4 assign req[k] = sram_otp_key_i[k-3].req;
Tests: T2 T4 T5 | T2 T4 T5 | T2 T4 T5 | T2 T4 T5
176 4/4 assign sram_otp_key_o[k-3].ack = gnt[k];
Tests: T2 T4 T5 | T2 T4 T5 | T2 T4 T5 | T2 T4 T5
177 4/4 assign req_bundles[k] = '{ingest_entropy: 1'b1, // ingest random data
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
178 chained_digest: 1'b0, // revert to netlist IV between blocks
179 digest_sel: SramDataKey,
180 fetch_nonce: 1'b1, // fetch nonce
181 nonce_size: 2'(SramNonceWidth/EdnDataWidth-1),
182 seed_valid: scrmbl_key_seed_valid_i,
183 seed: {sram_data_key_seed, // reuse same seed
184 sram_data_key_seed}};
185 end
186
187 // This arbitrates among incoming key derivation requests on a
188 // round robin basis to prevent deadlock.
189 logic req_valid, req_ready;
190 req_bundle_t req_bundle;
191
192 prim_arbiter_tree #(
193 .N(NumReq),
194 .DW($bits(req_bundle_t)))
195 u_req_arb (
196 .clk_i,
197 .rst_ni,
198 .req_chk_i ( 1'b1 ),
199 .req_i ( req ),
200 .data_i ( req_bundles ),
201 .gnt_o ( gnt ),
202 .idx_o ( ),
203 .valid_o ( req_valid ),
204 .data_o ( req_bundle ),
205 .ready_i ( req_ready )
206 );
207
208 //////////////////////////////
209 // Temporary Regs and Muxes //
210 //////////////////////////////
211
212 localparam int CntWidth = 2;
213 logic seed_cnt_clr, seed_cnt_en, entropy_cnt_clr, entropy_cnt_en, seed_cnt_err, entropy_cnt_err;
214 logic [CntWidth-1:0] seed_cnt, entropy_cnt;
215
216 // SEC_CM: KDI_SEED.CTR.REDUN
217 prim_count #(
218 .Width(CntWidth)
219 ) u_prim_count_seed (
220 .clk_i,
221 .rst_ni,
222 .clr_i(seed_cnt_clr),
223 .set_i(1'b0),
224 .set_cnt_i('0),
225 .incr_en_i(seed_cnt_en),
226 .decr_en_i(1'b0),
227 .step_i(CntWidth'(1)),
228 .commit_i(1'b1),
229 .cnt_o(seed_cnt),
230 .cnt_after_commit_o(),
231 .err_o(seed_cnt_err)
232 );
233
234 // SEC_CM: KDI_ENTROPY.CTR.REDUN
235 prim_count #(
236 .Width(CntWidth)
237 ) u_prim_count_entropy (
238 .clk_i,
239 .rst_ni,
240 .clr_i(entropy_cnt_clr),
241 .set_i(1'b0),
242 .set_cnt_i('0),
243 .incr_en_i(entropy_cnt_en),
244 .decr_en_i(1'b0),
245 .step_i(CntWidth'(1)),
246 .commit_i(1'b1),
247 .cnt_o(entropy_cnt),
248 .cnt_after_commit_o(),
249 .err_o(entropy_cnt_err)
250 );
251
252 logic seed_valid_reg_en;
253 logic key_reg_en, nonce_reg_en;
254 logic seed_valid_d, seed_valid_q;
255 logic [ScrmblKeyWidth/ScrmblBlockWidth-1:0][ScrmblBlockWidth-1:0] key_out_d, key_out_q;
256 logic [NumNonceChunks-1:0][ScrmblBlockWidth-1:0] nonce_out_d, nonce_out_q;
257
258 always_comb begin : p_outregs
259 1/1 key_out_d = key_out_q;
Tests: T1 T2 T3
260 1/1 nonce_out_d = nonce_out_q;
Tests: T1 T2 T3
261 1/1 seed_valid_d = seed_valid_q;
Tests: T1 T2 T3
262 1/1 if (key_reg_en) begin
Tests: T1 T2 T3
263 1/1 key_out_d[seed_cnt[1]] = scrmbl_data_i;
Tests: T2 T4 T5
264 end
MISSING_ELSE
265 1/1 if (nonce_reg_en) begin
Tests: T1 T2 T3
266 1/1 nonce_out_d[entropy_cnt[$clog2(NumNonceChunks)-1:0]] = edn_data_i;
Tests: T2 T4 T5
267 end
MISSING_ELSE
268 1/1 if (seed_valid_reg_en) begin
Tests: T1 T2 T3
269 1/1 seed_valid_d = req_bundle.seed_valid;
Tests: T2 T4 T5
270 end
MISSING_ELSE
271 end
272
273 // Connect keys/nonce outputs to output regs.
274 prim_sec_anchor_flop #(
275 .Width(ScrmblKeyWidth),
276 .ResetValue(RndCnstScrmblKeyInit.key)
277 ) u_key_out_anchor (
278 .clk_i,
279 .rst_ni,
280 .d_i(key_out_d),
281 .q_o(key_out_q)
282 );
283
284 1/1 assign otbn_otp_key_o.key = key_out_q;
Tests: T1 T2 T3
285 1/1 assign otbn_otp_key_o.nonce = nonce_out_q[OtbnNonceSel-1:0];
Tests: T1 T2 T3
286 1/1 assign otbn_otp_key_o.seed_valid = seed_valid_q;
Tests: T1 T2 T3
287
288 1/1 assign flash_otp_key_o.key = key_out_q;
Tests: T1 T2 T3
289 1/1 assign flash_otp_key_o.rand_key = nonce_out_q[FlashNonceSel-1:0];
Tests: T1 T2 T3
290 1/1 assign flash_otp_key_o.seed_valid = seed_valid_q;
Tests: T1 T2 T3
291
292 for (genvar k = 0; k < NumSramKeyReqSlots; k++) begin : gen_out_assign
293 4/4 assign sram_otp_key_o[k].key = key_out_q;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
294 4/4 assign sram_otp_key_o[k].nonce = nonce_out_q[SramNonceSel-1:0];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
295 4/4 assign sram_otp_key_o[k].seed_valid = seed_valid_q;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
296 end
297
298 typedef enum logic {
299 SeedData,
300 EntropyData
301 } data_sel_e;
302
303 // Select correct 64bit block.
304 data_sel_e data_sel;
305 1/1 assign scrmbl_data_o = (data_sel == EntropyData) ? nonce_out_q[entropy_cnt[0]] :
Tests: T1 T2 T3
306 // Gate seed value to '0 if invalid.
307 (req_bundle.seed_valid) ? req_bundle.seed[seed_cnt] : '0;
308
309 /////////////////
310 // Control FSM //
311 /////////////////
312
313 // SEC_CM: KDI.FSM.SPARSE
314 // Encoding generated with:
315 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 11 -n 10 \
316 // -s 2544133835 --language=sv
317 //
318 // Hamming distance histogram:
319 //
320 // 0: --
321 // 1: --
322 // 2: --
323 // 3: --
324 // 4: --
325 // 5: |||||||||||||||||||| (54.55%)
326 // 6: |||||||||||||||| (45.45%)
327 // 7: --
328 // 8: --
329 // 9: --
330 // 10: --
331 //
332 // Minimum Hamming distance: 5
333 // Maximum Hamming distance: 6
334 // Minimum Hamming weight: 3
335 // Maximum Hamming weight: 9
336 //
337 localparam int StateWidth = 10;
338 typedef enum logic [StateWidth-1:0] {
339 ResetSt = 10'b0101100001,
340 IdleSt = 10'b0001011011,
341 DigClrSt = 10'b1101010110,
342 DigLoadSt = 10'b0010110111,
343 FetchEntropySt = 10'b1000001101,
344 DigEntropySt = 10'b0100111100,
345 DigFinSt = 10'b1000100010,
346 DigWaitSt = 10'b1110010001,
347 FetchNonceSt = 10'b0011000100,
348 FinishSt = 10'b1011111000,
349 ErrorSt = 10'b1111101111
350 } state_e;
351
352 state_e state_d, state_q;
353 logic edn_req_d, edn_req_q;
354 1/1 assign edn_req_o = edn_req_q;
Tests: T1 T2 T3
355
356 always_comb begin : p_fsm
357 1/1 state_d = state_q;
Tests: T1 T2 T3
358
359 // FSM Error output
360 1/1 fsm_err_o = 1'b0;
Tests: T1 T2 T3
361
362 // Counters
363 1/1 seed_cnt_en = 1'b0;
Tests: T1 T2 T3
364 1/1 seed_cnt_clr = 1'b0;
Tests: T1 T2 T3
365 1/1 entropy_cnt_en = 1'b0;
Tests: T1 T2 T3
366 1/1 entropy_cnt_clr = 1'b0;
Tests: T1 T2 T3
367
368 // EDN 128bit block fetch request.
369 // This keeps the request alive until it has
370 // been acked to adhere to the req/ack protocol
371 // even in cases where the FSM jumps into
372 // an error state while waiting for a request.
373 1/1 edn_req_d = edn_req_q & ~edn_ack_i;
Tests: T1 T2 T3
374
375 // Data selection and temp registers
376 1/1 data_sel = SeedData;
Tests: T1 T2 T3
377 1/1 key_reg_en = 1'b0;
Tests: T1 T2 T3
378 1/1 nonce_reg_en = 1'b0;
Tests: T1 T2 T3
379 1/1 seed_valid_reg_en = 1'b0;
Tests: T1 T2 T3
380
381 // Scrambling datapath
382 1/1 scrmbl_mtx_req_o = 1'b0;
Tests: T1 T2 T3
383 1/1 scrmbl_sel_o = req_bundle.digest_sel;
Tests: T1 T2 T3
384 1/1 scrmbl_cmd_o = LoadShadow;
Tests: T1 T2 T3
385 1/1 scrmbl_mode_o = StandardMode;
Tests: T1 T2 T3
386
387 1/1 scrmbl_valid_o = 1'b0;
Tests: T1 T2 T3
388
389 // Request acknowledgement
390 1/1 req_ready = 1'b0;
Tests: T1 T2 T3
391
392 1/1 unique case (state_q)
Tests: T1 T2 T3
393 ///////////////////////////////////////////////////////////////////
394 // State right after reset. Wait here until KDI gets enabled.
395 ResetSt: begin
396 1/1 if (kdi_en_i) begin
Tests: T1 T2 T3
397 1/1 state_d = IdleSt;
Tests: T1 T2 T3
398 end
MISSING_ELSE
399 end
400 ///////////////////////////////////////////////////////////////////
401 // Wait for a request, then go and acquire the mutex.
402 IdleSt: begin
403 1/1 if (req_valid) begin
Tests: T1 T2 T3
404 1/1 state_d = DigClrSt;
Tests: T2 T4 T5
405 1/1 seed_cnt_clr = 1'b1;
Tests: T2 T4 T5
406 1/1 entropy_cnt_clr = 1'b1;
Tests: T2 T4 T5
407 end
MISSING_ELSE
408 end
409 ///////////////////////////////////////////////////////////////////
410 // First, acquire the mutex for the digest and clear the digest state.
411 DigClrSt: begin
412 1/1 scrmbl_mtx_req_o = 1'b1;
Tests: T2 T4 T5
413 1/1 scrmbl_valid_o = 1'b1;
Tests: T2 T4 T5
414 // Need to reset the digest state and set digest mode to "standard".
415 1/1 scrmbl_cmd_o = DigestInit;
Tests: T2 T4 T5
416 1/1 if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin
Tests: T2 T4 T5
417 1/1 state_d = DigLoadSt;
Tests: T2 T4 T5
418 end
MISSING_ELSE
419 end
420 ///////////////////////////////////////////////////////////////////
421 // Load two 64bit blocks of the seed, and trigger digest calculation.
422 DigLoadSt: begin
423 1/1 scrmbl_mtx_req_o = 1'b1;
Tests: T2 T4 T5
424 1/1 scrmbl_valid_o = 1'b1;
Tests: T2 T4 T5
425 // Trigger digest round in case this is the second block in a row.
426 1/1 if (seed_cnt[0]) begin
Tests: T2 T4 T5
427 1/1 scrmbl_cmd_o = Digest;
Tests: T2 T4 T5
428 1/1 if (scrmbl_ready_i) begin
Tests: T2 T4 T5
429 // Go and ingest a block of entropy if required.
430 1/1 if (req_bundle.ingest_entropy) begin
Tests: T2 T4 T5
431 1/1 state_d = FetchEntropySt;
Tests: T2 T4 T5
432 // Otherwise go to digest finalization state.
433 end else begin
434 1/1 state_d = DigFinSt;
Tests: T2 T4 T5
435 end
436 end
==> MISSING_ELSE
437 // Just load first 64bit block and stay here.
438 1/1 end else if (scrmbl_ready_i) begin
Tests: T2 T4 T5
439 1/1 seed_cnt_en = 1'b1;
Tests: T2 T4 T5
440 end
==> MISSING_ELSE
441 end
442 ///////////////////////////////////////////////////////////////////
443 // Fetch random data to ingest for key derivation.
444 FetchEntropySt: begin
445 1/1 scrmbl_mtx_req_o = 1'b1;
Tests: T2 T4 T5
446 1/1 edn_req_d = 1'b1;
Tests: T2 T4 T5
447 1/1 if (edn_ack_i) begin
Tests: T2 T4 T5
448 1/1 nonce_reg_en = 1'b1;
Tests: T2 T4 T5
449 // Finished, go and acknowledge this request.
450 1/1 if (entropy_cnt == 2'h1) begin
Tests: T2 T4 T5
451 1/1 state_d = DigEntropySt;
Tests: T2 T4 T5
452 1/1 entropy_cnt_clr = 1'b1;
Tests: T2 T4 T5
453 // Keep on requesting entropy.
454 end else begin
455 1/1 entropy_cnt_en = 1'b1;
Tests: T2 T4 T5
456 end
457 end
MISSING_ELSE
458 end
459 ///////////////////////////////////////////////////////////////////
460 // Load two 64bit blocks of entropy data.
461 DigEntropySt: begin
462 1/1 scrmbl_mtx_req_o = 1'b1;
Tests: T2 T4 T5
463 1/1 data_sel = EntropyData;
Tests: T2 T4 T5
464 1/1 scrmbl_valid_o = 1'b1;
Tests: T2 T4 T5
465 // Trigger digest round in case this is the second block in a row,
466 // and go to digest finalization.
467 1/1 if (entropy_cnt[0]) begin
Tests: T2 T4 T5
468 1/1 scrmbl_cmd_o = Digest;
Tests: T2 T4 T5
469 1/1 if (scrmbl_ready_i) begin
Tests: T2 T4 T5
470 1/1 state_d = DigFinSt;
Tests: T2 T4 T5
471 1/1 entropy_cnt_clr = 1'b1;
Tests: T2 T4 T5
472 end
==> MISSING_ELSE
473 // Just load first 64bit block and stay here.
474 1/1 end else if (scrmbl_ready_i) begin
Tests: T2 T4 T5
475 1/1 entropy_cnt_en = 1'b1;
Tests: T2 T4 T5
476 end
MISSING_ELSE
477 end
478 ///////////////////////////////////////////////////////////////////
479 // Trigger digest finalization and go wait for the result.
480 DigFinSt: begin
481 1/1 scrmbl_mtx_req_o = 1'b1;
Tests: T2 T4 T5
482 1/1 scrmbl_valid_o = 1'b1;
Tests: T2 T4 T5
483 1/1 scrmbl_cmd_o = DigestFinalize;
Tests: T2 T4 T5
484 1/1 if (scrmbl_ready_i) begin
Tests: T2 T4 T5
485 1/1 state_d = DigWaitSt;
Tests: T2 T4 T5
486 end
MISSING_ELSE
487 end
488 ///////////////////////////////////////////////////////////////////
489 // Wait for the digest to return, and write the result to the key
490 // output register. Go back and process the second part of the
491 // input seed if needed.
492 DigWaitSt: begin
493 1/1 scrmbl_mtx_req_o = 1'b1;
Tests: T2 T4 T5
494 1/1 if (scrmbl_valid_i) begin
Tests: T2 T4 T5
495 1/1 key_reg_en = 1'b1;
Tests: T2 T4 T5
496 // Not finished yet, need to go back and produce second 64bit block.
497 1/1 if (seed_cnt == 2'h1) begin
Tests: T2 T4 T5
498 1/1 seed_cnt_en = 1'b1;
Tests: T2 T4 T5
499 // In this case the previous digest state is kept,
500 // which leads to a chained digest.
501 1/1 if (req_bundle.chained_digest) begin
Tests: T2 T4 T5
502 0/1 ==> state_d = DigLoadSt;
503 // In this case we revert the digest state to the netlist IV.
504 end else begin
505 1/1 state_d = DigClrSt;
Tests: T2 T4 T5
506 end
507 // This was the second 64bit output block.
508 end else begin
509 1/1 seed_cnt_clr = 1'b1;
Tests: T2 T4 T5
510 // Make sure we output the status of the key seed in OTP.
511 1/1 seed_valid_reg_en = 1'b1;
Tests: T2 T4 T5
512 // Check whether we need to fetch additional nonce data.
513 1/1 if (req_bundle.fetch_nonce) begin
Tests: T2 T4 T5
514 1/1 state_d = FetchNonceSt;
Tests: T2 T4 T5
515 end else begin
516 // Finished, go and acknowledge this request.
517 0/1 ==> state_d = FinishSt;
518 end
519 end
520 end
MISSING_ELSE
521 end
522 ///////////////////////////////////////////////////////////////////
523 // Fetch additional nonce data. Note that the mutex is released in
524 // this state.
525 FetchNonceSt: begin
526 1/1 edn_req_d = 1'b1;
Tests: T2 T4 T5
527 1/1 if (edn_ack_i) begin
Tests: T2 T4 T5
528 1/1 nonce_reg_en = 1'b1;
Tests: T2 T4 T5
529 // Finished, go and acknowledge this request.
530 1/1 if (entropy_cnt == req_bundle.nonce_size) begin
Tests: T2 T4 T5
531 1/1 state_d = FinishSt;
Tests: T2 T4 T5
532 1/1 entropy_cnt_clr = 1'b1;
Tests: T2 T4 T5
533 // Keep on requesting entropy.
534 end else begin
535 1/1 entropy_cnt_en = 1'b1;
Tests: T2 T4 T5
536 end
537 end
MISSING_ELSE
538 end
539 ///////////////////////////////////////////////////////////////////
540 // Acknowledge request and go back to IdleSt.
541 FinishSt: begin
542 1/1 state_d = IdleSt;
Tests: T2 T4 T5
543 1/1 req_ready = 1'b1;
Tests: T2 T4 T5
544 end
545 ///////////////////////////////////////////////////////////////////
546 // Terminal error state. This raises an alert.
547 ErrorSt: begin
548 1/1 fsm_err_o = 1'b1;
Tests: T12 T110 T185
549 end
550 ///////////////////////////////////////////////////////////////////
551 // This should never happen, hence we directly jump into the
552 // error state, where an alert will be triggered.
553 default: begin
554 state_d = ErrorSt;
555 fsm_err_o = 1'b1;
556 end
557 ///////////////////////////////////////////////////////////////////
558 endcase // state_q
559
560 // Unconditionally jump into the terminal error state in case of escalation.
561 // SEC_CM: KDI.FSM.LOCAL_ESC, KDI.FSM.GLOBAL_ESC
562 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) ||
Tests: T1 T2 T3
563 seed_cnt_err || entropy_cnt_err) begin
564 1/1 state_d = ErrorSt;
Tests: T12 T110 T185
565 1/1 fsm_err_o = 1'b1;
Tests: T12 T110 T185
566 end
MISSING_ELSE
567 end
568
569 ///////////////
570 // Registers //
571 ///////////////
572
573 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
573.1 `ifdef SIMULATION
573.2 prim_sparse_fsm_flop #(
573.3 .StateEnumT(state_e),
573.4 .Width($bits(state_e)),
573.5 .ResetValue($bits(state_e)'(ResetSt)),
573.6 .EnableAlertTriggerSVA(1),
573.7 .CustomForceName("state_q")
573.8 ) u_state_regs (
573.9 .clk_i ( clk_i ),
573.10 .rst_ni ( rst_ni ),
573.11 .state_i ( state_d ),
573.12 .state_o ( )
573.13 );
573.14 always_ff @(posedge clk_i or negedge rst_ni) begin
573.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
573.16 1/1 state_q <= ResetSt;
Tests: T1 T2 T3
573.17 end else begin
573.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
573.19 end
573.20 end
573.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
573.22 else begin
573.23 `ifdef UVM
573.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
573.25 "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv", 573, "", 1);
573.26 `else
573.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
573.28 `PRIM_STRINGIFY(u_state_regs_A));
573.29 `endif
573.30 end
573.31 `else
573.32 prim_sparse_fsm_flop #(
573.33 .StateEnumT(state_e),
573.34 .Width($bits(state_e)),
573.35 .ResetValue($bits(state_e)'(ResetSt)),
573.36 .EnableAlertTriggerSVA(1)
573.37 ) u_state_regs (
573.38 .clk_i ( `PRIM_FLOP_CLK ),
573.39 .rst_ni ( `PRIM_FLOP_RST ),
573.40 .state_i ( state_d ),
573.41 .state_o ( state_q )
573.42 );
573.43 `endif574
575 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
576 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
577 1/1 nonce_out_q <= RndCnstScrmblKeyInit.nonce;
Tests: T1 T2 T3
578 1/1 seed_valid_q <= 1'b0;
Tests: T1 T2 T3
579 1/1 edn_req_q <= 1'b0;
Tests: T1 T2 T3
580 end else begin
581 1/1 nonce_out_q <= nonce_out_d;
Tests: T1 T2 T3
582 1/1 seed_valid_q <= seed_valid_d;
Tests: T1 T2 T3
583 1/1 edn_req_q <= edn_req_d;
Tests: T1 T2 T3
Cond Coverage for Module :
otp_ctrl_kdi
| Total | Covered | Percent |
|---|
| Conditions | 18 | 17 | 94.44 |
| Logical | 18 | 17 | 94.44 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 305
EXPRESSION ((data_sel == EntropyData) ? nonce_out_q[entropy_cnt[0]] : (req_bundle.seed_valid ? req_bundle.seed[seed_cnt] : '0))
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 305
SUB-EXPRESSION (data_sel == EntropyData)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 305
SUB-EXPRESSION (req_bundle.seed_valid ? req_bundle.seed[seed_cnt] : '0)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T13 |
LINE 373
EXPRESSION (edn_req_q & ((~edn_ack_i)))
----1---- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 416
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T23,T24,T25 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 450
EXPRESSION (entropy_cnt == 2'b1)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T2,T4,T5 |
LINE 497
EXPRESSION (seed_cnt == 2'b1)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T2,T4,T5 |
LINE 530
EXPRESSION (entropy_cnt == req_bundle.nonce_size)
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T2,T4,T5 |
FSM Coverage for Module :
otp_ctrl_kdi
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
11 |
11 |
100.00 |
(Not included in score) |
| Transitions |
24 |
20 |
83.33 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DigClrSt |
404 |
Covered |
T2,T4,T5 |
| DigEntropySt |
451 |
Covered |
T2,T4,T5 |
| DigFinSt |
434 |
Covered |
T2,T4,T5 |
| DigLoadSt |
417 |
Covered |
T2,T4,T5 |
| DigWaitSt |
485 |
Covered |
T2,T4,T5 |
| ErrorSt |
564 |
Covered |
T12,T110,T185 |
| FetchEntropySt |
431 |
Covered |
T2,T4,T5 |
| FetchNonceSt |
514 |
Covered |
T2,T4,T5 |
| FinishSt |
517 |
Covered |
T2,T4,T5 |
| IdleSt |
397 |
Covered |
T1,T2,T3 |
| ResetSt |
395 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| DigClrSt->DigLoadSt |
417 |
Covered |
T2,T4,T5 |
| DigClrSt->ErrorSt |
564 |
Covered |
T151,T148,T152 |
| DigEntropySt->DigFinSt |
470 |
Covered |
T2,T4,T5 |
| DigEntropySt->ErrorSt |
564 |
Covered |
T240 |
| DigFinSt->DigWaitSt |
485 |
Covered |
T2,T4,T5 |
| DigFinSt->ErrorSt |
564 |
Covered |
T121,T241,T242 |
| DigLoadSt->DigFinSt |
434 |
Covered |
T2,T4,T5 |
| DigLoadSt->ErrorSt |
564 |
Covered |
T12,T216,T243 |
| DigLoadSt->FetchEntropySt |
431 |
Covered |
T2,T4,T5 |
| DigWaitSt->DigClrSt |
505 |
Covered |
T2,T4,T5 |
| DigWaitSt->DigLoadSt |
502 |
Not Covered |
|
| DigWaitSt->ErrorSt |
564 |
Covered |
T244,T245,T246 |
| DigWaitSt->FetchNonceSt |
514 |
Covered |
T2,T4,T5 |
| DigWaitSt->FinishSt |
517 |
Not Covered |
|
| FetchEntropySt->DigEntropySt |
451 |
Covered |
T2,T4,T5 |
| FetchEntropySt->ErrorSt |
564 |
Covered |
T247,T248,T249 |
| FetchNonceSt->ErrorSt |
564 |
Not Covered |
|
| FetchNonceSt->FinishSt |
531 |
Covered |
T2,T4,T5 |
| FinishSt->ErrorSt |
564 |
Not Covered |
|
| FinishSt->IdleSt |
542 |
Covered |
T2,T4,T5 |
| IdleSt->DigClrSt |
404 |
Covered |
T2,T4,T5 |
| IdleSt->ErrorSt |
564 |
Covered |
T110,T185,T194 |
| ResetSt->ErrorSt |
564 |
Covered |
T113,T119,T250 |
| ResetSt->IdleSt |
397 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
otp_ctrl_kdi
| Line No. | Total | Covered | Percent |
| Branches |
|
46 |
41 |
89.13 |
| TERNARY |
305 |
3 |
3 |
100.00 |
| IF |
262 |
2 |
2 |
100.00 |
| IF |
265 |
2 |
2 |
100.00 |
| IF |
268 |
2 |
2 |
100.00 |
| CASE |
392 |
31 |
26 |
83.87 |
| IF |
562 |
2 |
2 |
100.00 |
| IF |
573 |
2 |
2 |
100.00 |
| IF |
576 |
2 |
2 |
100.00 |
305 assign scrmbl_data_o = (data_sel == EntropyData) ? nonce_out_q[entropy_cnt[0]] :
-1-
==>
306 // Gate seed value to '0 if invalid.
307 (req_bundle.seed_valid) ? req_bundle.seed[seed_cnt] : '0;
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T2,T4,T5 |
| 0 |
1 |
Covered |
T4,T5,T13 |
| 0 |
0 |
Covered |
T1,T2,T3 |
262 if (key_reg_en) begin
-1-
263 key_out_d[seed_cnt[1]] = scrmbl_data_i;
==>
264 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
265 if (nonce_reg_en) begin
-1-
266 nonce_out_d[entropy_cnt[$clog2(NumNonceChunks)-1:0]] = edn_data_i;
==>
267 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
268 if (seed_valid_reg_en) begin
-1-
269 seed_valid_d = req_bundle.seed_valid;
==>
270 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
392 unique case (state_q)
-1-
393 ///////////////////////////////////////////////////////////////////
394 // State right after reset. Wait here until KDI gets enabled.
395 ResetSt: begin
396 if (kdi_en_i) begin
-2-
397 state_d = IdleSt;
==>
398 end
MISSING_ELSE
==>
399 end
400 ///////////////////////////////////////////////////////////////////
401 // Wait for a request, then go and acquire the mutex.
402 IdleSt: begin
403 if (req_valid) begin
-3-
404 state_d = DigClrSt;
==>
405 seed_cnt_clr = 1'b1;
406 entropy_cnt_clr = 1'b1;
407 end
MISSING_ELSE
==>
408 end
409 ///////////////////////////////////////////////////////////////////
410 // First, acquire the mutex for the digest and clear the digest state.
411 DigClrSt: begin
412 scrmbl_mtx_req_o = 1'b1;
413 scrmbl_valid_o = 1'b1;
414 // Need to reset the digest state and set digest mode to "standard".
415 scrmbl_cmd_o = DigestInit;
416 if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin
-4-
417 state_d = DigLoadSt;
==>
418 end
MISSING_ELSE
==>
419 end
420 ///////////////////////////////////////////////////////////////////
421 // Load two 64bit blocks of the seed, and trigger digest calculation.
422 DigLoadSt: begin
423 scrmbl_mtx_req_o = 1'b1;
424 scrmbl_valid_o = 1'b1;
425 // Trigger digest round in case this is the second block in a row.
426 if (seed_cnt[0]) begin
-5-
427 scrmbl_cmd_o = Digest;
428 if (scrmbl_ready_i) begin
-6-
429 // Go and ingest a block of entropy if required.
430 if (req_bundle.ingest_entropy) begin
-7-
431 state_d = FetchEntropySt;
==>
432 // Otherwise go to digest finalization state.
433 end else begin
434 state_d = DigFinSt;
==>
435 end
436 end
MISSING_ELSE
==>
437 // Just load first 64bit block and stay here.
438 end else if (scrmbl_ready_i) begin
-8-
439 seed_cnt_en = 1'b1;
==>
440 end
MISSING_ELSE
==>
441 end
442 ///////////////////////////////////////////////////////////////////
443 // Fetch random data to ingest for key derivation.
444 FetchEntropySt: begin
445 scrmbl_mtx_req_o = 1'b1;
446 edn_req_d = 1'b1;
447 if (edn_ack_i) begin
-9-
448 nonce_reg_en = 1'b1;
449 // Finished, go and acknowledge this request.
450 if (entropy_cnt == 2'h1) begin
-10-
451 state_d = DigEntropySt;
==>
452 entropy_cnt_clr = 1'b1;
453 // Keep on requesting entropy.
454 end else begin
455 entropy_cnt_en = 1'b1;
==>
456 end
457 end
MISSING_ELSE
==>
458 end
459 ///////////////////////////////////////////////////////////////////
460 // Load two 64bit blocks of entropy data.
461 DigEntropySt: begin
462 scrmbl_mtx_req_o = 1'b1;
463 data_sel = EntropyData;
464 scrmbl_valid_o = 1'b1;
465 // Trigger digest round in case this is the second block in a row,
466 // and go to digest finalization.
467 if (entropy_cnt[0]) begin
-11-
468 scrmbl_cmd_o = Digest;
469 if (scrmbl_ready_i) begin
-12-
470 state_d = DigFinSt;
==>
471 entropy_cnt_clr = 1'b1;
472 end
MISSING_ELSE
==>
473 // Just load first 64bit block and stay here.
474 end else if (scrmbl_ready_i) begin
-13-
475 entropy_cnt_en = 1'b1;
==>
476 end
MISSING_ELSE
==>
477 end
478 ///////////////////////////////////////////////////////////////////
479 // Trigger digest finalization and go wait for the result.
480 DigFinSt: begin
481 scrmbl_mtx_req_o = 1'b1;
482 scrmbl_valid_o = 1'b1;
483 scrmbl_cmd_o = DigestFinalize;
484 if (scrmbl_ready_i) begin
-14-
485 state_d = DigWaitSt;
==>
486 end
MISSING_ELSE
==>
487 end
488 ///////////////////////////////////////////////////////////////////
489 // Wait for the digest to return, and write the result to the key
490 // output register. Go back and process the second part of the
491 // input seed if needed.
492 DigWaitSt: begin
493 scrmbl_mtx_req_o = 1'b1;
494 if (scrmbl_valid_i) begin
-15-
495 key_reg_en = 1'b1;
496 // Not finished yet, need to go back and produce second 64bit block.
497 if (seed_cnt == 2'h1) begin
-16-
498 seed_cnt_en = 1'b1;
499 // In this case the previous digest state is kept,
500 // which leads to a chained digest.
501 if (req_bundle.chained_digest) begin
-17-
502 state_d = DigLoadSt;
==>
503 // In this case we revert the digest state to the netlist IV.
504 end else begin
505 state_d = DigClrSt;
==>
506 end
507 // This was the second 64bit output block.
508 end else begin
509 seed_cnt_clr = 1'b1;
510 // Make sure we output the status of the key seed in OTP.
511 seed_valid_reg_en = 1'b1;
512 // Check whether we need to fetch additional nonce data.
513 if (req_bundle.fetch_nonce) begin
-18-
514 state_d = FetchNonceSt;
==>
515 end else begin
516 // Finished, go and acknowledge this request.
517 state_d = FinishSt;
==>
518 end
519 end
520 end
MISSING_ELSE
==>
521 end
522 ///////////////////////////////////////////////////////////////////
523 // Fetch additional nonce data. Note that the mutex is released in
524 // this state.
525 FetchNonceSt: begin
526 edn_req_d = 1'b1;
527 if (edn_ack_i) begin
-19-
528 nonce_reg_en = 1'b1;
529 // Finished, go and acknowledge this request.
530 if (entropy_cnt == req_bundle.nonce_size) begin
-20-
531 state_d = FinishSt;
==>
532 entropy_cnt_clr = 1'b1;
533 // Keep on requesting entropy.
534 end else begin
535 entropy_cnt_en = 1'b1;
==>
536 end
537 end
MISSING_ELSE
==>
538 end
539 ///////////////////////////////////////////////////////////////////
540 // Acknowledge request and go back to IdleSt.
541 FinishSt: begin
542 state_d = IdleSt;
==>
543 req_ready = 1'b1;
544 end
545 ///////////////////////////////////////////////////////////////////
546 // Terminal error state. This raises an alert.
547 ErrorSt: begin
548 fsm_err_o = 1'b1;
==>
549 end
550 ///////////////////////////////////////////////////////////////////
551 // This should never happen, hence we directly jump into the
552 // error state, where an alert will be triggered.
553 default: begin
554 state_d = ErrorSt;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | -19- | -20- | Status | Tests |
| ResetSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| IdleSt |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| DigClrSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| DigClrSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T105,T107,T159 |
| DigLoadSt |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| DigLoadSt |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| DigLoadSt |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| DigLoadSt |
- |
- |
- |
0 |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| DigLoadSt |
- |
- |
- |
0 |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| FetchEntropySt |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| FetchEntropySt |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| FetchEntropySt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| DigEntropySt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| DigEntropySt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| DigEntropySt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| DigEntropySt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T5,T13 |
| DigFinSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| DigFinSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| DigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
Not Covered |
|
| DigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
Covered |
T2,T4,T5 |
| DigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
1 |
- |
- |
Covered |
T2,T4,T5 |
| DigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
- |
- |
Not Covered |
|
| DigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| FetchNonceSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
Covered |
T2,T4,T5 |
| FetchNonceSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
Covered |
T2,T4,T5 |
| FetchNonceSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T2,T4,T5 |
| FinishSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T12,T110,T185 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T23,T24,T25 |
562 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) ||
-1-
563 seed_cnt_err || entropy_cnt_err) begin
564 state_d = ErrorSt;
==>
565 fsm_err_o = 1'b1;
566 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T12,T110,T185 |
| 0 |
Covered |
T1,T2,T3 |
573 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
576 if (!rst_ni) begin
-1-
577 nonce_out_q <= RndCnstScrmblKeyInit.nonce;
==>
578 seed_valid_q <= 1'b0;
579 edn_req_q <= 1'b0;
580 end else begin
581 nonce_out_q <= nonce_out_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
otp_ctrl_kdi
Assertion Details
EdnReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
EntropyWidthDividesDigestBlockWidth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
FlashOtpKeyRspKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
FsmErrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
KeyNonceSize0_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
KeyNonceSize1_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
KeyNonceSize2_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
KeyNonceSize3_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
KeyNonceSize4_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
KeyNonceSize5_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
KeyNonceSize6_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
NonceWidth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
OtbnOtpKeyRspKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ScrmblCmdKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ScrmblDataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ScrmblModeKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ScrmblMtxReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ScrmblSelKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ScrmblValidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
SramOtpKeyRspKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_otp_ctrl_kdi
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 147 | 146 | 99.32 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
| ALWAYS | 259 | 9 | 9 | 100.00 |
| CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 290 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 293 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 293 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 293 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 293 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 305 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
| ALWAYS | 357 | 87 | 86 | 98.85 |
| ALWAYS | 573 | 3 | 3 | 100.00 |
| ALWAYS | 576 | 7 | 7 | 100.00 |
112
113 1/1 assign req[0] = flash_otp_key_i.data_req;
Tests: T2 T4 T5
114 1/1 assign req[1] = flash_otp_key_i.addr_req;
Tests: T2 T4 T5
115 1/1 assign req[2] = otbn_otp_key_i.req;
Tests: T2 T4 T5
116
117 1/1 assign flash_otp_key_o.data_ack = gnt[0];
Tests: T2 T4 T5
118 1/1 assign flash_otp_key_o.addr_ack = gnt[1];
Tests: T2 T4 T5
119 1/1 assign otbn_otp_key_o.ack = gnt[2];
Tests: T2 T4 T5
120
121 // anchored seeds
122 logic [FlashKeySeedWidth-1:0] flash_data_key_seed;
123 logic [FlashKeySeedWidth-1:0] flash_addr_key_seed;
124 logic [SramKeySeedWidth-1:0] sram_data_key_seed;
125
126 prim_sec_anchor_buf #(
127 .Width(FlashKeySeedWidth)
128 ) u_flash_data_key_anchor (
129 .in_i(flash_data_key_seed_i),
130 .out_o(flash_data_key_seed)
131 );
132
133 prim_sec_anchor_buf #(
134 .Width(FlashKeySeedWidth)
135 ) u_flash_addr_key_anchor (
136 .in_i(flash_addr_key_seed_i),
137 .out_o(flash_addr_key_seed)
138 );
139
140 prim_sec_anchor_buf #(
141 .Width(SramKeySeedWidth)
142 ) u_sram_data_key_anchor (
143 .in_i(sram_data_key_seed_i),
144 .out_o(sram_data_key_seed)
145 );
146
147 // Flash data key
148 1/1 assign req_bundles[0] = '{ingest_entropy: 1'b0, // no random entropy added
Tests: T1 T2 T3
149 chained_digest: 1'b0, // revert to netlist IV between blocks
150 digest_sel: FlashDataKey,
151 fetch_nonce: 1'b1,
152 nonce_size: 2'(FlashKeyWidth/EdnDataWidth-1),
153 seed_valid: scrmbl_key_seed_valid_i,
154 seed: flash_data_key_seed}; // 2x128bit
155 // Flash addr key
156 1/1 assign req_bundles[1] = '{ingest_entropy: 1'b0, // no random entropy added
Tests: T1 T2 T3
157 chained_digest: 1'b0, // revert to netlist IV between blocks
158 digest_sel: FlashAddrKey,
159 fetch_nonce: 1'b1,
160 nonce_size: '0,
161 seed_valid: scrmbl_key_seed_valid_i,
162 seed: flash_addr_key_seed}; // 2x128bit
163 // OTBN key
164 1/1 assign req_bundles[2] = '{ingest_entropy: 1'b1, // ingest random data
Tests: T1 T2 T3
165 chained_digest: 1'b0, // revert to netlist IV between blocks
166 digest_sel: SramDataKey,
167 fetch_nonce: 1'b1, // fetch nonce
168 nonce_size: 2'(OtbnNonceWidth/EdnDataWidth-1),
169 seed_valid: scrmbl_key_seed_valid_i,
170 seed: {sram_data_key_seed, // reuse same seed
171 sram_data_key_seed}};
172
173 // SRAM keys
174 for (genvar k = 3; k < NumReq; k++) begin : gen_req_assign
175 4/4 assign req[k] = sram_otp_key_i[k-3].req;
Tests: T2 T4 T5 | T2 T4 T5 | T2 T4 T5 | T2 T4 T5
176 4/4 assign sram_otp_key_o[k-3].ack = gnt[k];
Tests: T2 T4 T5 | T2 T4 T5 | T2 T4 T5 | T2 T4 T5
177 4/4 assign req_bundles[k] = '{ingest_entropy: 1'b1, // ingest random data
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
178 chained_digest: 1'b0, // revert to netlist IV between blocks
179 digest_sel: SramDataKey,
180 fetch_nonce: 1'b1, // fetch nonce
181 nonce_size: 2'(SramNonceWidth/EdnDataWidth-1),
182 seed_valid: scrmbl_key_seed_valid_i,
183 seed: {sram_data_key_seed, // reuse same seed
184 sram_data_key_seed}};
185 end
186
187 // This arbitrates among incoming key derivation requests on a
188 // round robin basis to prevent deadlock.
189 logic req_valid, req_ready;
190 req_bundle_t req_bundle;
191
192 prim_arbiter_tree #(
193 .N(NumReq),
194 .DW($bits(req_bundle_t)))
195 u_req_arb (
196 .clk_i,
197 .rst_ni,
198 .req_chk_i ( 1'b1 ),
199 .req_i ( req ),
200 .data_i ( req_bundles ),
201 .gnt_o ( gnt ),
202 .idx_o ( ),
203 .valid_o ( req_valid ),
204 .data_o ( req_bundle ),
205 .ready_i ( req_ready )
206 );
207
208 //////////////////////////////
209 // Temporary Regs and Muxes //
210 //////////////////////////////
211
212 localparam int CntWidth = 2;
213 logic seed_cnt_clr, seed_cnt_en, entropy_cnt_clr, entropy_cnt_en, seed_cnt_err, entropy_cnt_err;
214 logic [CntWidth-1:0] seed_cnt, entropy_cnt;
215
216 // SEC_CM: KDI_SEED.CTR.REDUN
217 prim_count #(
218 .Width(CntWidth)
219 ) u_prim_count_seed (
220 .clk_i,
221 .rst_ni,
222 .clr_i(seed_cnt_clr),
223 .set_i(1'b0),
224 .set_cnt_i('0),
225 .incr_en_i(seed_cnt_en),
226 .decr_en_i(1'b0),
227 .step_i(CntWidth'(1)),
228 .commit_i(1'b1),
229 .cnt_o(seed_cnt),
230 .cnt_after_commit_o(),
231 .err_o(seed_cnt_err)
232 );
233
234 // SEC_CM: KDI_ENTROPY.CTR.REDUN
235 prim_count #(
236 .Width(CntWidth)
237 ) u_prim_count_entropy (
238 .clk_i,
239 .rst_ni,
240 .clr_i(entropy_cnt_clr),
241 .set_i(1'b0),
242 .set_cnt_i('0),
243 .incr_en_i(entropy_cnt_en),
244 .decr_en_i(1'b0),
245 .step_i(CntWidth'(1)),
246 .commit_i(1'b1),
247 .cnt_o(entropy_cnt),
248 .cnt_after_commit_o(),
249 .err_o(entropy_cnt_err)
250 );
251
252 logic seed_valid_reg_en;
253 logic key_reg_en, nonce_reg_en;
254 logic seed_valid_d, seed_valid_q;
255 logic [ScrmblKeyWidth/ScrmblBlockWidth-1:0][ScrmblBlockWidth-1:0] key_out_d, key_out_q;
256 logic [NumNonceChunks-1:0][ScrmblBlockWidth-1:0] nonce_out_d, nonce_out_q;
257
258 always_comb begin : p_outregs
259 1/1 key_out_d = key_out_q;
Tests: T1 T2 T3
260 1/1 nonce_out_d = nonce_out_q;
Tests: T1 T2 T3
261 1/1 seed_valid_d = seed_valid_q;
Tests: T1 T2 T3
262 1/1 if (key_reg_en) begin
Tests: T1 T2 T3
263 1/1 key_out_d[seed_cnt[1]] = scrmbl_data_i;
Tests: T2 T4 T5
264 end
MISSING_ELSE
265 1/1 if (nonce_reg_en) begin
Tests: T1 T2 T3
266 1/1 nonce_out_d[entropy_cnt[$clog2(NumNonceChunks)-1:0]] = edn_data_i;
Tests: T2 T4 T5
267 end
MISSING_ELSE
268 1/1 if (seed_valid_reg_en) begin
Tests: T1 T2 T3
269 1/1 seed_valid_d = req_bundle.seed_valid;
Tests: T2 T4 T5
270 end
MISSING_ELSE
271 end
272
273 // Connect keys/nonce outputs to output regs.
274 prim_sec_anchor_flop #(
275 .Width(ScrmblKeyWidth),
276 .ResetValue(RndCnstScrmblKeyInit.key)
277 ) u_key_out_anchor (
278 .clk_i,
279 .rst_ni,
280 .d_i(key_out_d),
281 .q_o(key_out_q)
282 );
283
284 1/1 assign otbn_otp_key_o.key = key_out_q;
Tests: T1 T2 T3
285 1/1 assign otbn_otp_key_o.nonce = nonce_out_q[OtbnNonceSel-1:0];
Tests: T1 T2 T3
286 1/1 assign otbn_otp_key_o.seed_valid = seed_valid_q;
Tests: T1 T2 T3
287
288 1/1 assign flash_otp_key_o.key = key_out_q;
Tests: T1 T2 T3
289 1/1 assign flash_otp_key_o.rand_key = nonce_out_q[FlashNonceSel-1:0];
Tests: T1 T2 T3
290 1/1 assign flash_otp_key_o.seed_valid = seed_valid_q;
Tests: T1 T2 T3
291
292 for (genvar k = 0; k < NumSramKeyReqSlots; k++) begin : gen_out_assign
293 4/4 assign sram_otp_key_o[k].key = key_out_q;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
294 4/4 assign sram_otp_key_o[k].nonce = nonce_out_q[SramNonceSel-1:0];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
295 4/4 assign sram_otp_key_o[k].seed_valid = seed_valid_q;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
296 end
297
298 typedef enum logic {
299 SeedData,
300 EntropyData
301 } data_sel_e;
302
303 // Select correct 64bit block.
304 data_sel_e data_sel;
305 1/1 assign scrmbl_data_o = (data_sel == EntropyData) ? nonce_out_q[entropy_cnt[0]] :
Tests: T1 T2 T3
306 // Gate seed value to '0 if invalid.
307 (req_bundle.seed_valid) ? req_bundle.seed[seed_cnt] : '0;
308
309 /////////////////
310 // Control FSM //
311 /////////////////
312
313 // SEC_CM: KDI.FSM.SPARSE
314 // Encoding generated with:
315 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 11 -n 10 \
316 // -s 2544133835 --language=sv
317 //
318 // Hamming distance histogram:
319 //
320 // 0: --
321 // 1: --
322 // 2: --
323 // 3: --
324 // 4: --
325 // 5: |||||||||||||||||||| (54.55%)
326 // 6: |||||||||||||||| (45.45%)
327 // 7: --
328 // 8: --
329 // 9: --
330 // 10: --
331 //
332 // Minimum Hamming distance: 5
333 // Maximum Hamming distance: 6
334 // Minimum Hamming weight: 3
335 // Maximum Hamming weight: 9
336 //
337 localparam int StateWidth = 10;
338 typedef enum logic [StateWidth-1:0] {
339 ResetSt = 10'b0101100001,
340 IdleSt = 10'b0001011011,
341 DigClrSt = 10'b1101010110,
342 DigLoadSt = 10'b0010110111,
343 FetchEntropySt = 10'b1000001101,
344 DigEntropySt = 10'b0100111100,
345 DigFinSt = 10'b1000100010,
346 DigWaitSt = 10'b1110010001,
347 FetchNonceSt = 10'b0011000100,
348 FinishSt = 10'b1011111000,
349 ErrorSt = 10'b1111101111
350 } state_e;
351
352 state_e state_d, state_q;
353 logic edn_req_d, edn_req_q;
354 1/1 assign edn_req_o = edn_req_q;
Tests: T1 T2 T3
355
356 always_comb begin : p_fsm
357 1/1 state_d = state_q;
Tests: T1 T2 T3
358
359 // FSM Error output
360 1/1 fsm_err_o = 1'b0;
Tests: T1 T2 T3
361
362 // Counters
363 1/1 seed_cnt_en = 1'b0;
Tests: T1 T2 T3
364 1/1 seed_cnt_clr = 1'b0;
Tests: T1 T2 T3
365 1/1 entropy_cnt_en = 1'b0;
Tests: T1 T2 T3
366 1/1 entropy_cnt_clr = 1'b0;
Tests: T1 T2 T3
367
368 // EDN 128bit block fetch request.
369 // This keeps the request alive until it has
370 // been acked to adhere to the req/ack protocol
371 // even in cases where the FSM jumps into
372 // an error state while waiting for a request.
373 1/1 edn_req_d = edn_req_q & ~edn_ack_i;
Tests: T1 T2 T3
374
375 // Data selection and temp registers
376 1/1 data_sel = SeedData;
Tests: T1 T2 T3
377 1/1 key_reg_en = 1'b0;
Tests: T1 T2 T3
378 1/1 nonce_reg_en = 1'b0;
Tests: T1 T2 T3
379 1/1 seed_valid_reg_en = 1'b0;
Tests: T1 T2 T3
380
381 // Scrambling datapath
382 1/1 scrmbl_mtx_req_o = 1'b0;
Tests: T1 T2 T3
383 1/1 scrmbl_sel_o = req_bundle.digest_sel;
Tests: T1 T2 T3
384 1/1 scrmbl_cmd_o = LoadShadow;
Tests: T1 T2 T3
385 1/1 scrmbl_mode_o = StandardMode;
Tests: T1 T2 T3
386
387 1/1 scrmbl_valid_o = 1'b0;
Tests: T1 T2 T3
388
389 // Request acknowledgement
390 1/1 req_ready = 1'b0;
Tests: T1 T2 T3
391
392 1/1 unique case (state_q)
Tests: T1 T2 T3
393 ///////////////////////////////////////////////////////////////////
394 // State right after reset. Wait here until KDI gets enabled.
395 ResetSt: begin
396 1/1 if (kdi_en_i) begin
Tests: T1 T2 T3
397 1/1 state_d = IdleSt;
Tests: T1 T2 T3
398 end
MISSING_ELSE
399 end
400 ///////////////////////////////////////////////////////////////////
401 // Wait for a request, then go and acquire the mutex.
402 IdleSt: begin
403 1/1 if (req_valid) begin
Tests: T1 T2 T3
404 1/1 state_d = DigClrSt;
Tests: T2 T4 T5
405 1/1 seed_cnt_clr = 1'b1;
Tests: T2 T4 T5
406 1/1 entropy_cnt_clr = 1'b1;
Tests: T2 T4 T5
407 end
MISSING_ELSE
408 end
409 ///////////////////////////////////////////////////////////////////
410 // First, acquire the mutex for the digest and clear the digest state.
411 DigClrSt: begin
412 1/1 scrmbl_mtx_req_o = 1'b1;
Tests: T2 T4 T5
413 1/1 scrmbl_valid_o = 1'b1;
Tests: T2 T4 T5
414 // Need to reset the digest state and set digest mode to "standard".
415 1/1 scrmbl_cmd_o = DigestInit;
Tests: T2 T4 T5
416 1/1 if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin
Tests: T2 T4 T5
417 1/1 state_d = DigLoadSt;
Tests: T2 T4 T5
418 end
MISSING_ELSE
419 end
420 ///////////////////////////////////////////////////////////////////
421 // Load two 64bit blocks of the seed, and trigger digest calculation.
422 DigLoadSt: begin
423 1/1 scrmbl_mtx_req_o = 1'b1;
Tests: T2 T4 T5
424 1/1 scrmbl_valid_o = 1'b1;
Tests: T2 T4 T5
425 // Trigger digest round in case this is the second block in a row.
426 1/1 if (seed_cnt[0]) begin
Tests: T2 T4 T5
427 1/1 scrmbl_cmd_o = Digest;
Tests: T2 T4 T5
428 1/1 if (scrmbl_ready_i) begin
Tests: T2 T4 T5
429 // Go and ingest a block of entropy if required.
430 1/1 if (req_bundle.ingest_entropy) begin
Tests: T2 T4 T5
431 1/1 state_d = FetchEntropySt;
Tests: T2 T4 T5
432 // Otherwise go to digest finalization state.
433 end else begin
434 1/1 state_d = DigFinSt;
Tests: T2 T4 T5
435 end
436 end
==> MISSING_ELSE
437 // Just load first 64bit block and stay here.
438 1/1 end else if (scrmbl_ready_i) begin
Tests: T2 T4 T5
439 1/1 seed_cnt_en = 1'b1;
Tests: T2 T4 T5
440 end
==> MISSING_ELSE
441 end
442 ///////////////////////////////////////////////////////////////////
443 // Fetch random data to ingest for key derivation.
444 FetchEntropySt: begin
445 1/1 scrmbl_mtx_req_o = 1'b1;
Tests: T2 T4 T5
446 1/1 edn_req_d = 1'b1;
Tests: T2 T4 T5
447 1/1 if (edn_ack_i) begin
Tests: T2 T4 T5
448 1/1 nonce_reg_en = 1'b1;
Tests: T2 T4 T5
449 // Finished, go and acknowledge this request.
450 1/1 if (entropy_cnt == 2'h1) begin
Tests: T2 T4 T5
451 1/1 state_d = DigEntropySt;
Tests: T2 T4 T5
452 1/1 entropy_cnt_clr = 1'b1;
Tests: T2 T4 T5
453 // Keep on requesting entropy.
454 end else begin
455 1/1 entropy_cnt_en = 1'b1;
Tests: T2 T4 T5
456 end
457 end
MISSING_ELSE
458 end
459 ///////////////////////////////////////////////////////////////////
460 // Load two 64bit blocks of entropy data.
461 DigEntropySt: begin
462 1/1 scrmbl_mtx_req_o = 1'b1;
Tests: T2 T4 T5
463 1/1 data_sel = EntropyData;
Tests: T2 T4 T5
464 1/1 scrmbl_valid_o = 1'b1;
Tests: T2 T4 T5
465 // Trigger digest round in case this is the second block in a row,
466 // and go to digest finalization.
467 1/1 if (entropy_cnt[0]) begin
Tests: T2 T4 T5
468 1/1 scrmbl_cmd_o = Digest;
Tests: T2 T4 T5
469 1/1 if (scrmbl_ready_i) begin
Tests: T2 T4 T5
470 1/1 state_d = DigFinSt;
Tests: T2 T4 T5
471 1/1 entropy_cnt_clr = 1'b1;
Tests: T2 T4 T5
472 end
==> MISSING_ELSE
473 // Just load first 64bit block and stay here.
474 1/1 end else if (scrmbl_ready_i) begin
Tests: T2 T4 T5
475 1/1 entropy_cnt_en = 1'b1;
Tests: T2 T4 T5
476 end
MISSING_ELSE
477 end
478 ///////////////////////////////////////////////////////////////////
479 // Trigger digest finalization and go wait for the result.
480 DigFinSt: begin
481 1/1 scrmbl_mtx_req_o = 1'b1;
Tests: T2 T4 T5
482 1/1 scrmbl_valid_o = 1'b1;
Tests: T2 T4 T5
483 1/1 scrmbl_cmd_o = DigestFinalize;
Tests: T2 T4 T5
484 1/1 if (scrmbl_ready_i) begin
Tests: T2 T4 T5
485 1/1 state_d = DigWaitSt;
Tests: T2 T4 T5
486 end
MISSING_ELSE
487 end
488 ///////////////////////////////////////////////////////////////////
489 // Wait for the digest to return, and write the result to the key
490 // output register. Go back and process the second part of the
491 // input seed if needed.
492 DigWaitSt: begin
493 1/1 scrmbl_mtx_req_o = 1'b1;
Tests: T2 T4 T5
494 1/1 if (scrmbl_valid_i) begin
Tests: T2 T4 T5
495 1/1 key_reg_en = 1'b1;
Tests: T2 T4 T5
496 // Not finished yet, need to go back and produce second 64bit block.
497 1/1 if (seed_cnt == 2'h1) begin
Tests: T2 T4 T5
498 1/1 seed_cnt_en = 1'b1;
Tests: T2 T4 T5
499 // In this case the previous digest state is kept,
500 // which leads to a chained digest.
501 1/1 if (req_bundle.chained_digest) begin
Tests: T2 T4 T5
502 excluded state_d = DigLoadSt;
Exclude Annotation: VC_COV_UNR
503 // In this case we revert the digest state to the netlist IV.
504 end else begin
505 1/1 state_d = DigClrSt;
Tests: T2 T4 T5
506 end
507 // This was the second 64bit output block.
508 end else begin
509 1/1 seed_cnt_clr = 1'b1;
Tests: T2 T4 T5
510 // Make sure we output the status of the key seed in OTP.
511 1/1 seed_valid_reg_en = 1'b1;
Tests: T2 T4 T5
512 // Check whether we need to fetch additional nonce data.
513 1/1 if (req_bundle.fetch_nonce) begin
Tests: T2 T4 T5
514 1/1 state_d = FetchNonceSt;
Tests: T2 T4 T5
515 end else begin
516 // Finished, go and acknowledge this request.
517 0/1 ==> state_d = FinishSt;
518 end
519 end
520 end
MISSING_ELSE
521 end
522 ///////////////////////////////////////////////////////////////////
523 // Fetch additional nonce data. Note that the mutex is released in
524 // this state.
525 FetchNonceSt: begin
526 1/1 edn_req_d = 1'b1;
Tests: T2 T4 T5
527 1/1 if (edn_ack_i) begin
Tests: T2 T4 T5
528 1/1 nonce_reg_en = 1'b1;
Tests: T2 T4 T5
529 // Finished, go and acknowledge this request.
530 1/1 if (entropy_cnt == req_bundle.nonce_size) begin
Tests: T2 T4 T5
531 1/1 state_d = FinishSt;
Tests: T2 T4 T5
532 1/1 entropy_cnt_clr = 1'b1;
Tests: T2 T4 T5
533 // Keep on requesting entropy.
534 end else begin
535 1/1 entropy_cnt_en = 1'b1;
Tests: T2 T4 T5
536 end
537 end
MISSING_ELSE
538 end
539 ///////////////////////////////////////////////////////////////////
540 // Acknowledge request and go back to IdleSt.
541 FinishSt: begin
542 1/1 state_d = IdleSt;
Tests: T2 T4 T5
543 1/1 req_ready = 1'b1;
Tests: T2 T4 T5
544 end
545 ///////////////////////////////////////////////////////////////////
546 // Terminal error state. This raises an alert.
547 ErrorSt: begin
548 1/1 fsm_err_o = 1'b1;
Tests: T12 T110 T185
549 end
550 ///////////////////////////////////////////////////////////////////
551 // This should never happen, hence we directly jump into the
552 // error state, where an alert will be triggered.
553 default: begin
554 state_d = ErrorSt;
555 fsm_err_o = 1'b1;
556 end
557 ///////////////////////////////////////////////////////////////////
558 endcase // state_q
559
560 // Unconditionally jump into the terminal error state in case of escalation.
561 // SEC_CM: KDI.FSM.LOCAL_ESC, KDI.FSM.GLOBAL_ESC
562 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) ||
Tests: T1 T2 T3
563 seed_cnt_err || entropy_cnt_err) begin
564 1/1 state_d = ErrorSt;
Tests: T12 T110 T185
565 1/1 fsm_err_o = 1'b1;
Tests: T12 T110 T185
566 end
MISSING_ELSE
567 end
568
569 ///////////////
570 // Registers //
571 ///////////////
572
573 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
573.1 `ifdef SIMULATION
573.2 prim_sparse_fsm_flop #(
573.3 .StateEnumT(state_e),
573.4 .Width($bits(state_e)),
573.5 .ResetValue($bits(state_e)'(ResetSt)),
573.6 .EnableAlertTriggerSVA(1),
573.7 .CustomForceName("state_q")
573.8 ) u_state_regs (
573.9 .clk_i ( clk_i ),
573.10 .rst_ni ( rst_ni ),
573.11 .state_i ( state_d ),
573.12 .state_o ( )
573.13 );
573.14 always_ff @(posedge clk_i or negedge rst_ni) begin
573.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
573.16 1/1 state_q <= ResetSt;
Tests: T1 T2 T3
573.17 end else begin
573.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
573.19 end
573.20 end
573.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
573.22 else begin
573.23 `ifdef UVM
573.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
573.25 "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv", 573, "", 1);
573.26 `else
573.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
573.28 `PRIM_STRINGIFY(u_state_regs_A));
573.29 `endif
573.30 end
573.31 `else
573.32 prim_sparse_fsm_flop #(
573.33 .StateEnumT(state_e),
573.34 .Width($bits(state_e)),
573.35 .ResetValue($bits(state_e)'(ResetSt)),
573.36 .EnableAlertTriggerSVA(1)
573.37 ) u_state_regs (
573.38 .clk_i ( `PRIM_FLOP_CLK ),
573.39 .rst_ni ( `PRIM_FLOP_RST ),
573.40 .state_i ( state_d ),
573.41 .state_o ( state_q )
573.42 );
573.43 `endif574
575 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
576 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
577 1/1 nonce_out_q <= RndCnstScrmblKeyInit.nonce;
Tests: T1 T2 T3
578 1/1 seed_valid_q <= 1'b0;
Tests: T1 T2 T3
579 1/1 edn_req_q <= 1'b0;
Tests: T1 T2 T3
580 end else begin
581 1/1 nonce_out_q <= nonce_out_d;
Tests: T1 T2 T3
582 1/1 seed_valid_q <= seed_valid_d;
Tests: T1 T2 T3
583 1/1 edn_req_q <= edn_req_d;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp_ctrl_kdi
| Total | Covered | Percent |
|---|
| Conditions | 17 | 17 | 100.00 |
| Logical | 17 | 17 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 305
EXPRESSION ((data_sel == EntropyData) ? nonce_out_q[entropy_cnt[0]] : (req_bundle.seed_valid ? req_bundle.seed[seed_cnt] : '0))
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 305
SUB-EXPRESSION (data_sel == EntropyData)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 305
SUB-EXPRESSION (req_bundle.seed_valid ? req_bundle.seed[seed_cnt] : '0)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T13 |
LINE 373
EXPRESSION (edn_req_q & ((~edn_ack_i)))
----1---- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 416
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T23,T24,T25 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 450
EXPRESSION (entropy_cnt == 2'b1)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T2,T4,T5 |
LINE 497
EXPRESSION (seed_cnt == 2'b1)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T2,T4,T5 |
LINE 530
EXPRESSION (entropy_cnt == req_bundle.nonce_size)
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T2,T4,T5 |
FSM Coverage for Instance : tb.dut.u_otp_ctrl_kdi
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
11 |
11 |
100.00 |
(Not included in score) |
| Transitions |
22 |
20 |
90.91 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DigClrSt |
404 |
Covered |
T2,T4,T5 |
| DigEntropySt |
451 |
Covered |
T2,T4,T5 |
| DigFinSt |
434 |
Covered |
T2,T4,T5 |
| DigLoadSt |
417 |
Covered |
T2,T4,T5 |
| DigWaitSt |
485 |
Covered |
T2,T4,T5 |
| ErrorSt |
564 |
Covered |
T12,T110,T185 |
| FetchEntropySt |
431 |
Covered |
T2,T4,T5 |
| FetchNonceSt |
514 |
Covered |
T2,T4,T5 |
| FinishSt |
517 |
Covered |
T2,T4,T5 |
| IdleSt |
397 |
Covered |
T1,T2,T3 |
| ResetSt |
395 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests | Exclude Annotation |
| DigClrSt->DigLoadSt |
417 |
Covered |
T2,T4,T5 |
|
| DigClrSt->ErrorSt |
564 |
Covered |
T151,T148,T152 |
|
| DigEntropySt->DigFinSt |
470 |
Covered |
T2,T4,T5 |
|
| DigEntropySt->ErrorSt |
564 |
Covered |
T240 |
|
| DigFinSt->DigWaitSt |
485 |
Covered |
T2,T4,T5 |
|
| DigFinSt->ErrorSt |
564 |
Covered |
T121,T241,T242 |
|
| DigLoadSt->DigFinSt |
434 |
Covered |
T2,T4,T5 |
|
| DigLoadSt->ErrorSt |
564 |
Covered |
T12,T216,T243 |
|
| DigLoadSt->FetchEntropySt |
431 |
Covered |
T2,T4,T5 |
|
| DigWaitSt->DigClrSt |
505 |
Covered |
T2,T4,T5 |
|
| DigWaitSt->DigLoadSt |
502 |
Excluded |
|
VC_COV_UNR |
| DigWaitSt->ErrorSt |
564 |
Covered |
T244,T245,T246 |
|
| DigWaitSt->FetchNonceSt |
514 |
Covered |
T2,T4,T5 |
|
| DigWaitSt->FinishSt |
517 |
Excluded |
|
|
| FetchEntropySt->DigEntropySt |
451 |
Covered |
T2,T4,T5 |
|
| FetchEntropySt->ErrorSt |
564 |
Covered |
T247,T248,T249 |
|
| FetchNonceSt->ErrorSt |
564 |
Not Covered |
|
|
| FetchNonceSt->FinishSt |
531 |
Covered |
T2,T4,T5 |
|
| FinishSt->ErrorSt |
564 |
Not Covered |
|
|
| FinishSt->IdleSt |
542 |
Covered |
T2,T4,T5 |
|
| IdleSt->DigClrSt |
404 |
Covered |
T2,T4,T5 |
|
| IdleSt->ErrorSt |
564 |
Covered |
T110,T185,T194 |
|
| ResetSt->ErrorSt |
564 |
Covered |
T113,T119,T250 |
|
| ResetSt->IdleSt |
397 |
Covered |
T1,T2,T3 |
|
Branch Coverage for Instance : tb.dut.u_otp_ctrl_kdi
| Line No. | Total | Covered | Percent |
| Branches |
|
45 |
41 |
91.11 |
| TERNARY |
305 |
3 |
3 |
100.00 |
| IF |
262 |
2 |
2 |
100.00 |
| IF |
265 |
2 |
2 |
100.00 |
| IF |
268 |
2 |
2 |
100.00 |
| CASE |
392 |
30 |
26 |
86.67 |
| IF |
562 |
2 |
2 |
100.00 |
| IF |
573 |
2 |
2 |
100.00 |
| IF |
576 |
2 |
2 |
100.00 |
305 assign scrmbl_data_o = (data_sel == EntropyData) ? nonce_out_q[entropy_cnt[0]] :
-1-
==>
306 // Gate seed value to '0 if invalid.
307 (req_bundle.seed_valid) ? req_bundle.seed[seed_cnt] : '0;
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T2,T4,T5 |
| 0 |
1 |
Covered |
T4,T5,T13 |
| 0 |
0 |
Covered |
T1,T2,T3 |
262 if (key_reg_en) begin
-1-
263 key_out_d[seed_cnt[1]] = scrmbl_data_i;
==>
264 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
265 if (nonce_reg_en) begin
-1-
266 nonce_out_d[entropy_cnt[$clog2(NumNonceChunks)-1:0]] = edn_data_i;
==>
267 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
268 if (seed_valid_reg_en) begin
-1-
269 seed_valid_d = req_bundle.seed_valid;
==>
270 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
392 unique case (state_q)
-1-
393 ///////////////////////////////////////////////////////////////////
394 // State right after reset. Wait here until KDI gets enabled.
395 ResetSt: begin
396 if (kdi_en_i) begin
-2-
397 state_d = IdleSt;
==>
398 end
MISSING_ELSE
==>
399 end
400 ///////////////////////////////////////////////////////////////////
401 // Wait for a request, then go and acquire the mutex.
402 IdleSt: begin
403 if (req_valid) begin
-3-
404 state_d = DigClrSt;
==>
405 seed_cnt_clr = 1'b1;
406 entropy_cnt_clr = 1'b1;
407 end
MISSING_ELSE
==>
408 end
409 ///////////////////////////////////////////////////////////////////
410 // First, acquire the mutex for the digest and clear the digest state.
411 DigClrSt: begin
412 scrmbl_mtx_req_o = 1'b1;
413 scrmbl_valid_o = 1'b1;
414 // Need to reset the digest state and set digest mode to "standard".
415 scrmbl_cmd_o = DigestInit;
416 if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin
-4-
417 state_d = DigLoadSt;
==>
418 end
MISSING_ELSE
==>
419 end
420 ///////////////////////////////////////////////////////////////////
421 // Load two 64bit blocks of the seed, and trigger digest calculation.
422 DigLoadSt: begin
423 scrmbl_mtx_req_o = 1'b1;
424 scrmbl_valid_o = 1'b1;
425 // Trigger digest round in case this is the second block in a row.
426 if (seed_cnt[0]) begin
-5-
427 scrmbl_cmd_o = Digest;
428 if (scrmbl_ready_i) begin
-6-
429 // Go and ingest a block of entropy if required.
430 if (req_bundle.ingest_entropy) begin
-7-
431 state_d = FetchEntropySt;
==>
432 // Otherwise go to digest finalization state.
433 end else begin
434 state_d = DigFinSt;
==>
435 end
436 end
MISSING_ELSE
==>
437 // Just load first 64bit block and stay here.
438 end else if (scrmbl_ready_i) begin
-8-
439 seed_cnt_en = 1'b1;
==>
440 end
MISSING_ELSE
==>
441 end
442 ///////////////////////////////////////////////////////////////////
443 // Fetch random data to ingest for key derivation.
444 FetchEntropySt: begin
445 scrmbl_mtx_req_o = 1'b1;
446 edn_req_d = 1'b1;
447 if (edn_ack_i) begin
-9-
448 nonce_reg_en = 1'b1;
449 // Finished, go and acknowledge this request.
450 if (entropy_cnt == 2'h1) begin
-10-
451 state_d = DigEntropySt;
==>
452 entropy_cnt_clr = 1'b1;
453 // Keep on requesting entropy.
454 end else begin
455 entropy_cnt_en = 1'b1;
==>
456 end
457 end
MISSING_ELSE
==>
458 end
459 ///////////////////////////////////////////////////////////////////
460 // Load two 64bit blocks of entropy data.
461 DigEntropySt: begin
462 scrmbl_mtx_req_o = 1'b1;
463 data_sel = EntropyData;
464 scrmbl_valid_o = 1'b1;
465 // Trigger digest round in case this is the second block in a row,
466 // and go to digest finalization.
467 if (entropy_cnt[0]) begin
-11-
468 scrmbl_cmd_o = Digest;
469 if (scrmbl_ready_i) begin
-12-
470 state_d = DigFinSt;
==>
471 entropy_cnt_clr = 1'b1;
472 end
MISSING_ELSE
==>
473 // Just load first 64bit block and stay here.
474 end else if (scrmbl_ready_i) begin
-13-
475 entropy_cnt_en = 1'b1;
==>
476 end
MISSING_ELSE
==>
477 end
478 ///////////////////////////////////////////////////////////////////
479 // Trigger digest finalization and go wait for the result.
480 DigFinSt: begin
481 scrmbl_mtx_req_o = 1'b1;
482 scrmbl_valid_o = 1'b1;
483 scrmbl_cmd_o = DigestFinalize;
484 if (scrmbl_ready_i) begin
-14-
485 state_d = DigWaitSt;
==>
486 end
MISSING_ELSE
==>
487 end
488 ///////////////////////////////////////////////////////////////////
489 // Wait for the digest to return, and write the result to the key
490 // output register. Go back and process the second part of the
491 // input seed if needed.
492 DigWaitSt: begin
493 scrmbl_mtx_req_o = 1'b1;
494 if (scrmbl_valid_i) begin
-15-
495 key_reg_en = 1'b1;
496 // Not finished yet, need to go back and produce second 64bit block.
497 if (seed_cnt == 2'h1) begin
-16-
498 seed_cnt_en = 1'b1;
499 // In this case the previous digest state is kept,
500 // which leads to a chained digest.
501 if (req_bundle.chained_digest) begin
-17-
502 state_d = DigLoadSt;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
503 // In this case we revert the digest state to the netlist IV.
504 end else begin
505 state_d = DigClrSt;
==>
506 end
507 // This was the second 64bit output block.
508 end else begin
509 seed_cnt_clr = 1'b1;
510 // Make sure we output the status of the key seed in OTP.
511 seed_valid_reg_en = 1'b1;
512 // Check whether we need to fetch additional nonce data.
513 if (req_bundle.fetch_nonce) begin
-18-
514 state_d = FetchNonceSt;
==>
515 end else begin
516 // Finished, go and acknowledge this request.
517 state_d = FinishSt;
==>
518 end
519 end
520 end
MISSING_ELSE
==>
521 end
522 ///////////////////////////////////////////////////////////////////
523 // Fetch additional nonce data. Note that the mutex is released in
524 // this state.
525 FetchNonceSt: begin
526 edn_req_d = 1'b1;
527 if (edn_ack_i) begin
-19-
528 nonce_reg_en = 1'b1;
529 // Finished, go and acknowledge this request.
530 if (entropy_cnt == req_bundle.nonce_size) begin
-20-
531 state_d = FinishSt;
==>
532 entropy_cnt_clr = 1'b1;
533 // Keep on requesting entropy.
534 end else begin
535 entropy_cnt_en = 1'b1;
==>
536 end
537 end
MISSING_ELSE
==>
538 end
539 ///////////////////////////////////////////////////////////////////
540 // Acknowledge request and go back to IdleSt.
541 FinishSt: begin
542 state_d = IdleSt;
==>
543 req_ready = 1'b1;
544 end
545 ///////////////////////////////////////////////////////////////////
546 // Terminal error state. This raises an alert.
547 ErrorSt: begin
548 fsm_err_o = 1'b1;
==>
549 end
550 ///////////////////////////////////////////////////////////////////
551 // This should never happen, hence we directly jump into the
552 // error state, where an alert will be triggered.
553 default: begin
554 state_d = ErrorSt;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | -19- | -20- | Status | Tests | Exclude Annotation |
| ResetSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| IdleSt |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| IdleSt |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| DigClrSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| DigClrSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T105,T107,T159 |
|
| DigLoadSt |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| DigLoadSt |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| DigLoadSt |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
|
| DigLoadSt |
- |
- |
- |
0 |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| DigLoadSt |
- |
- |
- |
0 |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
|
| FetchEntropySt |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| FetchEntropySt |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| FetchEntropySt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| DigEntropySt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| DigEntropySt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
|
| DigEntropySt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| DigEntropySt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T5,T13 |
|
| DigFinSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| DigFinSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| DigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
| DigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| DigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
1 |
- |
- |
Covered |
T2,T4,T5 |
|
| DigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
- |
- |
Not Covered |
|
|
| DigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| FetchNonceSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
Covered |
T2,T4,T5 |
|
| FetchNonceSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
Covered |
T2,T4,T5 |
|
| FetchNonceSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T2,T4,T5 |
|
| FinishSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T12,T110,T185 |
|
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T23,T24,T25 |
|
562 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) ||
-1-
563 seed_cnt_err || entropy_cnt_err) begin
564 state_d = ErrorSt;
==>
565 fsm_err_o = 1'b1;
566 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T12,T110,T185 |
| 0 |
Covered |
T1,T2,T3 |
573 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
576 if (!rst_ni) begin
-1-
577 nonce_out_q <= RndCnstScrmblKeyInit.nonce;
==>
578 seed_valid_q <= 1'b0;
579 edn_req_q <= 1'b0;
580 end else begin
581 nonce_out_q <= nonce_out_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_otp_ctrl_kdi
Assertion Details
EdnReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
EntropyWidthDividesDigestBlockWidth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
FlashOtpKeyRspKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
FsmErrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
KeyNonceSize0_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
KeyNonceSize1_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
KeyNonceSize2_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
KeyNonceSize3_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
KeyNonceSize4_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
KeyNonceSize5_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
KeyNonceSize6_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
NonceWidth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
OtbnOtpKeyRspKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ScrmblCmdKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ScrmblDataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ScrmblModeKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ScrmblMtxReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ScrmblSelKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ScrmblValidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
SramOtpKeyRspKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |