Line Coverage for Module :
otp_ctrl_lfsr_timer
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 91 | 91 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 190 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 243 | 1 | 1 | 100.00 |
| ALWAYS | 246 | 52 | 52 | 100.00 |
| ALWAYS | 367 | 3 | 3 | 100.00 |
| ALWAYS | 370 | 13 | 13 | 100.00 |
71 logic [$clog2(LfsrUsageThreshold+1)-1:0] reseed_cnt_d, reseed_cnt_q;
72 1/1 assign reseed_cnt_d = (reseed_en) ? '0 :
Tests: T1 T2 T3
73 (edn_req_o) ? reseed_cnt_q :
74 (lfsr_en) ? reseed_cnt_q + 1'b1 :
75 reseed_cnt_q;
76
77 1/1 assign edn_req_o = (reseed_cnt_q >= LfsrUsageThreshold);
Tests: T1 T2 T3
78 1/1 assign reseed_en = edn_req_o & edn_ack_i;
Tests: T1 T2 T3
79
80 ///////////////////////////
81 // Tandem LFSR Instances //
82 ///////////////////////////
83
84 logic lfsr_err;
85 logic [LfsrWidth-1:0] entropy;
86 logic [LfsrWidth-1:0] lfsr_state;
87 1/1 assign entropy = (reseed_en) ? edn_data_i[LfsrWidth-1:0] : '0;
Tests: T1 T2 T3
88
89 // We employ two redundant LFSRs to guard against FI attacks.
90 // If any of the two is glitched and the two LFSR states do not agree,
91 // the FSM below is moved into a terminal error state.
92 // SEC_CM: TIMER.LFSR.REDUN
93 prim_double_lfsr #(
94 .LfsrDw ( LfsrWidth ),
95 .EntropyDw ( LfsrWidth ),
96 .StateOutDw ( LfsrWidth ),
97 .DefaultSeed ( RndCnstLfsrSeed ),
98 .StatePermEn ( 1'b1 ),
99 .StatePerm ( RndCnstLfsrPerm ),
100 .ExtSeedSVA ( 1'b0 )
101 ) u_prim_double_lfsr (
102 .clk_i,
103 .rst_ni,
104 .seed_en_i ( 1'b0 ),
105 .seed_i ( '0 ),
106 .lfsr_en_i ( reseed_en || lfsr_en ),
107 .entropy_i ( entropy ),
108 .state_o ( lfsr_state ),
109 .err_o ( lfsr_err )
110 );
111
112 // Not all entropy bits are used.
113 logic unused_seed;
114 1/1 assign unused_seed = ^edn_data_i;
Tests: T1 T2 T3
115
116 `ASSERT_INIT(EdnIsWideEnough_A, EdnDataWidth >= LfsrWidth)
117
118 //////////////////////////////
119 // Tandem Counter Instances //
120 //////////////////////////////
121
122 // We employ redundant counters to guard against FI attacks.
123 // If any of them is glitched and the redundant counter states do not agree,
124 // the FSM below is moved into a terminal error state.
125 logic [LfsrWidth-1:0] integ_cnt, cnsty_cnt, integ_cnt_set_val, cnsty_cnt_set_val;
126 logic [LfsrWidth-1:0] integ_mask, cnsty_mask;
127 logic integ_set_period, integ_set_timeout, integ_cnt_zero;
128 logic cnsty_set_period, cnsty_set_timeout, cnsty_cnt_zero;
129 logic integ_cnt_set, cnsty_cnt_set, integ_cnt_err, cnsty_cnt_err;
130 logic timeout_zero, integ_msk_zero, cnsty_msk_zero, cnsty_cnt_pause;
131
132 1/1 assign timeout_zero = (timeout_i == '0);
Tests: T1 T2 T3
133 1/1 assign integ_msk_zero = (integ_period_msk_i == '0);
Tests: T1 T2 T3
134 1/1 assign cnsty_msk_zero = (cnsty_period_msk_i == '0);
Tests: T1 T2 T3
135 1/1 assign integ_cnt_zero = (integ_cnt == '0);
Tests: T1 T2 T3
136 1/1 assign cnsty_cnt_zero = (cnsty_cnt == '0);
Tests: T1 T2 T3
137
138 1/1 assign integ_cnt_set = integ_set_period || integ_set_timeout;
Tests: T1 T2 T3
139 1/1 assign cnsty_cnt_set = cnsty_set_period || cnsty_set_timeout;
Tests: T1 T2 T3
140
141 1/1 assign integ_mask = {integ_period_msk_i, {LfsrWidth-32{1'b1}}};
Tests: T1 T2 T3
142 1/1 assign cnsty_mask = {cnsty_period_msk_i, {LfsrWidth-32{1'b1}}};
Tests: T1 T2 T3
143 1/1 assign integ_cnt_set_val = (integ_set_period) ? (lfsr_state & integ_mask) : LfsrWidth'(timeout_i);
Tests: T1 T2 T3
144 1/1 assign cnsty_cnt_set_val = (cnsty_set_period) ? (lfsr_state & cnsty_mask) : LfsrWidth'(timeout_i);
Tests: T1 T2 T3
145
146 // SEC_CM: TIMER_INTEG.CTR.REDUN
147 prim_count #(
148 .Width(LfsrWidth)
149 ) u_prim_count_integ (
150 .clk_i,
151 .rst_ni,
152 .clr_i(1'b0),
153 .set_i(integ_cnt_set),
154 .set_cnt_i(integ_cnt_set_val),
155 .incr_en_i(1'b0),
156 .decr_en_i(!integ_cnt_zero),
157 .step_i(LfsrWidth'(1)),
158 .commit_i(1'b1),
159 .cnt_o(integ_cnt),
160 .cnt_after_commit_o(),
161 .err_o(integ_cnt_err)
162 );
163
164 // SEC_CM: TIMER_CNSTY.CTR.REDUN
165 prim_count #(
166 .Width(LfsrWidth)
167 ) u_prim_count_cnsty (
168 .clk_i,
169 .rst_ni,
170 .clr_i(1'b0),
171 .set_i(cnsty_cnt_set),
172 .set_cnt_i(cnsty_cnt_set_val),
173 .incr_en_i(1'b0),
174 .decr_en_i(!cnsty_cnt_zero && !cnsty_cnt_pause),
175 .step_i(LfsrWidth'(1)),
176 .commit_i(1'b1),
177 .cnt_o(cnsty_cnt),
178 .cnt_after_commit_o(),
179 .err_o(cnsty_cnt_err)
180 );
181
182 /////////////////////
183 // Request signals //
184 /////////////////////
185
186 logic set_all_integ_reqs, set_all_cnsty_reqs;
187 logic [NumPart-1:0] integ_chk_req_d, integ_chk_req_q;
188 logic [NumPart-1:0] cnsty_chk_req_d, cnsty_chk_req_q;
189 1/1 assign integ_chk_req_o = integ_chk_req_q;
Tests: T1 T2 T3
190 1/1 assign cnsty_chk_req_o = cnsty_chk_req_q;
Tests: T1 T2 T3
191 1/1 assign integ_chk_req_d = (set_all_integ_reqs) ? {NumPart{1'b1}} :
Tests: T1 T2 T3
192 integ_chk_req_q & ~integ_chk_ack_i;
193 1/1 assign cnsty_chk_req_d = (set_all_cnsty_reqs) ? {NumPart{1'b1}} :
Tests: T1 T2 T3
194 cnsty_chk_req_q & ~cnsty_chk_ack_i;
195
196
197 // external triggers
198 logic clr_integ_chk_trig, clr_cnsty_chk_trig;
199 logic integ_chk_trig_d, integ_chk_trig_q;
200 logic cnsty_chk_trig_d, cnsty_chk_trig_q;
201 1/1 assign integ_chk_trig_d = (integ_chk_trig_q & ~clr_integ_chk_trig) | integ_chk_trig_i;
Tests: T1 T2 T3
202 1/1 assign cnsty_chk_trig_d = (cnsty_chk_trig_q & ~clr_cnsty_chk_trig) | cnsty_chk_trig_i;
Tests: T1 T2 T3
203
204 ////////////////////////////
205 // Ping and Timeout Logic //
206 ////////////////////////////
207
208 // SEC_CM: TIMER.FSM.SPARSE
209 // Encoding generated with:
210 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \
211 // -s 628816752 --language=sv
212 //
213 // Hamming distance histogram:
214 //
215 // 0: --
216 // 1: --
217 // 2: --
218 // 3: --
219 // 4: --
220 // 5: |||||||||||||||||||| (60.00%)
221 // 6: ||||||||||||| (40.00%)
222 // 7: --
223 // 8: --
224 // 9: --
225 //
226 // Minimum Hamming distance: 5
227 // Maximum Hamming distance: 6
228 // Minimum Hamming weight: 4
229 // Maximum Hamming weight: 6
230 //
231 localparam int StateWidth = 9;
232 typedef enum logic [StateWidth-1:0] {
233 ResetSt = 9'b100100101,
234 IdleSt = 9'b001101110,
235 IntegWaitSt = 9'b010110011,
236 CnstyWaitSt = 9'b111010110,
237 ErrorSt = 9'b001011001
238 } state_e;
239
240 state_e state_d, state_q;
241 logic chk_timeout_d, chk_timeout_q;
242
243 1/1 assign chk_timeout_o = chk_timeout_q;
Tests: T1 T2 T3
244
245 always_comb begin : p_fsm
246 1/1 state_d = state_q;
Tests: T1 T2 T3
247
248 // LFSR and counter signals
249 1/1 lfsr_en = 1'b0;
Tests: T1 T2 T3
250 1/1 integ_set_period = 1'b0;
Tests: T1 T2 T3
251 1/1 cnsty_set_period = 1'b0;
Tests: T1 T2 T3
252 1/1 integ_set_timeout = 1'b0;
Tests: T1 T2 T3
253 1/1 cnsty_set_timeout = 1'b0;
Tests: T1 T2 T3
254 1/1 cnsty_cnt_pause = 1'b0;
Tests: T1 T2 T3
255
256 // Requests going to partitions.
257 1/1 set_all_integ_reqs = '0;
Tests: T1 T2 T3
258 1/1 set_all_cnsty_reqs = '0;
Tests: T1 T2 T3
259
260 // Status signals going to CSRs and error logic.
261 1/1 chk_timeout_d = chk_timeout_q;
Tests: T1 T2 T3
262 1/1 chk_pending_o = cnsty_chk_trig_q || integ_chk_trig_q;
Tests: T1 T2 T3
263 1/1 fsm_err_o = 1'b0;
Tests: T1 T2 T3
264
265 // Clear signals for external triggers
266 1/1 clr_integ_chk_trig = 1'b0;
Tests: T1 T2 T3
267 1/1 clr_cnsty_chk_trig = 1'b0;
Tests: T1 T2 T3
268
269 1/1 unique case (state_q)
Tests: T1 T2 T3
270 ///////////////////////////////////////////////////////////////////
271 // Wait until enabled. We never return to this state
272 // once enabled!
273 ResetSt: begin
274 1/1 if (timer_en_i) begin
Tests: T1 T2 T3
275 1/1 state_d = IdleSt;
Tests: T1 T2 T3
276 1/1 lfsr_en = 1'b1;
Tests: T1 T2 T3
277 end
MISSING_ELSE
278 end
279 ///////////////////////////////////////////////////////////////////
280 // Wait here until one of the two timers expires (if enabled) or if
281 // a check is triggered externally.
282 IdleSt: begin
283 1/1 if ((!integ_msk_zero && integ_cnt_zero) || integ_chk_trig_q) begin
Tests: T1 T2 T3
284 1/1 state_d = IntegWaitSt;
Tests: T2 T4 T5
285 1/1 integ_set_timeout = 1'b1;
Tests: T2 T4 T5
286 1/1 set_all_integ_reqs = 1'b1;
Tests: T2 T4 T5
287 1/1 clr_integ_chk_trig = integ_chk_trig_q;
Tests: T2 T4 T5
288 1/1 end else if ((!cnsty_msk_zero && cnsty_cnt_zero) || cnsty_chk_trig_q) begin
Tests: T1 T2 T3
289 1/1 state_d = CnstyWaitSt;
Tests: T2 T4 T5
290 1/1 cnsty_set_timeout = 1'b1;
Tests: T2 T4 T5
291 1/1 set_all_cnsty_reqs = 1'b1;
Tests: T2 T4 T5
292 1/1 clr_cnsty_chk_trig = cnsty_chk_trig_q;
Tests: T2 T4 T5
293 end
MISSING_ELSE
294 end
295 ///////////////////////////////////////////////////////////////////
296 // Wait for all the partitions to respond and go back to idle.
297 // If the timeout is enabled, bail out into terminal error state
298 // if the timeout counter expires (this will raise an alert).
299 IntegWaitSt: begin
300 1/1 chk_pending_o = 1'b1;
Tests: T2 T4 T5
301 1/1 if (!timeout_zero && integ_cnt_zero) begin
Tests: T2 T4 T5
302 1/1 state_d = ErrorSt;
Tests: T4 T93 T61
303 1/1 chk_timeout_d = 1'b1;
Tests: T4 T93 T61
304 1/1 end else if (integ_chk_req_q == '0) begin
Tests: T2 T4 T5
305 1/1 state_d = IdleSt;
Tests: T2 T4 T5
306 // This draws the next wait period.
307 1/1 integ_set_period = 1'b1;
Tests: T2 T4 T5
308 1/1 lfsr_en = 1'b1;
Tests: T2 T4 T5
309 end
MISSING_ELSE
310 end
311 ///////////////////////////////////////////////////////////////////
312 // Wait for all the partitions to respond and go back to idle.
313 // If the timeout is enabled, bail out into terminal error state
314 // if the timeout counter expires (this will raise an alert).
315 CnstyWaitSt: begin
316 1/1 chk_pending_o = 1'b1;
Tests: T2 T4 T5
317 // Note that consistency checks go back and read from OTP. Hence,
318 // life cycle transitions and DAI programming operations
319 // may interfere with these checks and cause them to take longer
320 // than typically expected. Therefore, the timeout counter is stopped
321 // during programming operations.
322 1/1 cnsty_cnt_pause = otp_prog_busy_i;
Tests: T2 T4 T5
323 1/1 if (!timeout_zero && cnsty_cnt_zero) begin
Tests: T2 T4 T5
324 1/1 state_d = ErrorSt;
Tests: T13 T90 T91
325 1/1 chk_timeout_d = 1'b1;
Tests: T13 T90 T91
326 1/1 end else if (cnsty_chk_req_q == '0) begin
Tests: T2 T4 T5
327 1/1 state_d = IdleSt;
Tests: T2 T4 T5
328 // This draws the next wait period.
329 1/1 cnsty_set_period = 1'b1;
Tests: T2 T4 T5
330 1/1 lfsr_en = 1'b1;
Tests: T2 T4 T5
331 end
MISSING_ELSE
332 end
333 ///////////////////////////////////////////////////////////////////
334 // Terminal error state. This raises an alert.
335 ErrorSt: begin
336 // Continuously clear pending checks.
337 1/1 clr_integ_chk_trig = 1'b1;
Tests: T4 T12 T13
338 1/1 clr_cnsty_chk_trig = 1'b1;
Tests: T4 T12 T13
339 1/1 if (!chk_timeout_q) begin
Tests: T4 T12 T13
340 1/1 fsm_err_o = 1'b1;
Tests: T12 T110 T185
341 end
MISSING_ELSE
342 end
343 ///////////////////////////////////////////////////////////////////
344 // This should never happen, hence we directly jump into the
345 // error state, where an alert will be triggered.
346 default: begin
347 state_d = ErrorSt;
348 fsm_err_o = 1'b1;
349 end
350 ///////////////////////////////////////////////////////////////////
351 endcase // state_q
352
353 // Unconditionally jump into the terminal error state in case of escalation,
354 // or if the two LFSR or counter states do not agree.
355 // SEC_CM: TIMER.FSM.LOCAL_ESC, TIMER.FSM.GLOBAL_ESC
356 1/1 if (lfsr_err || integ_cnt_err || cnsty_cnt_err ||
Tests: T1 T2 T3
357 lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
358 1/1 state_d = ErrorSt;
Tests: T12 T110 T185
359 1/1 fsm_err_o = 1'b1;
Tests: T12 T110 T185
360 end
MISSING_ELSE
361 end
362
363 ///////////////
364 // Registers //
365 ///////////////
366
367 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
367.1 `ifdef SIMULATION
367.2 prim_sparse_fsm_flop #(
367.3 .StateEnumT(state_e),
367.4 .Width($bits(state_e)),
367.5 .ResetValue($bits(state_e)'(ResetSt)),
367.6 .EnableAlertTriggerSVA(1),
367.7 .CustomForceName("state_q")
367.8 ) u_state_regs (
367.9 .clk_i ( clk_i ),
367.10 .rst_ni ( rst_ni ),
367.11 .state_i ( state_d ),
367.12 .state_o ( )
367.13 );
367.14 always_ff @(posedge clk_i or negedge rst_ni) begin
367.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
367.16 1/1 state_q <= ResetSt;
Tests: T1 T2 T3
367.17 end else begin
367.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
367.19 end
367.20 end
367.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
367.22 else begin
367.23 `ifdef UVM
367.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
367.25 "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv", 367, "", 1);
367.26 `else
367.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
367.28 `PRIM_STRINGIFY(u_state_regs_A));
367.29 `endif
367.30 end
367.31 `else
367.32 prim_sparse_fsm_flop #(
367.33 .StateEnumT(state_e),
367.34 .Width($bits(state_e)),
367.35 .ResetValue($bits(state_e)'(ResetSt)),
367.36 .EnableAlertTriggerSVA(1)
367.37 ) u_state_regs (
367.38 .clk_i ( `PRIM_FLOP_CLK ),
367.39 .rst_ni ( `PRIM_FLOP_RST ),
367.40 .state_i ( state_d ),
367.41 .state_o ( state_q )
367.42 );
367.43 `endif368
369 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
370 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
371 1/1 integ_chk_req_q <= '0;
Tests: T1 T2 T3
372 1/1 cnsty_chk_req_q <= '0;
Tests: T1 T2 T3
373 1/1 chk_timeout_q <= 1'b0;
Tests: T1 T2 T3
374 1/1 reseed_cnt_q <= '0;
Tests: T1 T2 T3
375 1/1 integ_chk_trig_q <= 1'b0;
Tests: T1 T2 T3
376 1/1 cnsty_chk_trig_q <= 1'b0;
Tests: T1 T2 T3
377 end else begin
378 1/1 integ_chk_req_q <= integ_chk_req_d;
Tests: T1 T2 T3
379 1/1 cnsty_chk_req_q <= cnsty_chk_req_d;
Tests: T1 T2 T3
380 1/1 chk_timeout_q <= chk_timeout_d;
Tests: T1 T2 T3
381 1/1 reseed_cnt_q <= reseed_cnt_d;
Tests: T1 T2 T3
382 1/1 integ_chk_trig_q <= integ_chk_trig_d;
Tests: T1 T2 T3
383 1/1 cnsty_chk_trig_q <= cnsty_chk_trig_d;
Tests: T1 T2 T3
Cond Coverage for Module :
otp_ctrl_lfsr_timer
| Total | Covered | Percent |
|---|
| Conditions | 78 | 69 | 88.46 |
| Logical | 78 | 69 | 88.46 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 72
EXPRESSION (reseed_en ? '0 : (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 72
SUB-EXPRESSION (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 72
SUB-EXPRESSION (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (edn_req_o & edn_ack_i)
----1---- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 87
EXPRESSION (reseed_en ? edn_data_i[(otp_ctrl_pkg::LfsrWidth - 1):0] : '0)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 101
EXPRESSION (reseed_en || lfsr_en)
----1---- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
LINE 132
EXPRESSION (timeout_i == '0)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 133
EXPRESSION (integ_period_msk_i == '0)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 134
EXPRESSION (cnsty_period_msk_i == '0)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 135
EXPRESSION (integ_cnt == '0)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 136
EXPRESSION (cnsty_cnt == '0)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (integ_set_period || integ_set_timeout)
--------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 139
EXPRESSION (cnsty_set_period || cnsty_set_timeout)
--------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 143
EXPRESSION (integ_set_period ? ((lfsr_state & integ_mask)) : (40'(timeout_i)))
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
EXPRESSION (cnsty_set_period ? ((lfsr_state & cnsty_mask)) : (40'(timeout_i)))
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 167
EXPRESSION (((!cnsty_cnt_zero)) && ((!cnsty_cnt_pause)))
---------1--------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T106,T125 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 191
EXPRESSION (set_all_integ_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((integ_chk_req_q & (~integ_chk_ack_i))))
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 193
EXPRESSION (set_all_cnsty_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((cnsty_chk_req_q & (~cnsty_chk_ack_i))))
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 201
EXPRESSION ((integ_chk_trig_q & ((~clr_integ_chk_trig))) | integ_chk_trig_i)
----------------------1--------------------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Not Covered | |
LINE 201
SUB-EXPRESSION (integ_chk_trig_q & ((~clr_integ_chk_trig)))
--------1------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Not Covered | |
LINE 202
EXPRESSION ((cnsty_chk_trig_q & ((~clr_cnsty_chk_trig))) | cnsty_chk_trig_i)
----------------------1--------------------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T5,T11 |
| 1 | 0 | Covered | T5,T12,T18 |
LINE 202
SUB-EXPRESSION (cnsty_chk_trig_q & ((~clr_cnsty_chk_trig)))
--------1------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T5,T11 |
| 1 | 1 | Covered | T5,T12,T18 |
LINE 262
EXPRESSION (cnsty_chk_trig_q || integ_chk_trig_q)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T5,T11 |
LINE 283
EXPRESSION ((((!integ_msk_zero)) && integ_cnt_zero) || integ_chk_trig_q)
-------------------1------------------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T4,T93,T91 |
LINE 283
SUB-EXPRESSION (((!integ_msk_zero)) && integ_cnt_zero)
---------1--------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T93,T91 |
| 1 | 1 | Covered | T4,T93,T91 |
LINE 288
EXPRESSION ((((!cnsty_msk_zero)) && cnsty_cnt_zero) || cnsty_chk_trig_q)
-------------------1------------------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T5,T11 |
| 1 | 0 | Covered | T4,T93,T91 |
LINE 288
SUB-EXPRESSION (((!cnsty_msk_zero)) && cnsty_cnt_zero)
---------1--------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T93,T91 |
| 1 | 1 | Covered | T4,T93,T91 |
LINE 301
EXPRESSION (((!timeout_zero)) && integ_cnt_zero)
--------1-------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T13,T93 |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Covered | T4,T93,T61 |
LINE 304
EXPRESSION (integ_chk_req_q == '0)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T2,T4,T5 |
LINE 323
EXPRESSION (((!timeout_zero)) && cnsty_cnt_zero)
--------1-------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T4,T11 |
| 1 | 0 | Covered | T5,T11,T12 |
| 1 | 1 | Covered | T13,T90,T91 |
LINE 326
EXPRESSION (cnsty_chk_req_q == '0)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T2,T4,T5 |
FSM Coverage for Module :
otp_ctrl_lfsr_timer
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
5 |
5 |
100.00 |
(Not included in score) |
| Transitions |
9 |
9 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| CnstyWaitSt |
289 |
Covered |
T2,T4,T5 |
| ErrorSt |
302 |
Covered |
T4,T12,T13 |
| IdleSt |
275 |
Covered |
T1,T2,T3 |
| IntegWaitSt |
284 |
Covered |
T2,T4,T5 |
| ResetSt |
273 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| CnstyWaitSt->ErrorSt |
324 |
Covered |
T13,T90,T91 |
| CnstyWaitSt->IdleSt |
327 |
Covered |
T2,T4,T5 |
| IdleSt->CnstyWaitSt |
289 |
Covered |
T2,T4,T5 |
| IdleSt->ErrorSt |
358 |
Covered |
T12,T110,T185 |
| IdleSt->IntegWaitSt |
284 |
Covered |
T2,T4,T5 |
| IntegWaitSt->ErrorSt |
302 |
Covered |
T4,T93,T61 |
| IntegWaitSt->IdleSt |
305 |
Covered |
T2,T4,T5 |
| ResetSt->ErrorSt |
358 |
Covered |
T113,T119,T250 |
| ResetSt->IdleSt |
275 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
otp_ctrl_lfsr_timer
| Line No. | Total | Covered | Percent |
| Branches |
|
34 |
31 |
91.18 |
| TERNARY |
72 |
4 |
2 |
50.00 |
| TERNARY |
87 |
2 |
1 |
50.00 |
| TERNARY |
143 |
2 |
2 |
100.00 |
| TERNARY |
144 |
2 |
2 |
100.00 |
| TERNARY |
191 |
2 |
2 |
100.00 |
| TERNARY |
193 |
2 |
2 |
100.00 |
| CASE |
269 |
14 |
14 |
100.00 |
| IF |
356 |
2 |
2 |
100.00 |
| IF |
367 |
2 |
2 |
100.00 |
| IF |
370 |
2 |
2 |
100.00 |
72 assign reseed_cnt_d = (reseed_en) ? '0 :
-1-
==>
73 (edn_req_o) ? reseed_cnt_q :
-2-
==>
74 (lfsr_en) ? reseed_cnt_q + 1'b1 :
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Not Covered |
|
| 0 |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
87 assign entropy = (reseed_en) ? edn_data_i[LfsrWidth-1:0] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Covered |
T1,T2,T3 |
143 assign integ_cnt_set_val = (integ_set_period) ? (lfsr_state & integ_mask) : LfsrWidth'(timeout_i);
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
144 assign cnsty_cnt_set_val = (cnsty_set_period) ? (lfsr_state & cnsty_mask) : LfsrWidth'(timeout_i);
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
191 assign integ_chk_req_d = (set_all_integ_reqs) ? {NumPart{1'b1}} :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
193 assign cnsty_chk_req_d = (set_all_cnsty_reqs) ? {NumPart{1'b1}} :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
269 unique case (state_q)
-1-
270 ///////////////////////////////////////////////////////////////////
271 // Wait until enabled. We never return to this state
272 // once enabled!
273 ResetSt: begin
274 if (timer_en_i) begin
-2-
275 state_d = IdleSt;
==>
276 lfsr_en = 1'b1;
277 end
MISSING_ELSE
==>
278 end
279 ///////////////////////////////////////////////////////////////////
280 // Wait here until one of the two timers expires (if enabled) or if
281 // a check is triggered externally.
282 IdleSt: begin
283 if ((!integ_msk_zero && integ_cnt_zero) || integ_chk_trig_q) begin
-3-
284 state_d = IntegWaitSt;
==>
285 integ_set_timeout = 1'b1;
286 set_all_integ_reqs = 1'b1;
287 clr_integ_chk_trig = integ_chk_trig_q;
288 end else if ((!cnsty_msk_zero && cnsty_cnt_zero) || cnsty_chk_trig_q) begin
-4-
289 state_d = CnstyWaitSt;
==>
290 cnsty_set_timeout = 1'b1;
291 set_all_cnsty_reqs = 1'b1;
292 clr_cnsty_chk_trig = cnsty_chk_trig_q;
293 end
MISSING_ELSE
==>
294 end
295 ///////////////////////////////////////////////////////////////////
296 // Wait for all the partitions to respond and go back to idle.
297 // If the timeout is enabled, bail out into terminal error state
298 // if the timeout counter expires (this will raise an alert).
299 IntegWaitSt: begin
300 chk_pending_o = 1'b1;
301 if (!timeout_zero && integ_cnt_zero) begin
-5-
302 state_d = ErrorSt;
==>
303 chk_timeout_d = 1'b1;
304 end else if (integ_chk_req_q == '0) begin
-6-
305 state_d = IdleSt;
==>
306 // This draws the next wait period.
307 integ_set_period = 1'b1;
308 lfsr_en = 1'b1;
309 end
MISSING_ELSE
==>
310 end
311 ///////////////////////////////////////////////////////////////////
312 // Wait for all the partitions to respond and go back to idle.
313 // If the timeout is enabled, bail out into terminal error state
314 // if the timeout counter expires (this will raise an alert).
315 CnstyWaitSt: begin
316 chk_pending_o = 1'b1;
317 // Note that consistency checks go back and read from OTP. Hence,
318 // life cycle transitions and DAI programming operations
319 // may interfere with these checks and cause them to take longer
320 // than typically expected. Therefore, the timeout counter is stopped
321 // during programming operations.
322 cnsty_cnt_pause = otp_prog_busy_i;
323 if (!timeout_zero && cnsty_cnt_zero) begin
-7-
324 state_d = ErrorSt;
==>
325 chk_timeout_d = 1'b1;
326 end else if (cnsty_chk_req_q == '0) begin
-8-
327 state_d = IdleSt;
==>
328 // This draws the next wait period.
329 cnsty_set_period = 1'b1;
330 lfsr_en = 1'b1;
331 end
MISSING_ELSE
==>
332 end
333 ///////////////////////////////////////////////////////////////////
334 // Terminal error state. This raises an alert.
335 ErrorSt: begin
336 // Continuously clear pending checks.
337 clr_integ_chk_trig = 1'b1;
338 clr_cnsty_chk_trig = 1'b1;
339 if (!chk_timeout_q) begin
-9-
340 fsm_err_o = 1'b1;
==>
341 end
MISSING_ELSE
==>
342 end
343 ///////////////////////////////////////////////////////////////////
344 // This should never happen, hence we directly jump into the
345 // error state, where an alert will be triggered.
346 default: begin
347 state_d = ErrorSt;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | Status | Tests |
| ResetSt |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| IdleSt |
- |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| IdleSt |
- |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IntegWaitSt |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T4,T93,T61 |
| IntegWaitSt |
- |
- |
- |
0 |
1 |
- |
- |
- |
Covered |
T2,T4,T5 |
| IntegWaitSt |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T2,T4,T5 |
| CnstyWaitSt |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T13,T90,T91 |
| CnstyWaitSt |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T2,T4,T5 |
| CnstyWaitSt |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T2,T4,T5 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T12,T110,T185 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T4,T13,T93 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T23,T24,T25 |
356 if (lfsr_err || integ_cnt_err || cnsty_cnt_err ||
-1-
357 lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
358 state_d = ErrorSt;
==>
359 fsm_err_o = 1'b1;
360 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T12,T110,T185 |
| 0 |
Covered |
T1,T2,T3 |
367 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
370 if (!rst_ni) begin
-1-
371 integ_chk_req_q <= '0;
==>
372 cnsty_chk_req_q <= '0;
373 chk_timeout_q <= 1'b0;
374 reseed_cnt_q <= '0;
375 integ_chk_trig_q <= 1'b0;
376 cnsty_chk_trig_q <= 1'b0;
377 end else begin
378 integ_chk_req_q <= integ_chk_req_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
otp_ctrl_lfsr_timer
Assertion Details
ChkPendingKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ChkTimeoutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
CnstyChkReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
EdnIsWideEnough_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
EdnReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
IntegChkReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 91 | 91 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 190 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 243 | 1 | 1 | 100.00 |
| ALWAYS | 246 | 52 | 52 | 100.00 |
| ALWAYS | 367 | 3 | 3 | 100.00 |
| ALWAYS | 370 | 13 | 13 | 100.00 |
71 logic [$clog2(LfsrUsageThreshold+1)-1:0] reseed_cnt_d, reseed_cnt_q;
72 1/1 assign reseed_cnt_d = (reseed_en) ? '0 :
Tests: T1 T2 T3
73 (edn_req_o) ? reseed_cnt_q :
74 (lfsr_en) ? reseed_cnt_q + 1'b1 :
75 reseed_cnt_q;
76
77 1/1 assign edn_req_o = (reseed_cnt_q >= LfsrUsageThreshold);
Tests: T1 T2 T3
78 1/1 assign reseed_en = edn_req_o & edn_ack_i;
Tests: T1 T2 T3
79
80 ///////////////////////////
81 // Tandem LFSR Instances //
82 ///////////////////////////
83
84 logic lfsr_err;
85 logic [LfsrWidth-1:0] entropy;
86 logic [LfsrWidth-1:0] lfsr_state;
87 1/1 assign entropy = (reseed_en) ? edn_data_i[LfsrWidth-1:0] : '0;
Tests: T1 T2 T3
88
89 // We employ two redundant LFSRs to guard against FI attacks.
90 // If any of the two is glitched and the two LFSR states do not agree,
91 // the FSM below is moved into a terminal error state.
92 // SEC_CM: TIMER.LFSR.REDUN
93 prim_double_lfsr #(
94 .LfsrDw ( LfsrWidth ),
95 .EntropyDw ( LfsrWidth ),
96 .StateOutDw ( LfsrWidth ),
97 .DefaultSeed ( RndCnstLfsrSeed ),
98 .StatePermEn ( 1'b1 ),
99 .StatePerm ( RndCnstLfsrPerm ),
100 .ExtSeedSVA ( 1'b0 )
101 ) u_prim_double_lfsr (
102 .clk_i,
103 .rst_ni,
104 .seed_en_i ( 1'b0 ),
105 .seed_i ( '0 ),
106 .lfsr_en_i ( reseed_en || lfsr_en ),
107 .entropy_i ( entropy ),
108 .state_o ( lfsr_state ),
109 .err_o ( lfsr_err )
110 );
111
112 // Not all entropy bits are used.
113 logic unused_seed;
114 1/1 assign unused_seed = ^edn_data_i;
Tests: T1 T2 T3
115
116 `ASSERT_INIT(EdnIsWideEnough_A, EdnDataWidth >= LfsrWidth)
117
118 //////////////////////////////
119 // Tandem Counter Instances //
120 //////////////////////////////
121
122 // We employ redundant counters to guard against FI attacks.
123 // If any of them is glitched and the redundant counter states do not agree,
124 // the FSM below is moved into a terminal error state.
125 logic [LfsrWidth-1:0] integ_cnt, cnsty_cnt, integ_cnt_set_val, cnsty_cnt_set_val;
126 logic [LfsrWidth-1:0] integ_mask, cnsty_mask;
127 logic integ_set_period, integ_set_timeout, integ_cnt_zero;
128 logic cnsty_set_period, cnsty_set_timeout, cnsty_cnt_zero;
129 logic integ_cnt_set, cnsty_cnt_set, integ_cnt_err, cnsty_cnt_err;
130 logic timeout_zero, integ_msk_zero, cnsty_msk_zero, cnsty_cnt_pause;
131
132 1/1 assign timeout_zero = (timeout_i == '0);
Tests: T1 T2 T3
133 1/1 assign integ_msk_zero = (integ_period_msk_i == '0);
Tests: T1 T2 T3
134 1/1 assign cnsty_msk_zero = (cnsty_period_msk_i == '0);
Tests: T1 T2 T3
135 1/1 assign integ_cnt_zero = (integ_cnt == '0);
Tests: T1 T2 T3
136 1/1 assign cnsty_cnt_zero = (cnsty_cnt == '0);
Tests: T1 T2 T3
137
138 1/1 assign integ_cnt_set = integ_set_period || integ_set_timeout;
Tests: T1 T2 T3
139 1/1 assign cnsty_cnt_set = cnsty_set_period || cnsty_set_timeout;
Tests: T1 T2 T3
140
141 1/1 assign integ_mask = {integ_period_msk_i, {LfsrWidth-32{1'b1}}};
Tests: T1 T2 T3
142 1/1 assign cnsty_mask = {cnsty_period_msk_i, {LfsrWidth-32{1'b1}}};
Tests: T1 T2 T3
143 1/1 assign integ_cnt_set_val = (integ_set_period) ? (lfsr_state & integ_mask) : LfsrWidth'(timeout_i);
Tests: T1 T2 T3
144 1/1 assign cnsty_cnt_set_val = (cnsty_set_period) ? (lfsr_state & cnsty_mask) : LfsrWidth'(timeout_i);
Tests: T1 T2 T3
145
146 // SEC_CM: TIMER_INTEG.CTR.REDUN
147 prim_count #(
148 .Width(LfsrWidth)
149 ) u_prim_count_integ (
150 .clk_i,
151 .rst_ni,
152 .clr_i(1'b0),
153 .set_i(integ_cnt_set),
154 .set_cnt_i(integ_cnt_set_val),
155 .incr_en_i(1'b0),
156 .decr_en_i(!integ_cnt_zero),
157 .step_i(LfsrWidth'(1)),
158 .commit_i(1'b1),
159 .cnt_o(integ_cnt),
160 .cnt_after_commit_o(),
161 .err_o(integ_cnt_err)
162 );
163
164 // SEC_CM: TIMER_CNSTY.CTR.REDUN
165 prim_count #(
166 .Width(LfsrWidth)
167 ) u_prim_count_cnsty (
168 .clk_i,
169 .rst_ni,
170 .clr_i(1'b0),
171 .set_i(cnsty_cnt_set),
172 .set_cnt_i(cnsty_cnt_set_val),
173 .incr_en_i(1'b0),
174 .decr_en_i(!cnsty_cnt_zero && !cnsty_cnt_pause),
175 .step_i(LfsrWidth'(1)),
176 .commit_i(1'b1),
177 .cnt_o(cnsty_cnt),
178 .cnt_after_commit_o(),
179 .err_o(cnsty_cnt_err)
180 );
181
182 /////////////////////
183 // Request signals //
184 /////////////////////
185
186 logic set_all_integ_reqs, set_all_cnsty_reqs;
187 logic [NumPart-1:0] integ_chk_req_d, integ_chk_req_q;
188 logic [NumPart-1:0] cnsty_chk_req_d, cnsty_chk_req_q;
189 1/1 assign integ_chk_req_o = integ_chk_req_q;
Tests: T1 T2 T3
190 1/1 assign cnsty_chk_req_o = cnsty_chk_req_q;
Tests: T1 T2 T3
191 1/1 assign integ_chk_req_d = (set_all_integ_reqs) ? {NumPart{1'b1}} :
Tests: T1 T2 T3
192 integ_chk_req_q & ~integ_chk_ack_i;
193 1/1 assign cnsty_chk_req_d = (set_all_cnsty_reqs) ? {NumPart{1'b1}} :
Tests: T1 T2 T3
194 cnsty_chk_req_q & ~cnsty_chk_ack_i;
195
196
197 // external triggers
198 logic clr_integ_chk_trig, clr_cnsty_chk_trig;
199 logic integ_chk_trig_d, integ_chk_trig_q;
200 logic cnsty_chk_trig_d, cnsty_chk_trig_q;
201 1/1 assign integ_chk_trig_d = (integ_chk_trig_q & ~clr_integ_chk_trig) | integ_chk_trig_i;
Tests: T1 T2 T3
202 1/1 assign cnsty_chk_trig_d = (cnsty_chk_trig_q & ~clr_cnsty_chk_trig) | cnsty_chk_trig_i;
Tests: T1 T2 T3
203
204 ////////////////////////////
205 // Ping and Timeout Logic //
206 ////////////////////////////
207
208 // SEC_CM: TIMER.FSM.SPARSE
209 // Encoding generated with:
210 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \
211 // -s 628816752 --language=sv
212 //
213 // Hamming distance histogram:
214 //
215 // 0: --
216 // 1: --
217 // 2: --
218 // 3: --
219 // 4: --
220 // 5: |||||||||||||||||||| (60.00%)
221 // 6: ||||||||||||| (40.00%)
222 // 7: --
223 // 8: --
224 // 9: --
225 //
226 // Minimum Hamming distance: 5
227 // Maximum Hamming distance: 6
228 // Minimum Hamming weight: 4
229 // Maximum Hamming weight: 6
230 //
231 localparam int StateWidth = 9;
232 typedef enum logic [StateWidth-1:0] {
233 ResetSt = 9'b100100101,
234 IdleSt = 9'b001101110,
235 IntegWaitSt = 9'b010110011,
236 CnstyWaitSt = 9'b111010110,
237 ErrorSt = 9'b001011001
238 } state_e;
239
240 state_e state_d, state_q;
241 logic chk_timeout_d, chk_timeout_q;
242
243 1/1 assign chk_timeout_o = chk_timeout_q;
Tests: T1 T2 T3
244
245 always_comb begin : p_fsm
246 1/1 state_d = state_q;
Tests: T1 T2 T3
247
248 // LFSR and counter signals
249 1/1 lfsr_en = 1'b0;
Tests: T1 T2 T3
250 1/1 integ_set_period = 1'b0;
Tests: T1 T2 T3
251 1/1 cnsty_set_period = 1'b0;
Tests: T1 T2 T3
252 1/1 integ_set_timeout = 1'b0;
Tests: T1 T2 T3
253 1/1 cnsty_set_timeout = 1'b0;
Tests: T1 T2 T3
254 1/1 cnsty_cnt_pause = 1'b0;
Tests: T1 T2 T3
255
256 // Requests going to partitions.
257 1/1 set_all_integ_reqs = '0;
Tests: T1 T2 T3
258 1/1 set_all_cnsty_reqs = '0;
Tests: T1 T2 T3
259
260 // Status signals going to CSRs and error logic.
261 1/1 chk_timeout_d = chk_timeout_q;
Tests: T1 T2 T3
262 1/1 chk_pending_o = cnsty_chk_trig_q || integ_chk_trig_q;
Tests: T1 T2 T3
263 1/1 fsm_err_o = 1'b0;
Tests: T1 T2 T3
264
265 // Clear signals for external triggers
266 1/1 clr_integ_chk_trig = 1'b0;
Tests: T1 T2 T3
267 1/1 clr_cnsty_chk_trig = 1'b0;
Tests: T1 T2 T3
268
269 1/1 unique case (state_q)
Tests: T1 T2 T3
270 ///////////////////////////////////////////////////////////////////
271 // Wait until enabled. We never return to this state
272 // once enabled!
273 ResetSt: begin
274 1/1 if (timer_en_i) begin
Tests: T1 T2 T3
275 1/1 state_d = IdleSt;
Tests: T1 T2 T3
276 1/1 lfsr_en = 1'b1;
Tests: T1 T2 T3
277 end
MISSING_ELSE
278 end
279 ///////////////////////////////////////////////////////////////////
280 // Wait here until one of the two timers expires (if enabled) or if
281 // a check is triggered externally.
282 IdleSt: begin
283 1/1 if ((!integ_msk_zero && integ_cnt_zero) || integ_chk_trig_q) begin
Tests: T1 T2 T3
284 1/1 state_d = IntegWaitSt;
Tests: T2 T4 T5
285 1/1 integ_set_timeout = 1'b1;
Tests: T2 T4 T5
286 1/1 set_all_integ_reqs = 1'b1;
Tests: T2 T4 T5
287 1/1 clr_integ_chk_trig = integ_chk_trig_q;
Tests: T2 T4 T5
288 1/1 end else if ((!cnsty_msk_zero && cnsty_cnt_zero) || cnsty_chk_trig_q) begin
Tests: T1 T2 T3
289 1/1 state_d = CnstyWaitSt;
Tests: T2 T4 T5
290 1/1 cnsty_set_timeout = 1'b1;
Tests: T2 T4 T5
291 1/1 set_all_cnsty_reqs = 1'b1;
Tests: T2 T4 T5
292 1/1 clr_cnsty_chk_trig = cnsty_chk_trig_q;
Tests: T2 T4 T5
293 end
MISSING_ELSE
294 end
295 ///////////////////////////////////////////////////////////////////
296 // Wait for all the partitions to respond and go back to idle.
297 // If the timeout is enabled, bail out into terminal error state
298 // if the timeout counter expires (this will raise an alert).
299 IntegWaitSt: begin
300 1/1 chk_pending_o = 1'b1;
Tests: T2 T4 T5
301 1/1 if (!timeout_zero && integ_cnt_zero) begin
Tests: T2 T4 T5
302 1/1 state_d = ErrorSt;
Tests: T4 T93 T61
303 1/1 chk_timeout_d = 1'b1;
Tests: T4 T93 T61
304 1/1 end else if (integ_chk_req_q == '0) begin
Tests: T2 T4 T5
305 1/1 state_d = IdleSt;
Tests: T2 T4 T5
306 // This draws the next wait period.
307 1/1 integ_set_period = 1'b1;
Tests: T2 T4 T5
308 1/1 lfsr_en = 1'b1;
Tests: T2 T4 T5
309 end
MISSING_ELSE
310 end
311 ///////////////////////////////////////////////////////////////////
312 // Wait for all the partitions to respond and go back to idle.
313 // If the timeout is enabled, bail out into terminal error state
314 // if the timeout counter expires (this will raise an alert).
315 CnstyWaitSt: begin
316 1/1 chk_pending_o = 1'b1;
Tests: T2 T4 T5
317 // Note that consistency checks go back and read from OTP. Hence,
318 // life cycle transitions and DAI programming operations
319 // may interfere with these checks and cause them to take longer
320 // than typically expected. Therefore, the timeout counter is stopped
321 // during programming operations.
322 1/1 cnsty_cnt_pause = otp_prog_busy_i;
Tests: T2 T4 T5
323 1/1 if (!timeout_zero && cnsty_cnt_zero) begin
Tests: T2 T4 T5
324 1/1 state_d = ErrorSt;
Tests: T13 T90 T91
325 1/1 chk_timeout_d = 1'b1;
Tests: T13 T90 T91
326 1/1 end else if (cnsty_chk_req_q == '0) begin
Tests: T2 T4 T5
327 1/1 state_d = IdleSt;
Tests: T2 T4 T5
328 // This draws the next wait period.
329 1/1 cnsty_set_period = 1'b1;
Tests: T2 T4 T5
330 1/1 lfsr_en = 1'b1;
Tests: T2 T4 T5
331 end
MISSING_ELSE
332 end
333 ///////////////////////////////////////////////////////////////////
334 // Terminal error state. This raises an alert.
335 ErrorSt: begin
336 // Continuously clear pending checks.
337 1/1 clr_integ_chk_trig = 1'b1;
Tests: T4 T12 T13
338 1/1 clr_cnsty_chk_trig = 1'b1;
Tests: T4 T12 T13
339 1/1 if (!chk_timeout_q) begin
Tests: T4 T12 T13
340 1/1 fsm_err_o = 1'b1;
Tests: T12 T110 T185
341 end
MISSING_ELSE
342 end
343 ///////////////////////////////////////////////////////////////////
344 // This should never happen, hence we directly jump into the
345 // error state, where an alert will be triggered.
346 default: begin
347 state_d = ErrorSt;
348 fsm_err_o = 1'b1;
349 end
350 ///////////////////////////////////////////////////////////////////
351 endcase // state_q
352
353 // Unconditionally jump into the terminal error state in case of escalation,
354 // or if the two LFSR or counter states do not agree.
355 // SEC_CM: TIMER.FSM.LOCAL_ESC, TIMER.FSM.GLOBAL_ESC
356 1/1 if (lfsr_err || integ_cnt_err || cnsty_cnt_err ||
Tests: T1 T2 T3
357 lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
358 1/1 state_d = ErrorSt;
Tests: T12 T110 T185
359 1/1 fsm_err_o = 1'b1;
Tests: T12 T110 T185
360 end
MISSING_ELSE
361 end
362
363 ///////////////
364 // Registers //
365 ///////////////
366
367 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
367.1 `ifdef SIMULATION
367.2 prim_sparse_fsm_flop #(
367.3 .StateEnumT(state_e),
367.4 .Width($bits(state_e)),
367.5 .ResetValue($bits(state_e)'(ResetSt)),
367.6 .EnableAlertTriggerSVA(1),
367.7 .CustomForceName("state_q")
367.8 ) u_state_regs (
367.9 .clk_i ( clk_i ),
367.10 .rst_ni ( rst_ni ),
367.11 .state_i ( state_d ),
367.12 .state_o ( )
367.13 );
367.14 always_ff @(posedge clk_i or negedge rst_ni) begin
367.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
367.16 1/1 state_q <= ResetSt;
Tests: T1 T2 T3
367.17 end else begin
367.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
367.19 end
367.20 end
367.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
367.22 else begin
367.23 `ifdef UVM
367.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
367.25 "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv", 367, "", 1);
367.26 `else
367.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
367.28 `PRIM_STRINGIFY(u_state_regs_A));
367.29 `endif
367.30 end
367.31 `else
367.32 prim_sparse_fsm_flop #(
367.33 .StateEnumT(state_e),
367.34 .Width($bits(state_e)),
367.35 .ResetValue($bits(state_e)'(ResetSt)),
367.36 .EnableAlertTriggerSVA(1)
367.37 ) u_state_regs (
367.38 .clk_i ( `PRIM_FLOP_CLK ),
367.39 .rst_ni ( `PRIM_FLOP_RST ),
367.40 .state_i ( state_d ),
367.41 .state_o ( state_q )
367.42 );
367.43 `endif368
369 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
370 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
371 1/1 integ_chk_req_q <= '0;
Tests: T1 T2 T3
372 1/1 cnsty_chk_req_q <= '0;
Tests: T1 T2 T3
373 1/1 chk_timeout_q <= 1'b0;
Tests: T1 T2 T3
374 1/1 reseed_cnt_q <= '0;
Tests: T1 T2 T3
375 1/1 integ_chk_trig_q <= 1'b0;
Tests: T1 T2 T3
376 1/1 cnsty_chk_trig_q <= 1'b0;
Tests: T1 T2 T3
377 end else begin
378 1/1 integ_chk_req_q <= integ_chk_req_d;
Tests: T1 T2 T3
379 1/1 cnsty_chk_req_q <= cnsty_chk_req_d;
Tests: T1 T2 T3
380 1/1 chk_timeout_q <= chk_timeout_d;
Tests: T1 T2 T3
381 1/1 reseed_cnt_q <= reseed_cnt_d;
Tests: T1 T2 T3
382 1/1 integ_chk_trig_q <= integ_chk_trig_d;
Tests: T1 T2 T3
383 1/1 cnsty_chk_trig_q <= cnsty_chk_trig_d;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer
| Total | Covered | Percent |
|---|
| Conditions | 77 | 69 | 89.61 |
| Logical | 77 | 69 | 89.61 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 72
EXPRESSION (reseed_en ? '0 : (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 72
SUB-EXPRESSION (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 72
SUB-EXPRESSION (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (edn_req_o & edn_ack_i)
----1---- ----2----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 87
EXPRESSION (reseed_en ? edn_data_i[(otp_ctrl_pkg::LfsrWidth - 1):0] : '0)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 101
EXPRESSION (reseed_en || lfsr_en)
----1---- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
LINE 132
EXPRESSION (timeout_i == '0)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 133
EXPRESSION (integ_period_msk_i == '0)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 134
EXPRESSION (cnsty_period_msk_i == '0)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 135
EXPRESSION (integ_cnt == '0)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 136
EXPRESSION (cnsty_cnt == '0)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (integ_set_period || integ_set_timeout)
--------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 139
EXPRESSION (cnsty_set_period || cnsty_set_timeout)
--------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 143
EXPRESSION (integ_set_period ? ((lfsr_state & integ_mask)) : (40'(timeout_i)))
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
EXPRESSION (cnsty_set_period ? ((lfsr_state & cnsty_mask)) : (40'(timeout_i)))
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 167
EXPRESSION (((!cnsty_cnt_zero)) && ((!cnsty_cnt_pause)))
---------1--------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T106,T125 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 191
EXPRESSION (set_all_integ_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((integ_chk_req_q & (~integ_chk_ack_i))))
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 193
EXPRESSION (set_all_cnsty_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((cnsty_chk_req_q & (~cnsty_chk_ack_i))))
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 201
EXPRESSION ((integ_chk_trig_q & ((~clr_integ_chk_trig))) | integ_chk_trig_i)
----------------------1--------------------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Not Covered | |
LINE 201
SUB-EXPRESSION (integ_chk_trig_q & ((~clr_integ_chk_trig)))
--------1------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Not Covered | |
LINE 202
EXPRESSION ((cnsty_chk_trig_q & ((~clr_cnsty_chk_trig))) | cnsty_chk_trig_i)
----------------------1--------------------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T5,T11 |
| 1 | 0 | Covered | T5,T12,T18 |
LINE 202
SUB-EXPRESSION (cnsty_chk_trig_q & ((~clr_cnsty_chk_trig)))
--------1------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T5,T11 |
| 1 | 1 | Covered | T5,T12,T18 |
LINE 262
EXPRESSION (cnsty_chk_trig_q || integ_chk_trig_q)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T5,T11 |
LINE 283
EXPRESSION ((((!integ_msk_zero)) && integ_cnt_zero) || integ_chk_trig_q)
-------------------1------------------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T4,T93,T91 |
LINE 283
SUB-EXPRESSION (((!integ_msk_zero)) && integ_cnt_zero)
---------1--------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T93,T91 |
| 1 | 1 | Covered | T4,T93,T91 |
LINE 288
EXPRESSION ((((!cnsty_msk_zero)) && cnsty_cnt_zero) || cnsty_chk_trig_q)
-------------------1------------------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T5,T11 |
| 1 | 0 | Covered | T4,T93,T91 |
LINE 288
SUB-EXPRESSION (((!cnsty_msk_zero)) && cnsty_cnt_zero)
---------1--------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T93,T91 |
| 1 | 1 | Covered | T4,T93,T91 |
LINE 301
EXPRESSION (((!timeout_zero)) && integ_cnt_zero)
--------1-------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T13,T93 |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Covered | T4,T93,T61 |
LINE 304
EXPRESSION (integ_chk_req_q == '0)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T2,T4,T5 |
LINE 323
EXPRESSION (((!timeout_zero)) && cnsty_cnt_zero)
--------1-------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T4,T11 |
| 1 | 0 | Covered | T5,T11,T12 |
| 1 | 1 | Covered | T13,T90,T91 |
LINE 326
EXPRESSION (cnsty_chk_req_q == '0)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T2,T4,T5 |
FSM Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
5 |
5 |
100.00 |
(Not included in score) |
| Transitions |
9 |
9 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| CnstyWaitSt |
289 |
Covered |
T2,T4,T5 |
| ErrorSt |
302 |
Covered |
T4,T12,T13 |
| IdleSt |
275 |
Covered |
T1,T2,T3 |
| IntegWaitSt |
284 |
Covered |
T2,T4,T5 |
| ResetSt |
273 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| CnstyWaitSt->ErrorSt |
324 |
Covered |
T13,T90,T91 |
| CnstyWaitSt->IdleSt |
327 |
Covered |
T2,T4,T5 |
| IdleSt->CnstyWaitSt |
289 |
Covered |
T2,T4,T5 |
| IdleSt->ErrorSt |
358 |
Covered |
T12,T110,T185 |
| IdleSt->IntegWaitSt |
284 |
Covered |
T2,T4,T5 |
| IntegWaitSt->ErrorSt |
302 |
Covered |
T4,T93,T61 |
| IntegWaitSt->IdleSt |
305 |
Covered |
T2,T4,T5 |
| ResetSt->ErrorSt |
358 |
Covered |
T113,T119,T250 |
| ResetSt->IdleSt |
275 |
Covered |
T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer
| Line No. | Total | Covered | Percent |
| Branches |
|
34 |
31 |
91.18 |
| TERNARY |
72 |
4 |
2 |
50.00 |
| TERNARY |
87 |
2 |
1 |
50.00 |
| TERNARY |
143 |
2 |
2 |
100.00 |
| TERNARY |
144 |
2 |
2 |
100.00 |
| TERNARY |
191 |
2 |
2 |
100.00 |
| TERNARY |
193 |
2 |
2 |
100.00 |
| CASE |
269 |
14 |
14 |
100.00 |
| IF |
356 |
2 |
2 |
100.00 |
| IF |
367 |
2 |
2 |
100.00 |
| IF |
370 |
2 |
2 |
100.00 |
72 assign reseed_cnt_d = (reseed_en) ? '0 :
-1-
==>
73 (edn_req_o) ? reseed_cnt_q :
-2-
==>
74 (lfsr_en) ? reseed_cnt_q + 1'b1 :
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Not Covered |
|
| 0 |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
87 assign entropy = (reseed_en) ? edn_data_i[LfsrWidth-1:0] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Covered |
T1,T2,T3 |
143 assign integ_cnt_set_val = (integ_set_period) ? (lfsr_state & integ_mask) : LfsrWidth'(timeout_i);
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
144 assign cnsty_cnt_set_val = (cnsty_set_period) ? (lfsr_state & cnsty_mask) : LfsrWidth'(timeout_i);
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
191 assign integ_chk_req_d = (set_all_integ_reqs) ? {NumPart{1'b1}} :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
193 assign cnsty_chk_req_d = (set_all_cnsty_reqs) ? {NumPart{1'b1}} :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
269 unique case (state_q)
-1-
270 ///////////////////////////////////////////////////////////////////
271 // Wait until enabled. We never return to this state
272 // once enabled!
273 ResetSt: begin
274 if (timer_en_i) begin
-2-
275 state_d = IdleSt;
==>
276 lfsr_en = 1'b1;
277 end
MISSING_ELSE
==>
278 end
279 ///////////////////////////////////////////////////////////////////
280 // Wait here until one of the two timers expires (if enabled) or if
281 // a check is triggered externally.
282 IdleSt: begin
283 if ((!integ_msk_zero && integ_cnt_zero) || integ_chk_trig_q) begin
-3-
284 state_d = IntegWaitSt;
==>
285 integ_set_timeout = 1'b1;
286 set_all_integ_reqs = 1'b1;
287 clr_integ_chk_trig = integ_chk_trig_q;
288 end else if ((!cnsty_msk_zero && cnsty_cnt_zero) || cnsty_chk_trig_q) begin
-4-
289 state_d = CnstyWaitSt;
==>
290 cnsty_set_timeout = 1'b1;
291 set_all_cnsty_reqs = 1'b1;
292 clr_cnsty_chk_trig = cnsty_chk_trig_q;
293 end
MISSING_ELSE
==>
294 end
295 ///////////////////////////////////////////////////////////////////
296 // Wait for all the partitions to respond and go back to idle.
297 // If the timeout is enabled, bail out into terminal error state
298 // if the timeout counter expires (this will raise an alert).
299 IntegWaitSt: begin
300 chk_pending_o = 1'b1;
301 if (!timeout_zero && integ_cnt_zero) begin
-5-
302 state_d = ErrorSt;
==>
303 chk_timeout_d = 1'b1;
304 end else if (integ_chk_req_q == '0) begin
-6-
305 state_d = IdleSt;
==>
306 // This draws the next wait period.
307 integ_set_period = 1'b1;
308 lfsr_en = 1'b1;
309 end
MISSING_ELSE
==>
310 end
311 ///////////////////////////////////////////////////////////////////
312 // Wait for all the partitions to respond and go back to idle.
313 // If the timeout is enabled, bail out into terminal error state
314 // if the timeout counter expires (this will raise an alert).
315 CnstyWaitSt: begin
316 chk_pending_o = 1'b1;
317 // Note that consistency checks go back and read from OTP. Hence,
318 // life cycle transitions and DAI programming operations
319 // may interfere with these checks and cause them to take longer
320 // than typically expected. Therefore, the timeout counter is stopped
321 // during programming operations.
322 cnsty_cnt_pause = otp_prog_busy_i;
323 if (!timeout_zero && cnsty_cnt_zero) begin
-7-
324 state_d = ErrorSt;
==>
325 chk_timeout_d = 1'b1;
326 end else if (cnsty_chk_req_q == '0) begin
-8-
327 state_d = IdleSt;
==>
328 // This draws the next wait period.
329 cnsty_set_period = 1'b1;
330 lfsr_en = 1'b1;
331 end
MISSING_ELSE
==>
332 end
333 ///////////////////////////////////////////////////////////////////
334 // Terminal error state. This raises an alert.
335 ErrorSt: begin
336 // Continuously clear pending checks.
337 clr_integ_chk_trig = 1'b1;
338 clr_cnsty_chk_trig = 1'b1;
339 if (!chk_timeout_q) begin
-9-
340 fsm_err_o = 1'b1;
==>
341 end
MISSING_ELSE
==>
342 end
343 ///////////////////////////////////////////////////////////////////
344 // This should never happen, hence we directly jump into the
345 // error state, where an alert will be triggered.
346 default: begin
347 state_d = ErrorSt;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | Status | Tests |
| ResetSt |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| IdleSt |
- |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| IdleSt |
- |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IntegWaitSt |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T4,T93,T61 |
| IntegWaitSt |
- |
- |
- |
0 |
1 |
- |
- |
- |
Covered |
T2,T4,T5 |
| IntegWaitSt |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T2,T4,T5 |
| CnstyWaitSt |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T13,T90,T91 |
| CnstyWaitSt |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T2,T4,T5 |
| CnstyWaitSt |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T2,T4,T5 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T12,T110,T185 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T4,T13,T93 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T23,T24,T25 |
356 if (lfsr_err || integ_cnt_err || cnsty_cnt_err ||
-1-
357 lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
358 state_d = ErrorSt;
==>
359 fsm_err_o = 1'b1;
360 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T12,T110,T185 |
| 0 |
Covered |
T1,T2,T3 |
367 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
370 if (!rst_ni) begin
-1-
371 integ_chk_req_q <= '0;
==>
372 cnsty_chk_req_q <= '0;
373 chk_timeout_q <= 1'b0;
374 reseed_cnt_q <= '0;
375 integ_chk_trig_q <= 1'b0;
376 cnsty_chk_trig_q <= 1'b0;
377 end else begin
378 integ_chk_req_q <= integ_chk_req_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer
Assertion Details
ChkPendingKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
ChkTimeoutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
CnstyChkReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
EdnIsWideEnough_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1120 |
1120 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
EdnReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
IntegChkReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
95995079 |
95123308 |
0 |
0 |
| T1 |
6346 |
6266 |
0 |
0 |
| T2 |
20779 |
20387 |
0 |
0 |
| T3 |
16526 |
16188 |
0 |
0 |
| T4 |
41540 |
41124 |
0 |
0 |
| T5 |
24984 |
24368 |
0 |
0 |
| T6 |
30776 |
30706 |
0 |
0 |
| T10 |
44472 |
44397 |
0 |
0 |
| T11 |
20926 |
20462 |
0 |
0 |
| T12 |
41197 |
40991 |
0 |
0 |
| T13 |
73799 |
72549 |
0 |
0 |