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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.70 93.76 96.20 95.67 90.69 97.00 96.28 93.28


Total test records in report: 1293
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T1260 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.2009662212 Aug 29 09:40:07 AM UTC 24 Aug 29 09:40:10 AM UTC 24 145598121 ps
T1261 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.935418277 Aug 29 09:40:07 AM UTC 24 Aug 29 09:40:10 AM UTC 24 557967790 ps
T1262 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.292361071 Aug 29 09:40:07 AM UTC 24 Aug 29 09:40:10 AM UTC 24 146497591 ps
T1263 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.3038057702 Aug 29 09:40:07 AM UTC 24 Aug 29 09:40:10 AM UTC 24 83433824 ps
T1264 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.4194148022 Aug 29 09:40:07 AM UTC 24 Aug 29 09:40:10 AM UTC 24 508287025 ps
T1265 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.4091499290 Aug 29 09:40:07 AM UTC 24 Aug 29 09:40:10 AM UTC 24 44670087 ps
T1266 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.3347452520 Aug 29 09:40:07 AM UTC 24 Aug 29 09:40:10 AM UTC 24 576503185 ps
T1267 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.2177461144 Aug 29 09:40:07 AM UTC 24 Aug 29 09:40:10 AM UTC 24 137069802 ps
T1268 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.990544001 Aug 29 09:40:07 AM UTC 24 Aug 29 09:40:10 AM UTC 24 51021315 ps
T1269 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3418417006 Aug 29 09:40:04 AM UTC 24 Aug 29 09:40:11 AM UTC 24 152657826 ps
T1270 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.947212963 Aug 29 09:40:09 AM UTC 24 Aug 29 09:40:12 AM UTC 24 536559608 ps
T1271 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3446426382 Aug 29 09:40:09 AM UTC 24 Aug 29 09:40:12 AM UTC 24 571128472 ps
T1272 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.2154042135 Aug 29 09:40:09 AM UTC 24 Aug 29 09:40:12 AM UTC 24 38297836 ps
T1273 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.31255485 Aug 29 09:40:09 AM UTC 24 Aug 29 09:40:12 AM UTC 24 67146542 ps
T1274 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.3181211180 Aug 29 09:40:09 AM UTC 24 Aug 29 09:40:12 AM UTC 24 68861416 ps
T1275 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.3425726340 Aug 29 09:40:09 AM UTC 24 Aug 29 09:40:12 AM UTC 24 539851367 ps
T1276 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.2040752337 Aug 29 09:40:09 AM UTC 24 Aug 29 09:40:12 AM UTC 24 39245348 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1524175091 Aug 29 09:39:59 AM UTC 24 Aug 29 09:40:12 AM UTC 24 608405098 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2258363598 Aug 29 09:39:52 AM UTC 24 Aug 29 09:40:12 AM UTC 24 10360032362 ps
T1277 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2304956895 Aug 29 09:40:05 AM UTC 24 Aug 29 09:40:12 AM UTC 24 71987881 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3255481920 Aug 29 09:39:54 AM UTC 24 Aug 29 09:40:12 AM UTC 24 10987505626 ps
T1278 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.3124524926 Aug 29 09:40:11 AM UTC 24 Aug 29 09:40:14 AM UTC 24 549020165 ps
T1279 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.2889452585 Aug 29 09:40:09 AM UTC 24 Aug 29 09:40:12 AM UTC 24 581963514 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2449045723 Aug 29 09:39:51 AM UTC 24 Aug 29 09:40:12 AM UTC 24 2378871537 ps
T1280 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.2002780916 Aug 29 09:40:11 AM UTC 24 Aug 29 09:40:13 AM UTC 24 146272442 ps
T1281 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.303872909 Aug 29 09:40:11 AM UTC 24 Aug 29 09:40:13 AM UTC 24 44746866 ps
T1282 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.556496172 Aug 29 09:40:11 AM UTC 24 Aug 29 09:40:14 AM UTC 24 69580528 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1080636762 Aug 29 09:39:55 AM UTC 24 Aug 29 09:40:14 AM UTC 24 2619419434 ps
T1283 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.2272721437 Aug 29 09:40:11 AM UTC 24 Aug 29 09:40:14 AM UTC 24 57853075 ps
T1284 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.3455467221 Aug 29 09:40:11 AM UTC 24 Aug 29 09:40:14 AM UTC 24 89950426 ps
T1285 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.1841793196 Aug 29 09:40:11 AM UTC 24 Aug 29 09:40:14 AM UTC 24 40057739 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.113308474 Aug 29 09:39:57 AM UTC 24 Aug 29 09:40:14 AM UTC 24 10278640323 ps
T1286 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.422744826 Aug 29 09:40:11 AM UTC 24 Aug 29 09:40:14 AM UTC 24 42438057 ps
T1287 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1936901529 Aug 29 09:40:02 AM UTC 24 Aug 29 09:40:14 AM UTC 24 2604673299 ps
T1288 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3604817008 Aug 29 09:40:11 AM UTC 24 Aug 29 09:40:14 AM UTC 24 535524746 ps
T1289 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.3130910795 Aug 29 09:40:11 AM UTC 24 Aug 29 09:40:15 AM UTC 24 598228728 ps
T1290 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3922718748 Aug 29 09:39:49 AM UTC 24 Aug 29 09:40:16 AM UTC 24 19993423384 ps
T1291 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.738755540 Aug 29 09:40:04 AM UTC 24 Aug 29 09:40:16 AM UTC 24 707894166 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1990098937 Aug 29 09:39:59 AM UTC 24 Aug 29 09:40:18 AM UTC 24 1844262189 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.325326456 Aug 29 09:39:59 AM UTC 24 Aug 29 09:40:21 AM UTC 24 1400634005 ps
T1292 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2733145486 Aug 29 09:40:01 AM UTC 24 Aug 29 09:40:25 AM UTC 24 1481753681 ps
T1293 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1298000226 Aug 29 09:40:05 AM UTC 24 Aug 29 09:40:27 AM UTC 24 2515182510 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2789719823 Aug 29 09:40:04 AM UTC 24 Aug 29 09:40:30 AM UTC 24 4968011472 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.1182396005
Short name T13
Test name
Test status
Simulation time 12300199059 ps
CPU time 15.16 seconds
Started Aug 29 09:17:28 AM UTC 24
Finished Aug 29 09:17:45 AM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182396005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.1182396005
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.1609354384
Short name T109
Test name
Test status
Simulation time 6002189464 ps
CPU time 202.67 seconds
Started Aug 29 09:18:00 AM UTC 24
Finished Aug 29 09:21:26 AM UTC 24
Peak memory 257464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609354384 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.1609354384
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.2804474526
Short name T14
Test name
Test status
Simulation time 24439131170 ps
CPU time 90.29 seconds
Started Aug 29 09:20:30 AM UTC 24
Finished Aug 29 09:22:03 AM UTC 24
Peak memory 268172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2804474526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.otp_ctrl_stress_all_with_rand_reset.2804474526
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.1377759570
Short name T94
Test name
Test status
Simulation time 4767461351 ps
CPU time 182.38 seconds
Started Aug 29 09:20:32 AM UTC 24
Finished Aug 29 09:23:37 AM UTC 24
Peak memory 257500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377759570 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.1377759570
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.327540506
Short name T18
Test name
Test status
Simulation time 2511912016 ps
CPU time 29.23 seconds
Started Aug 29 09:17:46 AM UTC 24
Finished Aug 29 09:18:16 AM UTC 24
Peak memory 257528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327540506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.327540506
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.1398781869
Short name T113
Test name
Test status
Simulation time 4676286094 ps
CPU time 132.79 seconds
Started Aug 29 09:19:31 AM UTC 24
Finished Aug 29 09:21:46 AM UTC 24
Peak memory 269848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398781869 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.1398781869
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.862895592
Short name T97
Test name
Test status
Simulation time 333393144 ps
CPU time 6.48 seconds
Started Aug 29 09:20:01 AM UTC 24
Finished Aug 29 09:20:08 AM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862895592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.862895592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.3770051364
Short name T24
Test name
Test status
Simulation time 14457835288 ps
CPU time 236.48 seconds
Started Aug 29 09:19:35 AM UTC 24
Finished Aug 29 09:23:36 AM UTC 24
Peak memory 296056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770051364 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3770051364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.3657281500
Short name T157
Test name
Test status
Simulation time 5286156548 ps
CPU time 62.94 seconds
Started Aug 29 09:26:00 AM UTC 24
Finished Aug 29 09:27:05 AM UTC 24
Peak memory 257664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657281500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.3657281500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.2552804100
Short name T121
Test name
Test status
Simulation time 21990510816 ps
CPU time 281.55 seconds
Started Aug 29 09:24:49 AM UTC 24
Finished Aug 29 09:29:35 AM UTC 24
Peak memory 273876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552804100 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.2552804100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.3138251020
Short name T35
Test name
Test status
Simulation time 4067835754 ps
CPU time 37.09 seconds
Started Aug 29 09:23:40 AM UTC 24
Finished Aug 29 09:24:18 AM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138251020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.3138251020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.2676978039
Short name T221
Test name
Test status
Simulation time 30699300230 ps
CPU time 207.19 seconds
Started Aug 29 09:22:06 AM UTC 24
Finished Aug 29 09:25:36 AM UTC 24
Peak memory 257500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676978039 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.2676978039
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.3944037668
Short name T1158
Test name
Test status
Simulation time 137761210 ps
CPU time 4.85 seconds
Started Aug 29 09:39:40 AM UTC 24
Finished Aug 29 09:39:47 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944037668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.3944037668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3255481920
Short name T347
Test name
Test status
Simulation time 10987505626 ps
CPU time 17.3 seconds
Started Aug 29 09:39:54 AM UTC 24
Finished Aug 29 09:40:12 AM UTC 24
Peak memory 256988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255481920 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.3255481920
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.446749477
Short name T3
Test name
Test status
Simulation time 289964633 ps
CPU time 6.99 seconds
Started Aug 29 09:17:05 AM UTC 24
Finished Aug 29 09:17:13 AM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446749477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.446749477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.2151158069
Short name T307
Test name
Test status
Simulation time 59823023418 ps
CPU time 162.24 seconds
Started Aug 29 09:31:04 AM UTC 24
Finished Aug 29 09:33:49 AM UTC 24
Peak memory 274092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2151158069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.otp_ctrl_stress_all_with_rand_reset.2151158069
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.610792712
Short name T105
Test name
Test status
Simulation time 8737857427 ps
CPU time 52.63 seconds
Started Aug 29 09:17:35 AM UTC 24
Finished Aug 29 09:18:29 AM UTC 24
Peak memory 253400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610792712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.610792712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.3821179617
Short name T34
Test name
Test status
Simulation time 1567213696 ps
CPU time 27.29 seconds
Started Aug 29 09:29:17 AM UTC 24
Finished Aug 29 09:29:45 AM UTC 24
Peak memory 253656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821179617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.3821179617
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2251823804
Short name T284
Test name
Test status
Simulation time 41988364 ps
CPU time 1.84 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:39:52 AM UTC 24
Peak memory 254020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251823804 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.2251823804
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.2276956786
Short name T22
Test name
Test status
Simulation time 6908843251 ps
CPU time 186.76 seconds
Started Aug 29 09:27:07 AM UTC 24
Finished Aug 29 09:30:17 AM UTC 24
Peak memory 267948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2276956786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.otp_ctrl_stress_all_with_rand_reset.2276956786
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.824538517
Short name T149
Test name
Test status
Simulation time 20480229980 ps
CPU time 221.48 seconds
Started Aug 29 09:27:47 AM UTC 24
Finished Aug 29 09:31:33 AM UTC 24
Peak memory 273940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824538517 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.824538517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.2597653012
Short name T61
Test name
Test status
Simulation time 1320540480 ps
CPU time 19.27 seconds
Started Aug 29 09:20:17 AM UTC 24
Finished Aug 29 09:20:38 AM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597653012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.2597653012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.1079195441
Short name T73
Test name
Test status
Simulation time 2425483020 ps
CPU time 11.96 seconds
Started Aug 29 09:21:30 AM UTC 24
Finished Aug 29 09:21:43 AM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079195441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.1079195441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.173797326
Short name T42
Test name
Test status
Simulation time 136559001 ps
CPU time 5.83 seconds
Started Aug 29 09:37:55 AM UTC 24
Finished Aug 29 09:38:02 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173797326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.173797326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.664362398
Short name T63
Test name
Test status
Simulation time 1959775759 ps
CPU time 9.77 seconds
Started Aug 29 09:27:11 AM UTC 24
Finished Aug 29 09:27:22 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664362398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.664362398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.1846890685
Short name T414
Test name
Test status
Simulation time 4737829924 ps
CPU time 211.56 seconds
Started Aug 29 09:30:31 AM UTC 24
Finished Aug 29 09:34:06 AM UTC 24
Peak memory 268152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1846890685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.otp_ctrl_stress_all_with_rand_reset.1846890685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.2176341723
Short name T93
Test name
Test status
Simulation time 11128419515 ps
CPU time 33.33 seconds
Started Aug 29 09:18:20 AM UTC 24
Finished Aug 29 09:18:55 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176341723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.2176341723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.2686254390
Short name T44
Test name
Test status
Simulation time 128399791 ps
CPU time 5.43 seconds
Started Aug 29 09:27:29 AM UTC 24
Finished Aug 29 09:27:36 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686254390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.2686254390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.1611269257
Short name T153
Test name
Test status
Simulation time 33366015663 ps
CPU time 208.66 seconds
Started Aug 29 09:32:12 AM UTC 24
Finished Aug 29 09:35:45 AM UTC 24
Peak memory 274108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611269257 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.1611269257
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.497631134
Short name T82
Test name
Test status
Simulation time 164475973 ps
CPU time 5.83 seconds
Started Aug 29 09:38:35 AM UTC 24
Finished Aug 29 09:38:42 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497631134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.497631134
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.656298450
Short name T958
Test name
Test status
Simulation time 225723295 ps
CPU time 5.62 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:52 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656298450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.656298450
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.3691165583
Short name T166
Test name
Test status
Simulation time 147390769 ps
CPU time 3.55 seconds
Started Aug 29 09:32:35 AM UTC 24
Finished Aug 29 09:32:39 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691165583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3691165583
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.2921649795
Short name T250
Test name
Test status
Simulation time 839442264 ps
CPU time 17.88 seconds
Started Aug 29 09:24:19 AM UTC 24
Finished Aug 29 09:24:38 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921649795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.2921649795
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.3168622755
Short name T167
Test name
Test status
Simulation time 1568988023 ps
CPU time 6.41 seconds
Started Aug 29 09:24:53 AM UTC 24
Finished Aug 29 09:25:01 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168622755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3168622755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.3430590905
Short name T17
Test name
Test status
Simulation time 75799919 ps
CPU time 3.03 seconds
Started Aug 29 09:18:12 AM UTC 24
Finished Aug 29 09:18:16 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430590905 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.3430590905
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.3052476320
Short name T363
Test name
Test status
Simulation time 1057285844 ps
CPU time 13.83 seconds
Started Aug 29 09:26:46 AM UTC 24
Finished Aug 29 09:27:02 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052476320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.3052476320
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.1122908972
Short name T25
Test name
Test status
Simulation time 9911954435 ps
CPU time 236.19 seconds
Started Aug 29 09:21:18 AM UTC 24
Finished Aug 29 09:25:18 AM UTC 24
Peak memory 298080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122908972 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1122908972
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.1520129489
Short name T142
Test name
Test status
Simulation time 149717696 ps
CPU time 8.84 seconds
Started Aug 29 09:37:00 AM UTC 24
Finished Aug 29 09:37:10 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520129489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.1520129489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.3955681765
Short name T130
Test name
Test status
Simulation time 25950417095 ps
CPU time 297.09 seconds
Started Aug 29 09:29:29 AM UTC 24
Finished Aug 29 09:34:31 AM UTC 24
Peak memory 271808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955681765 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.3955681765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.2838786850
Short name T27
Test name
Test status
Simulation time 2108341589 ps
CPU time 8.19 seconds
Started Aug 29 09:37:49 AM UTC 24
Finished Aug 29 09:37:58 AM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838786850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.2838786850
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.516762308
Short name T162
Test name
Test status
Simulation time 563725208 ps
CPU time 19.14 seconds
Started Aug 29 09:20:56 AM UTC 24
Finished Aug 29 09:21:17 AM UTC 24
Peak memory 253596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516762308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.516762308
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.3916936535
Short name T59
Test name
Test status
Simulation time 2965666577 ps
CPU time 29.23 seconds
Started Aug 29 09:29:56 AM UTC 24
Finished Aug 29 09:30:27 AM UTC 24
Peak memory 257784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916936535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3916936535
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.1141648931
Short name T202
Test name
Test status
Simulation time 3548927783 ps
CPU time 44.67 seconds
Started Aug 29 09:20:58 AM UTC 24
Finished Aug 29 09:21:44 AM UTC 24
Peak memory 257528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141648931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1141648931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.3769259408
Short name T54
Test name
Test status
Simulation time 3221802714 ps
CPU time 14.12 seconds
Started Aug 29 09:34:46 AM UTC 24
Finished Aug 29 09:35:01 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769259408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.3769259408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.3967039943
Short name T136
Test name
Test status
Simulation time 310152770 ps
CPU time 3.65 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:29 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967039943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.3967039943
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2449045723
Short name T351
Test name
Test status
Simulation time 2378871537 ps
CPU time 20.54 seconds
Started Aug 29 09:39:51 AM UTC 24
Finished Aug 29 09:40:12 AM UTC 24
Peak memory 253012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449045723 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.2449045723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.846255056
Short name T129
Test name
Test status
Simulation time 8930322911 ps
CPU time 114.35 seconds
Started Aug 29 09:35:47 AM UTC 24
Finished Aug 29 09:37:43 AM UTC 24
Peak memory 269580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=846255056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
53.otp_ctrl_stress_all_with_rand_reset.846255056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.2164845328
Short name T127
Test name
Test status
Simulation time 190876652 ps
CPU time 9.45 seconds
Started Aug 29 09:36:13 AM UTC 24
Finished Aug 29 09:36:24 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164845328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2164845328
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.587456480
Short name T262
Test name
Test status
Simulation time 166442521 ps
CPU time 4.79 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:51 AM UTC 24
Peak memory 254752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587456480 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.587456480
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.1211935896
Short name T413
Test name
Test status
Simulation time 4572285508 ps
CPU time 119.32 seconds
Started Aug 29 09:31:59 AM UTC 24
Finished Aug 29 09:34:00 AM UTC 24
Peak memory 274068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1211935896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.otp_ctrl_stress_all_with_rand_reset.1211935896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.4005160469
Short name T395
Test name
Test status
Simulation time 185641309849 ps
CPU time 354.41 seconds
Started Aug 29 09:24:31 AM UTC 24
Finished Aug 29 09:30:30 AM UTC 24
Peak memory 284120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005160469 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.4005160469
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.3607130417
Short name T138
Test name
Test status
Simulation time 6145823770 ps
CPU time 128.59 seconds
Started Aug 29 09:32:26 AM UTC 24
Finished Aug 29 09:34:38 AM UTC 24
Peak memory 269996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3607130417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.otp_ctrl_stress_all_with_rand_reset.3607130417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.1607836381
Short name T240
Test name
Test status
Simulation time 2439319670 ps
CPU time 12.93 seconds
Started Aug 29 09:37:50 AM UTC 24
Finished Aug 29 09:38:04 AM UTC 24
Peak memory 253272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607836381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.1607836381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.1915144815
Short name T246
Test name
Test status
Simulation time 182176856 ps
CPU time 12.17 seconds
Started Aug 29 09:38:06 AM UTC 24
Finished Aug 29 09:38:21 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915144815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.1915144815
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.379455630
Short name T95
Test name
Test status
Simulation time 3601501908 ps
CPU time 10.41 seconds
Started Aug 29 09:30:08 AM UTC 24
Finished Aug 29 09:30:20 AM UTC 24
Peak memory 251576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379455630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.379455630
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.562754481
Short name T359
Test name
Test status
Simulation time 493666342 ps
CPU time 9.57 seconds
Started Aug 29 09:25:41 AM UTC 24
Finished Aug 29 09:25:51 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562754481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.562754481
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.833329341
Short name T101
Test name
Test status
Simulation time 2195228963 ps
CPU time 6.16 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:45 AM UTC 24
Peak memory 251552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833329341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.833329341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.2294729597
Short name T96
Test name
Test status
Simulation time 19821722209 ps
CPU time 211.85 seconds
Started Aug 29 09:22:42 AM UTC 24
Finished Aug 29 09:26:17 AM UTC 24
Peak memory 269852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294729597 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.2294729597
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.2460640361
Short name T48
Test name
Test status
Simulation time 586482935 ps
CPU time 17.76 seconds
Started Aug 29 09:24:22 AM UTC 24
Finished Aug 29 09:24:41 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460640361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2460640361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.2393895181
Short name T259
Test name
Test status
Simulation time 636917283 ps
CPU time 10.17 seconds
Started Aug 29 09:39:52 AM UTC 24
Finished Aug 29 09:40:04 AM UTC 24
Peak memory 252784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393895181 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.2393895181
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.2072312464
Short name T319
Test name
Test status
Simulation time 7176241906 ps
CPU time 86.58 seconds
Started Aug 29 09:27:59 AM UTC 24
Finished Aug 29 09:29:29 AM UTC 24
Peak memory 257708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2072312464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.otp_ctrl_stress_all_with_rand_reset.2072312464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.411719339
Short name T355
Test name
Test status
Simulation time 553594628 ps
CPU time 13.39 seconds
Started Aug 29 09:31:20 AM UTC 24
Finished Aug 29 09:31:35 AM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411719339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.411719339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.3391067337
Short name T330
Test name
Test status
Simulation time 37627604888 ps
CPU time 144.3 seconds
Started Aug 29 09:31:26 AM UTC 24
Finished Aug 29 09:33:53 AM UTC 24
Peak memory 267760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391067337 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.3391067337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.1402760686
Short name T132
Test name
Test status
Simulation time 2517951314 ps
CPU time 93.36 seconds
Started Aug 29 09:36:09 AM UTC 24
Finished Aug 29 09:37:44 AM UTC 24
Peak memory 267948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1402760686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 66.otp_ctrl_stress_all_with_rand_reset.1402760686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1069108788
Short name T295
Test name
Test status
Simulation time 84050552 ps
CPU time 1.88 seconds
Started Aug 29 09:39:54 AM UTC 24
Finished Aug 29 09:39:57 AM UTC 24
Peak memory 253956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069108788 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.1069108788
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.1464030516
Short name T135
Test name
Test status
Simulation time 50361432006 ps
CPU time 135.48 seconds
Started Aug 29 09:21:18 AM UTC 24
Finished Aug 29 09:23:36 AM UTC 24
Peak memory 267800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464030516 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.1464030516
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.2543952679
Short name T409
Test name
Test status
Simulation time 5088485138 ps
CPU time 129.23 seconds
Started Aug 29 09:34:55 AM UTC 24
Finished Aug 29 09:37:07 AM UTC 24
Peak memory 268052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2543952679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.otp_ctrl_stress_all_with_rand_reset.2543952679
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.2704061955
Short name T71
Test name
Test status
Simulation time 390868785 ps
CPU time 16.05 seconds
Started Aug 29 09:27:59 AM UTC 24
Finished Aug 29 09:28:17 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704061955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.2704061955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.758714103
Short name T222
Test name
Test status
Simulation time 414028919 ps
CPU time 20.76 seconds
Started Aug 29 09:23:08 AM UTC 24
Finished Aug 29 09:23:30 AM UTC 24
Peak memory 257692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758714103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.758714103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.2827862969
Short name T175
Test name
Test status
Simulation time 2465046161 ps
CPU time 8.42 seconds
Started Aug 29 09:24:32 AM UTC 24
Finished Aug 29 09:24:42 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827862969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.2827862969
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.1134646593
Short name T173
Test name
Test status
Simulation time 117389861 ps
CPU time 5.1 seconds
Started Aug 29 09:25:17 AM UTC 24
Finished Aug 29 09:25:24 AM UTC 24
Peak memory 253556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134646593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1134646593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.2672502007
Short name T56
Test name
Test status
Simulation time 155612200 ps
CPU time 3.74 seconds
Started Aug 29 09:38:30 AM UTC 24
Finished Aug 29 09:38:35 AM UTC 24
Peak memory 251524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672502007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.2672502007
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.2100643275
Short name T447
Test name
Test status
Simulation time 1348896557 ps
CPU time 23.31 seconds
Started Aug 29 09:25:41 AM UTC 24
Finished Aug 29 09:26:05 AM UTC 24
Peak memory 251648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100643275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.2100643275
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.3413938271
Short name T252
Test name
Test status
Simulation time 29940271154 ps
CPU time 102.29 seconds
Started Aug 29 09:27:44 AM UTC 24
Finished Aug 29 09:29:28 AM UTC 24
Peak memory 267948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3413938271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.otp_ctrl_stress_all_with_rand_reset.3413938271
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.434162002
Short name T231
Test name
Test status
Simulation time 806841996 ps
CPU time 15.73 seconds
Started Aug 29 09:24:55 AM UTC 24
Finished Aug 29 09:25:12 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434162002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.434162002
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.4284823879
Short name T1
Test name
Test status
Simulation time 63494896 ps
CPU time 2.7 seconds
Started Aug 29 09:16:38 AM UTC 24
Finished Aug 29 09:16:42 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284823879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes
t +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.4284823879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.2100382054
Short name T91
Test name
Test status
Simulation time 1686775780 ps
CPU time 27.99 seconds
Started Aug 29 09:20:01 AM UTC 24
Finished Aug 29 09:20:30 AM UTC 24
Peak memory 251632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100382054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.2100382054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.917645691
Short name T100
Test name
Test status
Simulation time 2365224145 ps
CPU time 7.41 seconds
Started Aug 29 09:38:16 AM UTC 24
Finished Aug 29 09:38:25 AM UTC 24
Peak memory 251232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917645691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.917645691
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.1948684442
Short name T40
Test name
Test status
Simulation time 167786516 ps
CPU time 5.85 seconds
Started Aug 29 09:33:04 AM UTC 24
Finished Aug 29 09:33:11 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948684442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.1948684442
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.874802252
Short name T380
Test name
Test status
Simulation time 1328777853 ps
CPU time 21.27 seconds
Started Aug 29 09:24:39 AM UTC 24
Finished Aug 29 09:25:01 AM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874802252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.874802252
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.325326456
Short name T269
Test name
Test status
Simulation time 1400634005 ps
CPU time 20.55 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:21 AM UTC 24
Peak memory 256788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325326456 -assert nopostproc +UVM_TEST
NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.325326456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2789719823
Short name T266
Test name
Test status
Simulation time 4968011472 ps
CPU time 25.2 seconds
Started Aug 29 09:40:04 AM UTC 24
Finished Aug 29 09:40:30 AM UTC 24
Peak memory 258892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789719823 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.2789719823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.4025611643
Short name T235
Test name
Test status
Simulation time 340498720 ps
CPU time 5.05 seconds
Started Aug 29 09:39:09 AM UTC 24
Finished Aug 29 09:39:15 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025611643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.4025611643
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.1263065046
Short name T236
Test name
Test status
Simulation time 3518898455 ps
CPU time 117.8 seconds
Started Aug 29 09:30:01 AM UTC 24
Finished Aug 29 09:32:02 AM UTC 24
Peak memory 267884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1263065046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.otp_ctrl_stress_all_with_rand_reset.1263065046
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.3578418489
Short name T234
Test name
Test status
Simulation time 9707687999 ps
CPU time 146.25 seconds
Started Aug 29 09:36:06 AM UTC 24
Finished Aug 29 09:38:35 AM UTC 24
Peak memory 268204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3578418489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 64.otp_ctrl_stress_all_with_rand_reset.3578418489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.2799101799
Short name T115
Test name
Test status
Simulation time 252051765 ps
CPU time 14.34 seconds
Started Aug 29 09:19:15 AM UTC 24
Finished Aug 29 09:19:30 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799101799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.2799101799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.3955464222
Short name T316
Test name
Test status
Simulation time 914919915 ps
CPU time 9.29 seconds
Started Aug 29 09:25:08 AM UTC 24
Finished Aug 29 09:25:18 AM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955464222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.3955464222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.2851023514
Short name T464
Test name
Test status
Simulation time 1317715436 ps
CPU time 15.14 seconds
Started Aug 29 09:26:55 AM UTC 24
Finished Aug 29 09:27:11 AM UTC 24
Peak memory 253528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851023514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.2851023514
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.611064773
Short name T913
Test name
Test status
Simulation time 590175686 ps
CPU time 7.35 seconds
Started Aug 29 09:38:21 AM UTC 24
Finished Aug 29 09:38:29 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611064773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.611064773
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.315146951
Short name T304
Test name
Test status
Simulation time 3032256838 ps
CPU time 6.35 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:53 AM UTC 24
Peak memory 252700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315146951 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.315146951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.854837765
Short name T264
Test name
Test status
Simulation time 68683538 ps
CPU time 1.82 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:48 AM UTC 24
Peak memory 251964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854837765 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.854837765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1865204970
Short name T365
Test name
Test status
Simulation time 282641156 ps
CPU time 2.76 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:49 AM UTC 24
Peak memory 258976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1865204970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_cs
r_mem_rw_with_rand_reset.1865204970
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.3440544280
Short name T267
Test name
Test status
Simulation time 98187879 ps
CPU time 1.62 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:48 AM UTC 24
Peak memory 251848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440544280 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.3440544280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.2204191390
Short name T1172
Test name
Test status
Simulation time 140971068 ps
CPU time 1.74 seconds
Started Aug 29 09:39:44 AM UTC 24
Finished Aug 29 09:39:48 AM UTC 24
Peak memory 241636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204191390 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2204191390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1576620345
Short name T1171
Test name
Test status
Simulation time 67765592 ps
CPU time 1.43 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:47 AM UTC 24
Peak memory 240544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576620345 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.1576620345
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.808488382
Short name T1170
Test name
Test status
Simulation time 74880380 ps
CPU time 1.44 seconds
Started Aug 29 09:39:44 AM UTC 24
Finished Aug 29 09:39:47 AM UTC 24
Peak memory 240324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808488382 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.808488382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.3427732520
Short name T261
Test name
Test status
Simulation time 282799596 ps
CPU time 3.12 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:49 AM UTC 24
Peak memory 252640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427732520 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.3427732520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3323494984
Short name T1169
Test name
Test status
Simulation time 59271729 ps
CPU time 3.29 seconds
Started Aug 29 09:39:41 AM UTC 24
Finished Aug 29 09:39:46 AM UTC 24
Peak memory 259072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323494984 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.3323494984
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.261924641
Short name T270
Test name
Test status
Simulation time 1795939174 ps
CPU time 20.01 seconds
Started Aug 29 09:39:44 AM UTC 24
Finished Aug 29 09:40:06 AM UTC 24
Peak memory 256860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261924641 -assert nopostproc +UVM_TEST
NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.261924641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1431700621
Short name T1194
Test name
Test status
Simulation time 2984607339 ps
CPU time 7.54 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:54 AM UTC 24
Peak memory 252896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431700621 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.1431700621
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1399596947
Short name T1203
Test name
Test status
Simulation time 1629339650 ps
CPU time 9.81 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:56 AM UTC 24
Peak memory 252644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399596947 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.1399596947
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2661801606
Short name T282
Test name
Test status
Simulation time 251557308 ps
CPU time 2.36 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:49 AM UTC 24
Peak memory 252692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661801606 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.2661801606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1116621516
Short name T367
Test name
Test status
Simulation time 75010653 ps
CPU time 2.15 seconds
Started Aug 29 09:39:47 AM UTC 24
Finished Aug 29 09:39:51 AM UTC 24
Peak memory 258840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1116621516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_cs
r_mem_rw_with_rand_reset.1116621516
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1123802809
Short name T268
Test name
Test status
Simulation time 75670883 ps
CPU time 1.6 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:48 AM UTC 24
Peak memory 251848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123802809 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1123802809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.858808867
Short name T1175
Test name
Test status
Simulation time 575266169 ps
CPU time 2.11 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:48 AM UTC 24
Peak memory 241724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858808867 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.858808867
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.833356488
Short name T1174
Test name
Test status
Simulation time 508091360 ps
CPU time 1.76 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:48 AM UTC 24
Peak memory 241000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833356488 -assert nopostproc +U
VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.833356488
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2095579298
Short name T1173
Test name
Test status
Simulation time 36372227 ps
CPU time 1.76 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:48 AM UTC 24
Peak memory 240088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095579298 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.2095579298
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.3097349650
Short name T265
Test name
Test status
Simulation time 134776354 ps
CPU time 3.89 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:51 AM UTC 24
Peak memory 254736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097349650 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.3097349650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2452397235
Short name T1176
Test name
Test status
Simulation time 86748613 ps
CPU time 3.48 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:39:50 AM UTC 24
Peak memory 259044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452397235 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.2452397235
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.166690762
Short name T260
Test name
Test status
Simulation time 1249004041 ps
CPU time 18.67 seconds
Started Aug 29 09:39:45 AM UTC 24
Finished Aug 29 09:40:05 AM UTC 24
Peak memory 256904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166690762 -assert nopostproc +UVM_TEST
NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.166690762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.507109208
Short name T1218
Test name
Test status
Simulation time 417772751 ps
CPU time 3.46 seconds
Started Aug 29 09:39:57 AM UTC 24
Finished Aug 29 09:40:01 AM UTC 24
Peak memory 258916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=507109208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_cs
r_mem_rw_with_rand_reset.507109208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3011890764
Short name T1205
Test name
Test status
Simulation time 59864236 ps
CPU time 2.1 seconds
Started Aug 29 09:39:55 AM UTC 24
Finished Aug 29 09:39:59 AM UTC 24
Peak memory 254764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011890764 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3011890764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.2039865423
Short name T1199
Test name
Test status
Simulation time 43520353 ps
CPU time 1.44 seconds
Started Aug 29 09:39:55 AM UTC 24
Finished Aug 29 09:39:58 AM UTC 24
Peak memory 241756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039865423 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.2039865423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2370203550
Short name T1214
Test name
Test status
Simulation time 189199605 ps
CPU time 3.24 seconds
Started Aug 29 09:39:56 AM UTC 24
Finished Aug 29 09:40:00 AM UTC 24
Peak memory 252680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370203550 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.2370203550
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3158380852
Short name T1221
Test name
Test status
Simulation time 501113832 ps
CPU time 5.63 seconds
Started Aug 29 09:39:55 AM UTC 24
Finished Aug 29 09:40:02 AM UTC 24
Peak memory 258968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158380852 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3158380852
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1097859043
Short name T271
Test name
Test status
Simulation time 1226093851 ps
CPU time 9.91 seconds
Started Aug 29 09:39:55 AM UTC 24
Finished Aug 29 09:40:06 AM UTC 24
Peak memory 252688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097859043 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.1097859043
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3353010216
Short name T1219
Test name
Test status
Simulation time 193966791 ps
CPU time 3.08 seconds
Started Aug 29 09:39:57 AM UTC 24
Finished Aug 29 09:40:02 AM UTC 24
Peak memory 258972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3353010216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_c
sr_mem_rw_with_rand_reset.3353010216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3990338339
Short name T1216
Test name
Test status
Simulation time 42560202 ps
CPU time 2.15 seconds
Started Aug 29 09:39:57 AM UTC 24
Finished Aug 29 09:40:01 AM UTC 24
Peak memory 252824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990338339 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.3990338339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.217779379
Short name T1215
Test name
Test status
Simulation time 68547983 ps
CPU time 1.81 seconds
Started Aug 29 09:39:57 AM UTC 24
Finished Aug 29 09:40:00 AM UTC 24
Peak memory 241752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217779379 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.217779379
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.4245218456
Short name T1217
Test name
Test status
Simulation time 181259758 ps
CPU time 2.98 seconds
Started Aug 29 09:39:57 AM UTC 24
Finished Aug 29 09:40:01 AM UTC 24
Peak memory 254804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245218456 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.4245218456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2751315568
Short name T1220
Test name
Test status
Simulation time 181871085 ps
CPU time 3.88 seconds
Started Aug 29 09:39:57 AM UTC 24
Finished Aug 29 09:40:02 AM UTC 24
Peak memory 259044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751315568 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.2751315568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.113308474
Short name T353
Test name
Test status
Simulation time 10278640323 ps
CPU time 15.91 seconds
Started Aug 29 09:39:57 AM UTC 24
Finished Aug 29 09:40:14 AM UTC 24
Peak memory 252764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113308474 -assert nopostproc +UVM_TEST
NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.113308474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2184886417
Short name T1226
Test name
Test status
Simulation time 79855553 ps
CPU time 2.32 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:03 AM UTC 24
Peak memory 256860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2184886417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_c
sr_mem_rw_with_rand_reset.2184886417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.4288862017
Short name T1225
Test name
Test status
Simulation time 66799098 ps
CPU time 2.38 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:03 AM UTC 24
Peak memory 252844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288862017 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.4288862017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.3031973887
Short name T1224
Test name
Test status
Simulation time 43088827 ps
CPU time 2.26 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:02 AM UTC 24
Peak memory 241740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031973887 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.3031973887
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.82285130
Short name T1228
Test name
Test status
Simulation time 117762332 ps
CPU time 3.36 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:04 AM UTC 24
Peak memory 252800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82285130 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.82285130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2745751903
Short name T1222
Test name
Test status
Simulation time 304393672 ps
CPU time 3.71 seconds
Started Aug 29 09:39:57 AM UTC 24
Finished Aug 29 09:40:02 AM UTC 24
Peak memory 258972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745751903 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2745751903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1920831584
Short name T1234
Test name
Test status
Simulation time 1666846954 ps
CPU time 3.91 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:04 AM UTC 24
Peak memory 259104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1920831584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_c
sr_mem_rw_with_rand_reset.1920831584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.359794626
Short name T298
Test name
Test status
Simulation time 61623816 ps
CPU time 1.89 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:02 AM UTC 24
Peak memory 251868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359794626 -assert nopostproc +UVM_TESTNAME=otp_
ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.359794626
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.1335578333
Short name T1223
Test name
Test status
Simulation time 68905291 ps
CPU time 1.84 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:02 AM UTC 24
Peak memory 241692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335578333 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1335578333
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2977278141
Short name T1241
Test name
Test status
Simulation time 266099561 ps
CPU time 5.6 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:06 AM UTC 24
Peak memory 252716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977278141 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.2977278141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1004325462
Short name T1231
Test name
Test status
Simulation time 242443733 ps
CPU time 3.58 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:04 AM UTC 24
Peak memory 259088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004325462 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.1004325462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1990098937
Short name T348
Test name
Test status
Simulation time 1844262189 ps
CPU time 17.62 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:18 AM UTC 24
Peak memory 252900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990098937 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.1990098937
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2134570108
Short name T1237
Test name
Test status
Simulation time 168300968 ps
CPU time 3.17 seconds
Started Aug 29 09:40:01 AM UTC 24
Finished Aug 29 09:40:05 AM UTC 24
Peak memory 259096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2134570108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_c
sr_mem_rw_with_rand_reset.2134570108
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.31525939
Short name T1232
Test name
Test status
Simulation time 42880559 ps
CPU time 2.17 seconds
Started Aug 29 09:40:01 AM UTC 24
Finished Aug 29 09:40:04 AM UTC 24
Peak memory 252636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31525939 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.31525939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.4208152386
Short name T1227
Test name
Test status
Simulation time 130324391 ps
CPU time 2.03 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:03 AM UTC 24
Peak memory 241676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208152386 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.4208152386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.4213238681
Short name T1236
Test name
Test status
Simulation time 58740037 ps
CPU time 3.12 seconds
Started Aug 29 09:40:01 AM UTC 24
Finished Aug 29 09:40:05 AM UTC 24
Peak memory 252632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213238681 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.4213238681
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2792258148
Short name T1238
Test name
Test status
Simulation time 223315124 ps
CPU time 4.66 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:05 AM UTC 24
Peak memory 258976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792258148 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.2792258148
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1524175091
Short name T352
Test name
Test status
Simulation time 608405098 ps
CPU time 11.11 seconds
Started Aug 29 09:39:59 AM UTC 24
Finished Aug 29 09:40:12 AM UTC 24
Peak memory 257112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524175091 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.1524175091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1394109784
Short name T1239
Test name
Test status
Simulation time 75129066 ps
CPU time 3.4 seconds
Started Aug 29 09:40:01 AM UTC 24
Finished Aug 29 09:40:06 AM UTC 24
Peak memory 258876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1394109784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_c
sr_mem_rw_with_rand_reset.1394109784
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.163928546
Short name T299
Test name
Test status
Simulation time 49034257 ps
CPU time 1.87 seconds
Started Aug 29 09:40:01 AM UTC 24
Finished Aug 29 09:40:04 AM UTC 24
Peak memory 251864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163928546 -assert nopostproc +UVM_TESTNAME=otp_
ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.163928546
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.2247988794
Short name T1230
Test name
Test status
Simulation time 42048279 ps
CPU time 1.94 seconds
Started Aug 29 09:40:01 AM UTC 24
Finished Aug 29 09:40:04 AM UTC 24
Peak memory 241704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247988794 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.2247988794
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.83313627
Short name T1233
Test name
Test status
Simulation time 169515239 ps
CPU time 2.03 seconds
Started Aug 29 09:40:01 AM UTC 24
Finished Aug 29 09:40:04 AM UTC 24
Peak memory 252648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83313627 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.83313627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.744044879
Short name T1240
Test name
Test status
Simulation time 165220659 ps
CPU time 4.07 seconds
Started Aug 29 09:40:01 AM UTC 24
Finished Aug 29 09:40:06 AM UTC 24
Peak memory 259024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744044879 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.744044879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2733145486
Short name T1292
Test name
Test status
Simulation time 1481753681 ps
CPU time 22.9 seconds
Started Aug 29 09:40:01 AM UTC 24
Finished Aug 29 09:40:25 AM UTC 24
Peak memory 259032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733145486 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.2733145486
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.4273702821
Short name T1242
Test name
Test status
Simulation time 407902797 ps
CPU time 2.76 seconds
Started Aug 29 09:40:02 AM UTC 24
Finished Aug 29 09:40:06 AM UTC 24
Peak memory 259104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4273702821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_c
sr_mem_rw_with_rand_reset.4273702821
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3892768698
Short name T300
Test name
Test status
Simulation time 44410974 ps
CPU time 1.66 seconds
Started Aug 29 09:40:02 AM UTC 24
Finished Aug 29 09:40:05 AM UTC 24
Peak memory 251864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892768698 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.3892768698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.1375225059
Short name T1235
Test name
Test status
Simulation time 69247269 ps
CPU time 1.48 seconds
Started Aug 29 09:40:02 AM UTC 24
Finished Aug 29 09:40:05 AM UTC 24
Peak memory 241136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375225059 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.1375225059
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.574185905
Short name T1247
Test name
Test status
Simulation time 132134782 ps
CPU time 3.52 seconds
Started Aug 29 09:40:02 AM UTC 24
Finished Aug 29 09:40:07 AM UTC 24
Peak memory 254780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574185905 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.574185905
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3205128930
Short name T1243
Test name
Test status
Simulation time 114525704 ps
CPU time 4.16 seconds
Started Aug 29 09:40:01 AM UTC 24
Finished Aug 29 09:40:06 AM UTC 24
Peak memory 258920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205128930 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.3205128930
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1936901529
Short name T1287
Test name
Test status
Simulation time 2604673299 ps
CPU time 10.81 seconds
Started Aug 29 09:40:02 AM UTC 24
Finished Aug 29 09:40:14 AM UTC 24
Peak memory 256784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936901529 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.1936901529
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1262824447
Short name T1248
Test name
Test status
Simulation time 253748934 ps
CPU time 2.09 seconds
Started Aug 29 09:40:04 AM UTC 24
Finished Aug 29 09:40:07 AM UTC 24
Peak memory 256892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1262824447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_c
sr_mem_rw_with_rand_reset.1262824447
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3983533979
Short name T1245
Test name
Test status
Simulation time 41921936 ps
CPU time 1.69 seconds
Started Aug 29 09:40:04 AM UTC 24
Finished Aug 29 09:40:07 AM UTC 24
Peak memory 251868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983533979 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3983533979
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.1689024825
Short name T1244
Test name
Test status
Simulation time 144938526 ps
CPU time 1.69 seconds
Started Aug 29 09:40:04 AM UTC 24
Finished Aug 29 09:40:07 AM UTC 24
Peak memory 241704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689024825 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.1689024825
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1795248212
Short name T1250
Test name
Test status
Simulation time 108244523 ps
CPU time 3.2 seconds
Started Aug 29 09:40:04 AM UTC 24
Finished Aug 29 09:40:08 AM UTC 24
Peak memory 252896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795248212 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.1795248212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1658284182
Short name T1251
Test name
Test status
Simulation time 56849816 ps
CPU time 3.72 seconds
Started Aug 29 09:40:03 AM UTC 24
Finished Aug 29 09:40:08 AM UTC 24
Peak memory 259036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658284182 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1658284182
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1008618813
Short name T1254
Test name
Test status
Simulation time 70321726 ps
CPU time 2.52 seconds
Started Aug 29 09:40:05 AM UTC 24
Finished Aug 29 09:40:09 AM UTC 24
Peak memory 256828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1008618813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_c
sr_mem_rw_with_rand_reset.1008618813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1531513860
Short name T1252
Test name
Test status
Simulation time 38317562 ps
CPU time 2.22 seconds
Started Aug 29 09:40:05 AM UTC 24
Finished Aug 29 09:40:09 AM UTC 24
Peak memory 254748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531513860 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.1531513860
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.3189069925
Short name T1246
Test name
Test status
Simulation time 40312770 ps
CPU time 1.43 seconds
Started Aug 29 09:40:04 AM UTC 24
Finished Aug 29 09:40:07 AM UTC 24
Peak memory 241196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189069925 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.3189069925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3809903652
Short name T1257
Test name
Test status
Simulation time 121227766 ps
CPU time 3.12 seconds
Started Aug 29 09:40:05 AM UTC 24
Finished Aug 29 09:40:09 AM UTC 24
Peak memory 254712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809903652 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.3809903652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3418417006
Short name T1269
Test name
Test status
Simulation time 152657826 ps
CPU time 5.62 seconds
Started Aug 29 09:40:04 AM UTC 24
Finished Aug 29 09:40:11 AM UTC 24
Peak memory 259044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418417006 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.3418417006
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.738755540
Short name T1291
Test name
Test status
Simulation time 707894166 ps
CPU time 10.56 seconds
Started Aug 29 09:40:04 AM UTC 24
Finished Aug 29 09:40:16 AM UTC 24
Peak memory 256732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738755540 -assert nopostproc +UVM_TEST
NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.738755540
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3472355258
Short name T1256
Test name
Test status
Simulation time 68819283 ps
CPU time 2.54 seconds
Started Aug 29 09:40:05 AM UTC 24
Finished Aug 29 09:40:09 AM UTC 24
Peak memory 257020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3472355258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_c
sr_mem_rw_with_rand_reset.3472355258
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2456241326
Short name T301
Test name
Test status
Simulation time 68669745 ps
CPU time 2.51 seconds
Started Aug 29 09:40:05 AM UTC 24
Finished Aug 29 09:40:09 AM UTC 24
Peak memory 254748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456241326 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.2456241326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.1852601521
Short name T1249
Test name
Test status
Simulation time 38663158 ps
CPU time 1.52 seconds
Started Aug 29 09:40:05 AM UTC 24
Finished Aug 29 09:40:08 AM UTC 24
Peak memory 241196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852601521 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1852601521
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.561662198
Short name T1253
Test name
Test status
Simulation time 90704109 ps
CPU time 2.3 seconds
Started Aug 29 09:40:05 AM UTC 24
Finished Aug 29 09:40:09 AM UTC 24
Peak memory 254912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561662198 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.561662198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2304956895
Short name T1277
Test name
Test status
Simulation time 71987881 ps
CPU time 5.9 seconds
Started Aug 29 09:40:05 AM UTC 24
Finished Aug 29 09:40:12 AM UTC 24
Peak memory 258908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304956895 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2304956895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1298000226
Short name T1293
Test name
Test status
Simulation time 2515182510 ps
CPU time 19.81 seconds
Started Aug 29 09:40:05 AM UTC 24
Finished Aug 29 09:40:27 AM UTC 24
Peak memory 256860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298000226 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.1298000226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.259138542
Short name T287
Test name
Test status
Simulation time 469623156 ps
CPU time 4.71 seconds
Started Aug 29 09:39:47 AM UTC 24
Finished Aug 29 09:39:53 AM UTC 24
Peak memory 254892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259138542 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.259138542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3061438171
Short name T290
Test name
Test status
Simulation time 158572316 ps
CPU time 4.15 seconds
Started Aug 29 09:39:47 AM UTC 24
Finished Aug 29 09:39:53 AM UTC 24
Peak memory 252552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061438171 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.3061438171
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2643878107
Short name T283
Test name
Test status
Simulation time 177020683 ps
CPU time 2.72 seconds
Started Aug 29 09:39:47 AM UTC 24
Finished Aug 29 09:39:51 AM UTC 24
Peak memory 252848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643878107 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.2643878107
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1028589592
Short name T366
Test name
Test status
Simulation time 281778395 ps
CPU time 3.58 seconds
Started Aug 29 09:39:47 AM UTC 24
Finished Aug 29 09:39:52 AM UTC 24
Peak memory 258944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1028589592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_cs
r_mem_rw_with_rand_reset.1028589592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1569131560
Short name T288
Test name
Test status
Simulation time 41582256 ps
CPU time 1.64 seconds
Started Aug 29 09:39:47 AM UTC 24
Finished Aug 29 09:39:50 AM UTC 24
Peak memory 251800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569131560 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.1569131560
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.2111037631
Short name T1178
Test name
Test status
Simulation time 76144007 ps
CPU time 1.95 seconds
Started Aug 29 09:39:47 AM UTC 24
Finished Aug 29 09:39:50 AM UTC 24
Peak memory 241080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111037631 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.2111037631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1830572781
Short name T1179
Test name
Test status
Simulation time 72781710 ps
CPU time 1.87 seconds
Started Aug 29 09:39:47 AM UTC 24
Finished Aug 29 09:39:50 AM UTC 24
Peak memory 240276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830572781 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.1830572781
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.227431433
Short name T1177
Test name
Test status
Simulation time 41024983 ps
CPU time 1.48 seconds
Started Aug 29 09:39:47 AM UTC 24
Finished Aug 29 09:39:50 AM UTC 24
Peak memory 240328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227431433 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.227431433
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.970129995
Short name T263
Test name
Test status
Simulation time 156046486 ps
CPU time 2.46 seconds
Started Aug 29 09:39:47 AM UTC 24
Finished Aug 29 09:39:51 AM UTC 24
Peak memory 252644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970129995 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.970129995
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2486000668
Short name T1192
Test name
Test status
Simulation time 1672199589 ps
CPU time 5.72 seconds
Started Aug 29 09:39:47 AM UTC 24
Finished Aug 29 09:39:54 AM UTC 24
Peak memory 259164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486000668 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2486000668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1612531828
Short name T258
Test name
Test status
Simulation time 675119060 ps
CPU time 10.4 seconds
Started Aug 29 09:39:47 AM UTC 24
Finished Aug 29 09:39:59 AM UTC 24
Peak memory 256920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612531828 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.1612531828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.292361071
Short name T1262
Test name
Test status
Simulation time 146497591 ps
CPU time 2.04 seconds
Started Aug 29 09:40:07 AM UTC 24
Finished Aug 29 09:40:10 AM UTC 24
Peak memory 241788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292361071 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.292361071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.752095730
Short name T1258
Test name
Test status
Simulation time 573610392 ps
CPU time 1.7 seconds
Started Aug 29 09:40:07 AM UTC 24
Finished Aug 29 09:40:10 AM UTC 24
Peak memory 241700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752095730 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.752095730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.3303850756
Short name T1259
Test name
Test status
Simulation time 581418555 ps
CPU time 1.79 seconds
Started Aug 29 09:40:07 AM UTC 24
Finished Aug 29 09:40:10 AM UTC 24
Peak memory 241704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303850756 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.3303850756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.935418277
Short name T1261
Test name
Test status
Simulation time 557967790 ps
CPU time 1.8 seconds
Started Aug 29 09:40:07 AM UTC 24
Finished Aug 29 09:40:10 AM UTC 24
Peak memory 241224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935418277 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.935418277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.4091499290
Short name T1265
Test name
Test status
Simulation time 44670087 ps
CPU time 2.03 seconds
Started Aug 29 09:40:07 AM UTC 24
Finished Aug 29 09:40:10 AM UTC 24
Peak memory 241840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091499290 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.4091499290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.3347452520
Short name T1266
Test name
Test status
Simulation time 576503185 ps
CPU time 2 seconds
Started Aug 29 09:40:07 AM UTC 24
Finished Aug 29 09:40:10 AM UTC 24
Peak memory 241196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347452520 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.3347452520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.2009662212
Short name T1260
Test name
Test status
Simulation time 145598121 ps
CPU time 1.75 seconds
Started Aug 29 09:40:07 AM UTC 24
Finished Aug 29 09:40:10 AM UTC 24
Peak memory 241704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009662212 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.2009662212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.4194148022
Short name T1264
Test name
Test status
Simulation time 508287025 ps
CPU time 1.83 seconds
Started Aug 29 09:40:07 AM UTC 24
Finished Aug 29 09:40:10 AM UTC 24
Peak memory 241136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194148022 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.4194148022
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.3038057702
Short name T1263
Test name
Test status
Simulation time 83433824 ps
CPU time 1.72 seconds
Started Aug 29 09:40:07 AM UTC 24
Finished Aug 29 09:40:10 AM UTC 24
Peak memory 241088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038057702 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.3038057702
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.2177461144
Short name T1267
Test name
Test status
Simulation time 137069802 ps
CPU time 1.87 seconds
Started Aug 29 09:40:07 AM UTC 24
Finished Aug 29 09:40:10 AM UTC 24
Peak memory 241196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177461144 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2177461144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2271342985
Short name T1190
Test name
Test status
Simulation time 1761287548 ps
CPU time 3.66 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:39:54 AM UTC 24
Peak memory 252700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271342985 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.2271342985
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2293357861
Short name T297
Test name
Test status
Simulation time 842201879 ps
CPU time 8.89 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:39:59 AM UTC 24
Peak memory 252684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293357861 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.2293357861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3569824604
Short name T285
Test name
Test status
Simulation time 70849744 ps
CPU time 1.87 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:39:52 AM UTC 24
Peak memory 251924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569824604 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.3569824604
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.4207673996
Short name T1191
Test name
Test status
Simulation time 75482683 ps
CPU time 3.61 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:39:54 AM UTC 24
Peak memory 258968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4207673996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_cs
r_mem_rw_with_rand_reset.4207673996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.921474278
Short name T1182
Test name
Test status
Simulation time 100611709 ps
CPU time 2.22 seconds
Started Aug 29 09:39:48 AM UTC 24
Finished Aug 29 09:39:51 AM UTC 24
Peak memory 241976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921474278 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.921474278
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2341866193
Short name T1181
Test name
Test status
Simulation time 35977095 ps
CPU time 1.66 seconds
Started Aug 29 09:39:48 AM UTC 24
Finished Aug 29 09:39:51 AM UTC 24
Peak memory 241528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341866193 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.2341866193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.687128526
Short name T1180
Test name
Test status
Simulation time 73478901 ps
CPU time 1.64 seconds
Started Aug 29 09:39:48 AM UTC 24
Finished Aug 29 09:39:51 AM UTC 24
Peak memory 240332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687128526 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.687128526
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.36742082
Short name T286
Test name
Test status
Simulation time 94875084 ps
CPU time 2.35 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:39:53 AM UTC 24
Peak memory 254764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36742082 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.36742082
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.2768668994
Short name T1183
Test name
Test status
Simulation time 64444130 ps
CPU time 3.73 seconds
Started Aug 29 09:39:48 AM UTC 24
Finished Aug 29 09:39:53 AM UTC 24
Peak memory 252964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768668994 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.2768668994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2471196925
Short name T350
Test name
Test status
Simulation time 1391322253 ps
CPU time 20.34 seconds
Started Aug 29 09:39:48 AM UTC 24
Finished Aug 29 09:40:09 AM UTC 24
Peak memory 256920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471196925 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.2471196925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.990544001
Short name T1268
Test name
Test status
Simulation time 51021315 ps
CPU time 2 seconds
Started Aug 29 09:40:07 AM UTC 24
Finished Aug 29 09:40:10 AM UTC 24
Peak memory 241080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990544001 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.990544001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.2154042135
Short name T1272
Test name
Test status
Simulation time 38297836 ps
CPU time 2.07 seconds
Started Aug 29 09:40:09 AM UTC 24
Finished Aug 29 09:40:12 AM UTC 24
Peak memory 242000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154042135 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.2154042135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.3425726340
Short name T1275
Test name
Test status
Simulation time 539851367 ps
CPU time 2.1 seconds
Started Aug 29 09:40:09 AM UTC 24
Finished Aug 29 09:40:12 AM UTC 24
Peak memory 241540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425726340 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.3425726340
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.3181211180
Short name T1274
Test name
Test status
Simulation time 68861416 ps
CPU time 2.1 seconds
Started Aug 29 09:40:09 AM UTC 24
Finished Aug 29 09:40:12 AM UTC 24
Peak memory 241716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181211180 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.3181211180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.947212963
Short name T1270
Test name
Test status
Simulation time 536559608 ps
CPU time 1.88 seconds
Started Aug 29 09:40:09 AM UTC 24
Finished Aug 29 09:40:12 AM UTC 24
Peak memory 241212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947212963 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.947212963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3446426382
Short name T1271
Test name
Test status
Simulation time 571128472 ps
CPU time 1.87 seconds
Started Aug 29 09:40:09 AM UTC 24
Finished Aug 29 09:40:12 AM UTC 24
Peak memory 241704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446426382 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3446426382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.2889452585
Short name T1279
Test name
Test status
Simulation time 581963514 ps
CPU time 2.46 seconds
Started Aug 29 09:40:09 AM UTC 24
Finished Aug 29 09:40:12 AM UTC 24
Peak memory 242612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889452585 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.2889452585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.31255485
Short name T1273
Test name
Test status
Simulation time 67146542 ps
CPU time 1.76 seconds
Started Aug 29 09:40:09 AM UTC 24
Finished Aug 29 09:40:12 AM UTC 24
Peak memory 241140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31255485 -assert nopostproc +UVM_TESTNAME=otp_ctrl
_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.31255485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.2040752337
Short name T1276
Test name
Test status
Simulation time 39245348 ps
CPU time 1.85 seconds
Started Aug 29 09:40:09 AM UTC 24
Finished Aug 29 09:40:12 AM UTC 24
Peak memory 241196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040752337 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2040752337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.3124524926
Short name T1278
Test name
Test status
Simulation time 549020165 ps
CPU time 1.71 seconds
Started Aug 29 09:40:11 AM UTC 24
Finished Aug 29 09:40:14 AM UTC 24
Peak memory 241204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124524926 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.3124524926
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1754742324
Short name T292
Test name
Test status
Simulation time 433698014 ps
CPU time 3.84 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:39:54 AM UTC 24
Peak memory 252712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754742324 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.1754742324
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.670078520
Short name T1229
Test name
Test status
Simulation time 6864315149 ps
CPU time 13.09 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:40:04 AM UTC 24
Peak memory 242456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670078520 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.670078520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2084955701
Short name T293
Test name
Test status
Simulation time 1557035083 ps
CPU time 4.4 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:39:55 AM UTC 24
Peak memory 252616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084955701 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.2084955701
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.108432479
Short name T1196
Test name
Test status
Simulation time 212713655 ps
CPU time 3.19 seconds
Started Aug 29 09:39:51 AM UTC 24
Finished Aug 29 09:39:55 AM UTC 24
Peak memory 258968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=108432479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr
_mem_rw_with_rand_reset.108432479
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2451368558
Short name T289
Test name
Test status
Simulation time 42307077 ps
CPU time 2.04 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:39:53 AM UTC 24
Peak memory 252592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451368558 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.2451368558
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.1321653686
Short name T1187
Test name
Test status
Simulation time 140626212 ps
CPU time 2.31 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:39:53 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321653686 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1321653686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2303857946
Short name T1185
Test name
Test status
Simulation time 131338329 ps
CPU time 2.08 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:39:53 AM UTC 24
Peak memory 241208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303857946 -assert nopostproc +
UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.2303857946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.242936541
Short name T1186
Test name
Test status
Simulation time 37048117 ps
CPU time 2.21 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:39:53 AM UTC 24
Peak memory 241292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242936541 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.242936541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3725831697
Short name T302
Test name
Test status
Simulation time 54921666 ps
CPU time 2.97 seconds
Started Aug 29 09:39:51 AM UTC 24
Finished Aug 29 09:39:55 AM UTC 24
Peak memory 252636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725831697 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.3725831697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.713149164
Short name T1195
Test name
Test status
Simulation time 100107802 ps
CPU time 4.47 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:39:55 AM UTC 24
Peak memory 259140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713149164 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.713149164
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3922718748
Short name T1290
Test name
Test status
Simulation time 19993423384 ps
CPU time 24.97 seconds
Started Aug 29 09:39:49 AM UTC 24
Finished Aug 29 09:40:16 AM UTC 24
Peak memory 257052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922718748 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.3922718748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.303872909
Short name T1281
Test name
Test status
Simulation time 44746866 ps
CPU time 1.53 seconds
Started Aug 29 09:40:11 AM UTC 24
Finished Aug 29 09:40:13 AM UTC 24
Peak memory 241628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303872909 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.303872909
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.2002780916
Short name T1280
Test name
Test status
Simulation time 146272442 ps
CPU time 1.5 seconds
Started Aug 29 09:40:11 AM UTC 24
Finished Aug 29 09:40:13 AM UTC 24
Peak memory 241340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002780916 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.2002780916
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.3455467221
Short name T1284
Test name
Test status
Simulation time 89950426 ps
CPU time 2.09 seconds
Started Aug 29 09:40:11 AM UTC 24
Finished Aug 29 09:40:14 AM UTC 24
Peak memory 241668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455467221 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.3455467221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.2081534787
Short name T1255
Test name
Test status
Simulation time 80357890 ps
CPU time 1.47 seconds
Started Aug 29 09:40:11 AM UTC 24
Finished Aug 29 09:40:13 AM UTC 24
Peak memory 241204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081534787 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.2081534787
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.556496172
Short name T1282
Test name
Test status
Simulation time 69580528 ps
CPU time 1.56 seconds
Started Aug 29 09:40:11 AM UTC 24
Finished Aug 29 09:40:14 AM UTC 24
Peak memory 241192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556496172 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.556496172
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.3130910795
Short name T1289
Test name
Test status
Simulation time 598228728 ps
CPU time 2.55 seconds
Started Aug 29 09:40:11 AM UTC 24
Finished Aug 29 09:40:15 AM UTC 24
Peak memory 242612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130910795 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.3130910795
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.2272721437
Short name T1283
Test name
Test status
Simulation time 57853075 ps
CPU time 1.78 seconds
Started Aug 29 09:40:11 AM UTC 24
Finished Aug 29 09:40:14 AM UTC 24
Peak memory 241084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272721437 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2272721437
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.1841793196
Short name T1285
Test name
Test status
Simulation time 40057739 ps
CPU time 1.99 seconds
Started Aug 29 09:40:11 AM UTC 24
Finished Aug 29 09:40:14 AM UTC 24
Peak memory 241196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841793196 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.1841793196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.422744826
Short name T1286
Test name
Test status
Simulation time 42438057 ps
CPU time 2.13 seconds
Started Aug 29 09:40:11 AM UTC 24
Finished Aug 29 09:40:14 AM UTC 24
Peak memory 241740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422744826 -assert nopostproc +UVM_TESTNAME=otp_ctr
l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.422744826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3604817008
Short name T1288
Test name
Test status
Simulation time 535524746 ps
CPU time 2.07 seconds
Started Aug 29 09:40:11 AM UTC 24
Finished Aug 29 09:40:14 AM UTC 24
Peak memory 241696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604817008 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3604817008
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3130308798
Short name T291
Test name
Test status
Simulation time 92635057 ps
CPU time 2.34 seconds
Started Aug 29 09:39:51 AM UTC 24
Finished Aug 29 09:39:54 AM UTC 24
Peak memory 252748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130308798 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.3130308798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.4080676130
Short name T1188
Test name
Test status
Simulation time 139063220 ps
CPU time 1.54 seconds
Started Aug 29 09:39:51 AM UTC 24
Finished Aug 29 09:39:53 AM UTC 24
Peak memory 241088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080676130 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.4080676130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.2403905375
Short name T1200
Test name
Test status
Simulation time 324719158 ps
CPU time 2.93 seconds
Started Aug 29 09:39:52 AM UTC 24
Finished Aug 29 09:39:56 AM UTC 24
Peak memory 254816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403905375 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.2403905375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1914626150
Short name T1197
Test name
Test status
Simulation time 55091078 ps
CPU time 3.42 seconds
Started Aug 29 09:39:51 AM UTC 24
Finished Aug 29 09:39:55 AM UTC 24
Peak memory 258968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914626150 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.1914626150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.74407852
Short name T294
Test name
Test status
Simulation time 42522679 ps
CPU time 1.78 seconds
Started Aug 29 09:39:52 AM UTC 24
Finished Aug 29 09:39:55 AM UTC 24
Peak memory 251860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74407852 -assert nopostproc +UVM_TESTNAME=otp_c
trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.74407852
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.2177990623
Short name T1198
Test name
Test status
Simulation time 158046642 ps
CPU time 1.96 seconds
Started Aug 29 09:39:52 AM UTC 24
Finished Aug 29 09:39:55 AM UTC 24
Peak memory 241080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177990623 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2177990623
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3882716499
Short name T1206
Test name
Test status
Simulation time 458451422 ps
CPU time 4.1 seconds
Started Aug 29 09:39:52 AM UTC 24
Finished Aug 29 09:39:57 AM UTC 24
Peak memory 252864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882716499 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.3882716499
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2074492118
Short name T1201
Test name
Test status
Simulation time 133814789 ps
CPU time 5.1 seconds
Started Aug 29 09:39:52 AM UTC 24
Finished Aug 29 09:39:58 AM UTC 24
Peak memory 259200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074492118 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.2074492118
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2258363598
Short name T346
Test name
Test status
Simulation time 10360032362 ps
CPU time 18.83 seconds
Started Aug 29 09:39:52 AM UTC 24
Finished Aug 29 09:40:12 AM UTC 24
Peak memory 256836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258363598 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.2258363598
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3423722360
Short name T1184
Test name
Test status
Simulation time 146251110 ps
CPU time 3.14 seconds
Started Aug 29 09:39:54 AM UTC 24
Finished Aug 29 09:39:58 AM UTC 24
Peak memory 258968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3423722360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_cs
r_mem_rw_with_rand_reset.3423722360
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1543546374
Short name T296
Test name
Test status
Simulation time 146318921 ps
CPU time 2.39 seconds
Started Aug 29 09:39:54 AM UTC 24
Finished Aug 29 09:39:57 AM UTC 24
Peak memory 252824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543546374 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.1543546374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.3918264393
Short name T1202
Test name
Test status
Simulation time 128564690 ps
CPU time 1.55 seconds
Started Aug 29 09:39:54 AM UTC 24
Finished Aug 29 09:39:56 AM UTC 24
Peak memory 241692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918264393 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3918264393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3887492191
Short name T1209
Test name
Test status
Simulation time 195577296 ps
CPU time 4.18 seconds
Started Aug 29 09:39:54 AM UTC 24
Finished Aug 29 09:39:59 AM UTC 24
Peak memory 252764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887492191 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.3887492191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3374179687
Short name T1193
Test name
Test status
Simulation time 303610300 ps
CPU time 6.99 seconds
Started Aug 29 09:39:52 AM UTC 24
Finished Aug 29 09:40:00 AM UTC 24
Peak memory 259164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374179687 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3374179687
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2920822203
Short name T1208
Test name
Test status
Simulation time 378932804 ps
CPU time 3.46 seconds
Started Aug 29 09:39:54 AM UTC 24
Finished Aug 29 09:39:59 AM UTC 24
Peak memory 259080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2920822203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_cs
r_mem_rw_with_rand_reset.2920822203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.2813499615
Short name T1204
Test name
Test status
Simulation time 36703318 ps
CPU time 1.53 seconds
Started Aug 29 09:39:54 AM UTC 24
Finished Aug 29 09:39:57 AM UTC 24
Peak memory 241176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813499615 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.2813499615
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2359821955
Short name T1207
Test name
Test status
Simulation time 113893109 ps
CPU time 3.03 seconds
Started Aug 29 09:39:54 AM UTC 24
Finished Aug 29 09:39:58 AM UTC 24
Peak memory 252824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359821955 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.2359821955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.4165950996
Short name T1210
Test name
Test status
Simulation time 836066535 ps
CPU time 4.41 seconds
Started Aug 29 09:39:54 AM UTC 24
Finished Aug 29 09:39:59 AM UTC 24
Peak memory 259008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165950996 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.4165950996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1946886287
Short name T1212
Test name
Test status
Simulation time 282728641 ps
CPU time 3.02 seconds
Started Aug 29 09:39:55 AM UTC 24
Finished Aug 29 09:39:59 AM UTC 24
Peak memory 258972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1946886287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_cs
r_mem_rw_with_rand_reset.1946886287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1607582259
Short name T303
Test name
Test status
Simulation time 69875452 ps
CPU time 1.89 seconds
Started Aug 29 09:39:55 AM UTC 24
Finished Aug 29 09:39:58 AM UTC 24
Peak memory 254088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607582259 -assert nopostproc +UVM_TESTNAME=otp
_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1607582259
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.1891740364
Short name T1189
Test name
Test status
Simulation time 65759445 ps
CPU time 1.94 seconds
Started Aug 29 09:39:55 AM UTC 24
Finished Aug 29 09:39:58 AM UTC 24
Peak memory 241160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891740364 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1891740364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.2861513692
Short name T1211
Test name
Test status
Simulation time 122863710 ps
CPU time 3.09 seconds
Started Aug 29 09:39:55 AM UTC 24
Finished Aug 29 09:39:59 AM UTC 24
Peak memory 252736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861513692 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.2861513692
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3847179879
Short name T1213
Test name
Test status
Simulation time 183656129 ps
CPU time 4.37 seconds
Started Aug 29 09:39:54 AM UTC 24
Finished Aug 29 09:40:00 AM UTC 24
Peak memory 258912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847179879 -assert nopostproc +UVM_TESTNAME=otp_ct
rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.3847179879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1080636762
Short name T349
Test name
Test status
Simulation time 2619419434 ps
CPU time 17.23 seconds
Started Aug 29 09:39:55 AM UTC 24
Finished Aug 29 09:40:14 AM UTC 24
Peak memory 258988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080636762 -assert nopostproc +UVM_TES
TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.1080636762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.4216630805
Short name T4
Test name
Test status
Simulation time 944108507 ps
CPU time 16 seconds
Started Aug 29 09:17:10 AM UTC 24
Finished Aug 29 09:17:28 AM UTC 24
Peak memory 251308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216630805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.4216630805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.2925264125
Short name T7
Test name
Test status
Simulation time 1449280508 ps
CPU time 46.47 seconds
Started Aug 29 09:17:22 AM UTC 24
Finished Aug 29 09:18:10 AM UTC 24
Peak memory 253288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925264125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.2925264125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.1150332067
Short name T11
Test name
Test status
Simulation time 597884104 ps
CPU time 12.01 seconds
Started Aug 29 09:17:21 AM UTC 24
Finished Aug 29 09:17:34 AM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150332067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.1150332067
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.1226651305
Short name T10
Test name
Test status
Simulation time 6890542867 ps
CPU time 25.86 seconds
Started Aug 29 09:16:55 AM UTC 24
Finished Aug 29 09:17:22 AM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226651305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.1226651305
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.4053131557
Short name T103
Test name
Test status
Simulation time 1210704703 ps
CPU time 45 seconds
Started Aug 29 09:17:32 AM UTC 24
Finished Aug 29 09:18:19 AM UTC 24
Peak memory 253376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053131557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.4053131557
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.816534865
Short name T12
Test name
Test status
Simulation time 6866534998 ps
CPU time 22.37 seconds
Started Aug 29 09:17:21 AM UTC 24
Finished Aug 29 09:17:45 AM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816534865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.816534865
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.830834120
Short name T5
Test name
Test status
Simulation time 520517467 ps
CPU time 15.27 seconds
Started Aug 29 09:17:14 AM UTC 24
Finished Aug 29 09:17:31 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830834120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.830834120
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.1288618575
Short name T6
Test name
Test status
Simulation time 654870706 ps
CPU time 28.25 seconds
Started Aug 29 09:16:47 AM UTC 24
Finished Aug 29 09:17:17 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288618575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1288618575
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.2677976234
Short name T102
Test name
Test status
Simulation time 192359764 ps
CPU time 5.33 seconds
Started Aug 29 09:17:46 AM UTC 24
Finished Aug 29 09:17:52 AM UTC 24
Peak memory 257364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677976234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.2677976234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.1571215417
Short name T23
Test name
Test status
Simulation time 12396524258 ps
CPU time 314.64 seconds
Started Aug 29 09:18:10 AM UTC 24
Finished Aug 29 09:23:30 AM UTC 24
Peak memory 300152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571215417 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.1571215417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.3923481392
Short name T2
Test name
Test status
Simulation time 216486369 ps
CPU time 10.1 seconds
Started Aug 29 09:16:42 AM UTC 24
Finished Aug 29 09:16:53 AM UTC 24
Peak memory 251300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923481392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.3923481392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.1301254759
Short name T19
Test name
Test status
Simulation time 206425088 ps
CPU time 2.81 seconds
Started Aug 29 09:19:44 AM UTC 24
Finished Aug 29 09:19:48 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301254759 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.1301254759
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.1821084728
Short name T90
Test name
Test status
Simulation time 301905428 ps
CPU time 4.48 seconds
Started Aug 29 09:18:56 AM UTC 24
Finished Aug 29 09:19:01 AM UTC 24
Peak memory 257408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821084728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1821084728
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.3475125880
Short name T137
Test name
Test status
Simulation time 18009743326 ps
CPU time 45.3 seconds
Started Aug 29 09:18:47 AM UTC 24
Finished Aug 29 09:19:34 AM UTC 24
Peak memory 257536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475125880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.3475125880
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.477820993
Short name T108
Test name
Test status
Simulation time 5137358106 ps
CPU time 93.25 seconds
Started Aug 29 09:18:31 AM UTC 24
Finished Aug 29 09:20:06 AM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477820993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.477820993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.3620565513
Short name T29
Test name
Test status
Simulation time 477186896 ps
CPU time 7.35 seconds
Started Aug 29 09:18:17 AM UTC 24
Finished Aug 29 09:18:26 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620565513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.3620565513
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.4114996833
Short name T111
Test name
Test status
Simulation time 460312708 ps
CPU time 15.48 seconds
Started Aug 29 09:19:01 AM UTC 24
Finished Aug 29 09:19:18 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114996833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.4114996833
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.2726880605
Short name T107
Test name
Test status
Simulation time 19980738446 ps
CPU time 56 seconds
Started Aug 29 09:19:02 AM UTC 24
Finished Aug 29 09:20:00 AM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726880605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.2726880605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.3253982956
Short name T110
Test name
Test status
Simulation time 4708980226 ps
CPU time 46.48 seconds
Started Aug 29 09:18:28 AM UTC 24
Finished Aug 29 09:19:16 AM UTC 24
Peak memory 253296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253982956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.3253982956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.3735170010
Short name T106
Test name
Test status
Simulation time 1462761412 ps
CPU time 31.68 seconds
Started Aug 29 09:18:27 AM UTC 24
Finished Aug 29 09:19:00 AM UTC 24
Peak memory 251512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735170010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.3735170010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.3518698980
Short name T104
Test name
Test status
Simulation time 215549200 ps
CPU time 8.28 seconds
Started Aug 29 09:18:17 AM UTC 24
Finished Aug 29 09:18:27 AM UTC 24
Peak memory 251684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518698980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3518698980
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.2158026921
Short name T8
Test name
Test status
Simulation time 1871924112 ps
CPU time 84.37 seconds
Started Aug 29 09:19:18 AM UTC 24
Finished Aug 29 09:20:45 AM UTC 24
Peak memory 257524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2158026921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.otp_ctrl_stress_all_with_rand_reset.2158026921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.1643121981
Short name T20
Test name
Test status
Simulation time 3528546397 ps
CPU time 47.05 seconds
Started Aug 29 09:19:17 AM UTC 24
Finished Aug 29 09:20:06 AM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643121981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.1643121981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.3166130472
Short name T436
Test name
Test status
Simulation time 232648050 ps
CPU time 2.71 seconds
Started Aug 29 09:24:49 AM UTC 24
Finished Aug 29 09:24:53 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166130472 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.3166130472
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.1596529585
Short name T343
Test name
Test status
Simulation time 250953625 ps
CPU time 15.85 seconds
Started Aug 29 09:24:37 AM UTC 24
Finished Aug 29 09:24:54 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596529585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.1596529585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.2679679276
Short name T435
Test name
Test status
Simulation time 169950342 ps
CPU time 6.52 seconds
Started Aug 29 09:24:37 AM UTC 24
Finished Aug 29 09:24:44 AM UTC 24
Peak memory 257656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679679276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2679679276
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.1254306305
Short name T172
Test name
Test status
Simulation time 6323882609 ps
CPU time 55.77 seconds
Started Aug 29 09:24:40 AM UTC 24
Finished Aug 29 09:25:37 AM UTC 24
Peak memory 253784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254306305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1254306305
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.3680497337
Short name T315
Test name
Test status
Simulation time 10582135633 ps
CPU time 32.84 seconds
Started Aug 29 09:24:41 AM UTC 24
Finished Aug 29 09:25:16 AM UTC 24
Peak memory 253464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680497337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.3680497337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.1774815877
Short name T247
Test name
Test status
Simulation time 440646357 ps
CPU time 10.81 seconds
Started Aug 29 09:24:37 AM UTC 24
Finished Aug 29 09:24:49 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774815877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.1774815877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.2457875772
Short name T375
Test name
Test status
Simulation time 1054922291 ps
CPU time 15.62 seconds
Started Aug 29 09:24:35 AM UTC 24
Finished Aug 29 09:24:52 AM UTC 24
Peak memory 257372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457875772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.2457875772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.318941029
Short name T362
Test name
Test status
Simulation time 1626506149 ps
CPU time 4.52 seconds
Started Aug 29 09:24:43 AM UTC 24
Finished Aug 29 09:24:48 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318941029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.318941029
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.526258437
Short name T433
Test name
Test status
Simulation time 238126760 ps
CPU time 9.3 seconds
Started Aug 29 09:24:31 AM UTC 24
Finished Aug 29 09:24:42 AM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526258437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.526258437
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.2771770230
Short name T146
Test name
Test status
Simulation time 4582804689 ps
CPU time 209.57 seconds
Started Aug 29 09:24:46 AM UTC 24
Finished Aug 29 09:28:19 AM UTC 24
Peak memory 267948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2771770230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.otp_ctrl_stress_all_with_rand_reset.2771770230
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.4288583582
Short name T386
Test name
Test status
Simulation time 1186457668 ps
CPU time 30.56 seconds
Started Aug 29 09:24:43 AM UTC 24
Finished Aug 29 09:25:14 AM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288583582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.4288583582
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.4277923070
Short name T842
Test name
Test status
Simulation time 457541215 ps
CPU time 6.41 seconds
Started Aug 29 09:37:48 AM UTC 24
Finished Aug 29 09:37:56 AM UTC 24
Peak memory 251524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277923070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.4277923070
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.1630532640
Short name T881
Test name
Test status
Simulation time 1049653015 ps
CPU time 15.82 seconds
Started Aug 29 09:37:49 AM UTC 24
Finished Aug 29 09:38:06 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630532640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.1630532640
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.543941928
Short name T867
Test name
Test status
Simulation time 241174287 ps
CPU time 5.59 seconds
Started Aug 29 09:37:54 AM UTC 24
Finished Aug 29 09:38:00 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543941928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.543941928
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.702391144
Short name T861
Test name
Test status
Simulation time 81446984 ps
CPU time 3.89 seconds
Started Aug 29 09:37:55 AM UTC 24
Finished Aug 29 09:38:00 AM UTC 24
Peak memory 251120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702391144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.702391144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.2258518745
Short name T895
Test name
Test status
Simulation time 2098114794 ps
CPU time 19.84 seconds
Started Aug 29 09:37:55 AM UTC 24
Finished Aug 29 09:38:16 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258518745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.2258518745
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.212783013
Short name T880
Test name
Test status
Simulation time 2786148053 ps
CPU time 7.21 seconds
Started Aug 29 09:37:57 AM UTC 24
Finished Aug 29 09:38:05 AM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212783013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.212783013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.1342996738
Short name T896
Test name
Test status
Simulation time 728656756 ps
CPU time 19.69 seconds
Started Aug 29 09:37:57 AM UTC 24
Finished Aug 29 09:38:17 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342996738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.1342996738
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.2147776197
Short name T882
Test name
Test status
Simulation time 146681875 ps
CPU time 6.2 seconds
Started Aug 29 09:37:59 AM UTC 24
Finished Aug 29 09:38:06 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147776197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.2147776197
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.3090888521
Short name T887
Test name
Test status
Simulation time 529743606 ps
CPU time 6.75 seconds
Started Aug 29 09:38:03 AM UTC 24
Finished Aug 29 09:38:11 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090888521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3090888521
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.1279928005
Short name T884
Test name
Test status
Simulation time 143515090 ps
CPU time 5.37 seconds
Started Aug 29 09:38:04 AM UTC 24
Finished Aug 29 09:38:10 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279928005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1279928005
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.355416326
Short name T890
Test name
Test status
Simulation time 118768258 ps
CPU time 7.27 seconds
Started Aug 29 09:38:04 AM UTC 24
Finished Aug 29 09:38:12 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355416326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.355416326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.3759554581
Short name T885
Test name
Test status
Simulation time 340072022 ps
CPU time 5.71 seconds
Started Aug 29 09:38:04 AM UTC 24
Finished Aug 29 09:38:10 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759554581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.3759554581
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.1578214826
Short name T893
Test name
Test status
Simulation time 456269661 ps
CPU time 10.69 seconds
Started Aug 29 09:38:04 AM UTC 24
Finished Aug 29 09:38:15 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578214826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.1578214826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.3074688837
Short name T889
Test name
Test status
Simulation time 146461999 ps
CPU time 6.82 seconds
Started Aug 29 09:38:04 AM UTC 24
Finished Aug 29 09:38:12 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074688837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3074688837
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.3542122446
Short name T886
Test name
Test status
Simulation time 143484514 ps
CPU time 4.56 seconds
Started Aug 29 09:38:05 AM UTC 24
Finished Aug 29 09:38:11 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542122446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3542122446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.477996903
Short name T55
Test name
Test status
Simulation time 136859496 ps
CPU time 4.91 seconds
Started Aug 29 09:38:06 AM UTC 24
Finished Aug 29 09:38:13 AM UTC 24
Peak memory 253332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477996903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.477996903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.3622326190
Short name T434
Test name
Test status
Simulation time 953739671 ps
CPU time 2.78 seconds
Started Aug 29 09:25:13 AM UTC 24
Finished Aug 29 09:25:16 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622326190 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.3622326190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.2911272828
Short name T318
Test name
Test status
Simulation time 2758254136 ps
CPU time 18.6 seconds
Started Aug 29 09:25:02 AM UTC 24
Finished Aug 29 09:25:22 AM UTC 24
Peak memory 257556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911272828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2911272828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.1668950922
Short name T341
Test name
Test status
Simulation time 3461501128 ps
CPU time 66.28 seconds
Started Aug 29 09:24:58 AM UTC 24
Finished Aug 29 09:26:06 AM UTC 24
Peak memory 263864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668950922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1668950922
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.1230007585
Short name T177
Test name
Test status
Simulation time 1479090019 ps
CPU time 53.07 seconds
Started Aug 29 09:25:02 AM UTC 24
Finished Aug 29 09:25:57 AM UTC 24
Peak memory 251584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230007585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.1230007585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.1781389256
Short name T215
Test name
Test status
Simulation time 1403219582 ps
CPU time 23.44 seconds
Started Aug 29 09:25:03 AM UTC 24
Finished Aug 29 09:25:28 AM UTC 24
Peak memory 257468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781389256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.1781389256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.2494078470
Short name T133
Test name
Test status
Simulation time 190924289 ps
CPU time 6.86 seconds
Started Aug 29 09:24:55 AM UTC 24
Finished Aug 29 09:25:03 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494078470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.2494078470
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.751716936
Short name T438
Test name
Test status
Simulation time 2928339297 ps
CPU time 10.96 seconds
Started Aug 29 09:24:53 AM UTC 24
Finished Aug 29 09:25:06 AM UTC 24
Peak memory 257428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751716936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.751716936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.1496640569
Short name T317
Test name
Test status
Simulation time 306346445 ps
CPU time 10.68 seconds
Started Aug 29 09:25:07 AM UTC 24
Finished Aug 29 09:25:18 AM UTC 24
Peak memory 251536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496640569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1496640569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.1614706249
Short name T437
Test name
Test status
Simulation time 2460735503 ps
CPU time 6.61 seconds
Started Aug 29 09:24:49 AM UTC 24
Finished Aug 29 09:24:57 AM UTC 24
Peak memory 251360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614706249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.1614706249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.4025548708
Short name T344
Test name
Test status
Simulation time 18355790461 ps
CPU time 111.55 seconds
Started Aug 29 09:25:10 AM UTC 24
Finished Aug 29 09:27:04 AM UTC 24
Peak memory 255424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025548708 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.4025548708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.3553607378
Short name T249
Test name
Test status
Simulation time 13674439897 ps
CPU time 114.3 seconds
Started Aug 29 09:25:10 AM UTC 24
Finished Aug 29 09:27:07 AM UTC 24
Peak memory 267768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3553607378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.otp_ctrl_stress_all_with_rand_reset.3553607378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.2479314321
Short name T892
Test name
Test status
Simulation time 1629488908 ps
CPU time 6.31 seconds
Started Aug 29 09:38:07 AM UTC 24
Finished Aug 29 09:38:15 AM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479314321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2479314321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.1493284686
Short name T894
Test name
Test status
Simulation time 232477521 ps
CPU time 4.65 seconds
Started Aug 29 09:38:09 AM UTC 24
Finished Aug 29 09:38:16 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493284686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.1493284686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.3488361385
Short name T899
Test name
Test status
Simulation time 249764076 ps
CPU time 6.07 seconds
Started Aug 29 09:38:12 AM UTC 24
Finished Aug 29 09:38:19 AM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488361385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3488361385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.1878520976
Short name T918
Test name
Test status
Simulation time 307390389 ps
CPU time 18.42 seconds
Started Aug 29 09:38:12 AM UTC 24
Finished Aug 29 09:38:31 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878520976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.1878520976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.1384791272
Short name T897
Test name
Test status
Simulation time 444132898 ps
CPU time 5.18 seconds
Started Aug 29 09:38:12 AM UTC 24
Finished Aug 29 09:38:18 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384791272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.1384791272
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.4205481877
Short name T900
Test name
Test status
Simulation time 327354779 ps
CPU time 5.96 seconds
Started Aug 29 09:38:13 AM UTC 24
Finished Aug 29 09:38:21 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205481877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.4205481877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.1724255891
Short name T903
Test name
Test status
Simulation time 1743781924 ps
CPU time 7.34 seconds
Started Aug 29 09:38:14 AM UTC 24
Finished Aug 29 09:38:22 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724255891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.1724255891
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.993158965
Short name T907
Test name
Test status
Simulation time 293427283 ps
CPU time 11.08 seconds
Started Aug 29 09:38:14 AM UTC 24
Finished Aug 29 09:38:26 AM UTC 24
Peak memory 251144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993158965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.993158965
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.1492988766
Short name T901
Test name
Test status
Simulation time 153145378 ps
CPU time 6.13 seconds
Started Aug 29 09:38:14 AM UTC 24
Finished Aug 29 09:38:21 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492988766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.1492988766
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.1660524070
Short name T902
Test name
Test status
Simulation time 241815340 ps
CPU time 5.54 seconds
Started Aug 29 09:38:15 AM UTC 24
Finished Aug 29 09:38:21 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660524070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.1660524070
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.2747806804
Short name T908
Test name
Test status
Simulation time 174093489 ps
CPU time 8.89 seconds
Started Aug 29 09:38:16 AM UTC 24
Finished Aug 29 09:38:26 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747806804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.2747806804
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.32293881
Short name T905
Test name
Test status
Simulation time 225573269 ps
CPU time 6.52 seconds
Started Aug 29 09:38:17 AM UTC 24
Finished Aug 29 09:38:24 AM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32293881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.32293881
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.2438508853
Short name T904
Test name
Test status
Simulation time 299512567 ps
CPU time 6.05 seconds
Started Aug 29 09:38:17 AM UTC 24
Finished Aug 29 09:38:24 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438508853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.2438508853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.531392711
Short name T906
Test name
Test status
Simulation time 168022669 ps
CPU time 4.93 seconds
Started Aug 29 09:38:18 AM UTC 24
Finished Aug 29 09:38:24 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531392711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.531392711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.347734304
Short name T915
Test name
Test status
Simulation time 744959216 ps
CPU time 11.4 seconds
Started Aug 29 09:38:18 AM UTC 24
Finished Aug 29 09:38:31 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347734304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.347734304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.1178176472
Short name T910
Test name
Test status
Simulation time 149243522 ps
CPU time 6.16 seconds
Started Aug 29 09:38:20 AM UTC 24
Finished Aug 29 09:38:28 AM UTC 24
Peak memory 251176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178176472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.1178176472
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.1447417097
Short name T920
Test name
Test status
Simulation time 148502200 ps
CPU time 10.08 seconds
Started Aug 29 09:38:20 AM UTC 24
Finished Aug 29 09:38:32 AM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447417097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.1447417097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.344733671
Short name T914
Test name
Test status
Simulation time 637307456 ps
CPU time 7.66 seconds
Started Aug 29 09:38:20 AM UTC 24
Finished Aug 29 09:38:29 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344733671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.344733671
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.3948918693
Short name T218
Test name
Test status
Simulation time 174865644 ps
CPU time 2.51 seconds
Started Aug 29 09:25:29 AM UTC 24
Finished Aug 29 09:25:33 AM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948918693 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.3948918693
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.2510665792
Short name T217
Test name
Test status
Simulation time 1083352967 ps
CPU time 9.01 seconds
Started Aug 29 09:25:21 AM UTC 24
Finished Aug 29 09:25:32 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510665792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.2510665792
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.2683807176
Short name T440
Test name
Test status
Simulation time 609918027 ps
CPU time 16.11 seconds
Started Aug 29 09:25:21 AM UTC 24
Finished Aug 29 09:25:39 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683807176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.2683807176
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.3791173628
Short name T376
Test name
Test status
Simulation time 1979713435 ps
CPU time 30.03 seconds
Started Aug 29 09:25:21 AM UTC 24
Finished Aug 29 09:25:53 AM UTC 24
Peak memory 250420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791173628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.3791173628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.2051515680
Short name T183
Test name
Test status
Simulation time 1576728727 ps
CPU time 31.36 seconds
Started Aug 29 09:25:23 AM UTC 24
Finished Aug 29 09:25:56 AM UTC 24
Peak memory 257600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051515680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.2051515680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.4060912007
Short name T238
Test name
Test status
Simulation time 8870872491 ps
CPU time 33.95 seconds
Started Aug 29 09:25:23 AM UTC 24
Finished Aug 29 09:25:58 AM UTC 24
Peak memory 253464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060912007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.4060912007
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.744435826
Short name T216
Test name
Test status
Simulation time 578232891 ps
CPU time 7.97 seconds
Started Aug 29 09:25:21 AM UTC 24
Finished Aug 29 09:25:30 AM UTC 24
Peak memory 250880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744435826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.744435826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.2872652285
Short name T219
Test name
Test status
Simulation time 5880102911 ps
CPU time 14.46 seconds
Started Aug 29 09:25:17 AM UTC 24
Finished Aug 29 09:25:33 AM UTC 24
Peak memory 253340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872652285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.2872652285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.3367108671
Short name T220
Test name
Test status
Simulation time 147846655 ps
CPU time 5.3 seconds
Started Aug 29 09:25:29 AM UTC 24
Finished Aug 29 09:25:36 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367108671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.3367108671
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.1778957085
Short name T214
Test name
Test status
Simulation time 171683909 ps
CPU time 7.93 seconds
Started Aug 29 09:25:16 AM UTC 24
Finished Aug 29 09:25:25 AM UTC 24
Peak memory 251304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778957085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.1778957085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.723639453
Short name T443
Test name
Test status
Simulation time 910297761 ps
CPU time 19.38 seconds
Started Aug 29 09:25:29 AM UTC 24
Finished Aug 29 09:25:50 AM UTC 24
Peak memory 253632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723639453 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.723639453
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.1264870554
Short name T141
Test name
Test status
Simulation time 29468051093 ps
CPU time 149.07 seconds
Started Aug 29 09:25:29 AM UTC 24
Finished Aug 29 09:28:01 AM UTC 24
Peak memory 269996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1264870554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.otp_ctrl_stress_all_with_rand_reset.1264870554
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.2649651867
Short name T406
Test name
Test status
Simulation time 986319544 ps
CPU time 36.34 seconds
Started Aug 29 09:25:29 AM UTC 24
Finished Aug 29 09:26:07 AM UTC 24
Peak memory 257784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649651867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.2649651867
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.2615314891
Short name T916
Test name
Test status
Simulation time 2463178536 ps
CPU time 11.21 seconds
Started Aug 29 09:38:26 AM UTC 24
Finished Aug 29 09:38:39 AM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615314891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.2615314891
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.2116856840
Short name T922
Test name
Test status
Simulation time 711571309 ps
CPU time 5.42 seconds
Started Aug 29 09:38:26 AM UTC 24
Finished Aug 29 09:38:33 AM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116856840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.2116856840
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.3678926010
Short name T122
Test name
Test status
Simulation time 2195143336 ps
CPU time 8.12 seconds
Started Aug 29 09:38:27 AM UTC 24
Finished Aug 29 09:38:36 AM UTC 24
Peak memory 251268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678926010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.3678926010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.4235590251
Short name T923
Test name
Test status
Simulation time 1075648967 ps
CPU time 7.75 seconds
Started Aug 29 09:38:27 AM UTC 24
Finished Aug 29 09:38:35 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235590251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.4235590251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.1489417906
Short name T921
Test name
Test status
Simulation time 420022642 ps
CPU time 4.78 seconds
Started Aug 29 09:38:27 AM UTC 24
Finished Aug 29 09:38:33 AM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489417906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.1489417906
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.2810898918
Short name T931
Test name
Test status
Simulation time 256133348 ps
CPU time 9.4 seconds
Started Aug 29 09:38:27 AM UTC 24
Finished Aug 29 09:38:37 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810898918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.2810898918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.4105718582
Short name T929
Test name
Test status
Simulation time 399629781 ps
CPU time 5.5 seconds
Started Aug 29 09:38:30 AM UTC 24
Finished Aug 29 09:38:36 AM UTC 24
Peak memory 251436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105718582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.4105718582
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.458769155
Short name T948
Test name
Test status
Simulation time 2046867587 ps
CPU time 17.37 seconds
Started Aug 29 09:38:30 AM UTC 24
Finished Aug 29 09:38:48 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458769155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.458769155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.2111973234
Short name T77
Test name
Test status
Simulation time 477556356 ps
CPU time 4.56 seconds
Started Aug 29 09:38:30 AM UTC 24
Finished Aug 29 09:38:35 AM UTC 24
Peak memory 251268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111973234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.2111973234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.2340223773
Short name T934
Test name
Test status
Simulation time 692433228 ps
CPU time 6.93 seconds
Started Aug 29 09:38:30 AM UTC 24
Finished Aug 29 09:38:38 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340223773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.2340223773
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.2641501121
Short name T924
Test name
Test status
Simulation time 637848682 ps
CPU time 4.59 seconds
Started Aug 29 09:38:30 AM UTC 24
Finished Aug 29 09:38:36 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641501121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.2641501121
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.3538694370
Short name T933
Test name
Test status
Simulation time 220195461 ps
CPU time 6.62 seconds
Started Aug 29 09:38:30 AM UTC 24
Finished Aug 29 09:38:38 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538694370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.3538694370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.2399949951
Short name T932
Test name
Test status
Simulation time 2297598700 ps
CPU time 6.18 seconds
Started Aug 29 09:38:30 AM UTC 24
Finished Aug 29 09:38:37 AM UTC 24
Peak memory 251100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399949951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.2399949951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.1163832792
Short name T927
Test name
Test status
Simulation time 120160389 ps
CPU time 5.07 seconds
Started Aug 29 09:38:30 AM UTC 24
Finished Aug 29 09:38:36 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163832792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.1163832792
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.3891262965
Short name T925
Test name
Test status
Simulation time 701397215 ps
CPU time 4.55 seconds
Started Aug 29 09:38:30 AM UTC 24
Finished Aug 29 09:38:36 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891262965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.3891262965
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.346308971
Short name T962
Test name
Test status
Simulation time 1784241670 ps
CPU time 21.1 seconds
Started Aug 29 09:38:30 AM UTC 24
Finished Aug 29 09:38:52 AM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346308971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.346308971
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.2862290762
Short name T928
Test name
Test status
Simulation time 259783331 ps
CPU time 4.87 seconds
Started Aug 29 09:38:30 AM UTC 24
Finished Aug 29 09:38:36 AM UTC 24
Peak memory 251124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862290762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.2862290762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.2830202370
Short name T963
Test name
Test status
Simulation time 340835406 ps
CPU time 16.56 seconds
Started Aug 29 09:38:35 AM UTC 24
Finished Aug 29 09:38:53 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830202370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2830202370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.4014142805
Short name T445
Test name
Test status
Simulation time 66812102 ps
CPU time 2.76 seconds
Started Aug 29 09:25:53 AM UTC 24
Finished Aug 29 09:25:57 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014142805 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.4014142805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.4047513820
Short name T442
Test name
Test status
Simulation time 907049051 ps
CPU time 7.02 seconds
Started Aug 29 09:25:41 AM UTC 24
Finished Aug 29 09:25:49 AM UTC 24
Peak memory 251608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047513820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.4047513820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.4240783899
Short name T444
Test name
Test status
Simulation time 644208203 ps
CPU time 17.44 seconds
Started Aug 29 09:25:37 AM UTC 24
Finished Aug 29 09:25:55 AM UTC 24
Peak memory 251520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240783899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.4240783899
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.1571542537
Short name T441
Test name
Test status
Simulation time 469408227 ps
CPU time 8.33 seconds
Started Aug 29 09:25:34 AM UTC 24
Finished Aug 29 09:25:44 AM UTC 24
Peak memory 257464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571542537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.1571542537
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.862955722
Short name T439
Test name
Test status
Simulation time 172738288 ps
CPU time 6.5 seconds
Started Aug 29 09:25:31 AM UTC 24
Finished Aug 29 09:25:39 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862955722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.862955722
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.2809647144
Short name T377
Test name
Test status
Simulation time 504207425 ps
CPU time 23.2 seconds
Started Aug 29 09:25:41 AM UTC 24
Finished Aug 29 09:26:05 AM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809647144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.2809647144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.803239453
Short name T368
Test name
Test status
Simulation time 662149146 ps
CPU time 22.04 seconds
Started Aug 29 09:25:34 AM UTC 24
Finished Aug 29 09:25:58 AM UTC 24
Peak memory 253236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803239453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.803239453
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.56781457
Short name T233
Test name
Test status
Simulation time 9568107114 ps
CPU time 41.8 seconds
Started Aug 29 09:25:32 AM UTC 24
Finished Aug 29 09:26:15 AM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56781457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.56781457
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.1829805536
Short name T446
Test name
Test status
Simulation time 1587320414 ps
CPU time 25.05 seconds
Started Aug 29 09:25:31 AM UTC 24
Finished Aug 29 09:25:57 AM UTC 24
Peak memory 251368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829805536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1829805536
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.3118373258
Short name T242
Test name
Test status
Simulation time 176194396710 ps
CPU time 345.08 seconds
Started Aug 29 09:25:52 AM UTC 24
Finished Aug 29 09:31:42 AM UTC 24
Peak memory 288216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118373258 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.3118373258
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.1708162641
Short name T89
Test name
Test status
Simulation time 6612568656 ps
CPU time 102.88 seconds
Started Aug 29 09:25:50 AM UTC 24
Finished Aug 29 09:27:35 AM UTC 24
Peak memory 267948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1708162641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.otp_ctrl_stress_all_with_rand_reset.1708162641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.2580308232
Short name T450
Test name
Test status
Simulation time 8902230254 ps
CPU time 30.12 seconds
Started Aug 29 09:25:45 AM UTC 24
Finished Aug 29 09:26:16 AM UTC 24
Peak memory 257592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580308232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.2580308232
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.4289164262
Short name T936
Test name
Test status
Simulation time 113371539 ps
CPU time 3.12 seconds
Started Aug 29 09:38:35 AM UTC 24
Finished Aug 29 09:38:39 AM UTC 24
Peak memory 251332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289164262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.4289164262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.1021944534
Short name T964
Test name
Test status
Simulation time 669909509 ps
CPU time 17.15 seconds
Started Aug 29 09:38:35 AM UTC 24
Finished Aug 29 09:38:53 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021944534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.1021944534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.369130741
Short name T911
Test name
Test status
Simulation time 2291881773 ps
CPU time 6.82 seconds
Started Aug 29 09:38:35 AM UTC 24
Finished Aug 29 09:38:43 AM UTC 24
Peak memory 251488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369130741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.369130741
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.1342073518
Short name T947
Test name
Test status
Simulation time 223977934 ps
CPU time 9.95 seconds
Started Aug 29 09:38:35 AM UTC 24
Finished Aug 29 09:38:46 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342073518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.1342073518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.900528275
Short name T937
Test name
Test status
Simulation time 335578070 ps
CPU time 3.22 seconds
Started Aug 29 09:38:35 AM UTC 24
Finished Aug 29 09:38:39 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900528275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.900528275
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.3382538357
Short name T306
Test name
Test status
Simulation time 296187691 ps
CPU time 8.52 seconds
Started Aug 29 09:38:35 AM UTC 24
Finished Aug 29 09:38:45 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382538357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.3382538357
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.1007164535
Short name T942
Test name
Test status
Simulation time 2278000994 ps
CPU time 6.97 seconds
Started Aug 29 09:38:35 AM UTC 24
Finished Aug 29 09:38:43 AM UTC 24
Peak memory 251268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007164535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.1007164535
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.2384198878
Short name T917
Test name
Test status
Simulation time 264989995 ps
CPU time 4.39 seconds
Started Aug 29 09:38:35 AM UTC 24
Finished Aug 29 09:38:41 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384198878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.2384198878
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.694868101
Short name T943
Test name
Test status
Simulation time 1913599101 ps
CPU time 5.73 seconds
Started Aug 29 09:38:37 AM UTC 24
Finished Aug 29 09:38:44 AM UTC 24
Peak memory 251056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694868101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.694868101
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.4066227142
Short name T953
Test name
Test status
Simulation time 668855367 ps
CPU time 12.11 seconds
Started Aug 29 09:38:37 AM UTC 24
Finished Aug 29 09:38:50 AM UTC 24
Peak memory 253236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066227142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.4066227142
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.4062020051
Short name T944
Test name
Test status
Simulation time 642990023 ps
CPU time 6.15 seconds
Started Aug 29 09:38:37 AM UTC 24
Finished Aug 29 09:38:44 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062020051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.4062020051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.1208081360
Short name T939
Test name
Test status
Simulation time 127893732 ps
CPU time 4.53 seconds
Started Aug 29 09:38:37 AM UTC 24
Finished Aug 29 09:38:43 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208081360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.1208081360
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.1119500492
Short name T946
Test name
Test status
Simulation time 346320366 ps
CPU time 6.4 seconds
Started Aug 29 09:38:37 AM UTC 24
Finished Aug 29 09:38:45 AM UTC 24
Peak memory 251504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119500492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.1119500492
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.2776075685
Short name T941
Test name
Test status
Simulation time 294462157 ps
CPU time 4.84 seconds
Started Aug 29 09:38:37 AM UTC 24
Finished Aug 29 09:38:43 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776075685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.2776075685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.2248927233
Short name T879
Test name
Test status
Simulation time 133661607 ps
CPU time 3.12 seconds
Started Aug 29 09:38:37 AM UTC 24
Finished Aug 29 09:38:41 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248927233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.2248927233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.2450529529
Short name T969
Test name
Test status
Simulation time 1130476705 ps
CPU time 17.05 seconds
Started Aug 29 09:38:37 AM UTC 24
Finished Aug 29 09:38:56 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450529529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.2450529529
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.760701726
Short name T926
Test name
Test status
Simulation time 280744844 ps
CPU time 3.86 seconds
Started Aug 29 09:38:37 AM UTC 24
Finished Aug 29 09:38:42 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760701726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.760701726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.3135198408
Short name T919
Test name
Test status
Simulation time 173462071 ps
CPU time 4.09 seconds
Started Aug 29 09:38:37 AM UTC 24
Finished Aug 29 09:38:43 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135198408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.3135198408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.2712346122
Short name T945
Test name
Test status
Simulation time 545788394 ps
CPU time 5.83 seconds
Started Aug 29 09:38:37 AM UTC 24
Finished Aug 29 09:38:44 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712346122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2712346122
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.3772159693
Short name T972
Test name
Test status
Simulation time 1448519926 ps
CPU time 11.41 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:57 AM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772159693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.3772159693
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.2120143509
Short name T449
Test name
Test status
Simulation time 213363009 ps
CPU time 2.04 seconds
Started Aug 29 09:26:12 AM UTC 24
Finished Aug 29 09:26:15 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120143509 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.2120143509
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.2008052719
Short name T69
Test name
Test status
Simulation time 1606771013 ps
CPU time 16.23 seconds
Started Aug 29 09:26:00 AM UTC 24
Finished Aug 29 09:26:17 AM UTC 24
Peak memory 251584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008052719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.2008052719
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.3511488676
Short name T226
Test name
Test status
Simulation time 1402582073 ps
CPU time 13.48 seconds
Started Aug 29 09:26:00 AM UTC 24
Finished Aug 29 09:26:15 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511488676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.3511488676
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.2748856786
Short name T493
Test name
Test status
Simulation time 24291962746 ps
CPU time 131.69 seconds
Started Aug 29 09:26:00 AM UTC 24
Finished Aug 29 09:28:14 AM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748856786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.2748856786
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.315249950
Short name T53
Test name
Test status
Simulation time 197542650 ps
CPU time 4.31 seconds
Started Aug 29 09:25:56 AM UTC 24
Finished Aug 29 09:26:01 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315249950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.315249950
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.1346077277
Short name T451
Test name
Test status
Simulation time 707866648 ps
CPU time 16.63 seconds
Started Aug 29 09:26:02 AM UTC 24
Finished Aug 29 09:26:20 AM UTC 24
Peak memory 257468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346077277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.1346077277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.3109706933
Short name T128
Test name
Test status
Simulation time 280903830 ps
CPU time 9.45 seconds
Started Aug 29 09:25:57 AM UTC 24
Finished Aug 29 09:26:08 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109706933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.3109706933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.2523605581
Short name T373
Test name
Test status
Simulation time 2527157416 ps
CPU time 30.05 seconds
Started Aug 29 09:25:57 AM UTC 24
Finished Aug 29 09:26:29 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523605581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.2523605581
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.3351418494
Short name T360
Test name
Test status
Simulation time 703730648 ps
CPU time 11.54 seconds
Started Aug 29 09:26:08 AM UTC 24
Finished Aug 29 09:26:20 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351418494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.3351418494
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.3876080839
Short name T448
Test name
Test status
Simulation time 1356136971 ps
CPU time 10.89 seconds
Started Aug 29 09:25:55 AM UTC 24
Finished Aug 29 09:26:06 AM UTC 24
Peak memory 251752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876080839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.3876080839
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.1308769500
Short name T391
Test name
Test status
Simulation time 6262376566 ps
CPU time 96.66 seconds
Started Aug 29 09:26:12 AM UTC 24
Finished Aug 29 09:27:51 AM UTC 24
Peak memory 269812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308769500 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.1308769500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.1534250989
Short name T453
Test name
Test status
Simulation time 5692948228 ps
CPU time 17.8 seconds
Started Aug 29 09:26:12 AM UTC 24
Finished Aug 29 09:26:31 AM UTC 24
Peak memory 251504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534250989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.1534250989
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.2961571003
Short name T83
Test name
Test status
Simulation time 499681140 ps
CPU time 4.61 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:50 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961571003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2961571003
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.3063297974
Short name T980
Test name
Test status
Simulation time 1086454134 ps
CPU time 14.52 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:39:00 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063297974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.3063297974
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.1553067485
Short name T951
Test name
Test status
Simulation time 119061100 ps
CPU time 4.34 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:50 AM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553067485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.1553067485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.1121687697
Short name T959
Test name
Test status
Simulation time 1757705524 ps
CPU time 5.76 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:52 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121687697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.1121687697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.2682187547
Short name T955
Test name
Test status
Simulation time 264640202 ps
CPU time 5.52 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:51 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682187547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.2682187547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.43757209
Short name T970
Test name
Test status
Simulation time 606149213 ps
CPU time 9.93 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:56 AM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43757209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.43757209
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.4222741184
Short name T974
Test name
Test status
Simulation time 1672320974 ps
CPU time 11.63 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:58 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222741184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.4222741184
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.2382632808
Short name T950
Test name
Test status
Simulation time 202619928 ps
CPU time 4.18 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:50 AM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382632808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.2382632808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.1352333594
Short name T954
Test name
Test status
Simulation time 1287494021 ps
CPU time 5.27 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:51 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352333594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1352333594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.2728449955
Short name T956
Test name
Test status
Simulation time 104870508 ps
CPU time 5.36 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:51 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728449955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.2728449955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.4181098925
Short name T966
Test name
Test status
Simulation time 192506298 ps
CPU time 9.05 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:55 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181098925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.4181098925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.730210161
Short name T952
Test name
Test status
Simulation time 491562971 ps
CPU time 4.08 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:50 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730210161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.730210161
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.4118891572
Short name T975
Test name
Test status
Simulation time 4140859252 ps
CPU time 12.89 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:59 AM UTC 24
Peak memory 251136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118891572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.4118891572
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.629619670
Short name T957
Test name
Test status
Simulation time 184778163 ps
CPU time 5.23 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:51 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629619670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.629619670
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.1088930629
Short name T968
Test name
Test status
Simulation time 755704226 ps
CPU time 9.25 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:55 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088930629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.1088930629
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.3648824763
Short name T960
Test name
Test status
Simulation time 149771536 ps
CPU time 5.43 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:52 AM UTC 24
Peak memory 253272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648824763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.3648824763
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.3187738226
Short name T965
Test name
Test status
Simulation time 678666089 ps
CPU time 7.81 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:54 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187738226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.3187738226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.517444215
Short name T961
Test name
Test status
Simulation time 159532280 ps
CPU time 5.74 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:52 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517444215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.517444215
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.1662306399
Short name T973
Test name
Test status
Simulation time 2050224311 ps
CPU time 10.73 seconds
Started Aug 29 09:38:45 AM UTC 24
Finished Aug 29 09:38:57 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662306399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1662306399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.956837210
Short name T455
Test name
Test status
Simulation time 78136413 ps
CPU time 2.43 seconds
Started Aug 29 09:26:30 AM UTC 24
Finished Aug 29 09:26:33 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956837210 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.956837210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.2827912276
Short name T46
Test name
Test status
Simulation time 975920862 ps
CPU time 16.05 seconds
Started Aug 29 09:26:17 AM UTC 24
Finished Aug 29 09:26:34 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827912276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.2827912276
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.3251875102
Short name T342
Test name
Test status
Simulation time 1160760208 ps
CPU time 36.4 seconds
Started Aug 29 09:26:17 AM UTC 24
Finished Aug 29 09:26:55 AM UTC 24
Peak memory 251512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251875102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.3251875102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.4120727381
Short name T407
Test name
Test status
Simulation time 2116497383 ps
CPU time 21.49 seconds
Started Aug 29 09:26:16 AM UTC 24
Finished Aug 29 09:26:38 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120727381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.4120727381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.48214627
Short name T176
Test name
Test status
Simulation time 1490877971 ps
CPU time 7.19 seconds
Started Aug 29 09:26:12 AM UTC 24
Finished Aug 29 09:26:20 AM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48214627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.48214627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.1927462037
Short name T210
Test name
Test status
Simulation time 479638518 ps
CPU time 11.47 seconds
Started Aug 29 09:26:22 AM UTC 24
Finished Aug 29 09:26:35 AM UTC 24
Peak memory 251584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927462037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1927462037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.1452664980
Short name T456
Test name
Test status
Simulation time 438403490 ps
CPU time 15.83 seconds
Started Aug 29 09:26:22 AM UTC 24
Finished Aug 29 09:26:39 AM UTC 24
Peak memory 251072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452664980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.1452664980
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.2977319094
Short name T243
Test name
Test status
Simulation time 7881241459 ps
CPU time 46.37 seconds
Started Aug 29 09:26:15 AM UTC 24
Finished Aug 29 09:27:03 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977319094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.2977319094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.3839908034
Short name T457
Test name
Test status
Simulation time 2667960666 ps
CPU time 28.51 seconds
Started Aug 29 09:26:13 AM UTC 24
Finished Aug 29 09:26:43 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839908034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.3839908034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.219225886
Short name T454
Test name
Test status
Simulation time 139264549 ps
CPU time 8.08 seconds
Started Aug 29 09:26:22 AM UTC 24
Finished Aug 29 09:26:31 AM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219225886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.219225886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.2137736047
Short name T452
Test name
Test status
Simulation time 1009472282 ps
CPU time 10.96 seconds
Started Aug 29 09:26:12 AM UTC 24
Finished Aug 29 09:26:24 AM UTC 24
Peak memory 251368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137736047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2137736047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.3243012075
Short name T497
Test name
Test status
Simulation time 13923971127 ps
CPU time 113.85 seconds
Started Aug 29 09:26:24 AM UTC 24
Finished Aug 29 09:28:21 AM UTC 24
Peak memory 259668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243012075 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.3243012075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.1920508240
Short name T479
Test name
Test status
Simulation time 31547837110 ps
CPU time 81.81 seconds
Started Aug 29 09:26:22 AM UTC 24
Finished Aug 29 09:27:46 AM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920508240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.1920508240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.778503772
Short name T977
Test name
Test status
Simulation time 110966112 ps
CPU time 3.74 seconds
Started Aug 29 09:38:55 AM UTC 24
Finished Aug 29 09:39:00 AM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778503772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.778503772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.2937251946
Short name T1009
Test name
Test status
Simulation time 4127291965 ps
CPU time 12.5 seconds
Started Aug 29 09:38:55 AM UTC 24
Finished Aug 29 09:39:09 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937251946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.2937251946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.1470788654
Short name T979
Test name
Test status
Simulation time 182073841 ps
CPU time 3.98 seconds
Started Aug 29 09:38:55 AM UTC 24
Finished Aug 29 09:39:00 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470788654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.1470788654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.3578734933
Short name T991
Test name
Test status
Simulation time 1773886243 ps
CPU time 7.33 seconds
Started Aug 29 09:38:55 AM UTC 24
Finished Aug 29 09:39:03 AM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578734933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.3578734933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.195418107
Short name T981
Test name
Test status
Simulation time 1536505255 ps
CPU time 4.4 seconds
Started Aug 29 09:38:55 AM UTC 24
Finished Aug 29 09:39:01 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195418107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.195418107
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.3368858728
Short name T985
Test name
Test status
Simulation time 686148281 ps
CPU time 5.78 seconds
Started Aug 29 09:38:55 AM UTC 24
Finished Aug 29 09:39:02 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368858728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.3368858728
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.3935841555
Short name T992
Test name
Test status
Simulation time 2390945962 ps
CPU time 7.17 seconds
Started Aug 29 09:38:55 AM UTC 24
Finished Aug 29 09:39:04 AM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935841555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.3935841555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.1421820793
Short name T999
Test name
Test status
Simulation time 659012800 ps
CPU time 8.69 seconds
Started Aug 29 09:38:55 AM UTC 24
Finished Aug 29 09:39:05 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421820793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.1421820793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.4045040402
Short name T982
Test name
Test status
Simulation time 205640334 ps
CPU time 4.96 seconds
Started Aug 29 09:38:55 AM UTC 24
Finished Aug 29 09:39:01 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045040402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.4045040402
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.4146447756
Short name T1034
Test name
Test status
Simulation time 2257703121 ps
CPU time 20.78 seconds
Started Aug 29 09:38:55 AM UTC 24
Finished Aug 29 09:39:18 AM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146447756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.4146447756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.971135907
Short name T990
Test name
Test status
Simulation time 2466353417 ps
CPU time 6.62 seconds
Started Aug 29 09:38:55 AM UTC 24
Finished Aug 29 09:39:03 AM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971135907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.971135907
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.3818719288
Short name T978
Test name
Test status
Simulation time 362399185 ps
CPU time 3.53 seconds
Started Aug 29 09:38:55 AM UTC 24
Finished Aug 29 09:39:00 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818719288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3818719288
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.101104138
Short name T984
Test name
Test status
Simulation time 1771338253 ps
CPU time 5.38 seconds
Started Aug 29 09:38:55 AM UTC 24
Finished Aug 29 09:39:02 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101104138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.101104138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.3014498264
Short name T1023
Test name
Test status
Simulation time 3129637491 ps
CPU time 16.67 seconds
Started Aug 29 09:38:56 AM UTC 24
Finished Aug 29 09:39:13 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014498264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.3014498264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.300537777
Short name T976
Test name
Test status
Simulation time 415112992 ps
CPU time 3.02 seconds
Started Aug 29 09:38:56 AM UTC 24
Finished Aug 29 09:39:00 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300537777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.300537777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.3082159311
Short name T1028
Test name
Test status
Simulation time 2407034875 ps
CPU time 19.13 seconds
Started Aug 29 09:38:56 AM UTC 24
Finished Aug 29 09:39:16 AM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082159311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.3082159311
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.2965003810
Short name T993
Test name
Test status
Simulation time 2768167485 ps
CPU time 7.13 seconds
Started Aug 29 09:38:56 AM UTC 24
Finished Aug 29 09:39:04 AM UTC 24
Peak memory 251472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965003810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.2965003810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.3174266571
Short name T1003
Test name
Test status
Simulation time 2513942272 ps
CPU time 9.48 seconds
Started Aug 29 09:38:56 AM UTC 24
Finished Aug 29 09:39:06 AM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174266571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.3174266571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.1768612667
Short name T983
Test name
Test status
Simulation time 171673924 ps
CPU time 4.73 seconds
Started Aug 29 09:38:56 AM UTC 24
Finished Aug 29 09:39:02 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768612667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1768612667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.1076111430
Short name T1029
Test name
Test status
Simulation time 513920645 ps
CPU time 19.19 seconds
Started Aug 29 09:38:56 AM UTC 24
Finished Aug 29 09:39:16 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076111430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1076111430
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.285889713
Short name T460
Test name
Test status
Simulation time 285386021 ps
CPU time 3.35 seconds
Started Aug 29 09:26:49 AM UTC 24
Finished Aug 29 09:26:54 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285889713 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.285889713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.1792145808
Short name T33
Test name
Test status
Simulation time 2332769418 ps
CPU time 40.47 seconds
Started Aug 29 09:26:40 AM UTC 24
Finished Aug 29 09:27:22 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792145808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.1792145808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.3235113829
Short name T459
Test name
Test status
Simulation time 364695594 ps
CPU time 10.86 seconds
Started Aug 29 09:26:38 AM UTC 24
Finished Aug 29 09:26:50 AM UTC 24
Peak memory 253304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235113829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.3235113829
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.1881978312
Short name T470
Test name
Test status
Simulation time 11251299394 ps
CPU time 47.36 seconds
Started Aug 29 09:26:36 AM UTC 24
Finished Aug 29 09:27:25 AM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881978312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.1881978312
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.799132289
Short name T164
Test name
Test status
Simulation time 118075099 ps
CPU time 5.79 seconds
Started Aug 29 09:26:32 AM UTC 24
Finished Aug 29 09:26:39 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799132289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.799132289
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.2556121333
Short name T392
Test name
Test status
Simulation time 1342317133 ps
CPU time 28.24 seconds
Started Aug 29 09:26:40 AM UTC 24
Finished Aug 29 09:27:09 AM UTC 24
Peak memory 253656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556121333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.2556121333
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.2953024106
Short name T239
Test name
Test status
Simulation time 172394601 ps
CPU time 7.14 seconds
Started Aug 29 09:26:40 AM UTC 24
Finished Aug 29 09:26:48 AM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953024106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2953024106
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.148015582
Short name T248
Test name
Test status
Simulation time 1877493757 ps
CPU time 19.86 seconds
Started Aug 29 09:26:36 AM UTC 24
Finished Aug 29 09:26:57 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148015582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.148015582
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.561728166
Short name T389
Test name
Test status
Simulation time 737867326 ps
CPU time 14.49 seconds
Started Aug 29 09:26:35 AM UTC 24
Finished Aug 29 09:26:50 AM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561728166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.561728166
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.2604486079
Short name T458
Test name
Test status
Simulation time 4722778120 ps
CPU time 10.64 seconds
Started Aug 29 09:26:31 AM UTC 24
Finished Aug 29 09:26:43 AM UTC 24
Peak memory 251496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604486079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2604486079
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.1116118358
Short name T328
Test name
Test status
Simulation time 66873299009 ps
CPU time 392.45 seconds
Started Aug 29 09:26:48 AM UTC 24
Finished Aug 29 09:33:27 AM UTC 24
Peak memory 273964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116118358 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.1116118358
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.3636498544
Short name T411
Test name
Test status
Simulation time 1597002916 ps
CPU time 19.82 seconds
Started Aug 29 09:26:46 AM UTC 24
Finished Aug 29 09:27:08 AM UTC 24
Peak memory 251312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636498544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.3636498544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.312860010
Short name T989
Test name
Test status
Simulation time 176867025 ps
CPU time 5.57 seconds
Started Aug 29 09:38:56 AM UTC 24
Finished Aug 29 09:39:03 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312860010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.312860010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.4232428324
Short name T1048
Test name
Test status
Simulation time 415859922 ps
CPU time 23.64 seconds
Started Aug 29 09:38:56 AM UTC 24
Finished Aug 29 09:39:21 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232428324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.4232428324
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.3748417100
Short name T986
Test name
Test status
Simulation time 320466108 ps
CPU time 5.24 seconds
Started Aug 29 09:38:56 AM UTC 24
Finished Aug 29 09:39:02 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748417100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3748417100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.1234537422
Short name T994
Test name
Test status
Simulation time 3009828284 ps
CPU time 7 seconds
Started Aug 29 09:38:56 AM UTC 24
Finished Aug 29 09:39:04 AM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234537422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.1234537422
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.904973765
Short name T84
Test name
Test status
Simulation time 686060473 ps
CPU time 5.78 seconds
Started Aug 29 09:38:56 AM UTC 24
Finished Aug 29 09:39:03 AM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904973765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.904973765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.736972351
Short name T1002
Test name
Test status
Simulation time 3253875411 ps
CPU time 8.32 seconds
Started Aug 29 09:38:56 AM UTC 24
Finished Aug 29 09:39:05 AM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736972351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.736972351
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.1784009197
Short name T995
Test name
Test status
Simulation time 1491362760 ps
CPU time 5.27 seconds
Started Aug 29 09:38:58 AM UTC 24
Finished Aug 29 09:39:04 AM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784009197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.1784009197
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.3876973020
Short name T996
Test name
Test status
Simulation time 480992328 ps
CPU time 5.3 seconds
Started Aug 29 09:38:58 AM UTC 24
Finished Aug 29 09:39:05 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876973020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.3876973020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.3331632779
Short name T998
Test name
Test status
Simulation time 1925582469 ps
CPU time 5.53 seconds
Started Aug 29 09:38:58 AM UTC 24
Finished Aug 29 09:39:05 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331632779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.3331632779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.2581591936
Short name T1062
Test name
Test status
Simulation time 1954402820 ps
CPU time 27.44 seconds
Started Aug 29 09:38:58 AM UTC 24
Finished Aug 29 09:39:27 AM UTC 24
Peak memory 251512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581591936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.2581591936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.1944346789
Short name T1000
Test name
Test status
Simulation time 1636452339 ps
CPU time 5.86 seconds
Started Aug 29 09:38:58 AM UTC 24
Finished Aug 29 09:39:05 AM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944346789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.1944346789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.2224950366
Short name T1165
Test name
Test status
Simulation time 17040477164 ps
CPU time 57.72 seconds
Started Aug 29 09:38:58 AM UTC 24
Finished Aug 29 09:39:58 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224950366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.2224950366
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.1962586716
Short name T987
Test name
Test status
Simulation time 216063202 ps
CPU time 2.96 seconds
Started Aug 29 09:38:58 AM UTC 24
Finished Aug 29 09:39:02 AM UTC 24
Peak memory 251524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962586716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.1962586716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.3844553561
Short name T1006
Test name
Test status
Simulation time 193866091 ps
CPU time 5.43 seconds
Started Aug 29 09:39:01 AM UTC 24
Finished Aug 29 09:39:07 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844553561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.3844553561
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.2641099038
Short name T997
Test name
Test status
Simulation time 114408313 ps
CPU time 2.86 seconds
Started Aug 29 09:39:01 AM UTC 24
Finished Aug 29 09:39:05 AM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641099038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.2641099038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.2112415643
Short name T1008
Test name
Test status
Simulation time 1582881884 ps
CPU time 6.46 seconds
Started Aug 29 09:39:01 AM UTC 24
Finished Aug 29 09:39:08 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112415643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.2112415643
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.909123614
Short name T1004
Test name
Test status
Simulation time 563726971 ps
CPU time 4.93 seconds
Started Aug 29 09:39:01 AM UTC 24
Finished Aug 29 09:39:07 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909123614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.909123614
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.1190686518
Short name T1015
Test name
Test status
Simulation time 2477517596 ps
CPU time 9 seconds
Started Aug 29 09:39:01 AM UTC 24
Finished Aug 29 09:39:11 AM UTC 24
Peak memory 251572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190686518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.1190686518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.2216361009
Short name T1001
Test name
Test status
Simulation time 165525304 ps
CPU time 3.23 seconds
Started Aug 29 09:39:01 AM UTC 24
Finished Aug 29 09:39:05 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216361009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.2216361009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.2877933639
Short name T1057
Test name
Test status
Simulation time 876978368 ps
CPU time 21.75 seconds
Started Aug 29 09:39:01 AM UTC 24
Finished Aug 29 09:39:24 AM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877933639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.2877933639
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.3732013561
Short name T465
Test name
Test status
Simulation time 253188968 ps
CPU time 2.84 seconds
Started Aug 29 09:27:09 AM UTC 24
Finished Aug 29 09:27:12 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732013561 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.3732013561
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.1718857507
Short name T47
Test name
Test status
Simulation time 825841325 ps
CPU time 37.51 seconds
Started Aug 29 09:26:59 AM UTC 24
Finished Aug 29 09:27:38 AM UTC 24
Peak memory 253720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718857507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1718857507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.2336215015
Short name T475
Test name
Test status
Simulation time 5979019842 ps
CPU time 36.91 seconds
Started Aug 29 09:26:59 AM UTC 24
Finished Aug 29 09:27:37 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336215015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.2336215015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.3719807866
Short name T462
Test name
Test status
Simulation time 436991226 ps
CPU time 10.36 seconds
Started Aug 29 09:26:57 AM UTC 24
Finished Aug 29 09:27:09 AM UTC 24
Peak memory 257528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719807866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.3719807866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.1353822281
Short name T182
Test name
Test status
Simulation time 160977643 ps
CPU time 5.3 seconds
Started Aug 29 09:26:52 AM UTC 24
Finished Aug 29 09:26:58 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353822281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.1353822281
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.4241837132
Short name T471
Test name
Test status
Simulation time 714641749 ps
CPU time 21.28 seconds
Started Aug 29 09:27:03 AM UTC 24
Finished Aug 29 09:27:26 AM UTC 24
Peak memory 253504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241837132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.4241837132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.2593683497
Short name T463
Test name
Test status
Simulation time 200304285 ps
CPU time 5.39 seconds
Started Aug 29 09:27:05 AM UTC 24
Finished Aug 29 09:27:11 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593683497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.2593683497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.2001253666
Short name T466
Test name
Test status
Simulation time 1385390109 ps
CPU time 16.28 seconds
Started Aug 29 09:26:56 AM UTC 24
Finished Aug 29 09:27:14 AM UTC 24
Peak memory 253236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001253666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.2001253666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.1458822733
Short name T364
Test name
Test status
Simulation time 298766525 ps
CPU time 7.92 seconds
Started Aug 29 09:27:07 AM UTC 24
Finished Aug 29 09:27:16 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458822733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.1458822733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.1890820361
Short name T461
Test name
Test status
Simulation time 1013368016 ps
CPU time 13.51 seconds
Started Aug 29 09:26:52 AM UTC 24
Finished Aug 29 09:27:07 AM UTC 24
Peak memory 251304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890820361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.1890820361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.207372853
Short name T408
Test name
Test status
Simulation time 24584890017 ps
CPU time 358.42 seconds
Started Aug 29 09:27:09 AM UTC 24
Finished Aug 29 09:33:12 AM UTC 24
Peak memory 290612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207372853 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.207372853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.2701842244
Short name T467
Test name
Test status
Simulation time 134254748 ps
CPU time 6.83 seconds
Started Aug 29 09:27:07 AM UTC 24
Finished Aug 29 09:27:15 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701842244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.2701842244
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.1544726517
Short name T1007
Test name
Test status
Simulation time 665518219 ps
CPU time 5.38 seconds
Started Aug 29 09:39:01 AM UTC 24
Finished Aug 29 09:39:08 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544726517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.1544726517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.3383247323
Short name T1014
Test name
Test status
Simulation time 143173993 ps
CPU time 6.83 seconds
Started Aug 29 09:39:03 AM UTC 24
Finished Aug 29 09:39:11 AM UTC 24
Peak memory 250752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383247323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.3383247323
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.3353376926
Short name T967
Test name
Test status
Simulation time 192857871 ps
CPU time 4.89 seconds
Started Aug 29 09:39:03 AM UTC 24
Finished Aug 29 09:39:09 AM UTC 24
Peak memory 250904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353376926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.3353376926
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.1342842507
Short name T1024
Test name
Test status
Simulation time 222403931 ps
CPU time 9.48 seconds
Started Aug 29 09:39:03 AM UTC 24
Finished Aug 29 09:39:14 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342842507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.1342842507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.1832358187
Short name T988
Test name
Test status
Simulation time 519945246 ps
CPU time 5.16 seconds
Started Aug 29 09:39:03 AM UTC 24
Finished Aug 29 09:39:09 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832358187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1832358187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.4200981858
Short name T1011
Test name
Test status
Simulation time 446604461 ps
CPU time 6.32 seconds
Started Aug 29 09:39:03 AM UTC 24
Finished Aug 29 09:39:11 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200981858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.4200981858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.1963976961
Short name T1012
Test name
Test status
Simulation time 268393144 ps
CPU time 6.62 seconds
Started Aug 29 09:39:03 AM UTC 24
Finished Aug 29 09:39:11 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963976961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.1963976961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.196656946
Short name T935
Test name
Test status
Simulation time 121700438 ps
CPU time 5.36 seconds
Started Aug 29 09:39:03 AM UTC 24
Finished Aug 29 09:39:10 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196656946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.196656946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.1048639713
Short name T971
Test name
Test status
Simulation time 580630643 ps
CPU time 4.69 seconds
Started Aug 29 09:39:03 AM UTC 24
Finished Aug 29 09:39:09 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048639713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.1048639713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.289675427
Short name T1044
Test name
Test status
Simulation time 4989689668 ps
CPU time 15.39 seconds
Started Aug 29 09:39:03 AM UTC 24
Finished Aug 29 09:39:20 AM UTC 24
Peak memory 251504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289675427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.289675427
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.4254896980
Short name T1010
Test name
Test status
Simulation time 130294951 ps
CPU time 3.88 seconds
Started Aug 29 09:39:05 AM UTC 24
Finished Aug 29 09:39:10 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254896980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.4254896980
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.990268686
Short name T1020
Test name
Test status
Simulation time 2213818426 ps
CPU time 6.31 seconds
Started Aug 29 09:39:05 AM UTC 24
Finished Aug 29 09:39:13 AM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990268686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.990268686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.3130997140
Short name T1018
Test name
Test status
Simulation time 613616511 ps
CPU time 5.76 seconds
Started Aug 29 09:39:05 AM UTC 24
Finished Aug 29 09:39:12 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130997140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3130997140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.915384861
Short name T1027
Test name
Test status
Simulation time 281292427 ps
CPU time 8.92 seconds
Started Aug 29 09:39:05 AM UTC 24
Finished Aug 29 09:39:15 AM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915384861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.915384861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.967909581
Short name T1019
Test name
Test status
Simulation time 188203238 ps
CPU time 5.95 seconds
Started Aug 29 09:39:05 AM UTC 24
Finished Aug 29 09:39:12 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967909581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.967909581
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.1005792647
Short name T1047
Test name
Test status
Simulation time 1924483845 ps
CPU time 14.08 seconds
Started Aug 29 09:39:05 AM UTC 24
Finished Aug 29 09:39:21 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005792647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.1005792647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.921165933
Short name T1017
Test name
Test status
Simulation time 157154191 ps
CPU time 5.29 seconds
Started Aug 29 09:39:05 AM UTC 24
Finished Aug 29 09:39:12 AM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921165933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.921165933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.2495204538
Short name T1013
Test name
Test status
Simulation time 169565597 ps
CPU time 4.53 seconds
Started Aug 29 09:39:05 AM UTC 24
Finished Aug 29 09:39:11 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495204538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.2495204538
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.2066180689
Short name T1016
Test name
Test status
Simulation time 379932127 ps
CPU time 4.52 seconds
Started Aug 29 09:39:05 AM UTC 24
Finished Aug 29 09:39:11 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066180689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.2066180689
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.1732834646
Short name T1026
Test name
Test status
Simulation time 801062277 ps
CPU time 6.75 seconds
Started Aug 29 09:39:07 AM UTC 24
Finished Aug 29 09:39:15 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732834646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.1732834646
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.4118729110
Short name T474
Test name
Test status
Simulation time 861155804 ps
CPU time 3.72 seconds
Started Aug 29 09:27:26 AM UTC 24
Finished Aug 29 09:27:31 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118729110 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.4118729110
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.1522303424
Short name T476
Test name
Test status
Simulation time 1005041654 ps
CPU time 23.78 seconds
Started Aug 29 09:27:16 AM UTC 24
Finished Aug 29 09:27:41 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522303424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1522303424
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.2613662371
Short name T486
Test name
Test status
Simulation time 13989924634 ps
CPU time 38.38 seconds
Started Aug 29 09:27:15 AM UTC 24
Finished Aug 29 09:27:55 AM UTC 24
Peak memory 253364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613662371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.2613662371
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.1117541002
Short name T481
Test name
Test status
Simulation time 5854879683 ps
CPU time 33.28 seconds
Started Aug 29 09:27:14 AM UTC 24
Finished Aug 29 09:27:48 AM UTC 24
Peak memory 257592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117541002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.1117541002
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.237826075
Short name T480
Test name
Test status
Simulation time 2422978545 ps
CPU time 28.35 seconds
Started Aug 29 09:27:17 AM UTC 24
Finished Aug 29 09:27:47 AM UTC 24
Peak memory 253568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237826075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.237826075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.4068947884
Short name T472
Test name
Test status
Simulation time 417803823 ps
CPU time 7.69 seconds
Started Aug 29 09:27:19 AM UTC 24
Finished Aug 29 09:27:28 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068947884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.4068947884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.904813602
Short name T336
Test name
Test status
Simulation time 399947660 ps
CPU time 4.97 seconds
Started Aug 29 09:27:13 AM UTC 24
Finished Aug 29 09:27:19 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904813602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.904813602
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.2779659806
Short name T469
Test name
Test status
Simulation time 430333831 ps
CPU time 11.69 seconds
Started Aug 29 09:27:11 AM UTC 24
Finished Aug 29 09:27:24 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779659806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.2779659806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.1653572395
Short name T473
Test name
Test status
Simulation time 129219813 ps
CPU time 5.47 seconds
Started Aug 29 09:27:23 AM UTC 24
Finished Aug 29 09:27:30 AM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653572395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1653572395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.667147321
Short name T468
Test name
Test status
Simulation time 1492764874 ps
CPU time 13.12 seconds
Started Aug 29 09:27:10 AM UTC 24
Finished Aug 29 09:27:24 AM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667147321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.667147321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.3655080033
Short name T329
Test name
Test status
Simulation time 129191091587 ps
CPU time 367.59 seconds
Started Aug 29 09:27:25 AM UTC 24
Finished Aug 29 09:33:38 AM UTC 24
Peak memory 290396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655080033 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.3655080033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.2810727262
Short name T383
Test name
Test status
Simulation time 2576727341 ps
CPU time 133.86 seconds
Started Aug 29 09:27:25 AM UTC 24
Finished Aug 29 09:29:41 AM UTC 24
Peak memory 267796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2810727262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.otp_ctrl_stress_all_with_rand_reset.2810727262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.2827335202
Short name T485
Test name
Test status
Simulation time 646914013 ps
CPU time 29.53 seconds
Started Aug 29 09:27:23 AM UTC 24
Finished Aug 29 09:27:54 AM UTC 24
Peak memory 253428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827335202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.2827335202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.3791243321
Short name T1022
Test name
Test status
Simulation time 188943431 ps
CPU time 5.05 seconds
Started Aug 29 09:39:07 AM UTC 24
Finished Aug 29 09:39:13 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791243321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3791243321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.3052257435
Short name T1055
Test name
Test status
Simulation time 1103870031 ps
CPU time 14.31 seconds
Started Aug 29 09:39:07 AM UTC 24
Finished Aug 29 09:39:23 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052257435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3052257435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.142644841
Short name T1021
Test name
Test status
Simulation time 2497624767 ps
CPU time 4.9 seconds
Started Aug 29 09:39:07 AM UTC 24
Finished Aug 29 09:39:13 AM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142644841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.142644841
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.746482969
Short name T1092
Test name
Test status
Simulation time 2967381408 ps
CPU time 23.52 seconds
Started Aug 29 09:39:07 AM UTC 24
Finished Aug 29 09:39:32 AM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746482969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.746482969
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.461948594
Short name T68
Test name
Test status
Simulation time 134770619 ps
CPU time 4.19 seconds
Started Aug 29 09:39:07 AM UTC 24
Finished Aug 29 09:39:13 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461948594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.461948594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.2364341191
Short name T1032
Test name
Test status
Simulation time 1798953981 ps
CPU time 6.87 seconds
Started Aug 29 09:39:09 AM UTC 24
Finished Aug 29 09:39:17 AM UTC 24
Peak memory 251128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364341191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.2364341191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.3319485102
Short name T1043
Test name
Test status
Simulation time 178916512 ps
CPU time 9.35 seconds
Started Aug 29 09:39:09 AM UTC 24
Finished Aug 29 09:39:20 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319485102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.3319485102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.1968690988
Short name T1025
Test name
Test status
Simulation time 120488382 ps
CPU time 4.05 seconds
Started Aug 29 09:39:09 AM UTC 24
Finished Aug 29 09:39:15 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968690988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1968690988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.2844318824
Short name T1037
Test name
Test status
Simulation time 174177306 ps
CPU time 7.55 seconds
Started Aug 29 09:39:10 AM UTC 24
Finished Aug 29 09:39:18 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844318824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.2844318824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.1911133573
Short name T1036
Test name
Test status
Simulation time 214577831 ps
CPU time 5.85 seconds
Started Aug 29 09:39:11 AM UTC 24
Finished Aug 29 09:39:18 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911133573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1911133573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.2910850509
Short name T1045
Test name
Test status
Simulation time 285855573 ps
CPU time 7.83 seconds
Started Aug 29 09:39:11 AM UTC 24
Finished Aug 29 09:39:20 AM UTC 24
Peak memory 251144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910850509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.2910850509
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.33960472
Short name T1030
Test name
Test status
Simulation time 131444700 ps
CPU time 4.87 seconds
Started Aug 29 09:39:11 AM UTC 24
Finished Aug 29 09:39:17 AM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33960472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.33960472
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.3569305742
Short name T1061
Test name
Test status
Simulation time 587439026 ps
CPU time 14.62 seconds
Started Aug 29 09:39:11 AM UTC 24
Finished Aug 29 09:39:27 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569305742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.3569305742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.1127573733
Short name T1041
Test name
Test status
Simulation time 1687633464 ps
CPU time 6.75 seconds
Started Aug 29 09:39:11 AM UTC 24
Finished Aug 29 09:39:19 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127573733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1127573733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.3636341445
Short name T1033
Test name
Test status
Simulation time 221575973 ps
CPU time 4.97 seconds
Started Aug 29 09:39:11 AM UTC 24
Finished Aug 29 09:39:17 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636341445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.3636341445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.1017536842
Short name T1042
Test name
Test status
Simulation time 389580299 ps
CPU time 5.55 seconds
Started Aug 29 09:39:13 AM UTC 24
Finished Aug 29 09:39:20 AM UTC 24
Peak memory 253272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017536842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.1017536842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.3734820265
Short name T1046
Test name
Test status
Simulation time 189079351 ps
CPU time 6.29 seconds
Started Aug 29 09:39:13 AM UTC 24
Finished Aug 29 09:39:20 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734820265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.3734820265
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.116788698
Short name T1039
Test name
Test status
Simulation time 425238694 ps
CPU time 4.93 seconds
Started Aug 29 09:39:13 AM UTC 24
Finished Aug 29 09:39:19 AM UTC 24
Peak memory 251232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116788698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.116788698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.3052418277
Short name T1059
Test name
Test status
Simulation time 540993813 ps
CPU time 12.17 seconds
Started Aug 29 09:39:13 AM UTC 24
Finished Aug 29 09:39:26 AM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052418277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.3052418277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.2279407950
Short name T483
Test name
Test status
Simulation time 70587189 ps
CPU time 2.77 seconds
Started Aug 29 09:27:49 AM UTC 24
Finished Aug 29 09:27:52 AM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279407950 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.2279407950
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.4080609762
Short name T118
Test name
Test status
Simulation time 2959722476 ps
CPU time 32.06 seconds
Started Aug 29 09:27:40 AM UTC 24
Finished Aug 29 09:28:13 AM UTC 24
Peak memory 253720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080609762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.4080609762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.1368199549
Short name T482
Test name
Test status
Simulation time 5034944202 ps
CPU time 13.17 seconds
Started Aug 29 09:27:37 AM UTC 24
Finished Aug 29 09:27:51 AM UTC 24
Peak memory 251488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368199549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.1368199549
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.1007734379
Short name T488
Test name
Test status
Simulation time 792045869 ps
CPU time 18.95 seconds
Started Aug 29 09:27:37 AM UTC 24
Finished Aug 29 09:27:57 AM UTC 24
Peak memory 253368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007734379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.1007734379
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.916157862
Short name T184
Test name
Test status
Simulation time 3882125743 ps
CPU time 33.24 seconds
Started Aug 29 09:27:40 AM UTC 24
Finished Aug 29 09:28:14 AM UTC 24
Peak memory 253528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916157862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.916157862
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.2673260075
Short name T321
Test name
Test status
Simulation time 20609820502 ps
CPU time 107.19 seconds
Started Aug 29 09:27:42 AM UTC 24
Finished Aug 29 09:29:32 AM UTC 24
Peak memory 253464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673260075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.2673260075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.351566349
Short name T477
Test name
Test status
Simulation time 1487503300 ps
CPU time 8.67 seconds
Started Aug 29 09:27:32 AM UTC 24
Finished Aug 29 09:27:41 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351566349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.351566349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.2455322030
Short name T402
Test name
Test status
Simulation time 601871774 ps
CPU time 23.45 seconds
Started Aug 29 09:27:31 AM UTC 24
Finished Aug 29 09:27:55 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455322030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2455322030
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.802799332
Short name T484
Test name
Test status
Simulation time 724342365 ps
CPU time 10.85 seconds
Started Aug 29 09:27:42 AM UTC 24
Finished Aug 29 09:27:54 AM UTC 24
Peak memory 251540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802799332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.802799332
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.2756492510
Short name T478
Test name
Test status
Simulation time 4784975477 ps
CPU time 14.44 seconds
Started Aug 29 09:27:26 AM UTC 24
Finished Aug 29 09:27:42 AM UTC 24
Peak memory 251368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756492510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.2756492510
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.3677635824
Short name T494
Test name
Test status
Simulation time 811569961 ps
CPU time 30.61 seconds
Started Aug 29 09:27:44 AM UTC 24
Finished Aug 29 09:28:15 AM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677635824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3677635824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.1891365801
Short name T1040
Test name
Test status
Simulation time 179728161 ps
CPU time 4.86 seconds
Started Aug 29 09:39:13 AM UTC 24
Finished Aug 29 09:39:19 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891365801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1891365801
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.1548907450
Short name T1060
Test name
Test status
Simulation time 208940330 ps
CPU time 12.15 seconds
Started Aug 29 09:39:13 AM UTC 24
Finished Aug 29 09:39:26 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548907450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.1548907450
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.2202578826
Short name T1038
Test name
Test status
Simulation time 585156945 ps
CPU time 3.95 seconds
Started Aug 29 09:39:13 AM UTC 24
Finished Aug 29 09:39:18 AM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202578826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.2202578826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.477433856
Short name T1052
Test name
Test status
Simulation time 836322442 ps
CPU time 7.73 seconds
Started Aug 29 09:39:13 AM UTC 24
Finished Aug 29 09:39:22 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477433856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.477433856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.331449099
Short name T1035
Test name
Test status
Simulation time 99458634 ps
CPU time 3.66 seconds
Started Aug 29 09:39:13 AM UTC 24
Finished Aug 29 09:39:18 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331449099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.331449099
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.2792248122
Short name T1087
Test name
Test status
Simulation time 3467892551 ps
CPU time 13.39 seconds
Started Aug 29 09:39:17 AM UTC 24
Finished Aug 29 09:39:31 AM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792248122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.2792248122
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.2591859639
Short name T1051
Test name
Test status
Simulation time 152636191 ps
CPU time 4.34 seconds
Started Aug 29 09:39:17 AM UTC 24
Finished Aug 29 09:39:22 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591859639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.2591859639
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.2222760518
Short name T1095
Test name
Test status
Simulation time 2064826872 ps
CPU time 14.96 seconds
Started Aug 29 09:39:17 AM UTC 24
Finished Aug 29 09:39:33 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222760518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.2222760518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.772214839
Short name T1054
Test name
Test status
Simulation time 706574291 ps
CPU time 4.63 seconds
Started Aug 29 09:39:17 AM UTC 24
Finished Aug 29 09:39:22 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772214839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.772214839
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.3807084642
Short name T1049
Test name
Test status
Simulation time 115759070 ps
CPU time 3.83 seconds
Started Aug 29 09:39:17 AM UTC 24
Finished Aug 29 09:39:22 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807084642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.3807084642
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.1765203613
Short name T1053
Test name
Test status
Simulation time 310441482 ps
CPU time 4.49 seconds
Started Aug 29 09:39:17 AM UTC 24
Finished Aug 29 09:39:22 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765203613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.1765203613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.2470086100
Short name T1058
Test name
Test status
Simulation time 266377557 ps
CPU time 8.2 seconds
Started Aug 29 09:39:17 AM UTC 24
Finished Aug 29 09:39:26 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470086100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.2470086100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.1224757981
Short name T1050
Test name
Test status
Simulation time 1762563823 ps
CPU time 3.79 seconds
Started Aug 29 09:39:17 AM UTC 24
Finished Aug 29 09:39:22 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224757981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.1224757981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.3230161908
Short name T1065
Test name
Test status
Simulation time 3595642109 ps
CPU time 9.72 seconds
Started Aug 29 09:39:17 AM UTC 24
Finished Aug 29 09:39:28 AM UTC 24
Peak memory 257368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230161908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.3230161908
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.2983597821
Short name T1056
Test name
Test status
Simulation time 599824877 ps
CPU time 4.7 seconds
Started Aug 29 09:39:17 AM UTC 24
Finished Aug 29 09:39:23 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983597821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.2983597821
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.691610575
Short name T1112
Test name
Test status
Simulation time 8398138171 ps
CPU time 19.41 seconds
Started Aug 29 09:39:17 AM UTC 24
Finished Aug 29 09:39:38 AM UTC 24
Peak memory 251504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691610575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.691610575
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.856227550
Short name T1074
Test name
Test status
Simulation time 2045256246 ps
CPU time 5.1 seconds
Started Aug 29 09:39:23 AM UTC 24
Finished Aug 29 09:39:29 AM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856227550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.856227550
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.2535624136
Short name T1148
Test name
Test status
Simulation time 5179019414 ps
CPU time 19.85 seconds
Started Aug 29 09:39:23 AM UTC 24
Finished Aug 29 09:39:44 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535624136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2535624136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.2890858188
Short name T1069
Test name
Test status
Simulation time 96955062 ps
CPU time 4.52 seconds
Started Aug 29 09:39:23 AM UTC 24
Finished Aug 29 09:39:29 AM UTC 24
Peak memory 251052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890858188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.2890858188
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.3460254524
Short name T1080
Test name
Test status
Simulation time 196229411 ps
CPU time 5.86 seconds
Started Aug 29 09:39:23 AM UTC 24
Finished Aug 29 09:39:30 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460254524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.3460254524
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.2505947107
Short name T186
Test name
Test status
Simulation time 67609265 ps
CPU time 2.87 seconds
Started Aug 29 09:20:39 AM UTC 24
Finished Aug 29 09:20:43 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505947107 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2505947107
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.1357708990
Short name T9
Test name
Test status
Simulation time 2913053304 ps
CPU time 61.48 seconds
Started Aug 29 09:20:13 AM UTC 24
Finished Aug 29 09:21:16 AM UTC 24
Peak memory 257384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357708990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1357708990
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.3262691765
Short name T124
Test name
Test status
Simulation time 473673902 ps
CPU time 23.58 seconds
Started Aug 29 09:20:13 AM UTC 24
Finished Aug 29 09:20:37 AM UTC 24
Peak memory 251496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262691765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.3262691765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.3368915535
Short name T161
Test name
Test status
Simulation time 734346454 ps
CPU time 14.37 seconds
Started Aug 29 09:20:17 AM UTC 24
Finished Aug 29 09:20:33 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368915535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.3368915535
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.52422194
Short name T159
Test name
Test status
Simulation time 469483545 ps
CPU time 8.01 seconds
Started Aug 29 09:20:17 AM UTC 24
Finished Aug 29 09:20:27 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52422194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.52422194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.206327899
Short name T185
Test name
Test status
Simulation time 394091880 ps
CPU time 15.35 seconds
Started Aug 29 09:20:12 AM UTC 24
Finished Aug 29 09:20:29 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206327899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.206327899
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.3001227123
Short name T125
Test name
Test status
Simulation time 7245324859 ps
CPU time 30.59 seconds
Started Aug 29 09:20:12 AM UTC 24
Finished Aug 29 09:20:44 AM UTC 24
Peak memory 257428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001227123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.3001227123
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.2664572632
Short name T187
Test name
Test status
Simulation time 3384034205 ps
CPU time 18.36 seconds
Started Aug 29 09:20:25 AM UTC 24
Finished Aug 29 09:20:44 AM UTC 24
Peak memory 257420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664572632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.2664572632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.3256525267
Short name T227
Test name
Test status
Simulation time 11452271436 ps
CPU time 280.08 seconds
Started Aug 29 09:20:34 AM UTC 24
Finished Aug 29 09:25:19 AM UTC 24
Peak memory 290004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256525267 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3256525267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.1752124810
Short name T116
Test name
Test status
Simulation time 743808804 ps
CPU time 8.96 seconds
Started Aug 29 09:19:49 AM UTC 24
Finished Aug 29 09:19:59 AM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752124810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1752124810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.3903577608
Short name T126
Test name
Test status
Simulation time 6011014133 ps
CPU time 26.36 seconds
Started Aug 29 09:20:28 AM UTC 24
Finished Aug 29 09:20:56 AM UTC 24
Peak memory 253688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903577608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.3903577608
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.4156422419
Short name T492
Test name
Test status
Simulation time 42396914 ps
CPU time 2.27 seconds
Started Aug 29 09:28:09 AM UTC 24
Finished Aug 29 09:28:12 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156422419 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.4156422419
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.2580087883
Short name T504
Test name
Test status
Simulation time 9698875652 ps
CPU time 32.46 seconds
Started Aug 29 09:27:59 AM UTC 24
Finished Aug 29 09:28:34 AM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580087883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.2580087883
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.3139472019
Short name T496
Test name
Test status
Simulation time 2785146489 ps
CPU time 22.87 seconds
Started Aug 29 09:27:56 AM UTC 24
Finished Aug 29 09:28:20 AM UTC 24
Peak memory 253436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139472019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3139472019
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.351399859
Short name T188
Test name
Test status
Simulation time 140111095 ps
CPU time 4.87 seconds
Started Aug 29 09:27:52 AM UTC 24
Finished Aug 29 09:27:58 AM UTC 24
Peak memory 250844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351399859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.351399859
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.1672895319
Short name T189
Test name
Test status
Simulation time 920985244 ps
CPU time 27.85 seconds
Started Aug 29 09:27:59 AM UTC 24
Finished Aug 29 09:28:29 AM UTC 24
Peak memory 257600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672895319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.1672895319
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.3482829984
Short name T498
Test name
Test status
Simulation time 1325542790 ps
CPU time 20.27 seconds
Started Aug 29 09:27:59 AM UTC 24
Finished Aug 29 09:28:22 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482829984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.3482829984
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.742374899
Short name T244
Test name
Test status
Simulation time 780230489 ps
CPU time 15.02 seconds
Started Aug 29 09:27:56 AM UTC 24
Finished Aug 29 09:28:12 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742374899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.742374899
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.2607603846
Short name T491
Test name
Test status
Simulation time 1111504261 ps
CPU time 16.81 seconds
Started Aug 29 09:27:52 AM UTC 24
Finished Aug 29 09:28:10 AM UTC 24
Peak memory 257028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607603846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.2607603846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.710476002
Short name T489
Test name
Test status
Simulation time 295954381 ps
CPU time 6.44 seconds
Started Aug 29 09:27:59 AM UTC 24
Finished Aug 29 09:28:08 AM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710476002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.710476002
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.2270189321
Short name T487
Test name
Test status
Simulation time 214649253 ps
CPU time 5.6 seconds
Started Aug 29 09:27:50 AM UTC 24
Finished Aug 29 09:27:57 AM UTC 24
Peak memory 251624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270189321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.2270189321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.4027822922
Short name T530
Test name
Test status
Simulation time 48469364469 ps
CPU time 113.27 seconds
Started Aug 29 09:28:03 AM UTC 24
Finished Aug 29 09:29:58 AM UTC 24
Peak memory 257628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027822922 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.4027822922
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.1036384765
Short name T490
Test name
Test status
Simulation time 236659203 ps
CPU time 8.4 seconds
Started Aug 29 09:27:59 AM UTC 24
Finished Aug 29 09:28:10 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036384765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.1036384765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.548685867
Short name T1064
Test name
Test status
Simulation time 404257125 ps
CPU time 3.2 seconds
Started Aug 29 09:39:23 AM UTC 24
Finished Aug 29 09:39:28 AM UTC 24
Peak memory 251036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548685867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.548685867
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.3723710213
Short name T1078
Test name
Test status
Simulation time 164190998 ps
CPU time 5.47 seconds
Started Aug 29 09:39:23 AM UTC 24
Finished Aug 29 09:39:30 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723710213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.3723710213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.1015915061
Short name T1066
Test name
Test status
Simulation time 137708650 ps
CPU time 3.5 seconds
Started Aug 29 09:39:23 AM UTC 24
Finished Aug 29 09:39:28 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015915061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.1015915061
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.2333644414
Short name T1071
Test name
Test status
Simulation time 494649153 ps
CPU time 4.5 seconds
Started Aug 29 09:39:23 AM UTC 24
Finished Aug 29 09:39:29 AM UTC 24
Peak memory 251104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333644414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.2333644414
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.801505014
Short name T1067
Test name
Test status
Simulation time 109658750 ps
CPU time 3.8 seconds
Started Aug 29 09:39:23 AM UTC 24
Finished Aug 29 09:39:28 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801505014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.801505014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.1544248625
Short name T1072
Test name
Test status
Simulation time 1179326384 ps
CPU time 4.43 seconds
Started Aug 29 09:39:23 AM UTC 24
Finished Aug 29 09:39:29 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544248625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.1544248625
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.3282891547
Short name T1063
Test name
Test status
Simulation time 192093274 ps
CPU time 2.93 seconds
Started Aug 29 09:39:23 AM UTC 24
Finished Aug 29 09:39:28 AM UTC 24
Peak memory 251612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282891547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.3282891547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.3834640941
Short name T1086
Test name
Test status
Simulation time 1796916251 ps
CPU time 6.1 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:31 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834640941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.3834640941
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.1673382114
Short name T1079
Test name
Test status
Simulation time 280419840 ps
CPU time 5.45 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:30 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673382114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.1673382114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.123757939
Short name T1088
Test name
Test status
Simulation time 2401002107 ps
CPU time 6.92 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:32 AM UTC 24
Peak memory 251616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123757939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.123757939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.1537960291
Short name T500
Test name
Test status
Simulation time 135595785 ps
CPU time 2.93 seconds
Started Aug 29 09:28:24 AM UTC 24
Finished Aug 29 09:28:28 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537960291 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.1537960291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.1338344892
Short name T36
Test name
Test status
Simulation time 1338495871 ps
CPU time 20.63 seconds
Started Aug 29 09:28:16 AM UTC 24
Finished Aug 29 09:28:38 AM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338344892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.1338344892
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.2334052223
Short name T340
Test name
Test status
Simulation time 5282170073 ps
CPU time 55.99 seconds
Started Aug 29 09:28:16 AM UTC 24
Finished Aug 29 09:29:13 AM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334052223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.2334052223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.3718188221
Short name T503
Test name
Test status
Simulation time 554659634 ps
CPU time 17.07 seconds
Started Aug 29 09:28:15 AM UTC 24
Finished Aug 29 09:28:34 AM UTC 24
Peak memory 253716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718188221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.3718188221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.3060925384
Short name T168
Test name
Test status
Simulation time 163693485 ps
CPU time 5.18 seconds
Started Aug 29 09:28:11 AM UTC 24
Finished Aug 29 09:28:18 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060925384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.3060925384
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.1430701937
Short name T396
Test name
Test status
Simulation time 2222037724 ps
CPU time 39.36 seconds
Started Aug 29 09:28:17 AM UTC 24
Finished Aug 29 09:28:58 AM UTC 24
Peak memory 255832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430701937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.1430701937
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.3355689946
Short name T509
Test name
Test status
Simulation time 1686591635 ps
CPU time 27.86 seconds
Started Aug 29 09:28:19 AM UTC 24
Finished Aug 29 09:28:48 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355689946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.3355689946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.1559445035
Short name T152
Test name
Test status
Simulation time 498674974 ps
CPU time 5.09 seconds
Started Aug 29 09:28:14 AM UTC 24
Finished Aug 29 09:28:20 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559445035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.1559445035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.2612482050
Short name T508
Test name
Test status
Simulation time 607523098 ps
CPU time 31.19 seconds
Started Aug 29 09:28:14 AM UTC 24
Finished Aug 29 09:28:46 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612482050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.2612482050
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.4177176139
Short name T502
Test name
Test status
Simulation time 359695868 ps
CPU time 10.85 seconds
Started Aug 29 09:28:19 AM UTC 24
Finished Aug 29 09:28:31 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177176139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.4177176139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.4070342988
Short name T499
Test name
Test status
Simulation time 494324606 ps
CPU time 15.74 seconds
Started Aug 29 09:28:10 AM UTC 24
Finished Aug 29 09:28:27 AM UTC 24
Peak memory 251624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070342988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.4070342988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.1363798113
Short name T397
Test name
Test status
Simulation time 8239166228 ps
CPU time 238.52 seconds
Started Aug 29 09:28:24 AM UTC 24
Finished Aug 29 09:32:27 AM UTC 24
Peak memory 274004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363798113 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.1363798113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.1351856816
Short name T272
Test name
Test status
Simulation time 1223590325 ps
CPU time 35.84 seconds
Started Aug 29 09:28:24 AM UTC 24
Finished Aug 29 09:29:01 AM UTC 24
Peak memory 257612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1351856816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.otp_ctrl_stress_all_with_rand_reset.1351856816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.566895532
Short name T501
Test name
Test status
Simulation time 114630952 ps
CPU time 5.49 seconds
Started Aug 29 09:28:24 AM UTC 24
Finished Aug 29 09:28:31 AM UTC 24
Peak memory 251636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566895532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.566895532
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.1425256660
Short name T1068
Test name
Test status
Simulation time 86553091 ps
CPU time 3.92 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:29 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425256660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1425256660
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.2453977384
Short name T1073
Test name
Test status
Simulation time 154271405 ps
CPU time 4.39 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:29 AM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453977384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2453977384
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.2991668856
Short name T1076
Test name
Test status
Simulation time 568953880 ps
CPU time 4.59 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:29 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991668856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.2991668856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.3404859882
Short name T1083
Test name
Test status
Simulation time 582300718 ps
CPU time 5.59 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:30 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404859882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.3404859882
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.220179666
Short name T1084
Test name
Test status
Simulation time 2014834701 ps
CPU time 5.71 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:31 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220179666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.220179666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.526290534
Short name T1082
Test name
Test status
Simulation time 155715139 ps
CPU time 5.4 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:30 AM UTC 24
Peak memory 251488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526290534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.526290534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.4180217764
Short name T28
Test name
Test status
Simulation time 280294927 ps
CPU time 4.13 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:29 AM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180217764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.4180217764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.4035468061
Short name T1075
Test name
Test status
Simulation time 542604845 ps
CPU time 4.33 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:29 AM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035468061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.4035468061
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.1410170406
Short name T1093
Test name
Test status
Simulation time 2194421093 ps
CPU time 7.33 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:32 AM UTC 24
Peak memory 251268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410170406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.1410170406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.2590903622
Short name T1070
Test name
Test status
Simulation time 172445745 ps
CPU time 3.74 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:29 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590903622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2590903622
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.4235510609
Short name T510
Test name
Test status
Simulation time 1101046454 ps
CPU time 3.9 seconds
Started Aug 29 09:28:44 AM UTC 24
Finished Aug 29 09:28:49 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235510609 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.4235510609
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.3397854157
Short name T86
Test name
Test status
Simulation time 11603010361 ps
CPU time 42.37 seconds
Started Aug 29 09:28:31 AM UTC 24
Finished Aug 29 09:29:15 AM UTC 24
Peak memory 257296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397854157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.3397854157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.210374939
Short name T519
Test name
Test status
Simulation time 2797289019 ps
CPU time 44.22 seconds
Started Aug 29 09:28:31 AM UTC 24
Finished Aug 29 09:29:17 AM UTC 24
Peak memory 251360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210374939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.210374939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.4213742812
Short name T506
Test name
Test status
Simulation time 886902366 ps
CPU time 12.17 seconds
Started Aug 29 09:28:30 AM UTC 24
Finished Aug 29 09:28:44 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213742812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.4213742812
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.207440232
Short name T178
Test name
Test status
Simulation time 351239925 ps
CPU time 5.3 seconds
Started Aug 29 09:28:28 AM UTC 24
Finished Aug 29 09:28:34 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207440232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.207440232
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.748684461
Short name T513
Test name
Test status
Simulation time 7075579323 ps
CPU time 26.64 seconds
Started Aug 29 09:28:35 AM UTC 24
Finished Aug 29 09:29:03 AM UTC 24
Peak memory 251392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748684461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.748684461
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.642242112
Short name T514
Test name
Test status
Simulation time 1053545992 ps
CPU time 29.37 seconds
Started Aug 29 09:28:36 AM UTC 24
Finished Aug 29 09:29:06 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642242112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.642242112
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.1918588706
Short name T334
Test name
Test status
Simulation time 368137584 ps
CPU time 15.41 seconds
Started Aug 29 09:28:29 AM UTC 24
Finished Aug 29 09:28:45 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918588706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.1918588706
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.57517615
Short name T404
Test name
Test status
Simulation time 1489595471 ps
CPU time 35.09 seconds
Started Aug 29 09:28:28 AM UTC 24
Finished Aug 29 09:29:04 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57517615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.57517615
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.744621915
Short name T512
Test name
Test status
Simulation time 3519400294 ps
CPU time 16.72 seconds
Started Aug 29 09:28:36 AM UTC 24
Finished Aug 29 09:28:53 AM UTC 24
Peak memory 251344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744621915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.744621915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.847223909
Short name T505
Test name
Test status
Simulation time 239529651 ps
CPU time 8.99 seconds
Started Aug 29 09:28:24 AM UTC 24
Finished Aug 29 09:28:34 AM UTC 24
Peak memory 257724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847223909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.847223909
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.1665481097
Short name T241
Test name
Test status
Simulation time 25825289801 ps
CPU time 163.14 seconds
Started Aug 29 09:28:44 AM UTC 24
Finished Aug 29 09:31:30 AM UTC 24
Peak memory 257692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665481097 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.1665481097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.154067940
Short name T253
Test name
Test status
Simulation time 2927662118 ps
CPU time 74.06 seconds
Started Aug 29 09:28:39 AM UTC 24
Finished Aug 29 09:29:55 AM UTC 24
Peak memory 268144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=154067940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
22.otp_ctrl_stress_all_with_rand_reset.154067940
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.468801171
Short name T507
Test name
Test status
Simulation time 447965761 ps
CPU time 6.96 seconds
Started Aug 29 09:28:36 AM UTC 24
Finished Aug 29 09:28:44 AM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468801171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.468801171
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.616357929
Short name T1081
Test name
Test status
Simulation time 115342382 ps
CPU time 5.09 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:30 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616357929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.616357929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.3339941550
Short name T1085
Test name
Test status
Simulation time 584434839 ps
CPU time 5.43 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:31 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339941550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3339941550
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.1558994030
Short name T1077
Test name
Test status
Simulation time 183202557 ps
CPU time 4.22 seconds
Started Aug 29 09:39:24 AM UTC 24
Finished Aug 29 09:39:30 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558994030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.1558994030
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.4082921122
Short name T57
Test name
Test status
Simulation time 106286131 ps
CPU time 3.44 seconds
Started Aug 29 09:39:26 AM UTC 24
Finished Aug 29 09:39:30 AM UTC 24
Peak memory 251528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082921122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.4082921122
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.3572308013
Short name T1089
Test name
Test status
Simulation time 148803571 ps
CPU time 4.99 seconds
Started Aug 29 09:39:26 AM UTC 24
Finished Aug 29 09:39:32 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572308013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.3572308013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.1892576959
Short name T1090
Test name
Test status
Simulation time 404812853 ps
CPU time 3.37 seconds
Started Aug 29 09:39:27 AM UTC 24
Finished Aug 29 09:39:32 AM UTC 24
Peak memory 253028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892576959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.1892576959
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.4284733513
Short name T1094
Test name
Test status
Simulation time 307061356 ps
CPU time 4.21 seconds
Started Aug 29 09:39:27 AM UTC 24
Finished Aug 29 09:39:33 AM UTC 24
Peak memory 250772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284733513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.4284733513
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.314366633
Short name T1096
Test name
Test status
Simulation time 440975529 ps
CPU time 4.67 seconds
Started Aug 29 09:39:27 AM UTC 24
Finished Aug 29 09:39:33 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314366633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.314366633
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.1879870465
Short name T1099
Test name
Test status
Simulation time 702834745 ps
CPU time 3.84 seconds
Started Aug 29 09:39:30 AM UTC 24
Finished Aug 29 09:39:35 AM UTC 24
Peak memory 251212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879870465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.1879870465
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.1299105357
Short name T516
Test name
Test status
Simulation time 140049618 ps
CPU time 3.05 seconds
Started Aug 29 09:29:07 AM UTC 24
Finished Aug 29 09:29:11 AM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299105357 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.1299105357
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.1138229822
Short name T49
Test name
Test status
Simulation time 5943885780 ps
CPU time 66.65 seconds
Started Aug 29 09:28:54 AM UTC 24
Finished Aug 29 09:30:02 AM UTC 24
Peak memory 257792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138229822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.1138229822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.1586711853
Short name T339
Test name
Test status
Simulation time 4248930287 ps
CPU time 31.36 seconds
Started Aug 29 09:28:53 AM UTC 24
Finished Aug 29 09:29:25 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586711853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1586711853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.3493021379
Short name T518
Test name
Test status
Simulation time 2160055846 ps
CPU time 19.93 seconds
Started Aug 29 09:28:51 AM UTC 24
Finished Aug 29 09:29:13 AM UTC 24
Peak memory 253428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493021379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.3493021379
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.1061795782
Short name T190
Test name
Test status
Simulation time 118196618 ps
CPU time 4.17 seconds
Started Aug 29 09:28:48 AM UTC 24
Finished Aug 29 09:28:53 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061795782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.1061795782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.4293899210
Short name T191
Test name
Test status
Simulation time 13370123494 ps
CPU time 61.62 seconds
Started Aug 29 09:28:54 AM UTC 24
Finished Aug 29 09:29:57 AM UTC 24
Peak memory 257880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293899210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.4293899210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.519694131
Short name T326
Test name
Test status
Simulation time 12650039851 ps
CPU time 44.08 seconds
Started Aug 29 09:28:55 AM UTC 24
Finished Aug 29 09:29:41 AM UTC 24
Peak memory 253552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519694131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.519694131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.1628472148
Short name T335
Test name
Test status
Simulation time 792807335 ps
CPU time 14.7 seconds
Started Aug 29 09:28:51 AM UTC 24
Finished Aug 29 09:29:07 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628472148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.1628472148
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.3635445823
Short name T387
Test name
Test status
Simulation time 2099729275 ps
CPU time 26.96 seconds
Started Aug 29 09:28:51 AM UTC 24
Finished Aug 29 09:29:20 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635445823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.3635445823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.1487055391
Short name T517
Test name
Test status
Simulation time 4638823034 ps
CPU time 10.92 seconds
Started Aug 29 09:29:00 AM UTC 24
Finished Aug 29 09:29:12 AM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487055391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.1487055391
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.3344695131
Short name T511
Test name
Test status
Simulation time 405392610 ps
CPU time 5.34 seconds
Started Aug 29 09:28:47 AM UTC 24
Finished Aug 29 09:28:53 AM UTC 24
Peak memory 251368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344695131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.3344695131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.4048286648
Short name T388
Test name
Test status
Simulation time 26288611141 ps
CPU time 89.75 seconds
Started Aug 29 09:29:06 AM UTC 24
Finished Aug 29 09:30:38 AM UTC 24
Peak memory 255424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048286648 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.4048286648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.2118439075
Short name T515
Test name
Test status
Simulation time 441329092 ps
CPU time 8.44 seconds
Started Aug 29 09:29:02 AM UTC 24
Finished Aug 29 09:29:11 AM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118439075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.2118439075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.1244294389
Short name T1101
Test name
Test status
Simulation time 159583329 ps
CPU time 4.49 seconds
Started Aug 29 09:39:30 AM UTC 24
Finished Aug 29 09:39:36 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244294389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.1244294389
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.1563958490
Short name T1105
Test name
Test status
Simulation time 387311034 ps
CPU time 4.87 seconds
Started Aug 29 09:39:30 AM UTC 24
Finished Aug 29 09:39:36 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563958490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.1563958490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.3378607213
Short name T1098
Test name
Test status
Simulation time 2061931771 ps
CPU time 3.56 seconds
Started Aug 29 09:39:30 AM UTC 24
Finished Aug 29 09:39:35 AM UTC 24
Peak memory 251332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378607213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.3378607213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.1715559420
Short name T1107
Test name
Test status
Simulation time 200777251 ps
CPU time 5.12 seconds
Started Aug 29 09:39:30 AM UTC 24
Finished Aug 29 09:39:37 AM UTC 24
Peak memory 251524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715559420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.1715559420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.3179394492
Short name T1108
Test name
Test status
Simulation time 501331492 ps
CPU time 5.38 seconds
Started Aug 29 09:39:30 AM UTC 24
Finished Aug 29 09:39:37 AM UTC 24
Peak memory 253404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179394492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3179394492
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.638578477
Short name T1103
Test name
Test status
Simulation time 355711695 ps
CPU time 4.37 seconds
Started Aug 29 09:39:30 AM UTC 24
Finished Aug 29 09:39:36 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638578477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.638578477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.556228745
Short name T1100
Test name
Test status
Simulation time 440005855 ps
CPU time 4.25 seconds
Started Aug 29 09:39:30 AM UTC 24
Finished Aug 29 09:39:36 AM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556228745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.556228745
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.1150164261
Short name T1115
Test name
Test status
Simulation time 1906789327 ps
CPU time 6.46 seconds
Started Aug 29 09:39:30 AM UTC 24
Finished Aug 29 09:39:38 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150164261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.1150164261
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1446528984
Short name T1097
Test name
Test status
Simulation time 113383407 ps
CPU time 3.24 seconds
Started Aug 29 09:39:30 AM UTC 24
Finished Aug 29 09:39:35 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446528984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.1446528984
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.3630602824
Short name T1110
Test name
Test status
Simulation time 2171819381 ps
CPU time 5.45 seconds
Started Aug 29 09:39:30 AM UTC 24
Finished Aug 29 09:39:37 AM UTC 24
Peak memory 250816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630602824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.3630602824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.2641604189
Short name T322
Test name
Test status
Simulation time 141430213 ps
CPU time 3.24 seconds
Started Aug 29 09:29:32 AM UTC 24
Finished Aug 29 09:29:36 AM UTC 24
Peak memory 250744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641604189 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.2641604189
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.718779090
Short name T532
Test name
Test status
Simulation time 2161603449 ps
CPU time 49.42 seconds
Started Aug 29 09:29:15 AM UTC 24
Finished Aug 29 09:30:06 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718779090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.718779090
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.87915286
Short name T521
Test name
Test status
Simulation time 422764446 ps
CPU time 12.22 seconds
Started Aug 29 09:29:14 AM UTC 24
Finished Aug 29 09:29:27 AM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87915286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.87915286
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.3148309990
Short name T165
Test name
Test status
Simulation time 197056667 ps
CPU time 6.13 seconds
Started Aug 29 09:29:12 AM UTC 24
Finished Aug 29 09:29:19 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148309990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.3148309990
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.3217818987
Short name T324
Test name
Test status
Simulation time 3753270891 ps
CPU time 19.57 seconds
Started Aug 29 09:29:18 AM UTC 24
Finished Aug 29 09:29:39 AM UTC 24
Peak memory 251392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217818987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.3217818987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.3120846201
Short name T537
Test name
Test status
Simulation time 1447702204 ps
CPU time 47.58 seconds
Started Aug 29 09:29:21 AM UTC 24
Finished Aug 29 09:30:10 AM UTC 24
Peak memory 253400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120846201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.3120846201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.3806935194
Short name T320
Test name
Test status
Simulation time 975568974 ps
CPU time 16.76 seconds
Started Aug 29 09:29:14 AM UTC 24
Finished Aug 29 09:29:32 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806935194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.3806935194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.348111503
Short name T325
Test name
Test status
Simulation time 1412770954 ps
CPU time 26.43 seconds
Started Aug 29 09:29:12 AM UTC 24
Finished Aug 29 09:29:40 AM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348111503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.348111503
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.452127102
Short name T520
Test name
Test status
Simulation time 312132874 ps
CPU time 4.56 seconds
Started Aug 29 09:29:21 AM UTC 24
Finished Aug 29 09:29:27 AM UTC 24
Peak memory 257364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452127102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.452127102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.2956632017
Short name T495
Test name
Test status
Simulation time 4312952082 ps
CPU time 11.65 seconds
Started Aug 29 09:29:09 AM UTC 24
Finished Aug 29 09:29:22 AM UTC 24
Peak memory 251624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956632017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.2956632017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.1696311643
Short name T524
Test name
Test status
Simulation time 691058993 ps
CPU time 26 seconds
Started Aug 29 09:29:22 AM UTC 24
Finished Aug 29 09:29:49 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696311643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.1696311643
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.1698449118
Short name T1125
Test name
Test status
Simulation time 1981756473 ps
CPU time 7.35 seconds
Started Aug 29 09:39:30 AM UTC 24
Finished Aug 29 09:39:39 AM UTC 24
Peak memory 250836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698449118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.1698449118
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.2115717604
Short name T1104
Test name
Test status
Simulation time 127866396 ps
CPU time 4.41 seconds
Started Aug 29 09:39:30 AM UTC 24
Finished Aug 29 09:39:36 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115717604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.2115717604
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.4097523527
Short name T1106
Test name
Test status
Simulation time 90255350 ps
CPU time 4.45 seconds
Started Aug 29 09:39:31 AM UTC 24
Finished Aug 29 09:39:36 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097523527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.4097523527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.1297634996
Short name T1109
Test name
Test status
Simulation time 2139300343 ps
CPU time 5.03 seconds
Started Aug 29 09:39:31 AM UTC 24
Finished Aug 29 09:39:37 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297634996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1297634996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.606169923
Short name T1102
Test name
Test status
Simulation time 217420312 ps
CPU time 3.92 seconds
Started Aug 29 09:39:31 AM UTC 24
Finished Aug 29 09:39:36 AM UTC 24
Peak memory 251520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606169923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.606169923
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.3191795441
Short name T1122
Test name
Test status
Simulation time 2014931703 ps
CPU time 6.97 seconds
Started Aug 29 09:39:31 AM UTC 24
Finished Aug 29 09:39:39 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191795441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.3191795441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.1253649914
Short name T154
Test name
Test status
Simulation time 226190185 ps
CPU time 4.54 seconds
Started Aug 29 09:39:31 AM UTC 24
Finished Aug 29 09:39:36 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253649914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1253649914
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.2747109586
Short name T1123
Test name
Test status
Simulation time 303540941 ps
CPU time 5.37 seconds
Started Aug 29 09:39:32 AM UTC 24
Finished Aug 29 09:39:39 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747109586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.2747109586
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.772948529
Short name T1113
Test name
Test status
Simulation time 414142702 ps
CPU time 4.32 seconds
Started Aug 29 09:39:32 AM UTC 24
Finished Aug 29 09:39:38 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772948529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.772948529
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.2685527014
Short name T1117
Test name
Test status
Simulation time 584191795 ps
CPU time 4.83 seconds
Started Aug 29 09:39:32 AM UTC 24
Finished Aug 29 09:39:38 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685527014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.2685527014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.1261759682
Short name T523
Test name
Test status
Simulation time 277781068 ps
CPU time 2.78 seconds
Started Aug 29 09:29:44 AM UTC 24
Finished Aug 29 09:29:48 AM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261759682 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1261759682
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.3169961230
Short name T525
Test name
Test status
Simulation time 439684347 ps
CPU time 5.1 seconds
Started Aug 29 09:29:44 AM UTC 24
Finished Aug 29 09:29:50 AM UTC 24
Peak memory 257432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169961230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.3169961230
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.134403575
Short name T528
Test name
Test status
Simulation time 568541772 ps
CPU time 21.87 seconds
Started Aug 29 09:29:34 AM UTC 24
Finished Aug 29 09:29:58 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134403575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.134403575
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.427184119
Short name T526
Test name
Test status
Simulation time 1910777841 ps
CPU time 17.18 seconds
Started Aug 29 09:29:34 AM UTC 24
Finished Aug 29 09:29:53 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427184119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.427184119
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.2966828949
Short name T522
Test name
Test status
Simulation time 2625583339 ps
CPU time 9.77 seconds
Started Aug 29 09:29:32 AM UTC 24
Finished Aug 29 09:29:43 AM UTC 24
Peak memory 251572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966828949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.2966828949
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.4239733982
Short name T533
Test name
Test status
Simulation time 2193101748 ps
CPU time 21.55 seconds
Started Aug 29 09:29:44 AM UTC 24
Finished Aug 29 09:30:07 AM UTC 24
Peak memory 253428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239733982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.4239733982
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.1107265629
Short name T538
Test name
Test status
Simulation time 911031283 ps
CPU time 25.01 seconds
Started Aug 29 09:29:44 AM UTC 24
Finished Aug 29 09:30:10 AM UTC 24
Peak memory 251584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107265629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.1107265629
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.596301244
Short name T206
Test name
Test status
Simulation time 2534666197 ps
CPU time 20.84 seconds
Started Aug 29 09:29:32 AM UTC 24
Finished Aug 29 09:29:54 AM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596301244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.596301244
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.2051766407
Short name T540
Test name
Test status
Simulation time 2290915019 ps
CPU time 37.51 seconds
Started Aug 29 09:29:32 AM UTC 24
Finished Aug 29 09:30:11 AM UTC 24
Peak memory 251104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051766407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2051766407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.2505605395
Short name T527
Test name
Test status
Simulation time 3431577102 ps
CPU time 11.69 seconds
Started Aug 29 09:29:44 AM UTC 24
Finished Aug 29 09:29:57 AM UTC 24
Peak memory 257692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505605395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.2505605395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.4141928413
Short name T323
Test name
Test status
Simulation time 448677978 ps
CPU time 5.96 seconds
Started Aug 29 09:29:32 AM UTC 24
Finished Aug 29 09:29:39 AM UTC 24
Peak memory 251012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141928413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.4141928413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.3270132217
Short name T327
Test name
Test status
Simulation time 14964096242 ps
CPU time 212.12 seconds
Started Aug 29 09:29:44 AM UTC 24
Finished Aug 29 09:33:20 AM UTC 24
Peak memory 300572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270132217 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.3270132217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.435887007
Short name T549
Test name
Test status
Simulation time 5641619953 ps
CPU time 43.77 seconds
Started Aug 29 09:29:44 AM UTC 24
Finished Aug 29 09:30:29 AM UTC 24
Peak memory 253360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435887007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.435887007
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.2468105895
Short name T1111
Test name
Test status
Simulation time 572734640 ps
CPU time 3.73 seconds
Started Aug 29 09:39:32 AM UTC 24
Finished Aug 29 09:39:37 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468105895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.2468105895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.3706964116
Short name T58
Test name
Test status
Simulation time 148990196 ps
CPU time 4.34 seconds
Started Aug 29 09:39:33 AM UTC 24
Finished Aug 29 09:39:38 AM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706964116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.3706964116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.3997073298
Short name T1118
Test name
Test status
Simulation time 134423095 ps
CPU time 4.56 seconds
Started Aug 29 09:39:33 AM UTC 24
Finished Aug 29 09:39:38 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997073298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.3997073298
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.3485727877
Short name T1127
Test name
Test status
Simulation time 526515125 ps
CPU time 5.32 seconds
Started Aug 29 09:39:33 AM UTC 24
Finished Aug 29 09:39:39 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485727877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.3485727877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.934893104
Short name T1116
Test name
Test status
Simulation time 117465860 ps
CPU time 4.37 seconds
Started Aug 29 09:39:33 AM UTC 24
Finished Aug 29 09:39:38 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934893104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.934893104
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.3012417237
Short name T1119
Test name
Test status
Simulation time 410871133 ps
CPU time 4.7 seconds
Started Aug 29 09:39:33 AM UTC 24
Finished Aug 29 09:39:39 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012417237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.3012417237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.3839183679
Short name T1121
Test name
Test status
Simulation time 200873952 ps
CPU time 4.78 seconds
Started Aug 29 09:39:33 AM UTC 24
Finished Aug 29 09:39:39 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839183679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.3839183679
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.2560081236
Short name T1114
Test name
Test status
Simulation time 152023585 ps
CPU time 3.67 seconds
Started Aug 29 09:39:33 AM UTC 24
Finished Aug 29 09:39:38 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560081236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2560081236
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.730077441
Short name T1134
Test name
Test status
Simulation time 1911911308 ps
CPU time 7.43 seconds
Started Aug 29 09:39:33 AM UTC 24
Finished Aug 29 09:39:42 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730077441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.730077441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.3752519354
Short name T1126
Test name
Test status
Simulation time 529548224 ps
CPU time 4.93 seconds
Started Aug 29 09:39:33 AM UTC 24
Finished Aug 29 09:39:39 AM UTC 24
Peak memory 251520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752519354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.3752519354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.2424652801
Short name T534
Test name
Test status
Simulation time 70846844 ps
CPU time 2.95 seconds
Started Aug 29 09:30:04 AM UTC 24
Finished Aug 29 09:30:08 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424652801 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2424652801
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.2451120332
Short name T548
Test name
Test status
Simulation time 1275886498 ps
CPU time 27.38 seconds
Started Aug 29 09:29:56 AM UTC 24
Finished Aug 29 09:30:25 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451120332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.2451120332
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.2942899926
Short name T560
Test name
Test status
Simulation time 2054977891 ps
CPU time 48.88 seconds
Started Aug 29 09:29:53 AM UTC 24
Finished Aug 29 09:30:44 AM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942899926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.2942899926
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.3378308481
Short name T192
Test name
Test status
Simulation time 719093193 ps
CPU time 7.79 seconds
Started Aug 29 09:29:49 AM UTC 24
Finished Aug 29 09:29:58 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378308481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.3378308481
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.1734484515
Short name T536
Test name
Test status
Simulation time 978086153 ps
CPU time 10.71 seconds
Started Aug 29 09:29:58 AM UTC 24
Finished Aug 29 09:30:10 AM UTC 24
Peak memory 251584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734484515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.1734484515
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.2320742406
Short name T539
Test name
Test status
Simulation time 714250349 ps
CPU time 11.84 seconds
Started Aug 29 09:29:58 AM UTC 24
Finished Aug 29 09:30:11 AM UTC 24
Peak memory 251608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320742406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2320742406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.420016650
Short name T541
Test name
Test status
Simulation time 1031324456 ps
CPU time 22.4 seconds
Started Aug 29 09:29:51 AM UTC 24
Finished Aug 29 09:30:15 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420016650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.420016650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.1335515951
Short name T531
Test name
Test status
Simulation time 956982204 ps
CPU time 13.15 seconds
Started Aug 29 09:29:51 AM UTC 24
Finished Aug 29 09:30:05 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335515951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.1335515951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.16101103
Short name T535
Test name
Test status
Simulation time 148756937 ps
CPU time 7.17 seconds
Started Aug 29 09:30:01 AM UTC 24
Finished Aug 29 09:30:10 AM UTC 24
Peak memory 251600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16101103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_
test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ot
p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.16101103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.2871420710
Short name T529
Test name
Test status
Simulation time 3255376129 ps
CPU time 10.45 seconds
Started Aug 29 09:29:47 AM UTC 24
Finished Aug 29 09:29:58 AM UTC 24
Peak memory 251688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871420710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2871420710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.54910744
Short name T550
Test name
Test status
Simulation time 2213846267 ps
CPU time 28.34 seconds
Started Aug 29 09:30:01 AM UTC 24
Finished Aug 29 09:30:31 AM UTC 24
Peak memory 253376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54910744 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.54910744
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.2285695946
Short name T547
Test name
Test status
Simulation time 6421811755 ps
CPU time 21.28 seconds
Started Aug 29 09:30:01 AM UTC 24
Finished Aug 29 09:30:24 AM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285695946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.2285695946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.284282697
Short name T1124
Test name
Test status
Simulation time 116583378 ps
CPU time 4.51 seconds
Started Aug 29 09:39:33 AM UTC 24
Finished Aug 29 09:39:39 AM UTC 24
Peak memory 251268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284282697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.284282697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.1639417525
Short name T1130
Test name
Test status
Simulation time 478451054 ps
CPU time 6.05 seconds
Started Aug 29 09:39:33 AM UTC 24
Finished Aug 29 09:39:41 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639417525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.1639417525
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.1967987708
Short name T1131
Test name
Test status
Simulation time 168888887 ps
CPU time 4.44 seconds
Started Aug 29 09:39:35 AM UTC 24
Finished Aug 29 09:39:41 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967987708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.1967987708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.1235799219
Short name T1138
Test name
Test status
Simulation time 1813993953 ps
CPU time 5.89 seconds
Started Aug 29 09:39:35 AM UTC 24
Finished Aug 29 09:39:42 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235799219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.1235799219
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.1519121085
Short name T1133
Test name
Test status
Simulation time 1752689753 ps
CPU time 4.77 seconds
Started Aug 29 09:39:35 AM UTC 24
Finished Aug 29 09:39:41 AM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519121085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.1519121085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.437542918
Short name T1132
Test name
Test status
Simulation time 464948631 ps
CPU time 4.61 seconds
Started Aug 29 09:39:35 AM UTC 24
Finished Aug 29 09:39:41 AM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437542918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.437542918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.1231584261
Short name T1135
Test name
Test status
Simulation time 151214883 ps
CPU time 5.18 seconds
Started Aug 29 09:39:35 AM UTC 24
Finished Aug 29 09:39:42 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231584261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.1231584261
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.4142554075
Short name T1136
Test name
Test status
Simulation time 351734318 ps
CPU time 3.58 seconds
Started Aug 29 09:39:37 AM UTC 24
Finished Aug 29 09:39:42 AM UTC 24
Peak memory 251272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142554075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.4142554075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.3796872737
Short name T1140
Test name
Test status
Simulation time 310516850 ps
CPU time 3.88 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:43 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796872737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.3796872737
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.1159016884
Short name T1137
Test name
Test status
Simulation time 210970164 ps
CPU time 3.66 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:42 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159016884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.1159016884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.2036936752
Short name T546
Test name
Test status
Simulation time 114886183 ps
CPU time 2.57 seconds
Started Aug 29 09:30:20 AM UTC 24
Finished Aug 29 09:30:23 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036936752 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2036936752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.4189437507
Short name T543
Test name
Test status
Simulation time 563445572 ps
CPU time 7.99 seconds
Started Aug 29 09:30:11 AM UTC 24
Finished Aug 29 09:30:20 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189437507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.4189437507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.2862379832
Short name T551
Test name
Test status
Simulation time 5856810986 ps
CPU time 23.93 seconds
Started Aug 29 09:30:11 AM UTC 24
Finished Aug 29 09:30:36 AM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862379832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.2862379832
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.4081164555
Short name T556
Test name
Test status
Simulation time 1500509726 ps
CPU time 29.88 seconds
Started Aug 29 09:30:09 AM UTC 24
Finished Aug 29 09:30:41 AM UTC 24
Peak memory 253368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081164555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.4081164555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.3184783903
Short name T180
Test name
Test status
Simulation time 135712435 ps
CPU time 5.02 seconds
Started Aug 29 09:30:06 AM UTC 24
Finished Aug 29 09:30:12 AM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184783903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3184783903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.318993929
Short name T544
Test name
Test status
Simulation time 329245917 ps
CPU time 7.46 seconds
Started Aug 29 09:30:13 AM UTC 24
Finished Aug 29 09:30:22 AM UTC 24
Peak memory 252996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318993929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.318993929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.4063816462
Short name T573
Test name
Test status
Simulation time 12406135804 ps
CPU time 52.77 seconds
Started Aug 29 09:30:13 AM UTC 24
Finished Aug 29 09:31:08 AM UTC 24
Peak memory 253132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063816462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.4063816462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.1239711721
Short name T553
Test name
Test status
Simulation time 2118796947 ps
CPU time 27.22 seconds
Started Aug 29 09:30:08 AM UTC 24
Finished Aug 29 09:30:37 AM UTC 24
Peak memory 257368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239711721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.1239711721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.937722567
Short name T545
Test name
Test status
Simulation time 495016538 ps
CPU time 7.91 seconds
Started Aug 29 09:30:13 AM UTC 24
Finished Aug 29 09:30:23 AM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937722567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.937722567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.4011386305
Short name T542
Test name
Test status
Simulation time 4772764486 ps
CPU time 11.66 seconds
Started Aug 29 09:30:04 AM UTC 24
Finished Aug 29 09:30:17 AM UTC 24
Peak memory 251496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011386305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.4011386305
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.1842524393
Short name T273
Test name
Test status
Simulation time 17715309552 ps
CPU time 279.1 seconds
Started Aug 29 09:30:16 AM UTC 24
Finished Aug 29 09:35:00 AM UTC 24
Peak memory 257472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842524393 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.1842524393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.2280090426
Short name T147
Test name
Test status
Simulation time 11861935581 ps
CPU time 102.02 seconds
Started Aug 29 09:30:14 AM UTC 24
Finished Aug 29 09:31:58 AM UTC 24
Peak memory 257872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2280090426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.otp_ctrl_stress_all_with_rand_reset.2280090426
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.3332633595
Short name T552
Test name
Test status
Simulation time 1451327940 ps
CPU time 21.41 seconds
Started Aug 29 09:30:14 AM UTC 24
Finished Aug 29 09:30:36 AM UTC 24
Peak memory 257528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332633595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.3332633595
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.2978616400
Short name T1147
Test name
Test status
Simulation time 368911271 ps
CPU time 4.78 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:44 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978616400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2978616400
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.2168222330
Short name T1143
Test name
Test status
Simulation time 571099218 ps
CPU time 4.15 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:43 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168222330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.2168222330
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.3710934941
Short name T1150
Test name
Test status
Simulation time 2617738342 ps
CPU time 6.52 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:45 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710934941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.3710934941
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.2841228761
Short name T1141
Test name
Test status
Simulation time 125316708 ps
CPU time 3.71 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:43 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841228761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.2841228761
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.3486322265
Short name T78
Test name
Test status
Simulation time 120231338 ps
CPU time 4.21 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:43 AM UTC 24
Peak memory 251076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486322265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.3486322265
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.3408527586
Short name T1139
Test name
Test status
Simulation time 146815904 ps
CPU time 3.47 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:43 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408527586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.3408527586
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.3792398828
Short name T1145
Test name
Test status
Simulation time 323641123 ps
CPU time 4.14 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:43 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792398828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3792398828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.3585549192
Short name T1146
Test name
Test status
Simulation time 117751958 ps
CPU time 4.16 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:43 AM UTC 24
Peak memory 253152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585549192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.3585549192
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.1503520113
Short name T1142
Test name
Test status
Simulation time 111688683 ps
CPU time 3.5 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:43 AM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503520113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.1503520113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.382183145
Short name T558
Test name
Test status
Simulation time 302053112 ps
CPU time 3.13 seconds
Started Aug 29 09:30:39 AM UTC 24
Finished Aug 29 09:30:43 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382183145 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.382183145
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.827308779
Short name T87
Test name
Test status
Simulation time 899744654 ps
CPU time 30.77 seconds
Started Aug 29 09:30:25 AM UTC 24
Finished Aug 29 09:30:57 AM UTC 24
Peak memory 253452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827308779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.827308779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.2752668898
Short name T557
Test name
Test status
Simulation time 883427969 ps
CPU time 16.05 seconds
Started Aug 29 09:30:25 AM UTC 24
Finished Aug 29 09:30:42 AM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752668898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.2752668898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.2735200218
Short name T559
Test name
Test status
Simulation time 2873792803 ps
CPU time 19.61 seconds
Started Aug 29 09:30:23 AM UTC 24
Finished Aug 29 09:30:44 AM UTC 24
Peak memory 251672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735200218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.2735200218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.275365970
Short name T37
Test name
Test status
Simulation time 131676630 ps
CPU time 6.84 seconds
Started Aug 29 09:30:21 AM UTC 24
Finished Aug 29 09:30:29 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275365970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.275365970
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.1160387352
Short name T384
Test name
Test status
Simulation time 2810716894 ps
CPU time 33.08 seconds
Started Aug 29 09:30:26 AM UTC 24
Finished Aug 29 09:31:00 AM UTC 24
Peak memory 257816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160387352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.1160387352
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.4276923431
Short name T379
Test name
Test status
Simulation time 2067821900 ps
CPU time 40.87 seconds
Started Aug 29 09:30:29 AM UTC 24
Finished Aug 29 09:31:11 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276923431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.4276923431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.1188554781
Short name T415
Test name
Test status
Simulation time 404420139 ps
CPU time 16.83 seconds
Started Aug 29 09:30:23 AM UTC 24
Finished Aug 29 09:30:41 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188554781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.1188554781
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.3315186686
Short name T564
Test name
Test status
Simulation time 2059387007 ps
CPU time 23.17 seconds
Started Aug 29 09:30:21 AM UTC 24
Finished Aug 29 09:30:46 AM UTC 24
Peak memory 257628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315186686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.3315186686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.438751763
Short name T555
Test name
Test status
Simulation time 552060551 ps
CPU time 8.02 seconds
Started Aug 29 09:30:31 AM UTC 24
Finished Aug 29 09:30:40 AM UTC 24
Peak memory 257556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438751763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.438751763
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.3787099755
Short name T554
Test name
Test status
Simulation time 3849950434 ps
CPU time 17.01 seconds
Started Aug 29 09:30:20 AM UTC 24
Finished Aug 29 09:30:38 AM UTC 24
Peak memory 251556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787099755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.3787099755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.3659656650
Short name T276
Test name
Test status
Simulation time 27149581012 ps
CPU time 258.55 seconds
Started Aug 29 09:30:39 AM UTC 24
Finished Aug 29 09:35:01 AM UTC 24
Peak memory 257472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659656650 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.3659656650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.2772779656
Short name T567
Test name
Test status
Simulation time 2524324344 ps
CPU time 22.82 seconds
Started Aug 29 09:30:31 AM UTC 24
Finished Aug 29 09:30:55 AM UTC 24
Peak memory 253408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772779656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.2772779656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.4070928732
Short name T1144
Test name
Test status
Simulation time 1419586287 ps
CPU time 3.82 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:43 AM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070928732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.4070928732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.2655434378
Short name T1162
Test name
Test status
Simulation time 2996828277 ps
CPU time 8.55 seconds
Started Aug 29 09:39:38 AM UTC 24
Finished Aug 29 09:39:48 AM UTC 24
Peak memory 251268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655434378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.2655434378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.3206175872
Short name T1149
Test name
Test status
Simulation time 228182615 ps
CPU time 2.96 seconds
Started Aug 29 09:39:40 AM UTC 24
Finished Aug 29 09:39:45 AM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206175872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.3206175872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.4218738579
Short name T1163
Test name
Test status
Simulation time 1871697447 ps
CPU time 6.48 seconds
Started Aug 29 09:39:40 AM UTC 24
Finished Aug 29 09:39:48 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218738579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.4218738579
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.2585825959
Short name T1160
Test name
Test status
Simulation time 174662185 ps
CPU time 5.2 seconds
Started Aug 29 09:39:40 AM UTC 24
Finished Aug 29 09:39:47 AM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585825959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.2585825959
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.544020262
Short name T1151
Test name
Test status
Simulation time 180203615 ps
CPU time 3.72 seconds
Started Aug 29 09:39:40 AM UTC 24
Finished Aug 29 09:39:45 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544020262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.544020262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.4201813201
Short name T1156
Test name
Test status
Simulation time 206634883 ps
CPU time 4.32 seconds
Started Aug 29 09:39:40 AM UTC 24
Finished Aug 29 09:39:46 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201813201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.4201813201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.273071751
Short name T155
Test name
Test status
Simulation time 378673292 ps
CPU time 3.91 seconds
Started Aug 29 09:39:40 AM UTC 24
Finished Aug 29 09:39:46 AM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273071751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.273071751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.198759607
Short name T1154
Test name
Test status
Simulation time 208541518 ps
CPU time 3.97 seconds
Started Aug 29 09:39:40 AM UTC 24
Finished Aug 29 09:39:46 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198759607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.198759607
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.3992967564
Short name T565
Test name
Test status
Simulation time 109095756 ps
CPU time 3.01 seconds
Started Aug 29 09:30:47 AM UTC 24
Finished Aug 29 09:30:51 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992967564 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3992967564
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.2874614324
Short name T570
Test name
Test status
Simulation time 8324254063 ps
CPU time 16.04 seconds
Started Aug 29 09:30:43 AM UTC 24
Finished Aug 29 09:31:00 AM UTC 24
Peak memory 251392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874614324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.2874614324
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.125817423
Short name T595
Test name
Test status
Simulation time 20012733541 ps
CPU time 68.6 seconds
Started Aug 29 09:30:41 AM UTC 24
Finished Aug 29 09:31:51 AM UTC 24
Peak memory 257336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125817423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.125817423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.1802914923
Short name T627
Test name
Test status
Simulation time 9897518658 ps
CPU time 112.57 seconds
Started Aug 29 09:30:41 AM UTC 24
Finished Aug 29 09:32:36 AM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802914923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.1802914923
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.1835035544
Short name T563
Test name
Test status
Simulation time 1971676438 ps
CPU time 5.56 seconds
Started Aug 29 09:30:39 AM UTC 24
Finished Aug 29 09:30:45 AM UTC 24
Peak memory 250868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835035544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.1835035544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.3848989414
Short name T582
Test name
Test status
Simulation time 3822479014 ps
CPU time 43.27 seconds
Started Aug 29 09:30:43 AM UTC 24
Finished Aug 29 09:31:28 AM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848989414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.3848989414
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.4155800069
Short name T587
Test name
Test status
Simulation time 3298005201 ps
CPU time 54.1 seconds
Started Aug 29 09:30:43 AM UTC 24
Finished Aug 29 09:31:39 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155800069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.4155800069
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.2141554264
Short name T562
Test name
Test status
Simulation time 205058613 ps
CPU time 5.41 seconds
Started Aug 29 09:30:39 AM UTC 24
Finished Aug 29 09:30:45 AM UTC 24
Peak memory 251124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141554264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.2141554264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.4277443636
Short name T569
Test name
Test status
Simulation time 6759933223 ps
CPU time 16.51 seconds
Started Aug 29 09:30:39 AM UTC 24
Finished Aug 29 09:30:56 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277443636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.4277443636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.864125485
Short name T354
Test name
Test status
Simulation time 4295508523 ps
CPU time 17.39 seconds
Started Aug 29 09:30:44 AM UTC 24
Finished Aug 29 09:31:03 AM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864125485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.864125485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.2043572416
Short name T561
Test name
Test status
Simulation time 516626645 ps
CPU time 5.42 seconds
Started Aug 29 09:30:39 AM UTC 24
Finished Aug 29 09:30:45 AM UTC 24
Peak memory 251496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043572416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.2043572416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.3798708991
Short name T99
Test name
Test status
Simulation time 88222391390 ps
CPU time 266.31 seconds
Started Aug 29 09:30:47 AM UTC 24
Finished Aug 29 09:35:17 AM UTC 24
Peak memory 290524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798708991 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.3798708991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.1489113179
Short name T578
Test name
Test status
Simulation time 7442485586 ps
CPU time 27.94 seconds
Started Aug 29 09:30:47 AM UTC 24
Finished Aug 29 09:31:16 AM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489113179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.1489113179
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.3361422975
Short name T1153
Test name
Test status
Simulation time 155175688 ps
CPU time 3.81 seconds
Started Aug 29 09:39:40 AM UTC 24
Finished Aug 29 09:39:46 AM UTC 24
Peak memory 251524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361422975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.3361422975
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.3924850093
Short name T1161
Test name
Test status
Simulation time 1880798360 ps
CPU time 5.45 seconds
Started Aug 29 09:39:40 AM UTC 24
Finished Aug 29 09:39:47 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924850093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3924850093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.2454301816
Short name T1157
Test name
Test status
Simulation time 298045107 ps
CPU time 4.27 seconds
Started Aug 29 09:39:41 AM UTC 24
Finished Aug 29 09:39:46 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454301816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.2454301816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.1790598231
Short name T1152
Test name
Test status
Simulation time 2042733523 ps
CPU time 3.54 seconds
Started Aug 29 09:39:41 AM UTC 24
Finished Aug 29 09:39:45 AM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790598231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1790598231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.2133992287
Short name T1164
Test name
Test status
Simulation time 2300028208 ps
CPU time 6.26 seconds
Started Aug 29 09:39:41 AM UTC 24
Finished Aug 29 09:39:48 AM UTC 24
Peak memory 251268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133992287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.2133992287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.1934720461
Short name T1120
Test name
Test status
Simulation time 157537748 ps
CPU time 4.12 seconds
Started Aug 29 09:39:41 AM UTC 24
Finished Aug 29 09:39:46 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934720461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.1934720461
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.862284929
Short name T1155
Test name
Test status
Simulation time 155960888 ps
CPU time 3.79 seconds
Started Aug 29 09:39:41 AM UTC 24
Finished Aug 29 09:39:46 AM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862284929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.862284929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.661968500
Short name T1091
Test name
Test status
Simulation time 142742397 ps
CPU time 4 seconds
Started Aug 29 09:39:41 AM UTC 24
Finished Aug 29 09:39:46 AM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661968500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.661968500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.3496661144
Short name T1128
Test name
Test status
Simulation time 417806505 ps
CPU time 4.3 seconds
Started Aug 29 09:39:41 AM UTC 24
Finished Aug 29 09:39:46 AM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496661144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.3496661144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.4062614136
Short name T1159
Test name
Test status
Simulation time 146540081 ps
CPU time 4.23 seconds
Started Aug 29 09:39:41 AM UTC 24
Finished Aug 29 09:39:47 AM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062614136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.4062614136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.381309049
Short name T416
Test name
Test status
Simulation time 75009814 ps
CPU time 2.84 seconds
Started Aug 29 09:21:25 AM UTC 24
Finished Aug 29 09:21:29 AM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381309049 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.381309049
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.1819531147
Short name T112
Test name
Test status
Simulation time 1831054549 ps
CPU time 25.06 seconds
Started Aug 29 09:20:45 AM UTC 24
Finished Aug 29 09:21:12 AM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819531147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.1819531147
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.579241782
Short name T32
Test name
Test status
Simulation time 14462558900 ps
CPU time 91.05 seconds
Started Aug 29 09:20:56 AM UTC 24
Finished Aug 29 09:22:29 AM UTC 24
Peak memory 257532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579241782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.579241782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.780363127
Short name T16
Test name
Test status
Simulation time 4091380946 ps
CPU time 42.38 seconds
Started Aug 29 09:20:51 AM UTC 24
Finished Aug 29 09:21:35 AM UTC 24
Peak memory 255476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780363127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.780363127
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.2511071017
Short name T193
Test name
Test status
Simulation time 639027116 ps
CPU time 7.19 seconds
Started Aug 29 09:20:47 AM UTC 24
Finished Aug 29 09:20:55 AM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511071017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.2511071017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.3240408435
Short name T92
Test name
Test status
Simulation time 367199797 ps
CPU time 5.52 seconds
Started Aug 29 09:20:44 AM UTC 24
Finished Aug 29 09:20:50 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240408435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.3240408435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.3486404251
Short name T194
Test name
Test status
Simulation time 467051985 ps
CPU time 8.46 seconds
Started Aug 29 09:20:47 AM UTC 24
Finished Aug 29 09:20:56 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486404251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.3486404251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.459036479
Short name T160
Test name
Test status
Simulation time 857324725 ps
CPU time 11.3 seconds
Started Aug 29 09:20:45 AM UTC 24
Finished Aug 29 09:20:58 AM UTC 24
Peak memory 257368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459036479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.459036479
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.897934397
Short name T195
Test name
Test status
Simulation time 407275217 ps
CPU time 8.38 seconds
Started Aug 29 09:20:59 AM UTC 24
Finished Aug 29 09:21:08 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897934397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.897934397
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.3208299991
Short name T211
Test name
Test status
Simulation time 124956851 ps
CPU time 5.8 seconds
Started Aug 29 09:20:39 AM UTC 24
Finished Aug 29 09:20:46 AM UTC 24
Peak memory 251552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208299991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.3208299991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.1048961387
Short name T15
Test name
Test status
Simulation time 1771282870 ps
CPU time 83.06 seconds
Started Aug 29 09:21:13 AM UTC 24
Finished Aug 29 09:22:38 AM UTC 24
Peak memory 257576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1048961387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.otp_ctrl_stress_all_with_rand_reset.1048961387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.2216972503
Short name T196
Test name
Test status
Simulation time 445777193 ps
CPU time 13.62 seconds
Started Aug 29 09:21:09 AM UTC 24
Finished Aug 29 09:21:24 AM UTC 24
Peak memory 251568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216972503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.2216972503
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.2869465769
Short name T575
Test name
Test status
Simulation time 136728528 ps
CPU time 2.72 seconds
Started Aug 29 09:31:07 AM UTC 24
Finished Aug 29 09:31:11 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869465769 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.2869465769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.775977089
Short name T81
Test name
Test status
Simulation time 1803965366 ps
CPU time 17 seconds
Started Aug 29 09:30:59 AM UTC 24
Finished Aug 29 09:31:17 AM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775977089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.775977089
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.3896679698
Short name T604
Test name
Test status
Simulation time 2817701193 ps
CPU time 59.21 seconds
Started Aug 29 09:30:59 AM UTC 24
Finished Aug 29 09:32:00 AM UTC 24
Peak memory 261532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896679698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.3896679698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.1032829511
Short name T385
Test name
Test status
Simulation time 4358405306 ps
CPU time 14.39 seconds
Started Aug 29 09:30:56 AM UTC 24
Finished Aug 29 09:31:12 AM UTC 24
Peak memory 253528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032829511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.1032829511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.4262552033
Short name T566
Test name
Test status
Simulation time 270894632 ps
CPU time 4.24 seconds
Started Aug 29 09:30:47 AM UTC 24
Finished Aug 29 09:30:52 AM UTC 24
Peak memory 251488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262552033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.4262552033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.703846849
Short name T592
Test name
Test status
Simulation time 3787716759 ps
CPU time 48.06 seconds
Started Aug 29 09:30:59 AM UTC 24
Finished Aug 29 09:31:48 AM UTC 24
Peak memory 257944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703846849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.703846849
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.1343893334
Short name T574
Test name
Test status
Simulation time 303730596 ps
CPU time 8.93 seconds
Started Aug 29 09:30:59 AM UTC 24
Finished Aug 29 09:31:09 AM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343893334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.1343893334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.2462568476
Short name T572
Test name
Test status
Simulation time 539140804 ps
CPU time 9.07 seconds
Started Aug 29 09:30:56 AM UTC 24
Finished Aug 29 09:31:06 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462568476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.2462568476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.3216114502
Short name T571
Test name
Test status
Simulation time 1094391971 ps
CPU time 11.87 seconds
Started Aug 29 09:30:52 AM UTC 24
Finished Aug 29 09:31:05 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216114502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3216114502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.2476765523
Short name T577
Test name
Test status
Simulation time 909656539 ps
CPU time 13.18 seconds
Started Aug 29 09:31:01 AM UTC 24
Finished Aug 29 09:31:16 AM UTC 24
Peak memory 251116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476765523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.2476765523
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.2260064226
Short name T568
Test name
Test status
Simulation time 345958644 ps
CPU time 7.54 seconds
Started Aug 29 09:30:47 AM UTC 24
Finished Aug 29 09:30:55 AM UTC 24
Peak memory 251304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260064226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.2260064226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.3711521459
Short name T331
Test name
Test status
Simulation time 23042736705 ps
CPU time 250.25 seconds
Started Aug 29 09:31:06 AM UTC 24
Finished Aug 29 09:35:21 AM UTC 24
Peak memory 274228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711521459 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.3711521459
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.2689174325
Short name T581
Test name
Test status
Simulation time 1814467165 ps
CPU time 23.2 seconds
Started Aug 29 09:31:02 AM UTC 24
Finished Aug 29 09:31:26 AM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689174325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.2689174325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.4293422863
Short name T584
Test name
Test status
Simulation time 154823471 ps
CPU time 2.71 seconds
Started Aug 29 09:31:28 AM UTC 24
Finished Aug 29 09:31:31 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293422863 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.4293422863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.1719492214
Short name T588
Test name
Test status
Simulation time 786756138 ps
CPU time 17.68 seconds
Started Aug 29 09:31:20 AM UTC 24
Finished Aug 29 09:31:39 AM UTC 24
Peak memory 251608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719492214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.1719492214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.3991225863
Short name T586
Test name
Test status
Simulation time 265741337 ps
CPU time 15.58 seconds
Started Aug 29 09:31:16 AM UTC 24
Finished Aug 29 09:31:33 AM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991225863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.3991225863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.3635403370
Short name T600
Test name
Test status
Simulation time 2483054949 ps
CPU time 42.45 seconds
Started Aug 29 09:31:13 AM UTC 24
Finished Aug 29 09:31:57 AM UTC 24
Peak memory 253428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635403370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.3635403370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.169715085
Short name T576
Test name
Test status
Simulation time 162309208 ps
CPU time 4.56 seconds
Started Aug 29 09:31:10 AM UTC 24
Finished Aug 29 09:31:15 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169715085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.169715085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.2447562336
Short name T212
Test name
Test status
Simulation time 4778078241 ps
CPU time 39.37 seconds
Started Aug 29 09:31:20 AM UTC 24
Finished Aug 29 09:32:01 AM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447562336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2447562336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.2888036149
Short name T585
Test name
Test status
Simulation time 326803544 ps
CPU time 10.66 seconds
Started Aug 29 09:31:20 AM UTC 24
Finished Aug 29 09:31:32 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888036149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.2888036149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.4235299179
Short name T580
Test name
Test status
Simulation time 2451872540 ps
CPU time 11.39 seconds
Started Aug 29 09:31:13 AM UTC 24
Finished Aug 29 09:31:25 AM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235299179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.4235299179
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.2607570850
Short name T583
Test name
Test status
Simulation time 4825837268 ps
CPU time 17.37 seconds
Started Aug 29 09:31:13 AM UTC 24
Finished Aug 29 09:31:31 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607570850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.2607570850
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.571706801
Short name T579
Test name
Test status
Simulation time 2792278647 ps
CPU time 9.77 seconds
Started Aug 29 09:31:09 AM UTC 24
Finished Aug 29 09:31:20 AM UTC 24
Peak memory 251748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571706801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.571706801
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.4096944559
Short name T610
Test name
Test status
Simulation time 3678431048 ps
CPU time 44.85 seconds
Started Aug 29 09:31:22 AM UTC 24
Finished Aug 29 09:32:08 AM UTC 24
Peak memory 251640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096944559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.4096944559
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.345552201
Short name T597
Test name
Test status
Simulation time 410324558 ps
CPU time 7.47 seconds
Started Aug 29 09:31:47 AM UTC 24
Finished Aug 29 09:31:55 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345552201 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.345552201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.2856849895
Short name T598
Test name
Test status
Simulation time 1041363089 ps
CPU time 21.02 seconds
Started Aug 29 09:31:34 AM UTC 24
Finished Aug 29 09:31:56 AM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856849895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.2856849895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.281705947
Short name T593
Test name
Test status
Simulation time 210949714 ps
CPU time 15.71 seconds
Started Aug 29 09:31:34 AM UTC 24
Finished Aug 29 09:31:51 AM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281705947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.281705947
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.1994529555
Short name T620
Test name
Test status
Simulation time 6478125078 ps
CPU time 51.81 seconds
Started Aug 29 09:31:34 AM UTC 24
Finished Aug 29 09:32:27 AM UTC 24
Peak memory 253464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994529555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.1994529555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.1040846201
Short name T589
Test name
Test status
Simulation time 283786222 ps
CPU time 5.31 seconds
Started Aug 29 09:31:34 AM UTC 24
Finished Aug 29 09:31:40 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040846201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.1040846201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.720849002
Short name T603
Test name
Test status
Simulation time 552904875 ps
CPU time 19.97 seconds
Started Aug 29 09:31:38 AM UTC 24
Finished Aug 29 09:31:59 AM UTC 24
Peak memory 253568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720849002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.720849002
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.1890032378
Short name T609
Test name
Test status
Simulation time 1509739673 ps
CPU time 28.91 seconds
Started Aug 29 09:31:38 AM UTC 24
Finished Aug 29 09:32:08 AM UTC 24
Peak memory 257472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890032378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.1890032378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.1148681111
Short name T98
Test name
Test status
Simulation time 656709471 ps
CPU time 13.26 seconds
Started Aug 29 09:31:34 AM UTC 24
Finished Aug 29 09:31:48 AM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148681111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.1148681111
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.4169692870
Short name T596
Test name
Test status
Simulation time 479128904 ps
CPU time 19.96 seconds
Started Aug 29 09:31:34 AM UTC 24
Finished Aug 29 09:31:55 AM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169692870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.4169692870
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.816658856
Short name T594
Test name
Test status
Simulation time 474468626 ps
CPU time 8.97 seconds
Started Aug 29 09:31:41 AM UTC 24
Finished Aug 29 09:31:51 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816658856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.816658856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.4113301941
Short name T590
Test name
Test status
Simulation time 490985575 ps
CPU time 10.16 seconds
Started Aug 29 09:31:29 AM UTC 24
Finished Aug 29 09:31:40 AM UTC 24
Peak memory 251432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113301941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.4113301941
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.293823567
Short name T1168
Test name
Test status
Simulation time 66552015311 ps
CPU time 807.71 seconds
Started Aug 29 09:31:42 AM UTC 24
Finished Aug 29 09:45:20 AM UTC 24
Peak memory 278296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293823567 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.293823567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.4255983672
Short name T591
Test name
Test status
Simulation time 426688808 ps
CPU time 6.56 seconds
Started Aug 29 09:31:41 AM UTC 24
Finished Aug 29 09:31:48 AM UTC 24
Peak memory 251640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255983672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.4255983672
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.3378518523
Short name T606
Test name
Test status
Simulation time 270174812 ps
CPU time 2.98 seconds
Started Aug 29 09:31:59 AM UTC 24
Finished Aug 29 09:32:03 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378518523 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3378518523
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.1442090265
Short name T619
Test name
Test status
Simulation time 1124365746 ps
CPU time 26.5 seconds
Started Aug 29 09:31:56 AM UTC 24
Finished Aug 29 09:32:24 AM UTC 24
Peak memory 253464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442090265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.1442090265
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.4290092603
Short name T608
Test name
Test status
Simulation time 702963729 ps
CPU time 10.01 seconds
Started Aug 29 09:31:56 AM UTC 24
Finished Aug 29 09:32:07 AM UTC 24
Peak memory 251620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290092603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.4290092603
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.3235704968
Short name T605
Test name
Test status
Simulation time 1190356605 ps
CPU time 9.67 seconds
Started Aug 29 09:31:51 AM UTC 24
Finished Aug 29 09:32:02 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235704968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3235704968
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.1223732518
Short name T599
Test name
Test status
Simulation time 110615014 ps
CPU time 5.62 seconds
Started Aug 29 09:31:50 AM UTC 24
Finished Aug 29 09:31:56 AM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223732518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.1223732518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.3482753164
Short name T616
Test name
Test status
Simulation time 1503505162 ps
CPU time 22.73 seconds
Started Aug 29 09:31:58 AM UTC 24
Finished Aug 29 09:32:22 AM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482753164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.3482753164
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.2562839779
Short name T398
Test name
Test status
Simulation time 428963341 ps
CPU time 28.96 seconds
Started Aug 29 09:31:58 AM UTC 24
Finished Aug 29 09:32:29 AM UTC 24
Peak memory 253280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562839779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2562839779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.4164152666
Short name T144
Test name
Test status
Simulation time 521385888 ps
CPU time 8.61 seconds
Started Aug 29 09:31:51 AM UTC 24
Finished Aug 29 09:32:01 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164152666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.4164152666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.1247693845
Short name T601
Test name
Test status
Simulation time 299422927 ps
CPU time 6.01 seconds
Started Aug 29 09:31:50 AM UTC 24
Finished Aug 29 09:31:57 AM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247693845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1247693845
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.4192307686
Short name T607
Test name
Test status
Simulation time 124164093 ps
CPU time 5.37 seconds
Started Aug 29 09:31:58 AM UTC 24
Finished Aug 29 09:32:05 AM UTC 24
Peak memory 251540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192307686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.4192307686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.1699236245
Short name T602
Test name
Test status
Simulation time 484340510 ps
CPU time 6.3 seconds
Started Aug 29 09:31:50 AM UTC 24
Finished Aug 29 09:31:57 AM UTC 24
Peak memory 257384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699236245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.1699236245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.1707752136
Short name T828
Test name
Test status
Simulation time 127204577239 ps
CPU time 276.07 seconds
Started Aug 29 09:31:59 AM UTC 24
Finished Aug 29 09:36:39 AM UTC 24
Peak memory 302684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707752136 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.1707752136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.1390195753
Short name T617
Test name
Test status
Simulation time 2013618022 ps
CPU time 22.97 seconds
Started Aug 29 09:31:59 AM UTC 24
Finished Aug 29 09:32:23 AM UTC 24
Peak memory 251576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390195753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.1390195753
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.2334229342
Short name T614
Test name
Test status
Simulation time 94205662 ps
CPU time 2.52 seconds
Started Aug 29 09:32:13 AM UTC 24
Finished Aug 29 09:32:16 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334229342 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.2334229342
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.951183777
Short name T50
Test name
Test status
Simulation time 5445679358 ps
CPU time 40.48 seconds
Started Aug 29 09:32:03 AM UTC 24
Finished Aug 29 09:32:45 AM UTC 24
Peak memory 253464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951183777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.951183777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.2524372936
Short name T626
Test name
Test status
Simulation time 3548162723 ps
CPU time 28.96 seconds
Started Aug 29 09:32:03 AM UTC 24
Finished Aug 29 09:32:34 AM UTC 24
Peak memory 251360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524372936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2524372936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.3189787213
Short name T618
Test name
Test status
Simulation time 1605850454 ps
CPU time 18.78 seconds
Started Aug 29 09:32:03 AM UTC 24
Finished Aug 29 09:32:23 AM UTC 24
Peak memory 253372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189787213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3189787213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.1897753233
Short name T64
Test name
Test status
Simulation time 673847268 ps
CPU time 7.4 seconds
Started Aug 29 09:32:01 AM UTC 24
Finished Aug 29 09:32:10 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897753233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.1897753233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.67228957
Short name T613
Test name
Test status
Simulation time 420193945 ps
CPU time 9.61 seconds
Started Aug 29 09:32:05 AM UTC 24
Finished Aug 29 09:32:16 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67228957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.67228957
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.1983275581
Short name T623
Test name
Test status
Simulation time 645109481 ps
CPU time 22.86 seconds
Started Aug 29 09:32:06 AM UTC 24
Finished Aug 29 09:32:30 AM UTC 24
Peak memory 253400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983275581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.1983275581
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.2237228936
Short name T611
Test name
Test status
Simulation time 389216687 ps
CPU time 6.37 seconds
Started Aug 29 09:32:03 AM UTC 24
Finished Aug 29 09:32:11 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237228936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.2237228936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.698136836
Short name T381
Test name
Test status
Simulation time 961587704 ps
CPU time 25.31 seconds
Started Aug 29 09:32:01 AM UTC 24
Finished Aug 29 09:32:28 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698136836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.698136836
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.1300920214
Short name T624
Test name
Test status
Simulation time 3821666817 ps
CPU time 19.67 seconds
Started Aug 29 09:32:10 AM UTC 24
Finished Aug 29 09:32:31 AM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300920214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.1300920214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.93381930
Short name T612
Test name
Test status
Simulation time 302829575 ps
CPU time 8.55 seconds
Started Aug 29 09:32:01 AM UTC 24
Finished Aug 29 09:32:11 AM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93381930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.93381930
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.1318025808
Short name T382
Test name
Test status
Simulation time 36311492853 ps
CPU time 93.09 seconds
Started Aug 29 09:32:12 AM UTC 24
Finished Aug 29 09:33:48 AM UTC 24
Peak memory 270136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1318025808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.otp_ctrl_stress_all_with_rand_reset.1318025808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.1729350228
Short name T622
Test name
Test status
Simulation time 433149006 ps
CPU time 15.2 seconds
Started Aug 29 09:32:12 AM UTC 24
Finished Aug 29 09:32:29 AM UTC 24
Peak memory 251636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729350228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.1729350228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.2203534654
Short name T629
Test name
Test status
Simulation time 74214984 ps
CPU time 2.13 seconds
Started Aug 29 09:32:35 AM UTC 24
Finished Aug 29 09:32:38 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203534654 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2203534654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.3979189627
Short name T72
Test name
Test status
Simulation time 1755083445 ps
CPU time 46.01 seconds
Started Aug 29 09:32:24 AM UTC 24
Finished Aug 29 09:33:12 AM UTC 24
Peak memory 253400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979189627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.3979189627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.1224024996
Short name T670
Test name
Test status
Simulation time 22768887251 ps
CPU time 82.21 seconds
Started Aug 29 09:32:20 AM UTC 24
Finished Aug 29 09:33:44 AM UTC 24
Peak memory 263576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224024996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.1224024996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.530713044
Short name T625
Test name
Test status
Simulation time 1035085548 ps
CPU time 11.27 seconds
Started Aug 29 09:32:20 AM UTC 24
Finished Aug 29 09:32:32 AM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530713044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.530713044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.2960977753
Short name T38
Test name
Test status
Simulation time 400225233 ps
CPU time 5.29 seconds
Started Aug 29 09:32:13 AM UTC 24
Finished Aug 29 09:32:19 AM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960977753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.2960977753
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.2345563456
Short name T646
Test name
Test status
Simulation time 21598600108 ps
CPU time 40.83 seconds
Started Aug 29 09:32:24 AM UTC 24
Finished Aug 29 09:33:06 AM UTC 24
Peak memory 267928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345563456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.2345563456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.1165769847
Short name T628
Test name
Test status
Simulation time 501372246 ps
CPU time 12.24 seconds
Started Aug 29 09:32:24 AM UTC 24
Finished Aug 29 09:32:37 AM UTC 24
Peak memory 251580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165769847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1165769847
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.2728545070
Short name T150
Test name
Test status
Simulation time 706154685 ps
CPU time 7.87 seconds
Started Aug 29 09:32:17 AM UTC 24
Finished Aug 29 09:32:26 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728545070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.2728545070
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.2136860777
Short name T621
Test name
Test status
Simulation time 362734345 ps
CPU time 10.33 seconds
Started Aug 29 09:32:17 AM UTC 24
Finished Aug 29 09:32:28 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136860777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.2136860777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.2442167599
Short name T630
Test name
Test status
Simulation time 405719134 ps
CPU time 12.62 seconds
Started Aug 29 09:32:26 AM UTC 24
Finished Aug 29 09:32:40 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442167599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.2442167599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.2050701322
Short name T615
Test name
Test status
Simulation time 125390940 ps
CPU time 5.07 seconds
Started Aug 29 09:32:13 AM UTC 24
Finished Aug 29 09:32:19 AM UTC 24
Peak memory 251304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050701322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.2050701322
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.2251055897
Short name T257
Test name
Test status
Simulation time 1126888813 ps
CPU time 30.53 seconds
Started Aug 29 09:32:35 AM UTC 24
Finished Aug 29 09:33:06 AM UTC 24
Peak memory 253568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251055897 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.2251055897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.429051304
Short name T643
Test name
Test status
Simulation time 2473346662 ps
CPU time 35.78 seconds
Started Aug 29 09:32:26 AM UTC 24
Finished Aug 29 09:33:04 AM UTC 24
Peak memory 257780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429051304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.429051304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.3358785752
Short name T632
Test name
Test status
Simulation time 214101598 ps
CPU time 2.84 seconds
Started Aug 29 09:32:43 AM UTC 24
Finished Aug 29 09:32:47 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358785752 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.3358785752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.2515967080
Short name T88
Test name
Test status
Simulation time 955484621 ps
CPU time 32.95 seconds
Started Aug 29 09:32:35 AM UTC 24
Finished Aug 29 09:33:09 AM UTC 24
Peak memory 257752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515967080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.2515967080
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.1939034328
Short name T638
Test name
Test status
Simulation time 1291327888 ps
CPU time 19.41 seconds
Started Aug 29 09:32:35 AM UTC 24
Finished Aug 29 09:32:56 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939034328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.1939034328
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.1546909514
Short name T637
Test name
Test status
Simulation time 638188322 ps
CPU time 19.29 seconds
Started Aug 29 09:32:35 AM UTC 24
Finished Aug 29 09:32:55 AM UTC 24
Peak memory 251576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546909514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.1546909514
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.4056343309
Short name T642
Test name
Test status
Simulation time 1936085201 ps
CPU time 24.79 seconds
Started Aug 29 09:32:37 AM UTC 24
Finished Aug 29 09:33:03 AM UTC 24
Peak memory 257468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056343309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.4056343309
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.1918340782
Short name T651
Test name
Test status
Simulation time 1966115533 ps
CPU time 39.57 seconds
Started Aug 29 09:32:37 AM UTC 24
Finished Aug 29 09:33:18 AM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918340782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1918340782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.2173017618
Short name T145
Test name
Test status
Simulation time 542636423 ps
CPU time 6.38 seconds
Started Aug 29 09:32:35 AM UTC 24
Finished Aug 29 09:32:42 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173017618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.2173017618
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.2909890769
Short name T634
Test name
Test status
Simulation time 677057584 ps
CPU time 14.52 seconds
Started Aug 29 09:32:35 AM UTC 24
Finished Aug 29 09:32:50 AM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909890769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.2909890769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.337477543
Short name T631
Test name
Test status
Simulation time 303101548 ps
CPU time 6 seconds
Started Aug 29 09:32:38 AM UTC 24
Finished Aug 29 09:32:45 AM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337477543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.337477543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.2092095249
Short name T633
Test name
Test status
Simulation time 5223072554 ps
CPU time 12.15 seconds
Started Aug 29 09:32:35 AM UTC 24
Finished Aug 29 09:32:48 AM UTC 24
Peak memory 257552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092095249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.2092095249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.3155653415
Short name T685
Test name
Test status
Simulation time 11951736732 ps
CPU time 78.59 seconds
Started Aug 29 09:32:42 AM UTC 24
Finished Aug 29 09:34:02 AM UTC 24
Peak memory 255416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155653415 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.3155653415
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.1310309816
Short name T641
Test name
Test status
Simulation time 1050791044 ps
CPU time 19.71 seconds
Started Aug 29 09:32:38 AM UTC 24
Finished Aug 29 09:32:59 AM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310309816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.1310309816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.3007171600
Short name T644
Test name
Test status
Simulation time 218849799 ps
CPU time 3.01 seconds
Started Aug 29 09:33:00 AM UTC 24
Finished Aug 29 09:33:04 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007171600 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.3007171600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.4110506752
Short name T662
Test name
Test status
Simulation time 3215211105 ps
CPU time 37.98 seconds
Started Aug 29 09:32:55 AM UTC 24
Finished Aug 29 09:33:34 AM UTC 24
Peak memory 257880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110506752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.4110506752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.305057139
Short name T648
Test name
Test status
Simulation time 314451827 ps
CPU time 17.8 seconds
Started Aug 29 09:32:51 AM UTC 24
Finished Aug 29 09:33:10 AM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305057139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.305057139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.1709619505
Short name T653
Test name
Test status
Simulation time 2125642920 ps
CPU time 29.39 seconds
Started Aug 29 09:32:49 AM UTC 24
Finished Aug 29 09:33:20 AM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709619505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.1709619505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.2234284319
Short name T636
Test name
Test status
Simulation time 176669644 ps
CPU time 6.18 seconds
Started Aug 29 09:32:47 AM UTC 24
Finished Aug 29 09:32:54 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234284319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2234284319
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.3851822708
Short name T647
Test name
Test status
Simulation time 3781802843 ps
CPU time 11.94 seconds
Started Aug 29 09:32:56 AM UTC 24
Finished Aug 29 09:33:09 AM UTC 24
Peak memory 253824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851822708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.3851822708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.534414849
Short name T668
Test name
Test status
Simulation time 2893509631 ps
CPU time 44.62 seconds
Started Aug 29 09:32:56 AM UTC 24
Finished Aug 29 09:33:42 AM UTC 24
Peak memory 251372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534414849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.534414849
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.1225072256
Short name T639
Test name
Test status
Simulation time 2441323301 ps
CPU time 8.08 seconds
Started Aug 29 09:32:48 AM UTC 24
Finished Aug 29 09:32:57 AM UTC 24
Peak memory 253532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225072256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.1225072256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.2836914144
Short name T640
Test name
Test status
Simulation time 234860483 ps
CPU time 9.91 seconds
Started Aug 29 09:32:47 AM UTC 24
Finished Aug 29 09:32:58 AM UTC 24
Peak memory 257368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836914144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.2836914144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.3554541074
Short name T645
Test name
Test status
Simulation time 390397423 ps
CPU time 6.58 seconds
Started Aug 29 09:32:58 AM UTC 24
Finished Aug 29 09:33:05 AM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554541074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3554541074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.3305970653
Short name T635
Test name
Test status
Simulation time 288080305 ps
CPU time 7.41 seconds
Started Aug 29 09:32:45 AM UTC 24
Finished Aug 29 09:32:54 AM UTC 24
Peak memory 251304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305970653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.3305970653
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.3724038247
Short name T719
Test name
Test status
Simulation time 11732178347 ps
CPU time 94.49 seconds
Started Aug 29 09:32:59 AM UTC 24
Finished Aug 29 09:34:36 AM UTC 24
Peak memory 255512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724038247 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.3724038247
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.2327954938
Short name T649
Test name
Test status
Simulation time 809053326 ps
CPU time 14.16 seconds
Started Aug 29 09:32:58 AM UTC 24
Finished Aug 29 09:33:13 AM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327954938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.2327954938
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.2383515271
Short name T655
Test name
Test status
Simulation time 63763682 ps
CPU time 2.78 seconds
Started Aug 29 09:33:21 AM UTC 24
Finished Aug 29 09:33:25 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383515271 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.2383515271
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.1514716141
Short name T412
Test name
Test status
Simulation time 639927387 ps
CPU time 27.74 seconds
Started Aug 29 09:33:08 AM UTC 24
Finished Aug 29 09:33:37 AM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514716141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.1514716141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.1234866738
Short name T660
Test name
Test status
Simulation time 3997319193 ps
CPU time 19.93 seconds
Started Aug 29 09:33:08 AM UTC 24
Finished Aug 29 09:33:29 AM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234866738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.1234866738
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.1462857100
Short name T400
Test name
Test status
Simulation time 1020306424 ps
CPU time 13.81 seconds
Started Aug 29 09:33:06 AM UTC 24
Finished Aug 29 09:33:21 AM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462857100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.1462857100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.3023175833
Short name T663
Test name
Test status
Simulation time 6265611316 ps
CPU time 22.47 seconds
Started Aug 29 09:33:12 AM UTC 24
Finished Aug 29 09:33:36 AM UTC 24
Peak memory 257944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023175833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3023175833
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.2897731437
Short name T674
Test name
Test status
Simulation time 1057252490 ps
CPU time 26.08 seconds
Started Aug 29 09:33:21 AM UTC 24
Finished Aug 29 09:33:48 AM UTC 24
Peak memory 257724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897731437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.2897731437
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.3567268915
Short name T652
Test name
Test status
Simulation time 165875337 ps
CPU time 12.07 seconds
Started Aug 29 09:33:06 AM UTC 24
Finished Aug 29 09:33:19 AM UTC 24
Peak memory 253204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567268915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.3567268915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.119523803
Short name T654
Test name
Test status
Simulation time 687112137 ps
CPU time 16.35 seconds
Started Aug 29 09:33:06 AM UTC 24
Finished Aug 29 09:33:23 AM UTC 24
Peak memory 257620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119523803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.119523803
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.2893757417
Short name T656
Test name
Test status
Simulation time 644608945 ps
CPU time 6.12 seconds
Started Aug 29 09:33:21 AM UTC 24
Finished Aug 29 09:33:28 AM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893757417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.2893757417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.1515198834
Short name T650
Test name
Test status
Simulation time 1845580289 ps
CPU time 15.23 seconds
Started Aug 29 09:33:02 AM UTC 24
Finished Aug 29 09:33:18 AM UTC 24
Peak memory 251496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515198834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1515198834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.1250161981
Short name T792
Test name
Test status
Simulation time 14602074722 ps
CPU time 150.66 seconds
Started Aug 29 09:33:21 AM UTC 24
Finished Aug 29 09:35:54 AM UTC 24
Peak memory 304668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250161981 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.1250161981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.3200364191
Short name T665
Test name
Test status
Simulation time 831988222 ps
CPU time 18.32 seconds
Started Aug 29 09:33:21 AM UTC 24
Finished Aug 29 09:33:40 AM UTC 24
Peak memory 253368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200364191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3200364191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.2007319944
Short name T664
Test name
Test status
Simulation time 557389369 ps
CPU time 2.79 seconds
Started Aug 29 09:33:35 AM UTC 24
Finished Aug 29 09:33:40 AM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007319944 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.2007319944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.234881176
Short name T677
Test name
Test status
Simulation time 4137164528 ps
CPU time 25.94 seconds
Started Aug 29 09:33:25 AM UTC 24
Finished Aug 29 09:33:52 AM UTC 24
Peak memory 251640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234881176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.234881176
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.1152929240
Short name T666
Test name
Test status
Simulation time 907203517 ps
CPU time 15.11 seconds
Started Aug 29 09:33:25 AM UTC 24
Finished Aug 29 09:33:41 AM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152929240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1152929240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.2712031923
Short name T704
Test name
Test status
Simulation time 21373450777 ps
CPU time 56.27 seconds
Started Aug 29 09:33:25 AM UTC 24
Finished Aug 29 09:34:23 AM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712031923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.2712031923
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.2108217190
Short name T657
Test name
Test status
Simulation time 416315075 ps
CPU time 6.51 seconds
Started Aug 29 09:33:21 AM UTC 24
Finished Aug 29 09:33:29 AM UTC 24
Peak memory 251036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108217190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.2108217190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.3761572655
Short name T673
Test name
Test status
Simulation time 656349736 ps
CPU time 22.03 seconds
Started Aug 29 09:33:25 AM UTC 24
Finished Aug 29 09:33:48 AM UTC 24
Peak memory 255488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761572655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.3761572655
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.304916889
Short name T672
Test name
Test status
Simulation time 273259666 ps
CPU time 9.27 seconds
Started Aug 29 09:33:35 AM UTC 24
Finished Aug 29 09:33:47 AM UTC 24
Peak memory 257748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304916889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.304916889
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.3331364742
Short name T659
Test name
Test status
Simulation time 525334149 ps
CPU time 6.6 seconds
Started Aug 29 09:33:21 AM UTC 24
Finished Aug 29 09:33:29 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331364742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3331364742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.182230566
Short name T671
Test name
Test status
Simulation time 1379229130 ps
CPU time 23.63 seconds
Started Aug 29 09:33:21 AM UTC 24
Finished Aug 29 09:33:46 AM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182230566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.182230566
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.245472236
Short name T669
Test name
Test status
Simulation time 181883780 ps
CPU time 5.1 seconds
Started Aug 29 09:33:35 AM UTC 24
Finished Aug 29 09:33:42 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245472236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.245472236
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.853278914
Short name T661
Test name
Test status
Simulation time 706214005 ps
CPU time 7.95 seconds
Started Aug 29 09:33:21 AM UTC 24
Finished Aug 29 09:33:30 AM UTC 24
Peak memory 251620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853278914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.853278914
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.2065261490
Short name T797
Test name
Test status
Simulation time 4054204832 ps
CPU time 141.75 seconds
Started Aug 29 09:33:35 AM UTC 24
Finished Aug 29 09:36:01 AM UTC 24
Peak memory 268084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065261490 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.2065261490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.1106147254
Short name T683
Test name
Test status
Simulation time 895840165 ps
CPU time 22.12 seconds
Started Aug 29 09:33:35 AM UTC 24
Finished Aug 29 09:34:00 AM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106147254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.1106147254
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.3558508483
Short name T418
Test name
Test status
Simulation time 570652229 ps
CPU time 2.89 seconds
Started Aug 29 09:22:09 AM UTC 24
Finished Aug 29 09:22:13 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558508483 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.3558508483
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.1092354243
Short name T399
Test name
Test status
Simulation time 1388758047 ps
CPU time 12.91 seconds
Started Aug 29 09:21:37 AM UTC 24
Finished Aug 29 09:21:51 AM UTC 24
Peak memory 257432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092354243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.1092354243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.2685563600
Short name T70
Test name
Test status
Simulation time 9865452964 ps
CPU time 67.79 seconds
Started Aug 29 09:21:49 AM UTC 24
Finished Aug 29 09:22:59 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685563600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.2685563600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.1209738550
Short name T163
Test name
Test status
Simulation time 2943429684 ps
CPU time 16.6 seconds
Started Aug 29 09:21:45 AM UTC 24
Finished Aug 29 09:22:03 AM UTC 24
Peak memory 253284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209738550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.1209738550
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.1641022506
Short name T114
Test name
Test status
Simulation time 7018979918 ps
CPU time 21.38 seconds
Started Aug 29 09:21:45 AM UTC 24
Finished Aug 29 09:22:08 AM UTC 24
Peak memory 253440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641022506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.1641022506
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.2652490778
Short name T169
Test name
Test status
Simulation time 1483285931 ps
CPU time 14.33 seconds
Started Aug 29 09:21:49 AM UTC 24
Finished Aug 29 09:22:04 AM UTC 24
Peak memory 253396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652490778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.2652490778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.2933357010
Short name T237
Test name
Test status
Simulation time 1178438493 ps
CPU time 20.11 seconds
Started Aug 29 09:21:51 AM UTC 24
Finished Aug 29 09:22:13 AM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933357010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.2933357010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.3864089041
Short name T119
Test name
Test status
Simulation time 194814982 ps
CPU time 7.97 seconds
Started Aug 29 09:21:38 AM UTC 24
Finished Aug 29 09:21:47 AM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864089041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.3864089041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.4034858487
Short name T203
Test name
Test status
Simulation time 812487207 ps
CPU time 30.25 seconds
Started Aug 29 09:21:38 AM UTC 24
Finished Aug 29 09:22:10 AM UTC 24
Peak memory 257404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034858487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.4034858487
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.1807687223
Short name T357
Test name
Test status
Simulation time 382463203 ps
CPU time 5.91 seconds
Started Aug 29 09:21:59 AM UTC 24
Finished Aug 29 09:22:06 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807687223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1807687223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.2232480623
Short name T228
Test name
Test status
Simulation time 10494538648 ps
CPU time 240.44 seconds
Started Aug 29 09:22:07 AM UTC 24
Finished Aug 29 09:26:11 AM UTC 24
Peak memory 296188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232480623 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.2232480623
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.4211514250
Short name T417
Test name
Test status
Simulation time 300829050 ps
CPU time 5.09 seconds
Started Aug 29 09:21:29 AM UTC 24
Finished Aug 29 09:21:35 AM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211514250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.4211514250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.2125650758
Short name T205
Test name
Test status
Simulation time 3326579145 ps
CPU time 33.5 seconds
Started Aug 29 09:22:05 AM UTC 24
Finished Aug 29 09:22:40 AM UTC 24
Peak memory 251704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125650758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.2125650758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.3956269611
Short name T675
Test name
Test status
Simulation time 170813560 ps
CPU time 4.17 seconds
Started Aug 29 09:33:45 AM UTC 24
Finished Aug 29 09:33:50 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956269611 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.3956269611
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.2836392249
Short name T705
Test name
Test status
Simulation time 19244989017 ps
CPU time 39.23 seconds
Started Aug 29 09:33:42 AM UTC 24
Finished Aug 29 09:34:23 AM UTC 24
Peak memory 255512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836392249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.2836392249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.3421753715
Short name T690
Test name
Test status
Simulation time 1762814537 ps
CPU time 26.79 seconds
Started Aug 29 09:33:37 AM UTC 24
Finished Aug 29 09:34:06 AM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421753715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.3421753715
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.3804786052
Short name T692
Test name
Test status
Simulation time 2031279744 ps
CPU time 28.16 seconds
Started Aug 29 09:33:37 AM UTC 24
Finished Aug 29 09:34:07 AM UTC 24
Peak memory 251576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804786052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.3804786052
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.761467787
Short name T667
Test name
Test status
Simulation time 132999572 ps
CPU time 4.23 seconds
Started Aug 29 09:33:35 AM UTC 24
Finished Aug 29 09:33:42 AM UTC 24
Peak memory 253300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761467787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.761467787
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.350967606
Short name T687
Test name
Test status
Simulation time 1855407770 ps
CPU time 19.03 seconds
Started Aug 29 09:33:43 AM UTC 24
Finished Aug 29 09:34:03 AM UTC 24
Peak memory 253436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350967606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.350967606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.7628791
Short name T691
Test name
Test status
Simulation time 516977520 ps
CPU time 22.45 seconds
Started Aug 29 09:33:43 AM UTC 24
Finished Aug 29 09:34:06 AM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7628791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S
EQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.7628791
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.4169104361
Short name T245
Test name
Test status
Simulation time 1365031606 ps
CPU time 22.41 seconds
Started Aug 29 09:33:35 AM UTC 24
Finished Aug 29 09:34:00 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169104361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.4169104361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.2769128759
Short name T686
Test name
Test status
Simulation time 698474493 ps
CPU time 24.72 seconds
Started Aug 29 09:33:35 AM UTC 24
Finished Aug 29 09:34:02 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769128759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.2769128759
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.772363809
Short name T679
Test name
Test status
Simulation time 655527515 ps
CPU time 9.65 seconds
Started Aug 29 09:33:43 AM UTC 24
Finished Aug 29 09:33:53 AM UTC 24
Peak memory 257680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772363809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.772363809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.3859121746
Short name T676
Test name
Test status
Simulation time 1133846357 ps
CPU time 13.36 seconds
Started Aug 29 09:33:35 AM UTC 24
Finished Aug 29 09:33:51 AM UTC 24
Peak memory 251208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859121746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3859121746
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.540685235
Short name T940
Test name
Test status
Simulation time 8000341348 ps
CPU time 293.93 seconds
Started Aug 29 09:33:45 AM UTC 24
Finished Aug 29 09:38:43 AM UTC 24
Peak memory 267968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540685235 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.540685235
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.2705376637
Short name T786
Test name
Test status
Simulation time 45232758960 ps
CPU time 123.46 seconds
Started Aug 29 09:33:43 AM UTC 24
Finished Aug 29 09:35:49 AM UTC 24
Peak memory 274092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2705376637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.otp_ctrl_stress_all_with_rand_reset.2705376637
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.951622334
Short name T680
Test name
Test status
Simulation time 1445644487 ps
CPU time 11.88 seconds
Started Aug 29 09:33:43 AM UTC 24
Finished Aug 29 09:33:56 AM UTC 24
Peak memory 257396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951622334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.951622334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.333033414
Short name T681
Test name
Test status
Simulation time 856852684 ps
CPU time 2.17 seconds
Started Aug 29 09:33:56 AM UTC 24
Finished Aug 29 09:33:59 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333033414 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.333033414
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.3264376726
Short name T708
Test name
Test status
Simulation time 1429473877 ps
CPU time 32.9 seconds
Started Aug 29 09:33:51 AM UTC 24
Finished Aug 29 09:34:25 AM UTC 24
Peak memory 257624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264376726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.3264376726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.1356604149
Short name T713
Test name
Test status
Simulation time 10452356017 ps
CPU time 36.64 seconds
Started Aug 29 09:33:51 AM UTC 24
Finished Aug 29 09:34:29 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356604149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.1356604149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.885669044
Short name T698
Test name
Test status
Simulation time 1619953260 ps
CPU time 23.59 seconds
Started Aug 29 09:33:51 AM UTC 24
Finished Aug 29 09:34:16 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885669044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.885669044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.557990470
Short name T41
Test name
Test status
Simulation time 137564315 ps
CPU time 6.05 seconds
Started Aug 29 09:33:47 AM UTC 24
Finished Aug 29 09:33:54 AM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557990470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.557990470
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.1630713068
Short name T699
Test name
Test status
Simulation time 1345226690 ps
CPU time 21.47 seconds
Started Aug 29 09:33:53 AM UTC 24
Finished Aug 29 09:34:16 AM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630713068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.1630713068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.1332658210
Short name T714
Test name
Test status
Simulation time 1553207276 ps
CPU time 36.81 seconds
Started Aug 29 09:33:53 AM UTC 24
Finished Aug 29 09:34:31 AM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332658210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1332658210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.1264911790
Short name T684
Test name
Test status
Simulation time 173275482 ps
CPU time 8.26 seconds
Started Aug 29 09:33:50 AM UTC 24
Finished Aug 29 09:34:00 AM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264911790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.1264911790
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.2406078526
Short name T688
Test name
Test status
Simulation time 1959029458 ps
CPU time 15.75 seconds
Started Aug 29 09:33:48 AM UTC 24
Finished Aug 29 09:34:05 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406078526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.2406078526
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.2502438559
Short name T682
Test name
Test status
Simulation time 268924620 ps
CPU time 5.28 seconds
Started Aug 29 09:33:53 AM UTC 24
Finished Aug 29 09:33:59 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502438559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.2502438559
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.3324677806
Short name T678
Test name
Test status
Simulation time 239462958 ps
CPU time 5.39 seconds
Started Aug 29 09:33:47 AM UTC 24
Finished Aug 29 09:33:53 AM UTC 24
Peak memory 251432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324677806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.3324677806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.238610774
Short name T716
Test name
Test status
Simulation time 1472394883 ps
CPU time 35.57 seconds
Started Aug 29 09:33:56 AM UTC 24
Finished Aug 29 09:34:33 AM UTC 24
Peak memory 253616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238610774 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.238610774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.1834037263
Short name T410
Test name
Test status
Simulation time 4196760565 ps
CPU time 81.33 seconds
Started Aug 29 09:33:56 AM UTC 24
Finished Aug 29 09:35:19 AM UTC 24
Peak memory 267916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1834037263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.otp_ctrl_stress_all_with_rand_reset.1834037263
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.1276964563
Short name T745
Test name
Test status
Simulation time 5800874111 ps
CPU time 77.24 seconds
Started Aug 29 09:33:55 AM UTC 24
Finished Aug 29 09:35:15 AM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276964563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.1276964563
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.2303739385
Short name T696
Test name
Test status
Simulation time 195301928 ps
CPU time 2.7 seconds
Started Aug 29 09:34:11 AM UTC 24
Finished Aug 29 09:34:15 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303739385 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.2303739385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.650975563
Short name T693
Test name
Test status
Simulation time 2449818365 ps
CPU time 6.38 seconds
Started Aug 29 09:34:03 AM UTC 24
Finished Aug 29 09:34:10 AM UTC 24
Peak memory 257880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650975563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.650975563
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.599466526
Short name T702
Test name
Test status
Simulation time 205706537 ps
CPU time 14.28 seconds
Started Aug 29 09:34:03 AM UTC 24
Finished Aug 29 09:34:18 AM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599466526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.599466526
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.203457267
Short name T712
Test name
Test status
Simulation time 674393406 ps
CPU time 23.38 seconds
Started Aug 29 09:34:03 AM UTC 24
Finished Aug 29 09:34:28 AM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203457267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.203457267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.3708724757
Short name T658
Test name
Test status
Simulation time 133557775 ps
CPU time 6.52 seconds
Started Aug 29 09:34:00 AM UTC 24
Finished Aug 29 09:34:08 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708724757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.3708724757
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.2769992285
Short name T697
Test name
Test status
Simulation time 383894968 ps
CPU time 7.78 seconds
Started Aug 29 09:34:06 AM UTC 24
Finished Aug 29 09:34:15 AM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769992285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.2769992285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.3092733394
Short name T707
Test name
Test status
Simulation time 6352659133 ps
CPU time 17.08 seconds
Started Aug 29 09:34:06 AM UTC 24
Finished Aug 29 09:34:24 AM UTC 24
Peak memory 253720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092733394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.3092733394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.3293671135
Short name T728
Test name
Test status
Simulation time 2722490625 ps
CPU time 41.97 seconds
Started Aug 29 09:34:03 AM UTC 24
Finished Aug 29 09:34:46 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293671135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.3293671135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.4064697416
Short name T689
Test name
Test status
Simulation time 267598388 ps
CPU time 4.02 seconds
Started Aug 29 09:34:00 AM UTC 24
Finished Aug 29 09:34:05 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064697416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.4064697416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.2002106335
Short name T695
Test name
Test status
Simulation time 157591902 ps
CPU time 7.13 seconds
Started Aug 29 09:34:06 AM UTC 24
Finished Aug 29 09:34:15 AM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002106335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.2002106335
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.2445947588
Short name T694
Test name
Test status
Simulation time 3127967810 ps
CPU time 12.72 seconds
Started Aug 29 09:33:57 AM UTC 24
Finished Aug 29 09:34:11 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445947588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.2445947588
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.3748059857
Short name T755
Test name
Test status
Simulation time 23984274605 ps
CPU time 67.68 seconds
Started Aug 29 09:34:11 AM UTC 24
Finished Aug 29 09:35:21 AM UTC 24
Peak memory 257444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748059857 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.3748059857
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.1175632664
Short name T403
Test name
Test status
Simulation time 751051844 ps
CPU time 14.17 seconds
Started Aug 29 09:34:06 AM UTC 24
Finished Aug 29 09:34:22 AM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175632664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.1175632664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.2315713946
Short name T711
Test name
Test status
Simulation time 804920823 ps
CPU time 5.14 seconds
Started Aug 29 09:34:20 AM UTC 24
Finished Aug 29 09:34:26 AM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315713946 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.2315713946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.576388419
Short name T710
Test name
Test status
Simulation time 510663040 ps
CPU time 8.79 seconds
Started Aug 29 09:34:16 AM UTC 24
Finished Aug 29 09:34:26 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576388419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.576388419
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.266789519
Short name T720
Test name
Test status
Simulation time 615312628 ps
CPU time 20.38 seconds
Started Aug 29 09:34:16 AM UTC 24
Finished Aug 29 09:34:37 AM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266789519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.266789519
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.2334810891
Short name T740
Test name
Test status
Simulation time 1902964930 ps
CPU time 43.31 seconds
Started Aug 29 09:34:12 AM UTC 24
Finished Aug 29 09:34:57 AM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334810891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.2334810891
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.3767882360
Short name T701
Test name
Test status
Simulation time 153225078 ps
CPU time 4.72 seconds
Started Aug 29 09:34:11 AM UTC 24
Finished Aug 29 09:34:17 AM UTC 24
Peak memory 251232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767882360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.3767882360
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.1337416018
Short name T703
Test name
Test status
Simulation time 396378347 ps
CPU time 4.63 seconds
Started Aug 29 09:34:16 AM UTC 24
Finished Aug 29 09:34:21 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337416018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.1337416018
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.657126914
Short name T715
Test name
Test status
Simulation time 964692086 ps
CPU time 13.18 seconds
Started Aug 29 09:34:17 AM UTC 24
Finished Aug 29 09:34:32 AM UTC 24
Peak memory 251312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657126914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.657126914
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.3539542124
Short name T700
Test name
Test status
Simulation time 249309731 ps
CPU time 4.42 seconds
Started Aug 29 09:34:11 AM UTC 24
Finished Aug 29 09:34:17 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539542124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.3539542124
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.3002978047
Short name T709
Test name
Test status
Simulation time 1114928718 ps
CPU time 12.84 seconds
Started Aug 29 09:34:11 AM UTC 24
Finished Aug 29 09:34:25 AM UTC 24
Peak memory 257364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002978047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.3002978047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.2013039084
Short name T718
Test name
Test status
Simulation time 710911163 ps
CPU time 15.56 seconds
Started Aug 29 09:34:17 AM UTC 24
Finished Aug 29 09:34:34 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013039084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.2013039084
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.3478557466
Short name T706
Test name
Test status
Simulation time 320440259 ps
CPU time 11.12 seconds
Started Aug 29 09:34:11 AM UTC 24
Finished Aug 29 09:34:24 AM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478557466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.3478557466
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.2069363155
Short name T930
Test name
Test status
Simulation time 17780996936 ps
CPU time 252.79 seconds
Started Aug 29 09:34:20 AM UTC 24
Finished Aug 29 09:38:37 AM UTC 24
Peak memory 270196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069363155 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.2069363155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.665735280
Short name T305
Test name
Test status
Simulation time 10602476985 ps
CPU time 111.35 seconds
Started Aug 29 09:34:19 AM UTC 24
Finished Aug 29 09:36:12 AM UTC 24
Peak memory 267948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=665735280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
43.otp_ctrl_stress_all_with_rand_reset.665735280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.1439157705
Short name T717
Test name
Test status
Simulation time 669524999 ps
CPU time 14.42 seconds
Started Aug 29 09:34:17 AM UTC 24
Finished Aug 29 09:34:33 AM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439157705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.1439157705
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.671567940
Short name T726
Test name
Test status
Simulation time 203572955 ps
CPU time 2.88 seconds
Started Aug 29 09:34:40 AM UTC 24
Finished Aug 29 09:34:44 AM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671567940 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.671567940
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.2372315873
Short name T274
Test name
Test status
Simulation time 9426533251 ps
CPU time 31.36 seconds
Started Aug 29 09:34:27 AM UTC 24
Finished Aug 29 09:35:00 AM UTC 24
Peak memory 253528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372315873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.2372315873
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.2534576262
Short name T722
Test name
Test status
Simulation time 2579198427 ps
CPU time 13.08 seconds
Started Aug 29 09:34:25 AM UTC 24
Finished Aug 29 09:34:39 AM UTC 24
Peak memory 253536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534576262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.2534576262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.3677684264
Short name T724
Test name
Test status
Simulation time 1119587848 ps
CPU time 16.53 seconds
Started Aug 29 09:34:25 AM UTC 24
Finished Aug 29 09:34:42 AM UTC 24
Peak memory 257356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677684264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.3677684264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.3109251446
Short name T66
Test name
Test status
Simulation time 1674465478 ps
CPU time 7.27 seconds
Started Aug 29 09:34:23 AM UTC 24
Finished Aug 29 09:34:31 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109251446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.3109251446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.2099364378
Short name T281
Test name
Test status
Simulation time 2140803193 ps
CPU time 38.41 seconds
Started Aug 29 09:34:27 AM UTC 24
Finished Aug 29 09:35:07 AM UTC 24
Peak memory 255680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099364378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2099364378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.944140019
Short name T735
Test name
Test status
Simulation time 1683832889 ps
CPU time 23.08 seconds
Started Aug 29 09:34:27 AM UTC 24
Finished Aug 29 09:34:52 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944140019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.944140019
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.1192422656
Short name T725
Test name
Test status
Simulation time 7550741574 ps
CPU time 17.66 seconds
Started Aug 29 09:34:25 AM UTC 24
Finished Aug 29 09:34:44 AM UTC 24
Peak memory 251140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192422656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.1192422656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.3354893520
Short name T732
Test name
Test status
Simulation time 11170251016 ps
CPU time 25.46 seconds
Started Aug 29 09:34:23 AM UTC 24
Finished Aug 29 09:34:49 AM UTC 24
Peak memory 257432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354893520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.3354893520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.1650771421
Short name T721
Test name
Test status
Simulation time 2510797808 ps
CPU time 9.63 seconds
Started Aug 29 09:34:27 AM UTC 24
Finished Aug 29 09:34:38 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650771421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.1650771421
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.1017893370
Short name T723
Test name
Test status
Simulation time 575699103 ps
CPU time 17.6 seconds
Started Aug 29 09:34:20 AM UTC 24
Finished Aug 29 09:34:39 AM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017893370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1017893370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.92520671
Short name T139
Test name
Test status
Simulation time 83291419569 ps
CPU time 204.94 seconds
Started Aug 29 09:34:30 AM UTC 24
Finished Aug 29 09:37:59 AM UTC 24
Peak memory 270044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92520671 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.92520671
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.3680149264
Short name T777
Test name
Test status
Simulation time 2043605716 ps
CPU time 71.42 seconds
Started Aug 29 09:34:29 AM UTC 24
Finished Aug 29 09:35:42 AM UTC 24
Peak memory 268140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3680149264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.otp_ctrl_stress_all_with_rand_reset.3680149264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.2435112816
Short name T738
Test name
Test status
Simulation time 1509657548 ps
CPU time 25.72 seconds
Started Aug 29 09:34:27 AM UTC 24
Finished Aug 29 09:34:54 AM UTC 24
Peak memory 253344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435112816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.2435112816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.201313352
Short name T730
Test name
Test status
Simulation time 46507964 ps
CPU time 2.53 seconds
Started Aug 29 09:34:45 AM UTC 24
Finished Aug 29 09:34:48 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201313352 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.201313352
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.3594457360
Short name T736
Test name
Test status
Simulation time 262777827 ps
CPU time 10.83 seconds
Started Aug 29 09:34:40 AM UTC 24
Finished Aug 29 09:34:52 AM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594457360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.3594457360
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.1161443423
Short name T763
Test name
Test status
Simulation time 3595941489 ps
CPU time 51.43 seconds
Started Aug 29 09:34:40 AM UTC 24
Finished Aug 29 09:35:33 AM UTC 24
Peak memory 259512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161443423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.1161443423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.744358962
Short name T733
Test name
Test status
Simulation time 397557282 ps
CPU time 8.18 seconds
Started Aug 29 09:34:40 AM UTC 24
Finished Aug 29 09:34:49 AM UTC 24
Peak memory 257464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744358962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.744358962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.746862667
Short name T727
Test name
Test status
Simulation time 203519072 ps
CPU time 4.55 seconds
Started Aug 29 09:34:40 AM UTC 24
Finished Aug 29 09:34:46 AM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746862667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.746862667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.4193006518
Short name T744
Test name
Test status
Simulation time 1334719048 ps
CPU time 31.77 seconds
Started Aug 29 09:34:40 AM UTC 24
Finished Aug 29 09:35:13 AM UTC 24
Peak memory 257388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193006518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.4193006518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.536833337
Short name T739
Test name
Test status
Simulation time 951677397 ps
CPU time 15.56 seconds
Started Aug 29 09:34:40 AM UTC 24
Finished Aug 29 09:34:57 AM UTC 24
Peak memory 251604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536833337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.536833337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.131874885
Short name T743
Test name
Test status
Simulation time 15488362897 ps
CPU time 27.79 seconds
Started Aug 29 09:34:40 AM UTC 24
Finished Aug 29 09:35:09 AM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131874885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.131874885
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.3005359771
Short name T731
Test name
Test status
Simulation time 222678000 ps
CPU time 7.34 seconds
Started Aug 29 09:34:40 AM UTC 24
Finished Aug 29 09:34:48 AM UTC 24
Peak memory 257524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005359771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.3005359771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.981051368
Short name T734
Test name
Test status
Simulation time 597206423 ps
CPU time 8.61 seconds
Started Aug 29 09:34:40 AM UTC 24
Finished Aug 29 09:34:50 AM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981051368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.981051368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.3135691359
Short name T729
Test name
Test status
Simulation time 326263306 ps
CPU time 7.32 seconds
Started Aug 29 09:34:40 AM UTC 24
Finished Aug 29 09:34:48 AM UTC 24
Peak memory 251432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135691359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3135691359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.1869429628
Short name T883
Test name
Test status
Simulation time 44593385308 ps
CPU time 199.79 seconds
Started Aug 29 09:34:43 AM UTC 24
Finished Aug 29 09:38:06 AM UTC 24
Peak memory 267996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869429628 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.1869429628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.1737604746
Short name T758
Test name
Test status
Simulation time 2161206111 ps
CPU time 46.6 seconds
Started Aug 29 09:34:40 AM UTC 24
Finished Aug 29 09:35:29 AM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737604746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.1737604746
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.1921053654
Short name T275
Test name
Test status
Simulation time 192555208 ps
CPU time 1.84 seconds
Started Aug 29 09:34:58 AM UTC 24
Finished Aug 29 09:35:00 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921053654 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1921053654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.2864586041
Short name T60
Test name
Test status
Simulation time 3014634583 ps
CPU time 23.76 seconds
Started Aug 29 09:34:51 AM UTC 24
Finished Aug 29 09:35:16 AM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864586041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2864586041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.2427116748
Short name T750
Test name
Test status
Simulation time 333881369 ps
CPU time 26.53 seconds
Started Aug 29 09:34:49 AM UTC 24
Finished Aug 29 09:35:17 AM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427116748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2427116748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.3112285299
Short name T741
Test name
Test status
Simulation time 398603700 ps
CPU time 7.78 seconds
Started Aug 29 09:34:49 AM UTC 24
Finished Aug 29 09:34:58 AM UTC 24
Peak memory 257248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112285299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.3112285299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.1437462501
Short name T752
Test name
Test status
Simulation time 3986388564 ps
CPU time 25.35 seconds
Started Aug 29 09:34:51 AM UTC 24
Finished Aug 29 09:35:17 AM UTC 24
Peak memory 257556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437462501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.1437462501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.3754272846
Short name T746
Test name
Test status
Simulation time 756828808 ps
CPU time 23.43 seconds
Started Aug 29 09:34:51 AM UTC 24
Finished Aug 29 09:35:16 AM UTC 24
Peak memory 257468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754272846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.3754272846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.1258347603
Short name T277
Test name
Test status
Simulation time 293466562 ps
CPU time 11.69 seconds
Started Aug 29 09:34:49 AM UTC 24
Finished Aug 29 09:35:02 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258347603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1258347603
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.2732445757
Short name T278
Test name
Test status
Simulation time 675515330 ps
CPU time 13.07 seconds
Started Aug 29 09:34:48 AM UTC 24
Finished Aug 29 09:35:02 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732445757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.2732445757
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.3573156135
Short name T279
Test name
Test status
Simulation time 2233394535 ps
CPU time 8.63 seconds
Started Aug 29 09:34:52 AM UTC 24
Finished Aug 29 09:35:02 AM UTC 24
Peak memory 251344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573156135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.3573156135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.1583254379
Short name T737
Test name
Test status
Simulation time 1802289023 ps
CPU time 8.33 seconds
Started Aug 29 09:34:45 AM UTC 24
Finished Aug 29 09:34:54 AM UTC 24
Peak memory 251236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583254379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.1583254379
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.37431605
Short name T1031
Test name
Test status
Simulation time 28551379776 ps
CPU time 256.98 seconds
Started Aug 29 09:34:56 AM UTC 24
Finished Aug 29 09:39:17 AM UTC 24
Peak memory 267804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37431605 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.37431605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.2897792300
Short name T748
Test name
Test status
Simulation time 2305162401 ps
CPU time 21.46 seconds
Started Aug 29 09:34:54 AM UTC 24
Finished Aug 29 09:35:16 AM UTC 24
Peak memory 251640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897792300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.2897792300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.2324855994
Short name T749
Test name
Test status
Simulation time 148018433 ps
CPU time 3.52 seconds
Started Aug 29 09:35:12 AM UTC 24
Finished Aug 29 09:35:17 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324855994 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.2324855994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.3055176113
Short name T62
Test name
Test status
Simulation time 626873716 ps
CPU time 25.88 seconds
Started Aug 29 09:35:10 AM UTC 24
Finished Aug 29 09:35:37 AM UTC 24
Peak memory 253464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055176113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3055176113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.3767149581
Short name T795
Test name
Test status
Simulation time 1723435013 ps
CPU time 46.35 seconds
Started Aug 29 09:35:10 AM UTC 24
Finished Aug 29 09:35:58 AM UTC 24
Peak memory 263960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767149581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.3767149581
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.673515336
Short name T769
Test name
Test status
Simulation time 827548513 ps
CPU time 26.22 seconds
Started Aug 29 09:35:09 AM UTC 24
Finished Aug 29 09:35:37 AM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673515336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.673515336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.1966354772
Short name T280
Test name
Test status
Simulation time 459630215 ps
CPU time 4.78 seconds
Started Aug 29 09:35:00 AM UTC 24
Finished Aug 29 09:35:05 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966354772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.1966354772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.2295249312
Short name T158
Test name
Test status
Simulation time 1448690220 ps
CPU time 31.43 seconds
Started Aug 29 09:35:10 AM UTC 24
Finished Aug 29 09:35:43 AM UTC 24
Peak memory 257724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295249312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.2295249312
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.3360326288
Short name T760
Test name
Test status
Simulation time 5982400673 ps
CPU time 19.04 seconds
Started Aug 29 09:35:10 AM UTC 24
Finished Aug 29 09:35:30 AM UTC 24
Peak memory 253436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360326288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.3360326288
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.1590132934
Short name T753
Test name
Test status
Simulation time 470457300 ps
CPU time 6.9 seconds
Started Aug 29 09:35:09 AM UTC 24
Finished Aug 29 09:35:18 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590132934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.1590132934
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.1432475912
Short name T779
Test name
Test status
Simulation time 915574163 ps
CPU time 32.26 seconds
Started Aug 29 09:35:09 AM UTC 24
Finished Aug 29 09:35:43 AM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432475912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.1432475912
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.3158580393
Short name T747
Test name
Test status
Simulation time 402222328 ps
CPU time 5.19 seconds
Started Aug 29 09:35:10 AM UTC 24
Finished Aug 29 09:35:16 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158580393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.3158580393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.1126333956
Short name T751
Test name
Test status
Simulation time 4718889551 ps
CPU time 16.34 seconds
Started Aug 29 09:34:59 AM UTC 24
Finished Aug 29 09:35:17 AM UTC 24
Peak memory 251492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126333956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1126333956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.2581682473
Short name T1167
Test name
Test status
Simulation time 65413024818 ps
CPU time 338.04 seconds
Started Aug 29 09:35:12 AM UTC 24
Finished Aug 29 09:40:55 AM UTC 24
Peak memory 271832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581682473 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.2581682473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.1588266063
Short name T761
Test name
Test status
Simulation time 1023932271 ps
CPU time 19.15 seconds
Started Aug 29 09:35:10 AM UTC 24
Finished Aug 29 09:35:30 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588266063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.1588266063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.738265488
Short name T759
Test name
Test status
Simulation time 174981594 ps
CPU time 2.83 seconds
Started Aug 29 09:35:26 AM UTC 24
Finished Aug 29 09:35:30 AM UTC 24
Peak memory 251020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738265488 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.738265488
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.88475805
Short name T788
Test name
Test status
Simulation time 1862766036 ps
CPU time 34.06 seconds
Started Aug 29 09:35:17 AM UTC 24
Finished Aug 29 09:35:53 AM UTC 24
Peak memory 253368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88475805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.88475805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.2852549234
Short name T768
Test name
Test status
Simulation time 468121899 ps
CPU time 18.28 seconds
Started Aug 29 09:35:17 AM UTC 24
Finished Aug 29 09:35:37 AM UTC 24
Peak memory 251104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852549234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.2852549234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.739050364
Short name T757
Test name
Test status
Simulation time 322845152 ps
CPU time 8.33 seconds
Started Aug 29 09:35:17 AM UTC 24
Finished Aug 29 09:35:26 AM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739050364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.739050364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.1170960871
Short name T67
Test name
Test status
Simulation time 111418298 ps
CPU time 5.35 seconds
Started Aug 29 09:35:17 AM UTC 24
Finished Aug 29 09:35:23 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170960871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.1170960871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.2851712867
Short name T819
Test name
Test status
Simulation time 20925189470 ps
CPU time 59.49 seconds
Started Aug 29 09:35:26 AM UTC 24
Finished Aug 29 09:36:27 AM UTC 24
Peak memory 257920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851712867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2851712867
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.1724660931
Short name T778
Test name
Test status
Simulation time 1021129224 ps
CPU time 15.44 seconds
Started Aug 29 09:35:26 AM UTC 24
Finished Aug 29 09:35:43 AM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724660931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.1724660931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.3324387318
Short name T742
Test name
Test status
Simulation time 125102029 ps
CPU time 4.82 seconds
Started Aug 29 09:35:17 AM UTC 24
Finished Aug 29 09:35:23 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324387318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.3324387318
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.4146127852
Short name T770
Test name
Test status
Simulation time 761056935 ps
CPU time 19.82 seconds
Started Aug 29 09:35:17 AM UTC 24
Finished Aug 29 09:35:38 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146127852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.4146127852
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.1442533768
Short name T766
Test name
Test status
Simulation time 192550579 ps
CPU time 7.23 seconds
Started Aug 29 09:35:26 AM UTC 24
Finished Aug 29 09:35:34 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442533768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.1442533768
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.3422452562
Short name T754
Test name
Test status
Simulation time 142747852 ps
CPU time 4.87 seconds
Started Aug 29 09:35:14 AM UTC 24
Finished Aug 29 09:35:20 AM UTC 24
Peak memory 251304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422452562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.3422452562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.468535910
Short name T869
Test name
Test status
Simulation time 20432855831 ps
CPU time 127.7 seconds
Started Aug 29 09:35:26 AM UTC 24
Finished Aug 29 09:37:36 AM UTC 24
Peak memory 257724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468535910 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.468535910
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.2158970273
Short name T789
Test name
Test status
Simulation time 2780955036 ps
CPU time 25.47 seconds
Started Aug 29 09:35:26 AM UTC 24
Finished Aug 29 09:35:53 AM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158970273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.2158970273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.3332885224
Short name T773
Test name
Test status
Simulation time 86774486 ps
CPU time 3.07 seconds
Started Aug 29 09:35:36 AM UTC 24
Finished Aug 29 09:35:40 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332885224 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.3332885224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.3390142812
Short name T393
Test name
Test status
Simulation time 630149886 ps
CPU time 16.34 seconds
Started Aug 29 09:35:30 AM UTC 24
Finished Aug 29 09:35:47 AM UTC 24
Peak memory 253400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390142812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.3390142812
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.22062401
Short name T780
Test name
Test status
Simulation time 3804861983 ps
CPU time 16.27 seconds
Started Aug 29 09:35:27 AM UTC 24
Finished Aug 29 09:35:45 AM UTC 24
Peak memory 253592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22062401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.22062401
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.2048699855
Short name T765
Test name
Test status
Simulation time 2126423493 ps
CPU time 6.69 seconds
Started Aug 29 09:35:26 AM UTC 24
Finished Aug 29 09:35:34 AM UTC 24
Peak memory 251640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048699855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.2048699855
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.221301100
Short name T767
Test name
Test status
Simulation time 435643153 ps
CPU time 7.49 seconds
Started Aug 29 09:35:26 AM UTC 24
Finished Aug 29 09:35:35 AM UTC 24
Peak memory 251056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221301100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.221301100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.1655607906
Short name T781
Test name
Test status
Simulation time 592647690 ps
CPU time 12.74 seconds
Started Aug 29 09:35:32 AM UTC 24
Finished Aug 29 09:35:46 AM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655607906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.1655607906
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.718481213
Short name T798
Test name
Test status
Simulation time 1083768605 ps
CPU time 28.96 seconds
Started Aug 29 09:35:32 AM UTC 24
Finished Aug 29 09:36:02 AM UTC 24
Peak memory 257456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718481213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.718481213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.4150018394
Short name T764
Test name
Test status
Simulation time 509891744 ps
CPU time 6.37 seconds
Started Aug 29 09:35:26 AM UTC 24
Finished Aug 29 09:35:34 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150018394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.4150018394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.2223064099
Short name T772
Test name
Test status
Simulation time 6050654408 ps
CPU time 11.97 seconds
Started Aug 29 09:35:26 AM UTC 24
Finished Aug 29 09:35:39 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223064099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.2223064099
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.3278493408
Short name T774
Test name
Test status
Simulation time 768193764 ps
CPU time 8.13 seconds
Started Aug 29 09:35:32 AM UTC 24
Finished Aug 29 09:35:41 AM UTC 24
Peak memory 257684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278493408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.3278493408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.3025939193
Short name T771
Test name
Test status
Simulation time 396866409 ps
CPU time 10.63 seconds
Started Aug 29 09:35:26 AM UTC 24
Finished Aug 29 09:35:38 AM UTC 24
Peak memory 257508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025939193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.3025939193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.3554811900
Short name T123
Test name
Test status
Simulation time 22184514061 ps
CPU time 213.87 seconds
Started Aug 29 09:35:36 AM UTC 24
Finished Aug 29 09:39:13 AM UTC 24
Peak memory 274032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554811900 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.3554811900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.3408595197
Short name T817
Test name
Test status
Simulation time 1642741790 ps
CPU time 42.4 seconds
Started Aug 29 09:35:36 AM UTC 24
Finished Aug 29 09:36:20 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408595197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.3408595197
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.2370951401
Short name T420
Test name
Test status
Simulation time 99789173 ps
CPU time 2.86 seconds
Started Aug 29 09:22:43 AM UTC 24
Finished Aug 29 09:22:47 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370951401 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2370951401
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.3627117930
Short name T204
Test name
Test status
Simulation time 1443175684 ps
CPU time 15.09 seconds
Started Aug 29 09:22:14 AM UTC 24
Finished Aug 29 09:22:30 AM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627117930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.3627117930
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.749929718
Short name T170
Test name
Test status
Simulation time 195205762 ps
CPU time 6.17 seconds
Started Aug 29 09:22:26 AM UTC 24
Finished Aug 29 09:22:34 AM UTC 24
Peak memory 253240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749929718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.749929718
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.1183002277
Short name T198
Test name
Test status
Simulation time 2578699795 ps
CPU time 36.05 seconds
Started Aug 29 09:22:22 AM UTC 24
Finished Aug 29 09:23:00 AM UTC 24
Peak memory 253736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183002277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1183002277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.2124256856
Short name T232
Test name
Test status
Simulation time 18168459862 ps
CPU time 74.02 seconds
Started Aug 29 09:22:21 AM UTC 24
Finished Aug 29 09:23:37 AM UTC 24
Peak memory 257532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124256856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.2124256856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.1983156057
Short name T179
Test name
Test status
Simulation time 418367918 ps
CPU time 6.06 seconds
Started Aug 29 09:22:12 AM UTC 24
Finished Aug 29 09:22:19 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983156057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.1983156057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.592701103
Short name T171
Test name
Test status
Simulation time 3596612668 ps
CPU time 30.22 seconds
Started Aug 29 09:22:31 AM UTC 24
Finished Aug 29 09:23:03 AM UTC 24
Peak memory 257912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592701103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.592701103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.757225686
Short name T369
Test name
Test status
Simulation time 451399278 ps
CPU time 13.98 seconds
Started Aug 29 09:22:31 AM UTC 24
Finished Aug 29 09:22:47 AM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757225686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.757225686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.4030496871
Short name T255
Test name
Test status
Simulation time 4175165191 ps
CPU time 18.88 seconds
Started Aug 29 09:22:20 AM UTC 24
Finished Aug 29 09:22:40 AM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030496871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.4030496871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.3234053261
Short name T254
Test name
Test status
Simulation time 225122116 ps
CPU time 5.33 seconds
Started Aug 29 09:22:14 AM UTC 24
Finished Aug 29 09:22:20 AM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234053261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.3234053261
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.2276285508
Short name T356
Test name
Test status
Simulation time 467320254 ps
CPU time 6.59 seconds
Started Aug 29 09:22:35 AM UTC 24
Finished Aug 29 09:22:42 AM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276285508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.2276285508
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.1623292853
Short name T419
Test name
Test status
Simulation time 3440258825 ps
CPU time 11.06 seconds
Started Aug 29 09:22:09 AM UTC 24
Finished Aug 29 09:22:21 AM UTC 24
Peak memory 251388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623292853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.1623292853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.2647635158
Short name T21
Test name
Test status
Simulation time 4613202034 ps
CPU time 58.17 seconds
Started Aug 29 09:22:42 AM UTC 24
Finished Aug 29 09:23:42 AM UTC 24
Peak memory 257704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2647635158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.otp_ctrl_stress_all_with_rand_reset.2647635158
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.456187144
Short name T197
Test name
Test status
Simulation time 603782875 ps
CPU time 14.37 seconds
Started Aug 29 09:22:39 AM UTC 24
Finished Aug 29 09:22:55 AM UTC 24
Peak memory 251608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456187144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.456187144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.2018128184
Short name T45
Test name
Test status
Simulation time 508633189 ps
CPU time 6.07 seconds
Started Aug 29 09:35:36 AM UTC 24
Finished Aug 29 09:35:43 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018128184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.2018128184
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.1026983400
Short name T785
Test name
Test status
Simulation time 568422430 ps
CPU time 11.26 seconds
Started Aug 29 09:35:36 AM UTC 24
Finished Aug 29 09:35:48 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026983400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.1026983400
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.4079595252
Short name T775
Test name
Test status
Simulation time 111618334 ps
CPU time 3.38 seconds
Started Aug 29 09:35:37 AM UTC 24
Finished Aug 29 09:35:42 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079595252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.4079595252
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.2383515798
Short name T794
Test name
Test status
Simulation time 1507049898 ps
CPU time 15.3 seconds
Started Aug 29 09:35:40 AM UTC 24
Finished Aug 29 09:35:57 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383515798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.2383515798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.2999128777
Short name T857
Test name
Test status
Simulation time 18659020790 ps
CPU time 92.72 seconds
Started Aug 29 09:35:40 AM UTC 24
Finished Aug 29 09:37:15 AM UTC 24
Peak memory 257592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2999128777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 51.otp_ctrl_stress_all_with_rand_reset.2999128777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.1584932488
Short name T782
Test name
Test status
Simulation time 1185899423 ps
CPU time 4.58 seconds
Started Aug 29 09:35:41 AM UTC 24
Finished Aug 29 09:35:46 AM UTC 24
Peak memory 253240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584932488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.1584932488
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.1050187884
Short name T784
Test name
Test status
Simulation time 332893074 ps
CPU time 5 seconds
Started Aug 29 09:35:41 AM UTC 24
Finished Aug 29 09:35:47 AM UTC 24
Peak memory 253208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050187884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.1050187884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.3562119208
Short name T783
Test name
Test status
Simulation time 115407152 ps
CPU time 4.8 seconds
Started Aug 29 09:35:41 AM UTC 24
Finished Aug 29 09:35:46 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562119208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.3562119208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.1700755395
Short name T796
Test name
Test status
Simulation time 312344583 ps
CPU time 12.33 seconds
Started Aug 29 09:35:47 AM UTC 24
Finished Aug 29 09:36:00 AM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700755395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.1700755395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.38945914
Short name T791
Test name
Test status
Simulation time 157825602 ps
CPU time 6.09 seconds
Started Aug 29 09:35:47 AM UTC 24
Finished Aug 29 09:35:54 AM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38945914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.38945914
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.3286942164
Short name T790
Test name
Test status
Simulation time 428745479 ps
CPU time 5.43 seconds
Started Aug 29 09:35:47 AM UTC 24
Finished Aug 29 09:35:53 AM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286942164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3286942164
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.3296723219
Short name T787
Test name
Test status
Simulation time 218366088 ps
CPU time 4.59 seconds
Started Aug 29 09:35:47 AM UTC 24
Finished Aug 29 09:35:52 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296723219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.3296723219
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.2591262216
Short name T826
Test name
Test status
Simulation time 19673193787 ps
CPU time 44.83 seconds
Started Aug 29 09:35:47 AM UTC 24
Finished Aug 29 09:36:33 AM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591262216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.2591262216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.1056109348
Short name T26
Test name
Test status
Simulation time 290986478 ps
CPU time 5.42 seconds
Started Aug 29 09:35:47 AM UTC 24
Finished Aug 29 09:35:53 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056109348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.1056109348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.1704381149
Short name T816
Test name
Test status
Simulation time 2878449402 ps
CPU time 30.37 seconds
Started Aug 29 09:35:47 AM UTC 24
Finished Aug 29 09:36:19 AM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704381149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1704381149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.933368814
Short name T793
Test name
Test status
Simulation time 1732024366 ps
CPU time 7.56 seconds
Started Aug 29 09:35:47 AM UTC 24
Finished Aug 29 09:35:56 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933368814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.933368814
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.2987983517
Short name T802
Test name
Test status
Simulation time 509322762 ps
CPU time 11 seconds
Started Aug 29 09:35:55 AM UTC 24
Finished Aug 29 09:36:07 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987983517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.2987983517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.1742877762
Short name T799
Test name
Test status
Simulation time 1618160157 ps
CPU time 7.02 seconds
Started Aug 29 09:35:55 AM UTC 24
Finished Aug 29 09:36:03 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742877762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1742877762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.3206411639
Short name T821
Test name
Test status
Simulation time 10174765832 ps
CPU time 34.27 seconds
Started Aug 29 09:35:55 AM UTC 24
Finished Aug 29 09:36:30 AM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206411639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.3206411639
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.966139301
Short name T39
Test name
Test status
Simulation time 585103725 ps
CPU time 6.25 seconds
Started Aug 29 09:35:55 AM UTC 24
Finished Aug 29 09:36:02 AM UTC 24
Peak memory 251120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966139301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.966139301
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.3663756589
Short name T811
Test name
Test status
Simulation time 1086918164 ps
CPU time 19 seconds
Started Aug 29 09:35:55 AM UTC 24
Finished Aug 29 09:36:15 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663756589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.3663756589
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.3687716243
Short name T229
Test name
Test status
Simulation time 642874924 ps
CPU time 3.55 seconds
Started Aug 29 09:23:26 AM UTC 24
Finished Aug 29 09:23:31 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687716243 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.3687716243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.3382734935
Short name T134
Test name
Test status
Simulation time 2489442708 ps
CPU time 29.62 seconds
Started Aug 29 09:22:52 AM UTC 24
Finished Aug 29 09:23:23 AM UTC 24
Peak memory 257584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382734935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.3382734935
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.2590329590
Short name T120
Test name
Test status
Simulation time 1043015386 ps
CPU time 24.4 seconds
Started Aug 29 09:23:04 AM UTC 24
Finished Aug 29 09:23:30 AM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590329590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.2590329590
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.3933394555
Short name T208
Test name
Test status
Simulation time 545701428 ps
CPU time 22.84 seconds
Started Aug 29 09:23:01 AM UTC 24
Finished Aug 29 09:23:25 AM UTC 24
Peak memory 251392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933394555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.3933394555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.2572077894
Short name T200
Test name
Test status
Simulation time 3292377262 ps
CPU time 16.79 seconds
Started Aug 29 09:22:59 AM UTC 24
Finished Aug 29 09:23:17 AM UTC 24
Peak memory 251392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572077894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.2572077894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.1135123710
Short name T174
Test name
Test status
Simulation time 178239953 ps
CPU time 4.95 seconds
Started Aug 29 09:22:47 AM UTC 24
Finished Aug 29 09:22:53 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135123710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1135123710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.4101289283
Short name T207
Test name
Test status
Simulation time 5859121911 ps
CPU time 40.7 seconds
Started Aug 29 09:23:04 AM UTC 24
Finished Aug 29 09:23:46 AM UTC 24
Peak memory 253696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101289283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.4101289283
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.4125951569
Short name T151
Test name
Test status
Simulation time 386463114 ps
CPU time 10.63 seconds
Started Aug 29 09:22:55 AM UTC 24
Finished Aug 29 09:23:07 AM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125951569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.4125951569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.3875606926
Short name T230
Test name
Test status
Simulation time 2674951224 ps
CPU time 35.64 seconds
Started Aug 29 09:22:54 AM UTC 24
Finished Aug 29 09:23:31 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875606926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.3875606926
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.661732099
Short name T201
Test name
Test status
Simulation time 274383514 ps
CPU time 8.21 seconds
Started Aug 29 09:23:14 AM UTC 24
Finished Aug 29 09:23:23 AM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661732099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.661732099
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.3820564191
Short name T199
Test name
Test status
Simulation time 1350757248 ps
CPU time 15.06 seconds
Started Aug 29 09:22:47 AM UTC 24
Finished Aug 29 09:23:04 AM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820564191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.3820564191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.4285257997
Short name T337
Test name
Test status
Simulation time 2453447441 ps
CPU time 23.77 seconds
Started Aug 29 09:23:24 AM UTC 24
Finished Aug 29 09:23:50 AM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285257997 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.4285257997
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.3554097463
Short name T223
Test name
Test status
Simulation time 1600769321 ps
CPU time 19.76 seconds
Started Aug 29 09:23:18 AM UTC 24
Finished Aug 29 09:23:40 AM UTC 24
Peak memory 251632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554097463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.3554097463
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.3855636758
Short name T30
Test name
Test status
Simulation time 370241841 ps
CPU time 4.85 seconds
Started Aug 29 09:35:55 AM UTC 24
Finished Aug 29 09:36:01 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855636758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.3855636758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.4148749310
Short name T131
Test name
Test status
Simulation time 4667174766 ps
CPU time 16.06 seconds
Started Aug 29 09:35:55 AM UTC 24
Finished Aug 29 09:36:12 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148749310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.4148749310
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.662794697
Short name T801
Test name
Test status
Simulation time 2553019930 ps
CPU time 9.48 seconds
Started Aug 29 09:35:55 AM UTC 24
Finished Aug 29 09:36:06 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662794697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.662794697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.3687054266
Short name T805
Test name
Test status
Simulation time 692705274 ps
CPU time 12.36 seconds
Started Aug 29 09:35:55 AM UTC 24
Finished Aug 29 09:36:09 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687054266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3687054266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.1284483507
Short name T873
Test name
Test status
Simulation time 3198435451 ps
CPU time 103.03 seconds
Started Aug 29 09:35:59 AM UTC 24
Finished Aug 29 09:37:45 AM UTC 24
Peak memory 270048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1284483507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 61.otp_ctrl_stress_all_with_rand_reset.1284483507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.4272948001
Short name T800
Test name
Test status
Simulation time 590492350 ps
CPU time 4.03 seconds
Started Aug 29 09:36:00 AM UTC 24
Finished Aug 29 09:36:05 AM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272948001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.4272948001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.284085666
Short name T804
Test name
Test status
Simulation time 262962833 ps
CPU time 7.12 seconds
Started Aug 29 09:36:00 AM UTC 24
Finished Aug 29 09:36:08 AM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284085666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.284085666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.666993794
Short name T312
Test name
Test status
Simulation time 68244215836 ps
CPU time 175.79 seconds
Started Aug 29 09:36:00 AM UTC 24
Finished Aug 29 09:38:59 AM UTC 24
Peak memory 270256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=666993794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
62.otp_ctrl_stress_all_with_rand_reset.666993794
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.1904730567
Short name T803
Test name
Test status
Simulation time 182599515 ps
CPU time 4.94 seconds
Started Aug 29 09:36:01 AM UTC 24
Finished Aug 29 09:36:07 AM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904730567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.1904730567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.2932751116
Short name T813
Test name
Test status
Simulation time 848687504 ps
CPU time 8.88 seconds
Started Aug 29 09:36:06 AM UTC 24
Finished Aug 29 09:36:16 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932751116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.2932751116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.1730501485
Short name T854
Test name
Test status
Simulation time 7619850200 ps
CPU time 64.72 seconds
Started Aug 29 09:36:06 AM UTC 24
Finished Aug 29 09:37:13 AM UTC 24
Peak memory 257552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1730501485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 63.otp_ctrl_stress_all_with_rand_reset.1730501485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.4109946297
Short name T807
Test name
Test status
Simulation time 269036747 ps
CPU time 4.7 seconds
Started Aug 29 09:36:06 AM UTC 24
Finished Aug 29 09:36:12 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109946297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.4109946297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.2526005266
Short name T256
Test name
Test status
Simulation time 595319455 ps
CPU time 16.35 seconds
Started Aug 29 09:36:06 AM UTC 24
Finished Aug 29 09:36:24 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526005266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.2526005266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.492554228
Short name T812
Test name
Test status
Simulation time 1916180186 ps
CPU time 8.39 seconds
Started Aug 29 09:36:06 AM UTC 24
Finished Aug 29 09:36:16 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492554228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.492554228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.3460687640
Short name T809
Test name
Test status
Simulation time 130260608 ps
CPU time 6.81 seconds
Started Aug 29 09:36:06 AM UTC 24
Finished Aug 29 09:36:14 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460687640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3460687640
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.640123459
Short name T808
Test name
Test status
Simulation time 176583646 ps
CPU time 4.98 seconds
Started Aug 29 09:36:08 AM UTC 24
Finished Aug 29 09:36:14 AM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640123459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.640123459
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.3883134223
Short name T810
Test name
Test status
Simulation time 1282186042 ps
CPU time 10.78 seconds
Started Aug 29 09:36:08 AM UTC 24
Finished Aug 29 09:36:20 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883134223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3883134223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.1168803916
Short name T815
Test name
Test status
Simulation time 141926878 ps
CPU time 6.64 seconds
Started Aug 29 09:36:10 AM UTC 24
Finished Aug 29 09:36:18 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168803916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.1168803916
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.3597413473
Short name T74
Test name
Test status
Simulation time 178430622 ps
CPU time 6.86 seconds
Started Aug 29 09:36:13 AM UTC 24
Finished Aug 29 09:36:21 AM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597413473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.3597413473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.1280512446
Short name T823
Test name
Test status
Simulation time 4327737065 ps
CPU time 16.89 seconds
Started Aug 29 09:36:13 AM UTC 24
Finished Aug 29 09:36:31 AM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280512446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.1280512446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.3370856614
Short name T938
Test name
Test status
Simulation time 19030424493 ps
CPU time 144.71 seconds
Started Aug 29 09:36:14 AM UTC 24
Finished Aug 29 09:38:42 AM UTC 24
Peak memory 257704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3370856614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 68.otp_ctrl_stress_all_with_rand_reset.3370856614
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.2119992569
Short name T776
Test name
Test status
Simulation time 221138775 ps
CPU time 6.26 seconds
Started Aug 29 09:36:17 AM UTC 24
Finished Aug 29 09:36:24 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119992569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.2119992569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.811780606
Short name T762
Test name
Test status
Simulation time 167735417 ps
CPU time 5.84 seconds
Started Aug 29 09:36:17 AM UTC 24
Finished Aug 29 09:36:23 AM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811780606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.811780606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.4104950792
Short name T1129
Test name
Test status
Simulation time 11373591513 ps
CPU time 199.93 seconds
Started Aug 29 09:36:17 AM UTC 24
Finished Aug 29 09:39:40 AM UTC 24
Peak memory 267948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4104950792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 69.otp_ctrl_stress_all_with_rand_reset.4104950792
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.4100492388
Short name T422
Test name
Test status
Simulation time 211783791 ps
CPU time 2.61 seconds
Started Aug 29 09:23:46 AM UTC 24
Finished Aug 29 09:23:50 AM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100492388 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.4100492388
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.2708497508
Short name T432
Test name
Test status
Simulation time 26201001788 ps
CPU time 63.78 seconds
Started Aug 29 09:23:32 AM UTC 24
Finished Aug 29 09:24:37 AM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708497508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.2708497508
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.4074203558
Short name T338
Test name
Test status
Simulation time 3876476987 ps
CPU time 22.39 seconds
Started Aug 29 09:23:40 AM UTC 24
Finished Aug 29 09:24:03 AM UTC 24
Peak memory 251304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074203558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.4074203558
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.3315686860
Short name T378
Test name
Test status
Simulation time 2637898824 ps
CPU time 42.55 seconds
Started Aug 29 09:23:39 AM UTC 24
Finished Aug 29 09:24:24 AM UTC 24
Peak memory 251392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315686860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.3315686860
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.3297944992
Short name T43
Test name
Test status
Simulation time 512644757 ps
CPU time 7.72 seconds
Started Aug 29 09:23:32 AM UTC 24
Finished Aug 29 09:23:40 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297944992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.3297944992
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.3239915615
Short name T156
Test name
Test status
Simulation time 14376554283 ps
CPU time 39.95 seconds
Started Aug 29 09:23:40 AM UTC 24
Finished Aug 29 09:24:21 AM UTC 24
Peak memory 257664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239915615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.3239915615
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.1274663161
Short name T370
Test name
Test status
Simulation time 1765581071 ps
CPU time 29.7 seconds
Started Aug 29 09:23:46 AM UTC 24
Finished Aug 29 09:24:17 AM UTC 24
Peak memory 257492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274663161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.1274663161
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.4096551536
Short name T333
Test name
Test status
Simulation time 966466385 ps
CPU time 40.06 seconds
Started Aug 29 09:23:33 AM UTC 24
Finished Aug 29 09:24:15 AM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096551536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.4096551536
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.125478193
Short name T390
Test name
Test status
Simulation time 704461326 ps
CPU time 12.27 seconds
Started Aug 29 09:23:32 AM UTC 24
Finished Aug 29 09:23:45 AM UTC 24
Peak memory 257328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125478193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.125478193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.612504747
Short name T361
Test name
Test status
Simulation time 264915361 ps
CPU time 9.4 seconds
Started Aug 29 09:23:46 AM UTC 24
Finished Aug 29 09:23:57 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612504747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base
_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/o
tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.612504747
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.558481088
Short name T421
Test name
Test status
Simulation time 1320406994 ps
CPU time 12.19 seconds
Started Aug 29 09:23:32 AM UTC 24
Finished Aug 29 09:23:45 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558481088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.558481088
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.54456349
Short name T345
Test name
Test status
Simulation time 82183112 ps
CPU time 3.22 seconds
Started Aug 29 09:23:46 AM UTC 24
Finished Aug 29 09:23:51 AM UTC 24
Peak memory 251128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54456349 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.54456349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.2760728191
Short name T372
Test name
Test status
Simulation time 1067297754 ps
CPU time 15.27 seconds
Started Aug 29 09:23:46 AM UTC 24
Finished Aug 29 09:24:03 AM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760728191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2760728191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.4054108271
Short name T818
Test name
Test status
Simulation time 106356882 ps
CPU time 5.62 seconds
Started Aug 29 09:36:17 AM UTC 24
Finished Aug 29 09:36:23 AM UTC 24
Peak memory 251512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054108271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.4054108271
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.3497603906
Short name T841
Test name
Test status
Simulation time 936523010 ps
CPU time 33.18 seconds
Started Aug 29 09:36:17 AM UTC 24
Finished Aug 29 09:36:51 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497603906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.3497603906
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.2916694273
Short name T310
Test name
Test status
Simulation time 18906064699 ps
CPU time 131.57 seconds
Started Aug 29 09:36:18 AM UTC 24
Finished Aug 29 09:38:32 AM UTC 24
Peak memory 268176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2916694273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 70.otp_ctrl_stress_all_with_rand_reset.2916694273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.3389907654
Short name T806
Test name
Test status
Simulation time 419203156 ps
CPU time 5.41 seconds
Started Aug 29 09:36:19 AM UTC 24
Finished Aug 29 09:36:26 AM UTC 24
Peak memory 251300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389907654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.3389907654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.206560356
Short name T814
Test name
Test status
Simulation time 185434790 ps
CPU time 5.86 seconds
Started Aug 29 09:36:19 AM UTC 24
Finished Aug 29 09:36:26 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206560356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.206560356
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2055236761
Short name T875
Test name
Test status
Simulation time 9542195218 ps
CPU time 82.8 seconds
Started Aug 29 09:36:21 AM UTC 24
Finished Aug 29 09:37:46 AM UTC 24
Peak memory 272040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2055236761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 71.otp_ctrl_stress_all_with_rand_reset.2055236761
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.1614256180
Short name T820
Test name
Test status
Simulation time 128505581 ps
CPU time 6.41 seconds
Started Aug 29 09:36:22 AM UTC 24
Finished Aug 29 09:36:29 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614256180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.1614256180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.465165880
Short name T836
Test name
Test status
Simulation time 876501671 ps
CPU time 24.56 seconds
Started Aug 29 09:36:22 AM UTC 24
Finished Aug 29 09:36:47 AM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465165880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.465165880
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.972787327
Short name T756
Test name
Test status
Simulation time 93216155 ps
CPU time 5.11 seconds
Started Aug 29 09:36:23 AM UTC 24
Finished Aug 29 09:36:29 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972787327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.972787327
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.3811231432
Short name T825
Test name
Test status
Simulation time 2519274845 ps
CPU time 7.86 seconds
Started Aug 29 09:36:24 AM UTC 24
Finished Aug 29 09:36:33 AM UTC 24
Peak memory 257652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811231432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.3811231432
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.3645957510
Short name T79
Test name
Test status
Simulation time 262272727 ps
CPU time 5.53 seconds
Started Aug 29 09:36:26 AM UTC 24
Finished Aug 29 09:36:32 AM UTC 24
Peak memory 251088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645957510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.3645957510
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.3843046656
Short name T833
Test name
Test status
Simulation time 853795716 ps
CPU time 15.44 seconds
Started Aug 29 09:36:26 AM UTC 24
Finished Aug 29 09:36:42 AM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843046656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.3843046656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.768452856
Short name T75
Test name
Test status
Simulation time 601982884 ps
CPU time 6.41 seconds
Started Aug 29 09:36:27 AM UTC 24
Finished Aug 29 09:36:35 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768452856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.768452856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.2652073583
Short name T822
Test name
Test status
Simulation time 358510093 ps
CPU time 3.11 seconds
Started Aug 29 09:36:27 AM UTC 24
Finished Aug 29 09:36:31 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652073583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.2652073583
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.1746284127
Short name T912
Test name
Test status
Simulation time 49132066053 ps
CPU time 115.32 seconds
Started Aug 29 09:36:31 AM UTC 24
Finished Aug 29 09:38:29 AM UTC 24
Peak memory 268044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1746284127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 75.otp_ctrl_stress_all_with_rand_reset.1746284127
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.988402682
Short name T829
Test name
Test status
Simulation time 1685107314 ps
CPU time 7.11 seconds
Started Aug 29 09:36:31 AM UTC 24
Finished Aug 29 09:36:39 AM UTC 24
Peak memory 253300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988402682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.988402682
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.2414237261
Short name T837
Test name
Test status
Simulation time 1829496840 ps
CPU time 15.27 seconds
Started Aug 29 09:36:31 AM UTC 24
Finished Aug 29 09:36:48 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414237261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.2414237261
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.3698659679
Short name T308
Test name
Test status
Simulation time 1160555937 ps
CPU time 33.49 seconds
Started Aug 29 09:36:31 AM UTC 24
Finished Aug 29 09:37:06 AM UTC 24
Peak memory 257524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3698659679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 76.otp_ctrl_stress_all_with_rand_reset.3698659679
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.3171010273
Short name T85
Test name
Test status
Simulation time 153230582 ps
CPU time 5.05 seconds
Started Aug 29 09:36:33 AM UTC 24
Finished Aug 29 09:36:40 AM UTC 24
Peak memory 251488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171010273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3171010273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.1975267872
Short name T831
Test name
Test status
Simulation time 1424402603 ps
CPU time 6.11 seconds
Started Aug 29 09:36:33 AM UTC 24
Finished Aug 29 09:36:41 AM UTC 24
Peak memory 250708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975267872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.1975267872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.451056313
Short name T76
Test name
Test status
Simulation time 182376076 ps
CPU time 6.44 seconds
Started Aug 29 09:36:33 AM UTC 24
Finished Aug 29 09:36:41 AM UTC 24
Peak memory 251636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451056313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.451056313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.3649292587
Short name T852
Test name
Test status
Simulation time 2828696642 ps
CPU time 30.92 seconds
Started Aug 29 09:36:35 AM UTC 24
Finished Aug 29 09:37:08 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649292587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.3649292587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.621833201
Short name T1166
Test name
Test status
Simulation time 73576168167 ps
CPU time 222.26 seconds
Started Aug 29 09:36:35 AM UTC 24
Finished Aug 29 09:40:21 AM UTC 24
Peak memory 261720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=621833201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
78.otp_ctrl_stress_all_with_rand_reset.621833201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.306742812
Short name T832
Test name
Test status
Simulation time 242482597 ps
CPU time 5.12 seconds
Started Aug 29 09:36:35 AM UTC 24
Finished Aug 29 09:36:42 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306742812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.306742812
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.1508729245
Short name T835
Test name
Test status
Simulation time 507386970 ps
CPU time 8.74 seconds
Started Aug 29 09:36:36 AM UTC 24
Finished Aug 29 09:36:47 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508729245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.1508729245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.702255503
Short name T426
Test name
Test status
Simulation time 131074457 ps
CPU time 2.66 seconds
Started Aug 29 09:24:12 AM UTC 24
Finished Aug 29 09:24:16 AM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702255503 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.702255503
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.3982860307
Short name T224
Test name
Test status
Simulation time 3243104703 ps
CPU time 35.2 seconds
Started Aug 29 09:23:51 AM UTC 24
Finished Aug 29 09:24:27 AM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982860307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.3982860307
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.4230913601
Short name T117
Test name
Test status
Simulation time 421657622 ps
CPU time 7.38 seconds
Started Aug 29 09:23:57 AM UTC 24
Finished Aug 29 09:24:06 AM UTC 24
Peak memory 253656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230913601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.4230913601
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.2876564460
Short name T428
Test name
Test status
Simulation time 2337640522 ps
CPU time 32.41 seconds
Started Aug 29 09:23:55 AM UTC 24
Finished Aug 29 09:24:29 AM UTC 24
Peak memory 251688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876564460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.2876564460
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.876076262
Short name T424
Test name
Test status
Simulation time 335493006 ps
CPU time 10.06 seconds
Started Aug 29 09:23:54 AM UTC 24
Finished Aug 29 09:24:05 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876076262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.876076262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.66669901
Short name T51
Test name
Test status
Simulation time 315468890 ps
CPU time 5.12 seconds
Started Aug 29 09:23:48 AM UTC 24
Finished Aug 29 09:23:54 AM UTC 24
Peak memory 251236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66669901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.66669901
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.2868559504
Short name T181
Test name
Test status
Simulation time 880308614 ps
CPU time 9 seconds
Started Aug 29 09:24:01 AM UTC 24
Finished Aug 29 09:24:11 AM UTC 24
Peak memory 253456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868559504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.2868559504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.3944054756
Short name T225
Test name
Test status
Simulation time 6439843567 ps
CPU time 23.59 seconds
Started Aug 29 09:24:04 AM UTC 24
Finished Aug 29 09:24:29 AM UTC 24
Peak memory 253404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944054756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.3944054756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.1331817291
Short name T148
Test name
Test status
Simulation time 298183513 ps
CPU time 9.45 seconds
Started Aug 29 09:23:52 AM UTC 24
Finished Aug 29 09:24:02 AM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331817291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.1331817291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.4100612653
Short name T332
Test name
Test status
Simulation time 639314051 ps
CPU time 22.24 seconds
Started Aug 29 09:23:51 AM UTC 24
Finished Aug 29 09:24:14 AM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100612653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.4100612653
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.4266291423
Short name T425
Test name
Test status
Simulation time 122811675 ps
CPU time 7.24 seconds
Started Aug 29 09:24:04 AM UTC 24
Finished Aug 29 09:24:13 AM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266291423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.4266291423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.4034277350
Short name T423
Test name
Test status
Simulation time 3997182459 ps
CPU time 10.68 seconds
Started Aug 29 09:23:48 AM UTC 24
Finished Aug 29 09:24:00 AM UTC 24
Peak memory 251364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034277350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.4034277350
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.1138647096
Short name T213
Test name
Test status
Simulation time 2201064821 ps
CPU time 75.98 seconds
Started Aug 29 09:24:07 AM UTC 24
Finished Aug 29 09:25:25 AM UTC 24
Peak memory 253372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138647096 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.1138647096
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.373631442
Short name T374
Test name
Test status
Simulation time 2481378935 ps
CPU time 46.19 seconds
Started Aug 29 09:24:04 AM UTC 24
Finished Aug 29 09:24:52 AM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373631442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.373631442
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.226471215
Short name T838
Test name
Test status
Simulation time 113173889 ps
CPU time 4.51 seconds
Started Aug 29 09:36:42 AM UTC 24
Finished Aug 29 09:36:48 AM UTC 24
Peak memory 251500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226471215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.226471215
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.2854596325
Short name T845
Test name
Test status
Simulation time 1376310668 ps
CPU time 15.33 seconds
Started Aug 29 09:36:43 AM UTC 24
Finished Aug 29 09:36:59 AM UTC 24
Peak memory 251176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854596325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.2854596325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.3572370380
Short name T840
Test name
Test status
Simulation time 152818976 ps
CPU time 6.14 seconds
Started Aug 29 09:36:43 AM UTC 24
Finished Aug 29 09:36:50 AM UTC 24
Peak memory 250684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572370380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.3572370380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.1531898146
Short name T839
Test name
Test status
Simulation time 452904586 ps
CPU time 6.04 seconds
Started Aug 29 09:36:43 AM UTC 24
Finished Aug 29 09:36:50 AM UTC 24
Peak memory 251124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531898146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.1531898146
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1480331725
Short name T888
Test name
Test status
Simulation time 19137983853 ps
CPU time 86.49 seconds
Started Aug 29 09:36:43 AM UTC 24
Finished Aug 29 09:38:11 AM UTC 24
Peak memory 268140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1480331725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 81.otp_ctrl_stress_all_with_rand_reset.1480331725
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.2040692711
Short name T65
Test name
Test status
Simulation time 395660923 ps
CPU time 4.63 seconds
Started Aug 29 09:36:43 AM UTC 24
Finished Aug 29 09:36:49 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040692711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.2040692711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.2063958884
Short name T848
Test name
Test status
Simulation time 1615802056 ps
CPU time 16.73 seconds
Started Aug 29 09:36:44 AM UTC 24
Finished Aug 29 09:37:02 AM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063958884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.2063958884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.15075717
Short name T401
Test name
Test status
Simulation time 6314399923 ps
CPU time 95.15 seconds
Started Aug 29 09:36:48 AM UTC 24
Finished Aug 29 09:38:26 AM UTC 24
Peak memory 257252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=15075717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
82.otp_ctrl_stress_all_with_rand_reset.15075717
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.1435792987
Short name T31
Test name
Test status
Simulation time 453003206 ps
CPU time 6.04 seconds
Started Aug 29 09:36:48 AM UTC 24
Finished Aug 29 09:36:56 AM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435792987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.1435792987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.172813474
Short name T850
Test name
Test status
Simulation time 356400609 ps
CPU time 13.95 seconds
Started Aug 29 09:36:48 AM UTC 24
Finished Aug 29 09:37:04 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172813474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.172813474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.2226990691
Short name T843
Test name
Test status
Simulation time 620604810 ps
CPU time 6.49 seconds
Started Aug 29 09:36:50 AM UTC 24
Finished Aug 29 09:36:57 AM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226990691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2226990691
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.3857849357
Short name T846
Test name
Test status
Simulation time 268428265 ps
CPU time 8.86 seconds
Started Aug 29 09:36:50 AM UTC 24
Finished Aug 29 09:37:00 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857849357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3857849357
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.1845649954
Short name T394
Test name
Test status
Simulation time 3672623809 ps
CPU time 162.2 seconds
Started Aug 29 09:36:50 AM UTC 24
Finished Aug 29 09:39:35 AM UTC 24
Peak memory 268052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1845649954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 84.otp_ctrl_stress_all_with_rand_reset.1845649954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.2776014715
Short name T844
Test name
Test status
Simulation time 353650898 ps
CPU time 5.14 seconds
Started Aug 29 09:36:51 AM UTC 24
Finished Aug 29 09:36:57 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776014715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2776014715
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.3964754772
Short name T847
Test name
Test status
Simulation time 246925400 ps
CPU time 8.2 seconds
Started Aug 29 09:36:51 AM UTC 24
Finished Aug 29 09:37:00 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964754772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.3964754772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.3987628361
Short name T891
Test name
Test status
Simulation time 35658805215 ps
CPU time 80.18 seconds
Started Aug 29 09:36:52 AM UTC 24
Finished Aug 29 09:38:15 AM UTC 24
Peak memory 257708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3987628361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 85.otp_ctrl_stress_all_with_rand_reset.3987628361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.2470600140
Short name T849
Test name
Test status
Simulation time 136773504 ps
CPU time 4.95 seconds
Started Aug 29 09:36:57 AM UTC 24
Finished Aug 29 09:37:03 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470600140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.2470600140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.4260277340
Short name T855
Test name
Test status
Simulation time 221815017 ps
CPU time 14.88 seconds
Started Aug 29 09:36:57 AM UTC 24
Finished Aug 29 09:37:13 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260277340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.4260277340
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.3500621330
Short name T853
Test name
Test status
Simulation time 2388783466 ps
CPU time 10.42 seconds
Started Aug 29 09:36:58 AM UTC 24
Finished Aug 29 09:37:09 AM UTC 24
Peak memory 251488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500621330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.3500621330
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.439225705
Short name T909
Test name
Test status
Simulation time 5528004578 ps
CPU time 83.74 seconds
Started Aug 29 09:37:01 AM UTC 24
Finished Aug 29 09:38:27 AM UTC 24
Peak memory 257644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=439225705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
87.otp_ctrl_stress_all_with_rand_reset.439225705
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.2078786603
Short name T851
Test name
Test status
Simulation time 227893999 ps
CPU time 5.11 seconds
Started Aug 29 09:37:01 AM UTC 24
Finished Aug 29 09:37:08 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078786603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.2078786603
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.1536443821
Short name T863
Test name
Test status
Simulation time 13300283535 ps
CPU time 27.44 seconds
Started Aug 29 09:37:03 AM UTC 24
Finished Aug 29 09:37:32 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536443821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.1536443821
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.2821938670
Short name T1005
Test name
Test status
Simulation time 8145514557 ps
CPU time 120.77 seconds
Started Aug 29 09:37:04 AM UTC 24
Finished Aug 29 09:39:07 AM UTC 24
Peak memory 267920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2821938670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 88.otp_ctrl_stress_all_with_rand_reset.2821938670
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.1007985029
Short name T856
Test name
Test status
Simulation time 1760653133 ps
CPU time 7.35 seconds
Started Aug 29 09:37:05 AM UTC 24
Finished Aug 29 09:37:14 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007985029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.1007985029
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.1347990835
Short name T859
Test name
Test status
Simulation time 329452456 ps
CPU time 10.02 seconds
Started Aug 29 09:37:09 AM UTC 24
Finished Aug 29 09:37:20 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347990835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.1347990835
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.1420725065
Short name T898
Test name
Test status
Simulation time 4609083730 ps
CPU time 67.76 seconds
Started Aug 29 09:37:09 AM UTC 24
Finished Aug 29 09:38:18 AM UTC 24
Peak memory 257556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1420725065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 89.otp_ctrl_stress_all_with_rand_reset.1420725065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.724345702
Short name T431
Test name
Test status
Simulation time 826445403 ps
CPU time 3.67 seconds
Started Aug 29 09:24:31 AM UTC 24
Finished Aug 29 09:24:36 AM UTC 24
Peak memory 251104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724345702 -assert nopostproc +UVM_TESTNAME=ot
p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.724345702
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.665130729
Short name T405
Test name
Test status
Simulation time 728494803 ps
CPU time 11.83 seconds
Started Aug 29 09:24:17 AM UTC 24
Finished Aug 29 09:24:30 AM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665130729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.665130729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.831902408
Short name T314
Test name
Test status
Simulation time 2161063193 ps
CPU time 45.78 seconds
Started Aug 29 09:24:20 AM UTC 24
Finished Aug 29 09:25:08 AM UTC 24
Peak memory 255476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831902408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.831902408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.1184683699
Short name T371
Test name
Test status
Simulation time 848950728 ps
CPU time 27.13 seconds
Started Aug 29 09:24:19 AM UTC 24
Finished Aug 29 09:24:48 AM UTC 24
Peak memory 253632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184683699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.1184683699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.2678342981
Short name T52
Test name
Test status
Simulation time 157901530 ps
CPU time 6.66 seconds
Started Aug 29 09:24:16 AM UTC 24
Finished Aug 29 09:24:23 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678342981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.2678342981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.1635721015
Short name T209
Test name
Test status
Simulation time 258951394 ps
CPU time 11.15 seconds
Started Aug 29 09:24:24 AM UTC 24
Finished Aug 29 09:24:36 AM UTC 24
Peak memory 253460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635721015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.1635721015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.1541033139
Short name T429
Test name
Test status
Simulation time 685607172 ps
CPU time 6.47 seconds
Started Aug 29 09:24:24 AM UTC 24
Finished Aug 29 09:24:31 AM UTC 24
Peak memory 251576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541033139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.1541033139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.1276367764
Short name T430
Test name
Test status
Simulation time 794010125 ps
CPU time 16.5 seconds
Started Aug 29 09:24:17 AM UTC 24
Finished Aug 29 09:24:35 AM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276367764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.1276367764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.2603232744
Short name T358
Test name
Test status
Simulation time 325171643 ps
CPU time 6.22 seconds
Started Aug 29 09:24:27 AM UTC 24
Finished Aug 29 09:24:35 AM UTC 24
Peak memory 251276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603232744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas
e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.2603232744
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.191681859
Short name T427
Test name
Test status
Simulation time 203644421 ps
CPU time 4.4 seconds
Started Aug 29 09:24:14 AM UTC 24
Finished Aug 29 09:24:20 AM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191681859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.191681859
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.2503563559
Short name T251
Test name
Test status
Simulation time 850847756 ps
CPU time 36.34 seconds
Started Aug 29 09:24:29 AM UTC 24
Finished Aug 29 09:25:07 AM UTC 24
Peak memory 257520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2503563559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.otp_ctrl_stress_all_with_rand_reset.2503563559
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.523655165
Short name T313
Test name
Test status
Simulation time 2209815699 ps
CPU time 38.55 seconds
Started Aug 29 09:24:28 AM UTC 24
Finished Aug 29 09:25:07 AM UTC 24
Peak memory 251392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523655165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.523655165
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.1949747135
Short name T80
Test name
Test status
Simulation time 374974488 ps
CPU time 5.55 seconds
Started Aug 29 09:37:09 AM UTC 24
Finished Aug 29 09:37:16 AM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949747135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.1949747135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.1484286123
Short name T868
Test name
Test status
Simulation time 3179252718 ps
CPU time 25.62 seconds
Started Aug 29 09:37:09 AM UTC 24
Finished Aug 29 09:37:36 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484286123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.1484286123
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.1635843778
Short name T858
Test name
Test status
Simulation time 104548441 ps
CPU time 5.72 seconds
Started Aug 29 09:37:11 AM UTC 24
Finished Aug 29 09:37:18 AM UTC 24
Peak memory 251512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635843778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.1635843778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.1742174633
Short name T865
Test name
Test status
Simulation time 581992248 ps
CPU time 16.74 seconds
Started Aug 29 09:37:14 AM UTC 24
Finished Aug 29 09:37:32 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742174633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1742174633
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.2978630622
Short name T311
Test name
Test status
Simulation time 4009708459 ps
CPU time 86.66 seconds
Started Aug 29 09:37:14 AM UTC 24
Finished Aug 29 09:38:43 AM UTC 24
Peak memory 257552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2978630622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 91.otp_ctrl_stress_all_with_rand_reset.2978630622
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.15507590
Short name T860
Test name
Test status
Simulation time 129863069 ps
CPU time 5.33 seconds
Started Aug 29 09:37:14 AM UTC 24
Finished Aug 29 09:37:21 AM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15507590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_
SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.15507590
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.1201063149
Short name T143
Test name
Test status
Simulation time 14105016743 ps
CPU time 61.36 seconds
Started Aug 29 09:37:16 AM UTC 24
Finished Aug 29 09:38:19 AM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201063149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.1201063149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.805884261
Short name T140
Test name
Test status
Simulation time 10911308712 ps
CPU time 181.5 seconds
Started Aug 29 09:37:16 AM UTC 24
Finished Aug 29 09:40:20 AM UTC 24
Peak memory 288368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=805884261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
92.otp_ctrl_stress_all_with_rand_reset.805884261
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.3242590194
Short name T862
Test name
Test status
Simulation time 508396445 ps
CPU time 5.3 seconds
Started Aug 29 09:37:17 AM UTC 24
Finished Aug 29 09:37:23 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242590194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.3242590194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.2813929205
Short name T872
Test name
Test status
Simulation time 581887140 ps
CPU time 22.31 seconds
Started Aug 29 09:37:19 AM UTC 24
Finished Aug 29 09:37:42 AM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813929205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2813929205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.3601288879
Short name T309
Test name
Test status
Simulation time 1396157971 ps
CPU time 39.03 seconds
Started Aug 29 09:37:21 AM UTC 24
Finished Aug 29 09:38:02 AM UTC 24
Peak memory 257528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3601288879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 93.otp_ctrl_stress_all_with_rand_reset.3601288879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.233778896
Short name T864
Test name
Test status
Simulation time 2475893607 ps
CPU time 8.35 seconds
Started Aug 29 09:37:22 AM UTC 24
Finished Aug 29 09:37:32 AM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233778896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.233778896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.3938346802
Short name T870
Test name
Test status
Simulation time 800184897 ps
CPU time 13.19 seconds
Started Aug 29 09:37:24 AM UTC 24
Finished Aug 29 09:37:38 AM UTC 24
Peak memory 257332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938346802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.3938346802
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2779283163
Short name T949
Test name
Test status
Simulation time 9120255465 ps
CPU time 84.26 seconds
Started Aug 29 09:37:24 AM UTC 24
Finished Aug 29 09:38:50 AM UTC 24
Peak memory 257588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2779283163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 94.otp_ctrl_stress_all_with_rand_reset.2779283163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.1114968728
Short name T866
Test name
Test status
Simulation time 155531065 ps
CPU time 5.66 seconds
Started Aug 29 09:37:26 AM UTC 24
Finished Aug 29 09:37:33 AM UTC 24
Peak memory 251236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114968728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.1114968728
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.1127246032
Short name T874
Test name
Test status
Simulation time 483140649 ps
CPU time 10.82 seconds
Started Aug 29 09:37:33 AM UTC 24
Finished Aug 29 09:37:45 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127246032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.1127246032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.1489721257
Short name T876
Test name
Test status
Simulation time 2366712724 ps
CPU time 12.33 seconds
Started Aug 29 09:37:33 AM UTC 24
Finished Aug 29 09:37:46 AM UTC 24
Peak memory 251232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489721257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.1489721257
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.1499101131
Short name T871
Test name
Test status
Simulation time 133888171 ps
CPU time 6.15 seconds
Started Aug 29 09:37:34 AM UTC 24
Finished Aug 29 09:37:41 AM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499101131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.1499101131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.2380715635
Short name T877
Test name
Test status
Simulation time 223302661 ps
CPU time 6.82 seconds
Started Aug 29 09:37:40 AM UTC 24
Finished Aug 29 09:37:47 AM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380715635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2380715635
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.1022343897
Short name T834
Test name
Test status
Simulation time 786418271 ps
CPU time 14.82 seconds
Started Aug 29 09:37:40 AM UTC 24
Finished Aug 29 09:37:56 AM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022343897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.1022343897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.1174021248
Short name T878
Test name
Test status
Simulation time 182031688 ps
CPU time 5.42 seconds
Started Aug 29 09:37:42 AM UTC 24
Finished Aug 29 09:37:48 AM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174021248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.1174021248
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.447625645
Short name T824
Test name
Test status
Simulation time 583086900 ps
CPU time 9.94 seconds
Started Aug 29 09:37:43 AM UTC 24
Finished Aug 29 09:37:54 AM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447625645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST
_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.447625645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.2335053712
Short name T830
Test name
Test status
Simulation time 131697930 ps
CPU time 5.13 seconds
Started Aug 29 09:37:48 AM UTC 24
Finished Aug 29 09:37:54 AM UTC 24
Peak memory 250952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335053712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2335053712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.2784889375
Short name T827
Test name
Test status
Simulation time 1182166650 ps
CPU time 4.94 seconds
Started Aug 29 09:37:48 AM UTC 24
Finished Aug 29 09:37:54 AM UTC 24
Peak memory 251096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784889375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES
T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/otp_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.2784889375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest
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