Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1457020
Category 01457020

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1457020
Severity 01457020

Summary for Assertions
NUMBERPERCENT
Total Number1457100.00
Uncovered543.71
Success140396.29
Failure00.00
Incomplete110.75
Without Attempts50.34

Summary for Cover Sequences
NUMBERPERCENT
Total Number20100.00
Uncovered00.00
All Matches20100.00
First Matches20100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.AssertConnected_A 001122112200
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs.AssertConnected_A 001122112200
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs_A 001005209119967894300
tb.dut.u_otp_ctrl_scrmbl.CheckNumDecKeys_A 0010052091123745700
tb.dut.u_otp_ctrl_scrmbl.CheckNumDigest1_A 0010052091111897400
tb.dut.u_otp_ctrl_scrmbl.CheckNumEncKeys_A 0010052091125141100
tb.dut.u_otp_ctrl_scrmbl.DecKeyLutKnown_A 001005209119967894300
tb.dut.u_otp_ctrl_scrmbl.DigestConstLutKnown_A 001005209119967894300
tb.dut.u_otp_ctrl_scrmbl.DigestIvLutKnown_A 001005209119967894300
tb.dut.u_otp_ctrl_scrmbl.EncKeyLutKnown_A 001005209119967894300
tb.dut.u_otp_ctrl_scrmbl.NumMaxPresentRounds_A 001122112200
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds0_A 001122112200
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumPhysRounds1_A 001122112200
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedNumRounds_A 001122112200
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_dec.SupportedWidths_A 001122112200
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds0_A 001122112200
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumPhysRounds1_A 001122112200
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedNumRounds_A 001122112200
tb.dut.u_otp_ctrl_scrmbl.u_prim_present_enc.SupportedWidths_A 001122112200
tb.dut.u_otp_ctrl_scrmbl.u_state_regs.AssertConnected_A 001122112200
tb.dut.u_otp_ctrl_scrmbl.u_state_regs_A 001005209119967894300
tb.dut.u_otp_rsp_fifo.DataKnown_A 001005209111847383200
tb.dut.u_otp_rsp_fifo.DepthKnown_A 001005209119967894300
tb.dut.u_otp_rsp_fifo.RvalidKnown_A 001005209119967894300
tb.dut.u_otp_rsp_fifo.WreadyKnown_A 001005209119967894300
tb.dut.u_otp_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 001005209111847383200
tb.dut.u_part_sel_idx.CheckHotOne_A 001005209119967894300
tb.dut.u_part_sel_idx.CheckNGreaterZero_A 001122112200
tb.dut.u_part_sel_idx.GrantKnown_A 001005209119967894300
tb.dut.u_part_sel_idx.IdxKnown_A 001005209119967894300
tb.dut.u_part_sel_idx.Priority_A 001005209119967894300
tb.dut.u_part_sel_idx.ReqImpliesValid_A 001005209119967894300
tb.dut.u_part_sel_idx.ValidKnown_A 001005209119967894300
tb.dut.u_prim_edn_req.DataOutputDiffFromPrev_A 001005209114689879100
tb.dut.u_prim_edn_req.DataOutputValid_A 0010052091119321900
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 0010052091138687400
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 0010052091138681300
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq 0023982286738708500
tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq 0010052091119305300
tb.dut.u_prim_lc_sync_check_byp_en.NumCopiesMustBeGreaterZero_A 001122112200
tb.dut.u_prim_lc_sync_check_byp_en.OutputsKnown_A 001005209119967894300
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A 001005209119963968803333
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A 001122112200
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.OutputsKnown_A 001005209119967894300
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A 001005209119963968803333
tb.dut.u_prim_lc_sync_dft_en.NumCopiesMustBeGreaterZero_A 001122112200
tb.dut.u_prim_lc_sync_dft_en.OutputsKnown_A 001005209119967894300
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A 001005209119963968803333
tb.dut.u_prim_lc_sync_escalate_en.NumCopiesMustBeGreaterZero_A 001122112200
tb.dut.u_prim_lc_sync_escalate_en.OutputsKnown_A 001005209119967894300
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A 001005209119963968803333
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.NumCopiesMustBeGreaterZero_A 001122112200
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.OutputsKnown_A 001005209119967894300
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A 001005209119963968803333
tb.dut.u_prim_lc_sync_seed_hw_rd_en.NumCopiesMustBeGreaterZero_A 001122112200
tb.dut.u_prim_lc_sync_seed_hw_rd_en.OutputsKnown_A 001005209119967894300
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A 001005209119963968803333
tb.dut.u_reg_core.en2addrHit 00103474757645740800
tb.dut.u_reg_core.reAfterRv 00103474757645740800
tb.dut.u_reg_core.rePulse 00103474757555861600
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck 001296129600
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A 001296129600
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert 001296129600
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A 001296129600
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001296129600
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001296129600
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A 001296129600
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck 001296129600
tb.dut.u_reg_core.u_socket.NotOverflowed_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A 00103474757935874500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 001296129600
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A 001034747571379205500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 001296129600
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 00103474757139697700
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001296129600
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 00103474757142869400
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001296129600
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 00103474757741047500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001296129600
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 001034747571236336100
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 0010347475710258002500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001296129600
tb.dut.u_reg_core.u_socket.maxN 001296129600
tb.dut.u_reg_core.wePulse 0010347475789879200
tb.dut.u_scrmbl_mtx.CheckHotOne_A 001005209119967894300
tb.dut.u_scrmbl_mtx.CheckNGreaterZero_A 001122112200
tb.dut.u_scrmbl_mtx.GrantKnown_A 001005209119967894300
tb.dut.u_scrmbl_mtx.IdxKnown_A 001005209119967894300
tb.dut.u_scrmbl_mtx.NoReadyValidNoGrant_A 001005209115425271100
tb.dut.u_scrmbl_mtx.ReqImpliesValid_A 001005209114542623200
tb.dut.u_scrmbl_mtx.ValidKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.AddrOutKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.DataIntgOptions_A 001122112200
tb.dut.u_tlul_adapter_sram.ReqOutKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.SramDwHasByteGranularity_A 001122112200
tb.dut.u_tlul_adapter_sram.SramDwIsMultipleOfTlulWidth_A 001122112200
tb.dut.u_tlul_adapter_sram.TlOutKnownIfFifoKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.TlOutValidKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.WdataOutKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.WeOutKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.WmaskOutKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.adapterNoReadOrWrite 001122112200
tb.dut.u_tlul_adapter_sram.rvalidHighReqFifoEmpty 001005209118245300
tb.dut.u_tlul_adapter_sram.rvalidHighWhenRspFifoFull 001005209118245300
tb.dut.u_tlul_adapter_sram.u_err.dataWidthOnly32_A 001122112200
tb.dut.u_tlul_adapter_sram.u_reqfifo.DataKnown_A 00100520911187649200
tb.dut.u_tlul_adapter_sram.u_reqfifo.DepthKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.u_reqfifo.RvalidKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.u_reqfifo.WreadyKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00100520911187649200
tb.dut.u_tlul_adapter_sram.u_rsp_gen.DataWidthCheck_A 001122112200
tb.dut.u_tlul_adapter_sram.u_rsp_gen.PayLoadWidthCheck 001122112200
tb.dut.u_tlul_adapter_sram.u_rspfifo.DataKnown_A 0010052091119569400
tb.dut.u_tlul_adapter_sram.u_rspfifo.DepthKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.u_rspfifo.RvalidKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.u_rspfifo.WreadyKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0010052091119569400
tb.dut.u_tlul_adapter_sram.u_sram_byte.SramReadbackAndIntg 001122112200
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DataKnown_A 0010052091155078600
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DepthKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.RvalidKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.WreadyKnown_A 001005209119967894300
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0010052091155078600
tb.dut.u_tlul_lc_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001122112200
tb.dut.u_tlul_lc_gate.u_err_en_sync.OutputsKnown_A 001005209119967894300
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 001005209119967894300
tb.dut.u_tlul_lc_gate.u_state_regs.AssertConnected_A 001122112200
tb.dut.u_tlul_lc_gate.u_state_regs_A 001005209119967894300
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001122112200
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001122112200

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_edn_arb.RoundRobin_A 00100520911001111
tb.dut.u_otp_arb.RoundRobin_A 00100520911001111
tb.dut.u_otp_ctrl_kdi.u_req_arb.RoundRobin_A 00100520911001111
tb.dut.u_prim_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A 00100520911001111
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A 001005209119963968803333
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A 001005209119963968803333
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A 001005209119963968803333
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A 001005209119963968803333
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.OutputDelay_A 001005209119963968803333
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A 001005209119963968803333
tb.dut.u_scrmbl_mtx.RoundRobin_A 00100520911001111

Assertions Without Attempts:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.OtpErrorState_A 000000

Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 001034756827677670
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 001034756822512510
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 001034756822532530
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 001034756821631630
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0010347568233330
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 001034756821261260
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 001034756821201200
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00103475682326932690
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C 00103475682582058200
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C 00103475682319256131925611210
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 001034756823183180
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0010347568286861
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0010347568292921
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0010347568267671
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00103475682881
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0010347568252521
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0010347568256561
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 001034756829639630
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C 00103475682203320330
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C 00103475682582115821154

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 001034756827677670
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 001034756822512510
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 001034756822532530
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 001034756821631630
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0010347568233330
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 001034756821261260
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 001034756821201200
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 00103475682326932690
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C 00103475682582058200
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C 00103475682319256131925611210
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 001034756823183180
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0010347568286861
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0010347568292921
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0010347568267671
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00103475682881
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0010347568252521
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0010347568256561
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 001034756829639630
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C 00103475682203320330
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C 00103475682582115821154