Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4381457	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2424821

1

T1

5

T2

157

T3

212

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5697337	1			T1	4		T2	270		T3	442
values[0x0]	520273	1			T1	6		T2	102		T3	25
values[0x1]	588668	1			T1	9		T2	87		T3	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3221243	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3585035

1

T1

6

T2

240

T3

271

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21963	1			T2	4		T4	2		T6	3
valid_sources[0x01]	19914	1			T2	1		T4	5		T6	10
valid_sources[0x02]	19508	1			T2	1		T3	2		T4	10
valid_sources[0x03]	19694	1			T2	1		T4	2		T6	8
valid_sources[0x04]	41704	1			T2	2		T4	8		T11	5
valid_sources[0x05]	19986	1			T2	2		T4	3		T6	17
valid_sources[0x06]	22476	1			T2	1		T4	3		T10	5
valid_sources[0x07]	28458	1			T2	1		T3	3		T4	5
valid_sources[0x08]	23488	1			T2	2		T4	19		T6	3
valid_sources[0x09]	28990	1			T6	4		T11	1		T129	11
valid_sources[0x0a]	22552	1			T3	16		T4	3		T6	4
valid_sources[0x0b]	24097	1			T3	5		T4	2		T6	7
valid_sources[0x0c]	23926	1			T2	6		T4	5		T6	6
valid_sources[0x0d]	24542	1			T2	5		T6	12		T11	4
valid_sources[0x0e]	23834	1			T2	2		T4	5		T6	4
valid_sources[0x0f]	27119	1			T2	1		T3	11		T4	5
valid_sources[0x10]	28721	1			T2	2		T4	15		T6	4
valid_sources[0x11]	28429	1			T2	1		T6	8		T11	2
valid_sources[0x12]	26635	1			T2	1		T3	14		T4	5
valid_sources[0x13]	31824	1			T4	7		T6	6		T129	19
valid_sources[0x14]	19802	1			T2	3		T4	6		T6	4
valid_sources[0x15]	20814	1			T2	3		T6	9		T129	15
valid_sources[0x16]	25535	1			T2	1		T4	9		T6	1
valid_sources[0x17]	26233	1			T2	2		T4	4		T6	7
valid_sources[0x18]	19847	1			T2	1		T4	4		T6	7
valid_sources[0x19]	20698	1			T2	4		T6	6		T11	3
valid_sources[0x1a]	29893	1			T2	2		T11	1		T129	5
valid_sources[0x1b]	21153	1			T2	3		T3	4		T4	1
valid_sources[0x1c]	24722	1			T2	2		T3	14		T4	6
valid_sources[0x1d]	43698	1			T2	2		T4	1		T6	2
valid_sources[0x1e]	26940	1			T4	13		T5	2537		T6	10
valid_sources[0x1f]	46670	1			T2	4		T3	4		T4	9
valid_sources[0x20]	21587	1			T2	1		T4	6		T6	21
valid_sources[0x21]	27206	1			T2	2		T3	25		T4	3
valid_sources[0x22]	20439	1			T2	3		T4	5		T6	12
valid_sources[0x23]	20109	1			T4	19		T6	3		T11	1
valid_sources[0x24]	21913	1			T4	5		T6	5		T11	1
valid_sources[0x25]	26803	1			T4	6		T6	4		T11	2
valid_sources[0x26]	28189	1			T2	7		T4	8		T6	5
valid_sources[0x27]	27471	1			T6	2		T11	1		T129	18
valid_sources[0x28]	28479	1			T2	3		T3	6		T4	1
valid_sources[0x29]	27302	1			T2	1		T3	4		T6	6
valid_sources[0x2a]	31544	1			T2	5		T4	4		T6	10
valid_sources[0x2b]	41199	1			T4	6		T6	5		T11	1
valid_sources[0x2c]	21911	1			T2	3		T4	1		T6	4
valid_sources[0x2d]	19472	1			T2	5		T3	15		T4	9
valid_sources[0x2e]	26454	1			T2	1		T4	11		T6	2
valid_sources[0x2f]	23066	1			T2	7		T6	4		T11	3
valid_sources[0x30]	41078	1			T2	2		T4	3		T6	5
valid_sources[0x31]	33728	1			T2	2		T6	8		T11	3
valid_sources[0x32]	50495	1			T2	2		T6	4		T11	11
valid_sources[0x33]	23736	1			T2	2		T6	4		T11	6
valid_sources[0x34]	26001	1			T2	1		T6	1		T11	2
valid_sources[0x35]	22977	1			T3	2		T6	5		T11	6
valid_sources[0x36]	31316	1			T2	2		T4	1		T6	2
valid_sources[0x37]	23004	1			T2	2		T4	3		T6	7
valid_sources[0x38]	32522	1			T2	2		T3	19		T6	3
valid_sources[0x39]	25411	1			T2	4		T3	14		T4	10
valid_sources[0x3a]	20211	1			T2	2		T6	3		T11	2
valid_sources[0x3b]	22463	1			T2	1		T4	15		T6	11
valid_sources[0x3c]	29183	1			T2	1		T4	5		T6	10
valid_sources[0x3d]	20298	1			T3	1		T10	2		T6	12
valid_sources[0x3e]	33587	1			T2	1		T4	2		T6	8
valid_sources[0x3f]	20518	1			T2	2		T3	13		T6	8
valid_sources[0x40]	21414	1			T2	5		T6	10		T11	3
valid_sources[0x41]	22532	1			T4	2		T6	1		T11	2
valid_sources[0x42]	74806	1			T6	18		T129	17		T36	43
valid_sources[0x43]	24104	1			T4	4		T6	5		T129	18
valid_sources[0x44]	20469	1			T2	1		T3	5		T4	3
valid_sources[0x45]	20808	1			T2	3		T6	3		T11	3
valid_sources[0x46]	19537	1			T2	1		T3	18		T4	2
valid_sources[0x47]	33615	1			T2	4		T4	1		T6	4
valid_sources[0x48]	19833	1			T4	1		T6	4		T129	11
valid_sources[0x49]	20121	1			T2	1		T3	11		T6	14
valid_sources[0x4a]	21230	1			T2	2		T6	2		T11	5
valid_sources[0x4b]	43209	1			T2	1		T6	3		T11	7
valid_sources[0x4c]	24364	1			T2	1		T4	4		T6	16
valid_sources[0x4d]	24790	1			T4	3		T6	5		T11	2
valid_sources[0x4e]	22262	1			T4	4		T6	3		T11	8
valid_sources[0x4f]	28937	1			T2	2		T4	10		T6	1
valid_sources[0x50]	20225	1			T3	14		T4	8		T6	2
valid_sources[0x51]	32473	1			T2	4		T6	7		T11	4
valid_sources[0x52]	20484	1			T2	4		T4	5		T6	8
valid_sources[0x53]	20649	1			T2	1		T6	16		T11	2
valid_sources[0x54]	20611	1			T2	1		T4	2		T6	3
valid_sources[0x55]	21177	1			T2	1		T4	4		T6	2
valid_sources[0x56]	20884	1			T2	2		T4	2		T11	3
valid_sources[0x57]	20075	1			T2	3		T4	3		T6	9
valid_sources[0x58]	21134	1			T2	2		T4	5		T6	5
valid_sources[0x59]	19513	1			T2	3		T6	17		T11	9
valid_sources[0x5a]	45688	1			T2	1		T3	2		T6	2
valid_sources[0x5b]	26347	1			T2	1		T6	7		T11	8
valid_sources[0x5c]	20840	1			T2	3		T4	17		T6	7
valid_sources[0x5d]	30035	1			T2	1		T4	11		T6	9
valid_sources[0x5e]	21603	1			T4	3		T6	5		T11	5
valid_sources[0x5f]	35455	1			T2	2		T6	10		T11	2
valid_sources[0x60]	19559	1			T2	2		T4	3		T6	5
valid_sources[0x61]	33151	1			T2	4		T3	9		T6	5
valid_sources[0x62]	21343	1			T4	10		T6	7		T129	18
valid_sources[0x63]	19470	1			T2	2		T4	8		T6	6
valid_sources[0x64]	21955	1			T2	1		T3	12		T4	6
valid_sources[0x65]	21118	1			T2	2		T6	3		T11	4
valid_sources[0x66]	23022	1			T2	1		T4	13		T6	3
valid_sources[0x67]	19879	1			T2	2		T4	4		T6	5
valid_sources[0x68]	26681	1			T2	1		T4	8		T6	6
valid_sources[0x69]	20475	1			T2	1		T6	1		T11	3
valid_sources[0x6a]	35611	1			T4	5		T6	11		T11	8
valid_sources[0x6b]	32490	1			T2	5		T4	2		T11	2
valid_sources[0x6c]	30338	1			T2	3		T4	10		T6	4
valid_sources[0x6d]	22349	1			T2	4		T4	5		T6	5
valid_sources[0x6e]	21203	1			T2	4		T3	3		T6	1
valid_sources[0x6f]	21226	1			T2	1		T6	4		T11	3
valid_sources[0x70]	30225	1			T4	1		T6	5		T11	3
valid_sources[0x71]	19931	1			T2	5		T4	5		T6	16
valid_sources[0x72]	25120	1			T2	1		T3	14		T6	3
valid_sources[0x73]	20348	1			T4	5		T6	4		T11	4
valid_sources[0x74]	21055	1			T2	1		T4	2		T6	12
valid_sources[0x75]	20213	1			T2	2		T4	17		T6	6
valid_sources[0x76]	21315	1			T2	2		T4	11		T6	7
valid_sources[0x77]	20500	1			T2	2		T3	1		T6	10
valid_sources[0x78]	24720	1			T6	8		T11	4		T129	17
valid_sources[0x79]	32573	1			T3	2		T6	5		T129	7
valid_sources[0x7a]	20307	1			T2	2		T4	4		T10	2
valid_sources[0x7b]	26723	1			T2	1		T4	7		T6	4
valid_sources[0x7c]	26979	1			T2	3		T4	10		T6	3
valid_sources[0x7d]	21050	1			T2	7		T6	4		T11	3
valid_sources[0x7e]	25487	1			T2	2		T3	12		T4	4
valid_sources[0x7f]	19772	1			T2	3		T6	3		T11	4
valid_sources[0x80]	36779	1			T3	3		T4	1		T6	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1898167

1

T1

1

T2

69

T3

190

values[0x0]

all_enables

biggest_size

294651

1

T1

1

T2

58

T3

11

values[0x1]

all_enables

biggest_size

232003

1

T1

3

T2

30

T3

11

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27790	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

565451

1

T3

20

T4

40

T5

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	185294	1			T3	10		T4	20		T5	20
values[0x0]	198565	1			T3	4		T4	11		T5	9
values[0x1]	209382	1			T3	6		T4	9		T5	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14934	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

578307

1

T3

20

T4

40

T5

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1787	1			T3	1		T99	2		T20	1
valid_sources[0x01]	2322	1			T9	2		T120	1		T127	2
valid_sources[0x02]	2057	1			T99	1		T96	3		T19	1
valid_sources[0x03]	2391	1			T102	7		T92	1		T93	1
valid_sources[0x04]	2160	1			T96	1		T100	2		T118	1
valid_sources[0x05]	1776	1			T119	10		T9	1		T193	2
valid_sources[0x06]	2046	1			T93	1		T99	1		T115	1
valid_sources[0x07]	2803	1			T99	1		T118	3		T127	2
valid_sources[0x08]	2414	1			T102	9		T210	2		T219	1
valid_sources[0x09]	2643	1			T94	1		T126	1		T99	1
valid_sources[0x0a]	1934	1			T102	4		T99	1		T100	1
valid_sources[0x0b]	2492	1			T99	1		T116	2		T100	1
valid_sources[0x0c]	2213	1			T126	2		T116	3		T100	2
valid_sources[0x0d]	2080	1			T20	2		T127	2		T146	3
valid_sources[0x0e]	2686	1			T99	1		T19	1		T9	1
valid_sources[0x0f]	2081	1			T4	1		T92	1		T96	1
valid_sources[0x10]	2021	1			T18	5		T96	1		T20	1
valid_sources[0x11]	3187	1			T13	3		T94	1		T102	3
valid_sources[0x12]	2043	1			T92	2		T93	1		T19	1
valid_sources[0x13]	2445	1			T36	6		T94	1		T92	1
valid_sources[0x14]	2492	1			T99	1		T120	1		T165	5
valid_sources[0x15]	2091	1			T116	2		T9	1		T120	1
valid_sources[0x16]	1624	1			T4	1		T102	6		T92	1
valid_sources[0x17]	2248	1			T99	1		T20	1		T9	1
valid_sources[0x18]	2580	1			T118	2		T120	8		T122	3
valid_sources[0x19]	2480	1			T93	1		T99	1		T9	1
valid_sources[0x1a]	2672	1			T94	1		T93	3		T118	1
valid_sources[0x1b]	2433	1			T4	1		T93	1		T115	1
valid_sources[0x1c]	2375	1			T4	2		T94	1		T126	1
valid_sources[0x1d]	2283	1			T7	3		T96	2		T19	1
valid_sources[0x1e]	3409	1			T102	11		T100	2		T118	2
valid_sources[0x1f]	1899	1			T99	1		T96	1		T118	3
valid_sources[0x20]	1616	1			T94	2		T102	1		T99	1
valid_sources[0x21]	2973	1			T100	3		T20	2		T120	1
valid_sources[0x22]	2542	1			T116	3		T100	1		T9	1
valid_sources[0x23]	2542	1			T94	1		T92	1		T19	1
valid_sources[0x24]	1856	1			T13	2		T100	1		T19	1
valid_sources[0x25]	2514	1			T3	2		T93	2		T117	3
valid_sources[0x26]	2261	1			T93	3		T99	1		T18	2
valid_sources[0x27]	2224	1			T94	1		T102	12		T126	1
valid_sources[0x28]	1898	1			T3	1		T36	7		T96	1
valid_sources[0x29]	2131	1			T100	1		T120	1		T210	1
valid_sources[0x2a]	2093	1			T4	1		T93	2		T119	1
valid_sources[0x2b]	2372	1			T99	1		T116	2		T100	1
valid_sources[0x2c]	2295	1			T4	1		T94	1		T102	3
valid_sources[0x2d]	2255	1			T4	1		T13	3		T99	1
valid_sources[0x2e]	1786	1			T96	1		T100	1		T118	5
valid_sources[0x2f]	1714	1			T93	1		T99	1		T96	1
valid_sources[0x30]	2301	1			T99	1		T100	1		T118	4
valid_sources[0x31]	1698	1			T92	2		T99	1		T116	6
valid_sources[0x32]	2117	1			T3	1		T99	1		T120	1
valid_sources[0x33]	2117	1			T13	4		T36	16		T126	1
valid_sources[0x34]	2612	1			T96	1		T118	5		T119	10
valid_sources[0x35]	2014	1			T3	1		T99	2		T20	1
valid_sources[0x36]	2566	1			T100	1		T19	1		T120	2
valid_sources[0x37]	2906	1			T92	1		T99	1		T96	1
valid_sources[0x38]	2159	1			T94	1		T93	1		T99	2
valid_sources[0x39]	2054	1			T93	1		T18	1		T100	1
valid_sources[0x3a]	1985	1			T3	1		T94	1		T99	1
valid_sources[0x3b]	2281	1			T99	1		T19	1		T192	1
valid_sources[0x3c]	1982	1			T94	1		T96	2		T100	1
valid_sources[0x3d]	2149	1			T94	1		T92	1		T126	1
valid_sources[0x3e]	2988	1			T92	1		T18	3		T118	1
valid_sources[0x3f]	2520	1			T94	1		T116	5		T100	3
valid_sources[0x40]	2690	1			T94	1		T126	2		T99	2
valid_sources[0x41]	2409	1			T93	2		T19	1		T20	1
valid_sources[0x42]	1859	1			T99	1		T19	1		T20	2
valid_sources[0x43]	2123	1			T99	2		T118	1		T20	1
valid_sources[0x44]	2379	1			T102	7		T18	10		T100	1
valid_sources[0x45]	2543	1			T4	1		T118	4		T19	1
valid_sources[0x46]	2119	1			T94	1		T92	1		T116	1
valid_sources[0x47]	2395	1			T3	1		T4	1		T126	1
valid_sources[0x48]	2866	1			T117	12		T9	3		T210	1
valid_sources[0x49]	2520	1			T13	1		T102	2		T96	2
valid_sources[0x4a]	1977	1			T126	1		T99	2		T96	1
valid_sources[0x4b]	2495	1			T94	1		T126	2		T20	3
valid_sources[0x4c]	3929	1			T4	2		T94	1		T118	2
valid_sources[0x4d]	2846	1			T94	1		T126	3		T100	1
valid_sources[0x4e]	1860	1			T93	1		T118	2		T9	1
valid_sources[0x4f]	2418	1			T4	1		T99	1		T100	3
valid_sources[0x50]	2055	1			T36	3		T102	2		T118	1
valid_sources[0x51]	2129	1			T4	3		T13	1		T99	2
valid_sources[0x52]	2460	1			T36	10		T94	1		T115	1
valid_sources[0x53]	2364	1			T120	1		T185	1		T14	22
valid_sources[0x54]	2367	1			T120	1		T271	1		T277	1
valid_sources[0x55]	2872	1			T3	1		T102	12		T99	1
valid_sources[0x56]	2068	1			T94	1		T100	1		T19	1
valid_sources[0x57]	2309	1			T4	2		T94	1		T93	1
valid_sources[0x58]	2498	1			T94	1		T99	1		T18	1
valid_sources[0x59]	1908	1			T94	1		T93	1		T100	1
valid_sources[0x5a]	1948	1			T13	1		T93	1		T96	1
valid_sources[0x5b]	2676	1			T116	1		T19	1		T9	2
valid_sources[0x5c]	1898	1			T5	40		T93	1		T99	1
valid_sources[0x5d]	2358	1			T93	1		T99	1		T96	2
valid_sources[0x5e]	2235	1			T13	1		T36	4		T102	3
valid_sources[0x5f]	1979	1			T102	2		T96	1		T19	2
valid_sources[0x60]	1901	1			T93	1		T99	1		T100	3
valid_sources[0x61]	2796	1			T94	1		T99	2		T100	1
valid_sources[0x62]	2448	1			T19	1		T192	1		T276	2
valid_sources[0x63]	2589	1			T93	1		T119	12		T192	1
valid_sources[0x64]	2142	1			T100	1		T120	1		T192	1
valid_sources[0x65]	2445	1			T93	2		T119	2		T120	2
valid_sources[0x66]	4309	1			T93	1		T115	1		T96	1
valid_sources[0x67]	2655	1			T99	1		T7	2		T19	2
valid_sources[0x68]	3511	1			T99	3		T96	1		T20	2
valid_sources[0x69]	2065	1			T102	2		T93	1		T99	1
valid_sources[0x6a]	1850	1			T126	6		T117	4		T118	1
valid_sources[0x6b]	2214	1			T99	1		T100	5		T20	2
valid_sources[0x6c]	3232	1			T96	2		T100	2		T118	6
valid_sources[0x6d]	1941	1			T3	1		T20	1		T119	6
valid_sources[0x6e]	1967	1			T20	2		T210	1		T146	1
valid_sources[0x6f]	2635	1			T100	2		T9	4		T120	2
valid_sources[0x70]	2339	1			T102	5		T100	1		T19	1
valid_sources[0x71]	2518	1			T3	1		T94	1		T102	1
valid_sources[0x72]	2608	1			T94	1		T100	4		T144	5
valid_sources[0x73]	2321	1			T102	2		T92	1		T126	1
valid_sources[0x74]	1940	1			T36	3		T96	1		T100	1
valid_sources[0x75]	2586	1			T92	1		T18	1		T19	2
valid_sources[0x76]	1724	1			T96	1		T100	1		T20	2
valid_sources[0x77]	2378	1			T13	1		T94	1		T93	4
valid_sources[0x78]	2629	1			T126	1		T99	2		T20	1
valid_sources[0x79]	1996	1			T94	1		T102	2		T100	1
valid_sources[0x7a]	2843	1			T13	1		T94	1		T92	1
valid_sources[0x7b]	2558	1			T94	1		T93	1		T18	3
valid_sources[0x7c]	2047	1			T93	1		T99	3		T20	4
valid_sources[0x7d]	2031	1			T94	1		T92	1		T118	1
valid_sources[0x7e]	2697	1			T94	1		T96	1		T100	2
valid_sources[0x7f]	2260	1			T93	1		T96	1		T100	3
valid_sources[0x80]	2443	1			T36	11		T99	1		T9	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

172158

1

T3

10

T4

20

T5

20

values[0x0]

all_enables

biggest_size

196908

1

T3

4

T4

11

T5

9

values[0x1]

all_enables

biggest_size

196385

1

T3

6

T4

9

T5

11