Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5238327

1

T1

14

T2

302

T3

286

full_word

2477107

1

T1

5

T2

157

T3

212

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7715124	1			T1	19		T2	459		T3	498
auto[TlIntgErrCmd]	112	1			T282	7		T283	7		T284	3
auto[TlIntgErrData]	88	1			T282	5		T283	4		T284	3
auto[TlIntgErrBoth]	110	1			T282	8		T283	9		T284	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5760452

1

T1

4

T2

270

T3

442

auto[1]

1954982

1

T1

15

T2

189

T3

56

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3855688	1			T1	3		T2	201		T3	252
auto[TlIntgErrNone]	partial	auto[1]	1382362	1			T1	11		T2	101		T3	34
auto[TlIntgErrNone]	full_word	auto[0]	1904631	1			T1	1		T2	69		T3	190
auto[TlIntgErrNone]	full_word	auto[1]	572443	1			T1	4		T2	88		T3	22
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T282	3		T283	3		T284	1
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T282	4		T283	3		T284	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T284	1		T291	1		T289	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T283	1		T291	2		T368	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T282	5		T283	2		T291	2
auto[TlIntgErrData]	partial	auto[1]	38	1			T283	1		T284	3		T369	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T289	1		T363	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1			T283	1		T364	1		T291	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T282	3		T283	4		T284	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T282	4		T283	3		T284	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T369	1		T370	1		T371	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T282	1		T283	2		T364	1