Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

137                       // Output partition error state.
138        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
139                     
140                       // This partition cannot do any write accesses, hence we tie this
141                       // constantly off.
142                       assign otp_wdata_o = '0;
143                       // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144                       // calculations and checks. To be on the safe side, the partition filters error responses at this
145                       // point and does not report any integrity errors if integrity is disabled.
146                       otp_err_e otp_err;
147                       if (Info.integrity) begin : gen_integrity
148                         assign otp_cmd_o = prim_otp_pkg::Read;
149        1/1              assign otp_err = otp_err_e'(otp_err_i);
           Tests:       T1 T2 T3 
150                       end else begin : gen_no_integrity
151                         assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152                         always_comb begin
153                           if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
154                             otp_err = NoError;
155                           end else begin
156                             otp_err = otp_err_e'(otp_err_i);
157                           end
158                         end
159                       end
160                     
161                       `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162                       always_comb begin : p_fsm
163                         // Default assignments
164        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
165                     
166                         // Response to init request
167        1/1              init_done_o = 1'b0;
           Tests:       T1 T2 T3 
168                     
169                         // OTP signals
170        1/1              otp_req_o   = 1'b0;
           Tests:       T1 T2 T3 
171        1/1              otp_addr_sel = DigestAddrSel;
           Tests:       T1 T2 T3 
172                     
173                         // TL-UL signals
174        1/1              tlul_gnt_o      = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              tlul_rvalid_o   = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              tlul_rerror_o   = '0;
           Tests:       T1 T2 T3 
177                     
178                         // Enable for buffered digest register
179        1/1              digest_reg_en = 1'b0;
           Tests:       T1 T2 T3 
180                     
181                         // Error Register
182        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
183        1/1              pending_tlul_error_d = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           ///////////////////////////////////////////////////////////////////
188                           // State right after reset. Wait here until we get a an
189                           // initialization request.
190                           ResetSt: begin
191        1/1                  if (init_req_i) begin
           Tests:       T1 T2 T3 
192                               // If the partition does not have a digest, no initialization is necessary.
193        1/1                    if (Info.sw_digest) begin
           Tests:       T1 T2 T3 
194        1/1                      state_d = InitSt;
           Tests:       T1 T2 T3 
195                               end else begin
196        unreachable              state_d = IdleSt;
197                               end
198                             end
                        MISSING_ELSE
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Initialization reads out the digest only in unbuffered
202                           // partitions. Wait here until the OTP request has been granted.
203                           // And then wait until the OTP word comes back.
204                           InitSt: begin
205        1/1                  otp_req_o = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  if (otp_gnt_i) begin
           Tests:       T1 T2 T3 
207        1/1                    state_d = InitWaitSt;
           Tests:       T1 T2 T3 
208                             end
                        MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // Wait for OTP response and write to digest buffer register. In
212                           // case an OTP transaction fails, latch the  OTP error code and
213                           // jump to a terminal error state.
214                           InitWaitSt: begin
215        1/1                  if (otp_rvalid_i) begin
           Tests:       T1 T2 T3 
216        1/1                    digest_reg_en = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T1 T2 T3 
218        1/1                      state_d = IdleSt;
           Tests:       T1 T2 T3 
219                                 // At this point the only error that we could have gotten are correctable ECC errors.
220        1/1                      if (otp_err != NoError) begin
           Tests:       T1 T2 T3 
221        1/1                        error_d = MacroEccCorrError;
           Tests:       T103 T33 T48 
222                                 end
                        MISSING_ELSE
223                               end else begin
224        1/1                      state_d = ErrorSt;
           Tests:       T2 T184 T176 
225        1/1                      error_d = otp_err;
           Tests:       T2 T184 T176 
226                               end
227                             end
                        MISSING_ELSE
228                           end
229                           ///////////////////////////////////////////////////////////////////
230                           // Wait for TL-UL requests coming in.
231                           // Then latch address and go to readout state.
232                           IdleSt: begin
233        1/1                  init_done_o = 1'b1;
           Tests:       T1 T2 T3 
234        1/1                  if (tlul_req_i) begin
           Tests:       T1 T2 T3 
235        1/1                    error_d = NoError; // clear recoverable soft errors.
           Tests:       T2 T3 T4 
236        1/1                    state_d = ReadSt;
           Tests:       T2 T3 T4 
237        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T2 T3 T4 
238                             end
                        MISSING_ELSE
239                           end
240                           ///////////////////////////////////////////////////////////////////
241                           // If the address is out of bounds, or if the partition is
242                           // locked, signal back a bus error. Note that such an error does
243                           // not cause the partition to go into error state. Otherwise if
244                           // these checks pass, an OTP word is requested.
245                           ReadSt: begin
246        1/1                  init_done_o = 1'b1;
           Tests:       T2 T3 T4 
247                             // Double check the address range.
248        1/1                  if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
           Tests:       T2 T3 T4 
249        1/1                    otp_req_o = 1'b1;
           Tests:       T2 T3 T4 
250        1/1                    otp_addr_sel = DataAddrSel;
           Tests:       T2 T3 T4 
251        1/1                    if (otp_gnt_i) begin
           Tests:       T2 T3 T4 
252        1/1                      state_d = ReadWaitSt;
           Tests:       T2 T3 T4 
253                               end
                        MISSING_ELSE
254                             end else begin
255        1/1                    state_d = IdleSt;
           Tests:       T36 T94 T92 
256        1/1                    error_d = AccessError; // Signal this error, but do not go into terminal error state.
           Tests:       T36 T94 T92 
257        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T36 T94 T92 
258        1/1                    tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
           Tests:       T36 T94 T92 
259                             end
260                           end
261                           ///////////////////////////////////////////////////////////////////
262                           // Wait for OTP response and release the TL-UL response. In
263                           // case an OTP transaction fails, latch the OTP error code,
264                           // signal a TL-Ul bus error and jump to a terminal error state.
265                           ReadWaitSt: begin
266        1/1                  init_done_o = 1'b1;
           Tests:       T2 T3 T4 
267        1/1                  if (otp_rvalid_i) begin
           Tests:       T2 T3 T4 
268        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T2 T3 T4 
269        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T2 T3 T4 
270        1/1                      state_d = IdleSt;
           Tests:       T2 T3 T4 
271                                 // At this point the only error that we could have gotten are correctable ECC errors.
272        1/1                      if (otp_err != NoError) begin
           Tests:       T2 T3 T4 
273        1/1                        error_d = MacroEccCorrError;
           Tests:       T93 T100 T104 
274                                 end
                        MISSING_ELSE
275                               end else begin
276        1/1                      state_d = ErrorSt;
           Tests:       T167 T188 T187 
277        1/1                      error_d = otp_err;
           Tests:       T167 T188 T187 
278                                 // This causes the TL-UL adapter to return a bus error.
279        1/1                      tlul_rerror_o = 2'b11;
           Tests:       T167 T188 T187 
280                               end
281                             end
                        MISSING_ELSE
282                           end
283                           ///////////////////////////////////////////////////////////////////
284                           // Terminal Error State. This locks access to the partition.
285                           // Make sure the partition signals an error state if no error
286                           // code has been latched so far.
287                           ErrorSt: begin
288        1/1                  if (error_q == NoError) begin
           Tests:       T2 T4 T11 
289        1/1                    error_d = FsmStateError;
           Tests:       T27 T28 T29 
290                             end
                        MISSING_ELSE
291                     
292                             // Return bus errors if there are pending TL-UL requests.
293        1/1                  if (pending_tlul_error_q) begin
           Tests:       T2 T4 T11 
294        1/1                    tlul_rerror_o = 2'b11;
           Tests:       T4 T12 T102 
295        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T4 T12 T102 
296        1/1                  end else if (tlul_req_i) begin
           Tests:       T2 T4 T11 
297        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T4 T12 T102 
298        1/1                    pending_tlul_error_d = 1'b1;
           Tests:       T4 T12 T102 
299                             end
                        MISSING_ELSE
300                           end
301                           ///////////////////////////////////////////////////////////////////
302                           // We should never get here. If we do (e.g. via a malicious
303                           // glitch), error out immediately.
304                           default: begin
305                             state_d = ErrorSt;
306                             fsm_err_o = 1'b1;
307                           end
308                           ///////////////////////////////////////////////////////////////////
309                         endcase // state_q
310                     
311                         // Unconditionally jump into the terminal error state in case of
312                         // an ECC error or escalation, and lock access to the partition down.
313                         // SEC_CM: PART.FSM.LOCAL_ESC
314        1/1              if (ecc_err) begin
           Tests:       T1 T2 T3 
315        1/1                state_d = ErrorSt;
           Tests:       T173 T189 T183 
316        1/1                if (state_q != ErrorSt) begin
           Tests:       T173 T189 T183 
317        1/1                  error_d = CheckFailError;
           Tests:       T173 T189 T183 
318                           end
                        MISSING_ELSE
319                         end
                        MISSING_ELSE
320                         // SEC_CM: PART.FSM.GLOBAL_ESC
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                state_d = ErrorSt;
           Tests:       T2 T4 T11 
323        1/1                fsm_err_o = 1'b1;
           Tests:       T2 T4 T11 
324        1/1                if (state_q != ErrorSt) begin
           Tests:       T2 T4 T11 
325        1/1                  error_d = FsmStateError;
           Tests:       T4 T11 T12 
326                           end
                        MISSING_ELSE
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       ///////////////////////////////////
331                       // Signals to/from TL-UL Adapter //
332                       ///////////////////////////////////
333                     
334        1/1            assign tlul_addr_d  = tlul_addr_i;
           Tests:       T1 T2 T3 
335                       // Do not forward data in case of an error.
336        1/1            assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
           Tests:       T1 T2 T3 
337                     
338                       if (Info.offset == 0) begin : gen_zero_offset
339                         assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
340                     
341                       end else begin : gen_nonzero_offset
342        1/1              assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
           Tests:       T1 T2 T3 
343                                                     {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344                       end
345                     
346                       // Note that OTP works on halfword (16bit) addresses, hence need to
347                       // shift the addresses appropriately.
348                       logic [OtpByteAddrWidth-1:0] addr_calc;
349        1/1            assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
           Tests:       T1 T2 T3 
350        1/1            assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
           Tests:       T1 T2 T3 
351                     
352                       if (OtpAddrShift > 0) begin : gen_unused
353                         logic unused_bits;
354        1/1              assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
           Tests:       T1 T2 T3 
355                       end
356                     
357                       // Request 32bit except in case of the digest.
358        1/1            assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
           Tests:       T1 T2 T3 
359                                           OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360                                           OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361                     
362                       ////////////////
363                       // Digest Reg //
364                       ////////////////
365                     
366                       if (Info.sw_digest) begin : gen_ecc_reg
367                         // SEC_CM: PART.DATA_REG.INTEGRITY
368                         otp_ctrl_ecc_reg #(
369                           .Width ( ScrmblBlockWidth ),
370                           .Depth ( 1                )
371                         ) u_otp_ctrl_ecc_reg (
372                           .clk_i,
373                           .rst_ni,
374                           .wren_i    ( digest_reg_en ),
375                           .addr_i    ( '0            ),
376                           .wdata_i   ( otp_rdata_i   ),
377                           .rdata_o   (               ),
378                           .data_o    ( digest_o      ),
379                           .ecc_err_o ( ecc_err       )
380                         );
381                       end else begin : gen_no_ecc_reg
382                         logic unused_digest_reg_en;
383                         logic unused_rdata;
384                         assign unused_digest_reg_en = digest_reg_en;
385                         assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386                         assign digest_o = '0;
387                         assign ecc_err = 1'b0;
388                       end
389                     
390                       ////////////////////////
391                       // DAI Access Control //
392                       ////////////////////////
393                     
394                       mubi8_t init_locked;
395        1/1            assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
396                     
397                       // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398                       // Note that the locks are redundantly encoded values.
399                       part_access_t access_pre;
400                       prim_mubi8_sender #(
401                         .AsyncOn(0)
402                       ) u_prim_mubi8_sender_write_lock_pre (
403                         .clk_i,
404                         .rst_ni,
405                         .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406                         .mubi_o(access_pre.write_lock)
407                       );
408                       prim_mubi8_sender #(
409                         .AsyncOn(0)
410                       ) u_prim_mubi8_sender_read_lock_pre (
411                         .clk_i,
412                         .rst_ni,
413                         .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414                         .mubi_o(access_pre.read_lock)
415                       );
416                     
417                       // SEC_CM: PART.MEM.SW_UNWRITABLE
418                       if (Info.write_lock) begin : gen_digest_write_lock
419                         mubi8_t digest_locked;
420        1/1              assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
421                     
422                         // This prevents the synthesis tool from optimizing the multibit signal.
423                         prim_mubi8_sender #(
424                           .AsyncOn(0)
425                         ) u_prim_mubi8_sender_write_lock (
426                           .clk_i,
427                           .rst_ni,
428                           .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429                           .mubi_o(access_o.write_lock)
430                         );
431                     
432                         `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433                       end else begin : gen_no_digest_write_lock
434                         assign access_o.write_lock = access_pre.write_lock;
435                       end
436                     
437                       // SEC_CM: PART.MEM.SW_UNREADABLE
438                       if (Info.read_lock) begin : gen_digest_read_lock
439                         mubi8_t digest_locked;
440                         assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441                     
442                         // This prevents the synthesis tool from optimizing the multibit signal.
443                         prim_mubi8_sender #(
444                           .AsyncOn(0)
445                         ) u_prim_mubi8_sender_read_lock (
446                           .clk_i,
447                           .rst_ni,
448                           .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449                           .mubi_o(access_o.read_lock)
450                         );
451                     
452                         `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453                       end else begin : gen_no_digest_read_lock
454        1/1              assign access_o.read_lock = access_pre.read_lock;
           Tests:       T1 T2 T3 
455                       end
456                     
457                       ///////////////
458                       // Registers //
459                       ///////////////
460                     
461        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1                   `ifdef SIMULATION                                   
461.2                       prim_sparse_fsm_flop #(                           
461.3                         .StateEnumT(state_e),                            
461.4                         .Width($bits(state_e)),                          
461.5                         .ResetValue($bits(state_e)'(ResetSt)),          
461.6                         .EnableAlertTriggerSVA(1), 
461.7                         .CustomForceName("state_q")          
461.8                       ) u_state_regs (                                        
461.9                         .clk_i   ( clk_i   ),                           
461.10                        .rst_ni  ( rst_ni ),                           
461.11                        .state_i ( state_d     ),                           
461.12                        .state_o (         )                            
461.13                      );                                                
461.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
461.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
461.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
461.17                      end else begin                                    
461.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
461.19                      end                                               
461.20                    end  
461.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
461.22                      else begin                                                                           
461.23                        `ifdef UVM                                                                               
461.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
461.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);                                
461.26                  `else                                                                                    
461.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
461.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
461.29                  `endif                                                              
461.30                      end 
461.31                    `else                                               
461.32                      prim_sparse_fsm_flop #(                           
461.33                        .StateEnumT(state_e),                            
461.34                        .Width($bits(state_e)),                          
461.35                        .ResetValue($bits(state_e)'(ResetSt)),          
461.36                        .EnableAlertTriggerSVA(1)  
461.37                      ) u_state_regs (                                        
461.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
461.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
461.40                        .state_i ( state_d     ),                           
461.41                        .state_o ( state_q     )                            
461.42                      );                                                
461.43                    `endif462                     
463                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
465        1/1                error_q              <= NoError;
           Tests:       T1 T2 T3 
466        1/1                tlul_addr_q          <= '0;
           Tests:       T1 T2 T3 
467        1/1                pending_tlul_error_q <= 1'b0;
           Tests:       T1 T2 T3 
468                         end else begin
469        1/1                error_q              <= error_d;
           Tests:       T1 T2 T3 
470        1/1                pending_tlul_error_q <= pending_tlul_error_d;
           Tests:       T1 T2 T3 
471        1/1                if (tlul_gnt_o) begin
           Tests:       T1 T2 T3 
472        1/1                  tlul_addr_q <= tlul_addr_d;
           Tests:       T2 T3 T4 
473                           end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T33,T48

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T93,T100,T104

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T11
1	Covered	T27,T28,T29

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T173,T189,T183
1	Covered	T173,T189,T183

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T11
1	Covered	T4,T11,T12

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T12,T36
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T36

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T36

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T4,T11
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T4,T11,T12
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Covered	T178,T179,T180
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T2,T131,T132
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T36,T94,T92
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T167,T188,T187
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T109,T110,T111
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T36,T94,T92
CheckFailError	317	Covered	T173,T189,T183
FsmStateError	289	Covered	T4,T11,T12
MacroEccCorrError	221	Covered	T93,T100,T104
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T126,T9,T166
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T36,T94,T92
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T173,T189,T183
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T4,T11,T12
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T103,T224,T225
MacroEccCorrError->NoError	235	Covered	T93,T100,T104
NoError->AccessError	256	Covered	T36,T94,T92
NoError->CheckFailError	317	Covered	T173,T189,T183
NoError->FsmStateError	289	Covered	T4,T11,T12
NoError->MacroEccCorrError	221	Covered	T93,T100,T104

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

336          assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
                                                                          -1-  
                                                                          ==>  
                                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

349          assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

358          assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

395          assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

420            assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T36
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              ///////////////////////////////////////////////////////////////////
188              // State right after reset. Wait here until we get a an
189              // initialization request.
190              ResetSt: begin
191                if (init_req_i) begin
                   -2-  
192                  // If the partition does not have a digest, no initialization is necessary.
193                  if (Info.sw_digest) begin
                     -3-  
194                    state_d = InitSt;
                       ==>
195                  end else begin
196                    state_d = IdleSt;
                       ==> (Unreachable)
197                  end
198                end
                   MISSING_ELSE
                   ==>
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Initialization reads out the digest only in unbuffered
202              // partitions. Wait here until the OTP request has been granted.
203              // And then wait until the OTP word comes back.
204              InitSt: begin
205                otp_req_o = 1'b1;
206                if (otp_gnt_i) begin
                   -4-  
207                  state_d = InitWaitSt;
                     ==>
208                end
                   MISSING_ELSE
                   ==>
209              end
210              ///////////////////////////////////////////////////////////////////
211              // Wait for OTP response and write to digest buffer register. In
212              // case an OTP transaction fails, latch the  OTP error code and
213              // jump to a terminal error state.
214              InitWaitSt: begin
215                if (otp_rvalid_i) begin
                   -5-  
216                  digest_reg_en = 1'b1;
217                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -6-  
218                    state_d = IdleSt;
219                    // At this point the only error that we could have gotten are correctable ECC errors.
220                    if (otp_err != NoError) begin
                       -7-  
221                      error_d = MacroEccCorrError;
                         ==>
222                    end
                       MISSING_ELSE
                       ==>
223                  end else begin
224                    state_d = ErrorSt;
                       ==>
225                    error_d = otp_err;
226                  end
227                end
                   MISSING_ELSE
                   ==>
228              end
229              ///////////////////////////////////////////////////////////////////
230              // Wait for TL-UL requests coming in.
231              // Then latch address and go to readout state.
232              IdleSt: begin
233                init_done_o = 1'b1;
234                if (tlul_req_i) begin
                   -8-  
235                  error_d = NoError; // clear recoverable soft errors.
                     ==>
236                  state_d = ReadSt;
237                  tlul_gnt_o = 1'b1;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              ///////////////////////////////////////////////////////////////////
241              // If the address is out of bounds, or if the partition is
242              // locked, signal back a bus error. Note that such an error does
243              // not cause the partition to go into error state. Otherwise if
244              // these checks pass, an OTP word is requested.
245              ReadSt: begin
246                init_done_o = 1'b1;
247                // Double check the address range.
248                if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
                   -9-  
249                  otp_req_o = 1'b1;
250                  otp_addr_sel = DataAddrSel;
251                  if (otp_gnt_i) begin
                     -10-  
252                    state_d = ReadWaitSt;
                       ==>
253                  end
                     MISSING_ELSE
                     ==>
254                end else begin
255                  state_d = IdleSt;
                     ==>
256                  error_d = AccessError; // Signal this error, but do not go into terminal error state.
257                  tlul_rvalid_o = 1'b1;
258                  tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259                end
260              end
261              ///////////////////////////////////////////////////////////////////
262              // Wait for OTP response and release the TL-UL response. In
263              // case an OTP transaction fails, latch the OTP error code,
264              // signal a TL-Ul bus error and jump to a terminal error state.
265              ReadWaitSt: begin
266                init_done_o = 1'b1;
267                if (otp_rvalid_i) begin
                   -11-  
268                  tlul_rvalid_o = 1'b1;
269                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -12-  
270                    state_d = IdleSt;
271                    // At this point the only error that we could have gotten are correctable ECC errors.
272                    if (otp_err != NoError) begin
                       -13-  
273                      error_d = MacroEccCorrError;
                         ==>
274                    end
                       MISSING_ELSE
                       ==>
275                  end else begin
276                    state_d = ErrorSt;
                       ==>
277                    error_d = otp_err;
278                    // This causes the TL-UL adapter to return a bus error.
279                    tlul_rerror_o = 2'b11;
280                  end
281                end
                   MISSING_ELSE
                   ==>
282              end
283              ///////////////////////////////////////////////////////////////////
284              // Terminal Error State. This locks access to the partition.
285              // Make sure the partition signals an error state if no error
286              // code has been latched so far.
287              ErrorSt: begin
288                if (error_q == NoError) begin
                   -14-  
289                  error_d = FsmStateError;
                     ==>
290                end
                   MISSING_ELSE
                   ==>
291        
292                // Return bus errors if there are pending TL-UL requests.
293                if (pending_tlul_error_q) begin
                   -15-  
294                  tlul_rerror_o = 2'b11;
                     ==>
295                  tlul_rvalid_o = 1'b1;
296                end else if (tlul_req_i) begin
                            -16-  
297                  tlul_gnt_o = 1'b1;
                     ==>
298                  pending_tlul_error_d = 1'b1;
299                end
                   MISSING_ELSE
                   ==>
300              end
301              ///////////////////////////////////////////////////////////////////
302              // We should never get here. If we do (e.g. via a malicious
303              // glitch), error out immediately.
304              default: begin
305                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T103,T33,T48
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T184,T176
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T36,T9,T144
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T36,T94,T92
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T93,T100,T104
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T167,T188,T187
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T28,T29
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T4,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T12,T102
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T12,T102
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T4,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T28,T29

314            if (ecc_err) begin
               -1-  
315              state_d = ErrorSt;
316              if (state_q != ErrorSt) begin
                 -2-  
317                error_d = CheckFailError;
                   ==>
318              end
                 MISSING_ELSE
                 ==>
319            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T173,T189,T183
1	0	Covered	T173,T189,T183
0	-	Covered	T1,T2,T3

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
               -1-  
322              state_d = ErrorSt;
323              fsm_err_o = 1'b1;
324              if (state_q != ErrorSt) begin
                 -2-  
325                error_d = FsmStateError;
                   ==>
326              end
                 MISSING_ELSE
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T11,T12
1	0	Covered	T2,T4,T11
0	-	Covered	T1,T2,T3

461          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

464            if (!rst_ni) begin
               -1-  
465              error_q              <= NoError;
                 ==>
466              tlul_addr_q          <= '0;
467              pending_tlul_error_q <= 1'b0;
468            end else begin
469              error_q              <= error_d;
470              pending_tlul_error_q <= pending_tlul_error_d;
471              if (tlul_gnt_o) begin
                 -2-  
472                tlul_addr_q <= tlul_addr_d;
                   ==>
473              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	100520911	99678943	0	0
DigestKnown_A	100520911	99678943	0	0
DigestOffsetMustBeRepresentable_A	1122	1122	0	0
EccErrorState_A	100520911	8759	0	0
ErrorKnown_A	100520911	99678943	0	0
FsmStateKnown_A	100520911	99678943	0	0
InitDoneKnown_A	100520911	99678943	0	0
InitReadLocksPartition_A	100520911	16632604	0	0
InitWriteLocksPartition_A	100520911	16632604	0	0
OffsetMustBeBlockAligned_A	1122	1122	0	0
OtpAddrKnown_A	100520911	99678943	0	0
OtpCmdKnown_A	100520911	99678943	0	0
OtpErrorState_A	100520911	49	0	0
OtpReqKnown_A	100520911	99678943	0	0
OtpSizeKnown_A	100520911	99678943	0	0
OtpWdataKnown_A	100520911	99678943	0	0
ReadLockPropagation_A	100520911	17127253	0	0
SizeMustBeBlockAligned_A	1122	1122	0	0
TlulGntKnown_A	100520911	99678943	0	0
TlulRdataKnown_A	100520911	99678943	0	0
TlulReadOnReadLock_A	100520911	6327	0	0
TlulRerrorKnown_A	100520911	99678943	0	0
TlulRvalidKnown_A	100520911	99678943	0	0
WriteLockPropagation_A	100520911	2825569	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	100520911	30356544	0	0
u_state_regs_A	100520911	99678943	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1122	1122	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	8759	0	0
T26	197709	0	0	0
T173	10611	2672	0	0
T183	0	2684	0	0
T189	0	3403	0	0
T226	32609	0	0	0
T227	38990	0	0	0
T228	13281	0	0	0
T229	25055	0	0	0
T230	71431	0	0	0
T231	5581	0	0	0
T232	15730	0	0	0
T233	33495	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	16632604	0	0
T1	4694	107	0	0
T2	12395	4571	0	0
T3	13919	251	0	0
T4	14699	6264	0	0
T5	23906	1930	0	0
T6	23760	371	0	0
T10	4132	167	0	0
T11	15255	6142	0	0
T12	24721	16295	0	0
T13	35219	699	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	16632604	0	0
T1	4694	107	0	0
T2	12395	4571	0	0
T3	13919	251	0	0
T4	14699	6264	0	0
T5	23906	1930	0	0
T6	23760	371	0	0
T10	4132	167	0	0
T11	15255	6142	0	0
T12	24721	16295	0	0
T13	35219	699	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1122	1122	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	49	0	0
T2	12395	1	0	0
T3	13919	0	0	0
T4	14699	0	0	0
T5	23906	0	0	0
T6	23760	0	0	0
T10	4132	0	0	0
T11	15255	0	0	0
T12	24721	0	0	0
T13	35219	0	0	0
T129	38435	0	0	0
T167	0	2	0	0
T176	0	1	0	0
T181	0	1	0	0
T184	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	1	0	0
T234	0	1	0	0
T235	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	17127253	0	0
T12	24721	17502	0	0
T13	35219	0	0	0
T17	3538	0	0	0
T18	0	43048	0	0
T36	71599	7468	0	0
T92	19581	7166	0	0
T93	0	11238	0	0
T94	33983	3499	0	0
T96	0	4627	0	0
T97	11787	0	0	0
T99	0	21197	0	0
T100	0	20744	0	0
T102	18611	0	0	0
T125	70975	0	0	0
T126	0	2334	0	0
T129	38435	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1122	1122	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	6327	0	0
T4	14699	3	0	0
T5	23906	0	0	0
T6	23760	0	0	0
T7	0	5	0	0
T10	4132	0	0	0
T11	15255	0	0	0
T12	24721	13	0	0
T13	35219	0	0	0
T36	71599	10	0	0
T92	0	2	0	0
T93	0	5	0	0
T94	33983	2	0	0
T99	0	4	0	0
T102	0	12	0	0
T126	0	4	0	0
T129	38435	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	2825569	0	0
T17	3538	0	0	0
T18	0	18004	0	0
T20	0	22543	0	0
T36	71599	1511	0	0
T92	19581	0	0	0
T93	56317	15798	0	0
T94	33983	0	0	0
T96	0	3443	0	0
T97	11787	0	0	0
T99	132882	6838	0	0
T100	0	7472	0	0
T102	18611	0	0	0
T118	0	9255	0	0
T119	0	9511	0	0
T125	70975	0	0	0
T126	50550	0	0	0
T147	0	4628	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	30356544	0	0
T2	12395	2582	0	0
T3	13919	0	0	0
T4	14699	0	0	0
T5	23906	0	0	0
T6	23760	6149	0	0
T10	4132	0	0	0
T11	15255	0	0	0
T12	24721	0	0	0
T13	35219	0	0	0
T18	0	66681	0	0
T36	0	41552	0	0
T92	0	11167	0	0
T93	0	44074	0	0
T94	0	24650	0	0
T96	0	15821	0	0
T99	0	111123	0	0
T100	0	242682	0	0
T129	38435	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

137                       // Output partition error state.
138        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
139                     
140                       // This partition cannot do any write accesses, hence we tie this
141                       // constantly off.
142                       assign otp_wdata_o = '0;
143                       // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144                       // calculations and checks. To be on the safe side, the partition filters error responses at this
145                       // point and does not report any integrity errors if integrity is disabled.
146                       otp_err_e otp_err;
147                       if (Info.integrity) begin : gen_integrity
148                         assign otp_cmd_o = prim_otp_pkg::Read;
149        1/1              assign otp_err = otp_err_e'(otp_err_i);
           Tests:       T1 T2 T3 
150                       end else begin : gen_no_integrity
151                         assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152                         always_comb begin
153                           if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
154                             otp_err = NoError;
155                           end else begin
156                             otp_err = otp_err_e'(otp_err_i);
157                           end
158                         end
159                       end
160                     
161                       `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162                       always_comb begin : p_fsm
163                         // Default assignments
164        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
165                     
166                         // Response to init request
167        1/1              init_done_o = 1'b0;
           Tests:       T1 T2 T3 
168                     
169                         // OTP signals
170        1/1              otp_req_o   = 1'b0;
           Tests:       T1 T2 T3 
171        1/1              otp_addr_sel = DigestAddrSel;
           Tests:       T1 T2 T3 
172                     
173                         // TL-UL signals
174        1/1              tlul_gnt_o      = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              tlul_rvalid_o   = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              tlul_rerror_o   = '0;
           Tests:       T1 T2 T3 
177                     
178                         // Enable for buffered digest register
179        1/1              digest_reg_en = 1'b0;
           Tests:       T1 T2 T3 
180                     
181                         // Error Register
182        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
183        1/1              pending_tlul_error_d = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           ///////////////////////////////////////////////////////////////////
188                           // State right after reset. Wait here until we get a an
189                           // initialization request.
190                           ResetSt: begin
191        1/1                  if (init_req_i) begin
           Tests:       T1 T2 T3 
192                               // If the partition does not have a digest, no initialization is necessary.
193        1/1                    if (Info.sw_digest) begin
           Tests:       T1 T2 T3 
194        1/1                      state_d = InitSt;
           Tests:       T1 T2 T3 
195                               end else begin
196        unreachable              state_d = IdleSt;
197                               end
198                             end
                        MISSING_ELSE
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Initialization reads out the digest only in unbuffered
202                           // partitions. Wait here until the OTP request has been granted.
203                           // And then wait until the OTP word comes back.
204                           InitSt: begin
205        1/1                  otp_req_o = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  if (otp_gnt_i) begin
           Tests:       T1 T2 T3 
207        1/1                    state_d = InitWaitSt;
           Tests:       T1 T2 T3 
208                             end
                        MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // Wait for OTP response and write to digest buffer register. In
212                           // case an OTP transaction fails, latch the  OTP error code and
213                           // jump to a terminal error state.
214                           InitWaitSt: begin
215        1/1                  if (otp_rvalid_i) begin
           Tests:       T1 T2 T3 
216        1/1                    digest_reg_en = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T1 T2 T3 
218        1/1                      state_d = IdleSt;
           Tests:       T1 T2 T3 
219                                 // At this point the only error that we could have gotten are correctable ECC errors.
220        1/1                      if (otp_err != NoError) begin
           Tests:       T1 T2 T3 
221        1/1                        error_d = MacroEccCorrError;
           Tests:       T47 T33 T45 
222                                 end
                        MISSING_ELSE
223                               end else begin
224        1/1                      state_d = ErrorSt;
           Tests:       T103 T177 T190 
225        1/1                      error_d = otp_err;
           Tests:       T103 T177 T190 
226                               end
227                             end
                        MISSING_ELSE
228                           end
229                           ///////////////////////////////////////////////////////////////////
230                           // Wait for TL-UL requests coming in.
231                           // Then latch address and go to readout state.
232                           IdleSt: begin
233        1/1                  init_done_o = 1'b1;
           Tests:       T1 T2 T3 
234        1/1                  if (tlul_req_i) begin
           Tests:       T1 T2 T3 
235        1/1                    error_d = NoError; // clear recoverable soft errors.
           Tests:       T2 T5 T6 
236        1/1                    state_d = ReadSt;
           Tests:       T2 T5 T6 
237        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T2 T5 T6 
238                             end
                        MISSING_ELSE
239                           end
240                           ///////////////////////////////////////////////////////////////////
241                           // If the address is out of bounds, or if the partition is
242                           // locked, signal back a bus error. Note that such an error does
243                           // not cause the partition to go into error state. Otherwise if
244                           // these checks pass, an OTP word is requested.
245                           ReadSt: begin
246        1/1                  init_done_o = 1'b1;
           Tests:       T2 T5 T6 
247                             // Double check the address range.
248        1/1                  if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
           Tests:       T2 T5 T6 
249        1/1                    otp_req_o = 1'b1;
           Tests:       T2 T5 T6 
250        1/1                    otp_addr_sel = DataAddrSel;
           Tests:       T2 T5 T6 
251        1/1                    if (otp_gnt_i) begin
           Tests:       T2 T5 T6 
252        1/1                      state_d = ReadWaitSt;
           Tests:       T2 T5 T6 
253                               end
                        MISSING_ELSE
254                             end else begin
255        1/1                    state_d = IdleSt;
           Tests:       T12 T36 T94 
256        1/1                    error_d = AccessError; // Signal this error, but do not go into terminal error state.
           Tests:       T12 T36 T94 
257        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T12 T36 T94 
258        1/1                    tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
           Tests:       T12 T36 T94 
259                             end
260                           end
261                           ///////////////////////////////////////////////////////////////////
262                           // Wait for OTP response and release the TL-UL response. In
263                           // case an OTP transaction fails, latch the OTP error code,
264                           // signal a TL-Ul bus error and jump to a terminal error state.
265                           ReadWaitSt: begin
266        1/1                  init_done_o = 1'b1;
           Tests:       T2 T5 T6 
267        1/1                  if (otp_rvalid_i) begin
           Tests:       T2 T5 T6 
268        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T2 T5 T6 
269        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T2 T5 T6 
270        1/1                      state_d = IdleSt;
           Tests:       T2 T5 T6 
271                                 // At this point the only error that we could have gotten are correctable ECC errors.
272        1/1                      if (otp_err != NoError) begin
           Tests:       T2 T5 T6 
273        1/1                        error_d = MacroEccCorrError;
           Tests:       T93 T100 T128 
274                                 end
                        MISSING_ELSE
275                               end else begin
276        1/1                      state_d = ErrorSt;
           Tests:       T126 T147 T172 
277        1/1                      error_d = otp_err;
           Tests:       T126 T147 T172 
278                                 // This causes the TL-UL adapter to return a bus error.
279        1/1                      tlul_rerror_o = 2'b11;
           Tests:       T126 T147 T172 
280                               end
281                             end
                        MISSING_ELSE
282                           end
283                           ///////////////////////////////////////////////////////////////////
284                           // Terminal Error State. This locks access to the partition.
285                           // Make sure the partition signals an error state if no error
286                           // code has been latched so far.
287                           ErrorSt: begin
288        1/1                  if (error_q == NoError) begin
           Tests:       T2 T4 T11 
289        1/1                    error_d = FsmStateError;
           Tests:       T27 T28 T29 
290                             end
                        MISSING_ELSE
291                     
292                             // Return bus errors if there are pending TL-UL requests.
293        1/1                  if (pending_tlul_error_q) begin
           Tests:       T2 T4 T11 
294        1/1                    tlul_rerror_o = 2'b11;
           Tests:       T4 T12 T102 
295        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T4 T12 T102 
296        1/1                  end else if (tlul_req_i) begin
           Tests:       T2 T4 T11 
297        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T4 T12 T102 
298        1/1                    pending_tlul_error_d = 1'b1;
           Tests:       T4 T12 T102 
299                             end
                        MISSING_ELSE
300                           end
301                           ///////////////////////////////////////////////////////////////////
302                           // We should never get here. If we do (e.g. via a malicious
303                           // glitch), error out immediately.
304                           default: begin
305                             state_d = ErrorSt;
306                             fsm_err_o = 1'b1;
307                           end
308                           ///////////////////////////////////////////////////////////////////
309                         endcase // state_q
310                     
311                         // Unconditionally jump into the terminal error state in case of
312                         // an ECC error or escalation, and lock access to the partition down.
313                         // SEC_CM: PART.FSM.LOCAL_ESC
314        1/1              if (ecc_err) begin
           Tests:       T1 T2 T3 
315        1/1                state_d = ErrorSt;
           Tests:       T109 T110 T189 
316        1/1                if (state_q != ErrorSt) begin
           Tests:       T109 T110 T189 
317        1/1                  error_d = CheckFailError;
           Tests:       T109 T110 T189 
318                           end
                        MISSING_ELSE
319                         end
                        MISSING_ELSE
320                         // SEC_CM: PART.FSM.GLOBAL_ESC
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                state_d = ErrorSt;
           Tests:       T2 T4 T11 
323        1/1                fsm_err_o = 1'b1;
           Tests:       T2 T4 T11 
324        1/1                if (state_q != ErrorSt) begin
           Tests:       T2 T4 T11 
325        1/1                  error_d = FsmStateError;
           Tests:       T2 T4 T11 
326                           end
                        MISSING_ELSE
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       ///////////////////////////////////
331                       // Signals to/from TL-UL Adapter //
332                       ///////////////////////////////////
333                     
334        1/1            assign tlul_addr_d  = tlul_addr_i;
           Tests:       T1 T2 T3 
335                       // Do not forward data in case of an error.
336        1/1            assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
           Tests:       T1 T2 T3 
337                     
338                       if (Info.offset == 0) begin : gen_zero_offset
339                         assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
340                     
341                       end else begin : gen_nonzero_offset
342        1/1              assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
           Tests:       T1 T2 T3 
343                                                     {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344                       end
345                     
346                       // Note that OTP works on halfword (16bit) addresses, hence need to
347                       // shift the addresses appropriately.
348                       logic [OtpByteAddrWidth-1:0] addr_calc;
349        1/1            assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
           Tests:       T1 T2 T3 
350        1/1            assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
           Tests:       T1 T2 T3 
351                     
352                       if (OtpAddrShift > 0) begin : gen_unused
353                         logic unused_bits;
354        1/1              assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
           Tests:       T1 T2 T3 
355                       end
356                     
357                       // Request 32bit except in case of the digest.
358        1/1            assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
           Tests:       T1 T2 T3 
359                                           OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360                                           OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361                     
362                       ////////////////
363                       // Digest Reg //
364                       ////////////////
365                     
366                       if (Info.sw_digest) begin : gen_ecc_reg
367                         // SEC_CM: PART.DATA_REG.INTEGRITY
368                         otp_ctrl_ecc_reg #(
369                           .Width ( ScrmblBlockWidth ),
370                           .Depth ( 1                )
371                         ) u_otp_ctrl_ecc_reg (
372                           .clk_i,
373                           .rst_ni,
374                           .wren_i    ( digest_reg_en ),
375                           .addr_i    ( '0            ),
376                           .wdata_i   ( otp_rdata_i   ),
377                           .rdata_o   (               ),
378                           .data_o    ( digest_o      ),
379                           .ecc_err_o ( ecc_err       )
380                         );
381                       end else begin : gen_no_ecc_reg
382                         logic unused_digest_reg_en;
383                         logic unused_rdata;
384                         assign unused_digest_reg_en = digest_reg_en;
385                         assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386                         assign digest_o = '0;
387                         assign ecc_err = 1'b0;
388                       end
389                     
390                       ////////////////////////
391                       // DAI Access Control //
392                       ////////////////////////
393                     
394                       mubi8_t init_locked;
395        1/1            assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
396                     
397                       // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398                       // Note that the locks are redundantly encoded values.
399                       part_access_t access_pre;
400                       prim_mubi8_sender #(
401                         .AsyncOn(0)
402                       ) u_prim_mubi8_sender_write_lock_pre (
403                         .clk_i,
404                         .rst_ni,
405                         .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406                         .mubi_o(access_pre.write_lock)
407                       );
408                       prim_mubi8_sender #(
409                         .AsyncOn(0)
410                       ) u_prim_mubi8_sender_read_lock_pre (
411                         .clk_i,
412                         .rst_ni,
413                         .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414                         .mubi_o(access_pre.read_lock)
415                       );
416                     
417                       // SEC_CM: PART.MEM.SW_UNWRITABLE
418                       if (Info.write_lock) begin : gen_digest_write_lock
419                         mubi8_t digest_locked;
420        1/1              assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
421                     
422                         // This prevents the synthesis tool from optimizing the multibit signal.
423                         prim_mubi8_sender #(
424                           .AsyncOn(0)
425                         ) u_prim_mubi8_sender_write_lock (
426                           .clk_i,
427                           .rst_ni,
428                           .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429                           .mubi_o(access_o.write_lock)
430                         );
431                     
432                         `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433                       end else begin : gen_no_digest_write_lock
434                         assign access_o.write_lock = access_pre.write_lock;
435                       end
436                     
437                       // SEC_CM: PART.MEM.SW_UNREADABLE
438                       if (Info.read_lock) begin : gen_digest_read_lock
439                         mubi8_t digest_locked;
440                         assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441                     
442                         // This prevents the synthesis tool from optimizing the multibit signal.
443                         prim_mubi8_sender #(
444                           .AsyncOn(0)
445                         ) u_prim_mubi8_sender_read_lock (
446                           .clk_i,
447                           .rst_ni,
448                           .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449                           .mubi_o(access_o.read_lock)
450                         );
451                     
452                         `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453                       end else begin : gen_no_digest_read_lock
454        1/1              assign access_o.read_lock = access_pre.read_lock;
           Tests:       T1 T2 T3 
455                       end
456                     
457                       ///////////////
458                       // Registers //
459                       ///////////////
460                     
461        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1                   `ifdef SIMULATION                                   
461.2                       prim_sparse_fsm_flop #(                           
461.3                         .StateEnumT(state_e),                            
461.4                         .Width($bits(state_e)),                          
461.5                         .ResetValue($bits(state_e)'(ResetSt)),          
461.6                         .EnableAlertTriggerSVA(1), 
461.7                         .CustomForceName("state_q")          
461.8                       ) u_state_regs (                                        
461.9                         .clk_i   ( clk_i   ),                           
461.10                        .rst_ni  ( rst_ni ),                           
461.11                        .state_i ( state_d     ),                           
461.12                        .state_o (         )                            
461.13                      );                                                
461.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
461.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
461.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
461.17                      end else begin                                    
461.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
461.19                      end                                               
461.20                    end  
461.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
461.22                      else begin                                                                           
461.23                        `ifdef UVM                                                                               
461.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
461.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);                                
461.26                  `else                                                                                    
461.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
461.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
461.29                  `endif                                                              
461.30                      end 
461.31                    `else                                               
461.32                      prim_sparse_fsm_flop #(                           
461.33                        .StateEnumT(state_e),                            
461.34                        .Width($bits(state_e)),                          
461.35                        .ResetValue($bits(state_e)'(ResetSt)),          
461.36                        .EnableAlertTriggerSVA(1)  
461.37                      ) u_state_regs (                                        
461.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
461.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
461.40                        .state_i ( state_d     ),                           
461.41                        .state_o ( state_q     )                            
461.42                      );                                                
461.43                    `endif462                     
463                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
465        1/1                error_q              <= NoError;
           Tests:       T1 T2 T3 
466        1/1                tlul_addr_q          <= '0;
           Tests:       T1 T2 T3 
467        1/1                pending_tlul_error_q <= 1'b0;
           Tests:       T1 T2 T3 
468                         end else begin
469        1/1                error_q              <= error_d;
           Tests:       T1 T2 T3 
470        1/1                pending_tlul_error_q <= pending_tlul_error_d;
           Tests:       T1 T2 T3 
471        1/1                if (tlul_gnt_o) begin
           Tests:       T1 T2 T3 
472        1/1                  tlul_addr_q <= tlul_addr_d;
           Tests:       T2 T4 T5 
473                           end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T47,T33,T45

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T93,T100,T128

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T11
1	Covered	T27,T28,T29

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T109,T110,T189
1	Covered	T109,T110,T189

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T11
1	Covered	T2,T4,T11

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T12,T36
1	1	Covered	T2,T5,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T4,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T99,T18,T96

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T99,T18,T96

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T4,T11
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T5,T6
ReadWaitSt	252	Covered	T2,T5,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T4,T11,T12
IdleSt->ReadSt	236	Covered	T2,T5,T6
InitSt->ErrorSt	315	Covered	T131,T132,T175
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T2,T103,T184
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T12,T36,T94
ReadSt->ReadWaitSt	252	Covered	T2,T5,T6
ReadWaitSt->ErrorSt	276	Covered	T126,T147,T172
ReadWaitSt->IdleSt	270	Covered	T2,T5,T6
ResetSt->ErrorSt	315	Covered	T109,T110,T111
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T12,T36,T94
CheckFailError	317	Covered	T109,T110,T189
FsmStateError	289	Covered	T2,T4,T11
MacroEccCorrError	221	Covered	T93,T100,T128
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T12,T9,T223
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T12,T36,T94
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T109,T110,T189
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T4,T11
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T172,T185,T47
MacroEccCorrError->NoError	235	Covered	T93,T100,T128
NoError->AccessError	256	Covered	T12,T36,T94
NoError->CheckFailError	317	Covered	T109,T110,T189
NoError->FsmStateError	289	Covered	T2,T4,T11
NoError->MacroEccCorrError	221	Covered	T93,T100,T128

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

336          assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
                                                                          -1-  
                                                                          ==>  
                                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

349          assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

358          assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

395          assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

420            assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T99,T18,T96
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              ///////////////////////////////////////////////////////////////////
188              // State right after reset. Wait here until we get a an
189              // initialization request.
190              ResetSt: begin
191                if (init_req_i) begin
                   -2-  
192                  // If the partition does not have a digest, no initialization is necessary.
193                  if (Info.sw_digest) begin
                     -3-  
194                    state_d = InitSt;
                       ==>
195                  end else begin
196                    state_d = IdleSt;
                       ==> (Unreachable)
197                  end
198                end
                   MISSING_ELSE
                   ==>
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Initialization reads out the digest only in unbuffered
202              // partitions. Wait here until the OTP request has been granted.
203              // And then wait until the OTP word comes back.
204              InitSt: begin
205                otp_req_o = 1'b1;
206                if (otp_gnt_i) begin
                   -4-  
207                  state_d = InitWaitSt;
                     ==>
208                end
                   MISSING_ELSE
                   ==>
209              end
210              ///////////////////////////////////////////////////////////////////
211              // Wait for OTP response and write to digest buffer register. In
212              // case an OTP transaction fails, latch the  OTP error code and
213              // jump to a terminal error state.
214              InitWaitSt: begin
215                if (otp_rvalid_i) begin
                   -5-  
216                  digest_reg_en = 1'b1;
217                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -6-  
218                    state_d = IdleSt;
219                    // At this point the only error that we could have gotten are correctable ECC errors.
220                    if (otp_err != NoError) begin
                       -7-  
221                      error_d = MacroEccCorrError;
                         ==>
222                    end
                       MISSING_ELSE
                       ==>
223                  end else begin
224                    state_d = ErrorSt;
                       ==>
225                    error_d = otp_err;
226                  end
227                end
                   MISSING_ELSE
                   ==>
228              end
229              ///////////////////////////////////////////////////////////////////
230              // Wait for TL-UL requests coming in.
231              // Then latch address and go to readout state.
232              IdleSt: begin
233                init_done_o = 1'b1;
234                if (tlul_req_i) begin
                   -8-  
235                  error_d = NoError; // clear recoverable soft errors.
                     ==>
236                  state_d = ReadSt;
237                  tlul_gnt_o = 1'b1;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              ///////////////////////////////////////////////////////////////////
241              // If the address is out of bounds, or if the partition is
242              // locked, signal back a bus error. Note that such an error does
243              // not cause the partition to go into error state. Otherwise if
244              // these checks pass, an OTP word is requested.
245              ReadSt: begin
246                init_done_o = 1'b1;
247                // Double check the address range.
248                if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
                   -9-  
249                  otp_req_o = 1'b1;
250                  otp_addr_sel = DataAddrSel;
251                  if (otp_gnt_i) begin
                     -10-  
252                    state_d = ReadWaitSt;
                       ==>
253                  end
                     MISSING_ELSE
                     ==>
254                end else begin
255                  state_d = IdleSt;
                     ==>
256                  error_d = AccessError; // Signal this error, but do not go into terminal error state.
257                  tlul_rvalid_o = 1'b1;
258                  tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259                end
260              end
261              ///////////////////////////////////////////////////////////////////
262              // Wait for OTP response and release the TL-UL response. In
263              // case an OTP transaction fails, latch the OTP error code,
264              // signal a TL-Ul bus error and jump to a terminal error state.
265              ReadWaitSt: begin
266                init_done_o = 1'b1;
267                if (otp_rvalid_i) begin
                   -11-  
268                  tlul_rvalid_o = 1'b1;
269                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -12-  
270                    state_d = IdleSt;
271                    // At this point the only error that we could have gotten are correctable ECC errors.
272                    if (otp_err != NoError) begin
                       -13-  
273                      error_d = MacroEccCorrError;
                         ==>
274                    end
                       MISSING_ELSE
                       ==>
275                  end else begin
276                    state_d = ErrorSt;
                       ==>
277                    error_d = otp_err;
278                    // This causes the TL-UL adapter to return a bus error.
279                    tlul_rerror_o = 2'b11;
280                  end
281                end
                   MISSING_ELSE
                   ==>
282              end
283              ///////////////////////////////////////////////////////////////////
284              // Terminal Error State. This locks access to the partition.
285              // Make sure the partition signals an error state if no error
286              // code has been latched so far.
287              ErrorSt: begin
288                if (error_q == NoError) begin
                   -14-  
289                  error_d = FsmStateError;
                     ==>
290                end
                   MISSING_ELSE
                   ==>
291        
292                // Return bus errors if there are pending TL-UL requests.
293                if (pending_tlul_error_q) begin
                   -15-  
294                  tlul_rerror_o = 2'b11;
                     ==>
295                  tlul_rvalid_o = 1'b1;
296                end else if (tlul_req_i) begin
                            -16-  
297                  tlul_gnt_o = 1'b1;
                     ==>
298                  pending_tlul_error_d = 1'b1;
299                end
                   MISSING_ELSE
                   ==>
300              end
301              ///////////////////////////////////////////////////////////////////
302              // We should never get here. If we do (e.g. via a malicious
303              // glitch), error out immediately.
304              default: begin
305                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T47,T33,T45
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T103,T177,T190
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T5,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T36,T9,T144
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T12,T36,T94
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T93,T100,T128
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T5,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T126,T147,T172
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T28,T29
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T4,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T12,T102
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T12,T102
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T4,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T28,T29

314            if (ecc_err) begin
               -1-  
315              state_d = ErrorSt;
316              if (state_q != ErrorSt) begin
                 -2-  
317                error_d = CheckFailError;
                   ==>
318              end
                 MISSING_ELSE
                 ==>
319            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T109,T110,T189
1	0	Covered	T109,T110,T189
0	-	Covered	T1,T2,T3

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
               -1-  
322              state_d = ErrorSt;
323              fsm_err_o = 1'b1;
324              if (state_q != ErrorSt) begin
                 -2-  
325                error_d = FsmStateError;
                   ==>
326              end
                 MISSING_ELSE
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T4,T11
1	0	Covered	T2,T4,T11
0	-	Covered	T1,T2,T3

461          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

464            if (!rst_ni) begin
               -1-  
465              error_q              <= NoError;
                 ==>
466              tlul_addr_q          <= '0;
467              pending_tlul_error_q <= 1'b0;
468            end else begin
469              error_q              <= error_d;
470              pending_tlul_error_q <= pending_tlul_error_d;
471              if (tlul_gnt_o) begin
                 -2-  
472                tlul_addr_q <= tlul_addr_d;
                   ==>
473              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	100520911	99678943	0	0
DigestKnown_A	100520911	99678943	0	0
DigestOffsetMustBeRepresentable_A	1122	1122	0	0
EccErrorState_A	100520911	15884	0	0
ErrorKnown_A	100520911	99678943	0	0
FsmStateKnown_A	100520911	99678943	0	0
InitDoneKnown_A	100520911	99678943	0	0
InitReadLocksPartition_A	100520911	16805924	0	0
InitWriteLocksPartition_A	100520911	16805924	0	0
OffsetMustBeBlockAligned_A	1122	1122	0	0
OtpAddrKnown_A	100520911	99678943	0	0
OtpCmdKnown_A	100520911	99678943	0	0
OtpErrorState_A	100520911	43	0	0
OtpReqKnown_A	100520911	99678943	0	0
OtpSizeKnown_A	100520911	99678943	0	0
OtpWdataKnown_A	100520911	99678943	0	0
ReadLockPropagation_A	100520911	17596761	0	0
SizeMustBeBlockAligned_A	1122	1122	0	0
TlulGntKnown_A	100520911	99678943	0	0
TlulRdataKnown_A	100520911	99678943	0	0
TlulReadOnReadLock_A	100520911	5896	0	0
TlulRerrorKnown_A	100520911	99678943	0	0
TlulRvalidKnown_A	100520911	99678943	0	0
WriteLockPropagation_A	100520911	1706533	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	100520911	17564480	0	0
u_state_regs_A	100520911	99678943	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1122	1122	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	15884	0	0
T109	17416	3594	0	0
T110	0	2097	0	0
T122	60085	0	0	0
T141	78838	0	0	0
T144	65851	0	0	0
T146	47956	0	0	0
T165	9072	0	0	0
T170	12160	0	0	0
T174	0	3948	0	0
T189	0	3403	0	0
T191	0	2842	0	0
T192	20259	0	0	0
T193	34170	0	0	0
T194	28156	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	16805924	0	0
T1	4694	124	0	0
T2	12395	4588	0	0
T3	13919	285	0	0
T4	14699	6315	0	0
T5	23906	2015	0	0
T6	23760	422	0	0
T10	4132	184	0	0
T11	15255	6193	0	0
T12	24721	16346	0	0
T13	35219	784	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	16805924	0	0
T1	4694	124	0	0
T2	12395	4588	0	0
T3	13919	285	0	0
T4	14699	6315	0	0
T5	23906	2015	0	0
T6	23760	422	0	0
T10	4132	184	0	0
T11	15255	6193	0	0
T12	24721	16346	0	0
T13	35219	784	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1122	1122	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	43	0	0
T7	42380	0	0	0
T18	107019	0	0	0
T85	13582	0	0	0
T93	56317	0	0	0
T96	32312	0	0	0
T99	132882	0	0	0
T103	0	1	0	0
T115	17776	0	0	0
T116	12640	0	0	0
T117	15846	0	0	0
T126	50550	1	0	0
T147	0	1	0	0
T172	0	1	0	0
T177	0	1	0	0
T190	0	1	0	0
T224	0	1	0	0
T225	0	1	0	0
T236	0	1	0	0
T237	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	17596761	0	0
T6	23760	4551	0	0
T7	0	31681	0	0
T11	15255	0	0	0
T12	24721	17500	0	0
T13	35219	0	0	0
T36	71599	9431	0	0
T92	0	7162	0	0
T93	0	12838	0	0
T94	33983	2088	0	0
T97	11787	0	0	0
T99	0	16440	0	0
T102	18611	13200	0	0
T125	70975	0	0	0
T126	0	2344	0	0
T129	38435	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1122	1122	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	5896	0	0
T4	14699	1	0	0
T5	23906	0	0	0
T6	23760	0	0	0
T7	0	5	0	0
T10	4132	0	0	0
T11	15255	0	0	0
T12	24721	17	0	0
T13	35219	0	0	0
T36	71599	7	0	0
T92	0	4	0	0
T93	0	5	0	0
T94	33983	2	0	0
T99	0	1	0	0
T102	0	14	0	0
T126	0	2	0	0
T129	38435	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	1706533	0	0
T7	42380	0	0	0
T18	107019	0	0	0
T20	0	24815	0	0
T85	13582	0	0	0
T96	32312	3443	0	0
T99	132882	25991	0	0
T100	255596	36594	0	0
T104	77386	0	0	0
T115	17776	0	0	0
T116	12640	0	0	0
T117	15846	0	0	0
T120	0	11616	0	0
T121	0	20287	0	0
T135	0	4194	0	0
T142	0	2756	0	0
T238	0	12816	0	0
T239	0	14121	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	17564480	0	0
T7	42380	0	0	0
T18	107019	89936	0	0
T20	0	145431	0	0
T85	13582	0	0	0
T96	32312	23406	0	0
T99	132882	110936	0	0
T100	255596	242512	0	0
T104	77386	0	0	0
T115	17776	0	0	0
T116	12640	0	0	0
T117	15846	0	0	0
T120	0	106546	0	0
T121	0	128891	0	0
T194	0	4462	0	0
T218	0	27396	0	0
T219	0	10292	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100520911	99678943	0	0
T1	4694	4634	0	0
T2	12395	12162	0	0
T3	13919	13658	0	0
T4	14699	14449	0	0
T5	23906	23532	0	0
T6	23760	23518	0	0
T10	4132	4057	0	0
T11	15255	14984	0	0
T12	24721	24489	0	0
T13	35219	34664	0	0