| T1066 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.3440192683 |
|
|
Sep 01 07:03:32 PM UTC 24 |
Sep 01 07:03:40 PM UTC 24 |
288315051 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.2215502489 |
|
|
Sep 01 07:03:32 PM UTC 24 |
Sep 01 07:03:40 PM UTC 24 |
1540056998 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.2117139669 |
|
|
Sep 01 07:03:33 PM UTC 24 |
Sep 01 07:03:41 PM UTC 24 |
1803505486 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.154325816 |
|
|
Sep 01 07:03:33 PM UTC 24 |
Sep 01 07:03:41 PM UTC 24 |
464177676 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.257024705 |
|
|
Sep 01 07:03:28 PM UTC 24 |
Sep 01 07:03:41 PM UTC 24 |
904475006 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.2264153691 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:41 PM UTC 24 |
313957577 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.1701898867 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:41 PM UTC 24 |
114940737 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.46237942 |
|
|
Sep 01 07:03:28 PM UTC 24 |
Sep 01 07:03:42 PM UTC 24 |
2642475453 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.4284018537 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:42 PM UTC 24 |
142986915 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.3098506011 |
|
|
Sep 01 07:03:40 PM UTC 24 |
Sep 01 07:03:45 PM UTC 24 |
147974984 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.3222239556 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:42 PM UTC 24 |
199414600 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.1473205583 |
|
|
Sep 01 07:03:40 PM UTC 24 |
Sep 01 07:03:45 PM UTC 24 |
156161509 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.2006091533 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:42 PM UTC 24 |
646007145 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.2741688183 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:42 PM UTC 24 |
284250686 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.61751087 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:43 PM UTC 24 |
123801594 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.3805941087 |
|
|
Sep 01 07:03:32 PM UTC 24 |
Sep 01 07:03:43 PM UTC 24 |
4347458461 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.2934075796 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:43 PM UTC 24 |
443633877 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.299230635 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:43 PM UTC 24 |
176319551 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.3723506287 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:43 PM UTC 24 |
683740923 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.1720609194 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:43 PM UTC 24 |
571533643 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.3158280867 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:44 PM UTC 24 |
119325685 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.611174742 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:44 PM UTC 24 |
474753344 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.842480142 |
|
|
Sep 01 07:03:33 PM UTC 24 |
Sep 01 07:03:44 PM UTC 24 |
349402195 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.958310812 |
|
|
Sep 01 07:01:07 PM UTC 24 |
Sep 01 07:03:44 PM UTC 24 |
16697995757 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.1610929843 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:45 PM UTC 24 |
286855571 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.452441065 |
|
|
Sep 01 07:03:40 PM UTC 24 |
Sep 01 07:03:45 PM UTC 24 |
172795458 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.629297648 |
|
|
Sep 01 07:03:37 PM UTC 24 |
Sep 01 07:03:45 PM UTC 24 |
2040116716 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.1160674665 |
|
|
Sep 01 07:03:41 PM UTC 24 |
Sep 01 07:03:45 PM UTC 24 |
171621348 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.2730192369 |
|
|
Sep 01 07:03:23 PM UTC 24 |
Sep 01 07:03:45 PM UTC 24 |
4970311854 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.1616347056 |
|
|
Sep 01 07:03:41 PM UTC 24 |
Sep 01 07:03:45 PM UTC 24 |
131841894 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.2725320774 |
|
|
Sep 01 07:03:41 PM UTC 24 |
Sep 01 07:03:45 PM UTC 24 |
445415224 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.4044104236 |
|
|
Sep 01 07:03:41 PM UTC 24 |
Sep 01 07:03:46 PM UTC 24 |
1372033889 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.484179549 |
|
|
Sep 01 07:03:40 PM UTC 24 |
Sep 01 07:03:46 PM UTC 24 |
152983259 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.3860731986 |
|
|
Sep 01 07:03:40 PM UTC 24 |
Sep 01 07:03:46 PM UTC 24 |
703839527 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.1776369953 |
|
|
Sep 01 07:03:40 PM UTC 24 |
Sep 01 07:03:46 PM UTC 24 |
610345503 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.350988362 |
|
|
Sep 01 07:03:41 PM UTC 24 |
Sep 01 07:03:46 PM UTC 24 |
134807675 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.1383337826 |
|
|
Sep 01 07:03:14 PM UTC 24 |
Sep 01 07:03:47 PM UTC 24 |
11762635310 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.310868165 |
|
|
Sep 01 07:02:07 PM UTC 24 |
Sep 01 07:04:04 PM UTC 24 |
4985396521 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.3212391943 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:04 PM UTC 24 |
514728723 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.1311414702 |
|
|
Sep 01 07:01:06 PM UTC 24 |
Sep 01 07:03:47 PM UTC 24 |
17147973785 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.1850423388 |
|
|
Sep 01 07:03:41 PM UTC 24 |
Sep 01 07:03:48 PM UTC 24 |
655220281 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.3741331454 |
|
|
Sep 01 07:03:22 PM UTC 24 |
Sep 01 07:03:48 PM UTC 24 |
1581822421 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1366362600 |
|
|
Sep 01 07:01:56 PM UTC 24 |
Sep 01 07:03:48 PM UTC 24 |
8262721407 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.4255798842 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:49 PM UTC 24 |
251243859 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.3819261557 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:50 PM UTC 24 |
120472941 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.2454061821 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:50 PM UTC 24 |
163331242 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.2423415441 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:50 PM UTC 24 |
206470318 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.2499038823 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:50 PM UTC 24 |
185193823 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.381359496 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:50 PM UTC 24 |
292526891 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.3245351170 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:50 PM UTC 24 |
430908700 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3423317548 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:50 PM UTC 24 |
143405172 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.1042105902 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:50 PM UTC 24 |
247032262 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.670862857 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:50 PM UTC 24 |
339963283 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.2056268470 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:50 PM UTC 24 |
194845008 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1917254063 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:51 PM UTC 24 |
1463893604 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.82735579 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:51 PM UTC 24 |
123346244 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.2221833767 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:51 PM UTC 24 |
345745151 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.2561698582 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:51 PM UTC 24 |
388216291 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.899138472 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:04 PM UTC 24 |
1927535982 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.4007624114 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:51 PM UTC 24 |
289532821 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.581674867 |
|
|
Sep 01 07:03:14 PM UTC 24 |
Sep 01 07:03:51 PM UTC 24 |
4465277189 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.1032317735 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:51 PM UTC 24 |
384679902 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.905595976 |
|
|
Sep 01 07:03:45 PM UTC 24 |
Sep 01 07:03:51 PM UTC 24 |
177324843 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2913553730 |
|
|
Sep 01 07:01:19 PM UTC 24 |
Sep 01 07:03:51 PM UTC 24 |
15922085158 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.3222692271 |
|
|
Sep 01 07:03:49 PM UTC 24 |
Sep 01 07:03:53 PM UTC 24 |
109033759 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.576214337 |
|
|
Sep 01 07:03:49 PM UTC 24 |
Sep 01 07:03:54 PM UTC 24 |
414160309 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.1810378009 |
|
|
Sep 01 07:03:49 PM UTC 24 |
Sep 01 07:03:54 PM UTC 24 |
189527744 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.1766604412 |
|
|
Sep 01 07:03:49 PM UTC 24 |
Sep 01 07:03:54 PM UTC 24 |
154643248 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.560426676 |
|
|
Sep 01 07:03:49 PM UTC 24 |
Sep 01 07:03:54 PM UTC 24 |
205435150 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.2568700714 |
|
|
Sep 01 07:03:50 PM UTC 24 |
Sep 01 07:03:54 PM UTC 24 |
112895878 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.292121742 |
|
|
Sep 01 07:03:49 PM UTC 24 |
Sep 01 07:03:54 PM UTC 24 |
361798541 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.1639184476 |
|
|
Sep 01 07:03:50 PM UTC 24 |
Sep 01 07:03:55 PM UTC 24 |
177390822 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.842027118 |
|
|
Sep 01 07:03:50 PM UTC 24 |
Sep 01 07:03:55 PM UTC 24 |
281511650 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.2214307940 |
|
|
Sep 01 07:03:49 PM UTC 24 |
Sep 01 07:03:55 PM UTC 24 |
500707337 ps |
| T23 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.1654820868 |
|
|
Sep 01 07:00:57 PM UTC 24 |
Sep 01 07:03:55 PM UTC 24 |
19028209132 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.1431486626 |
|
|
Sep 01 07:03:50 PM UTC 24 |
Sep 01 07:03:55 PM UTC 24 |
420180973 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.3545498092 |
|
|
Sep 01 07:03:50 PM UTC 24 |
Sep 01 07:03:55 PM UTC 24 |
319895302 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.874377430 |
|
|
Sep 01 07:03:50 PM UTC 24 |
Sep 01 07:03:55 PM UTC 24 |
203719911 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.3095008172 |
|
|
Sep 01 07:03:50 PM UTC 24 |
Sep 01 07:03:55 PM UTC 24 |
151353065 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.3363769916 |
|
|
Sep 01 07:03:50 PM UTC 24 |
Sep 01 07:03:55 PM UTC 24 |
117887829 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.4180514544 |
|
|
Sep 01 07:03:50 PM UTC 24 |
Sep 01 07:03:55 PM UTC 24 |
374943373 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.2668779702 |
|
|
Sep 01 07:03:50 PM UTC 24 |
Sep 01 07:03:56 PM UTC 24 |
600392894 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.576305583 |
|
|
Sep 01 07:03:50 PM UTC 24 |
Sep 01 07:03:56 PM UTC 24 |
1652054055 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.3264236861 |
|
|
Sep 01 07:03:49 PM UTC 24 |
Sep 01 07:03:56 PM UTC 24 |
2656690087 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.3409931671 |
|
|
Sep 01 07:03:49 PM UTC 24 |
Sep 01 07:03:56 PM UTC 24 |
2643803355 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.2917434652 |
|
|
Sep 01 07:03:50 PM UTC 24 |
Sep 01 07:03:58 PM UTC 24 |
1651666959 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.569142377 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:01 PM UTC 24 |
283857952 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.2799169035 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:02 PM UTC 24 |
116613281 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.958508440 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:02 PM UTC 24 |
450282667 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.3202423549 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:02 PM UTC 24 |
128886354 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.1594859940 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:02 PM UTC 24 |
233829684 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.4075512804 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:02 PM UTC 24 |
295093396 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.729498815 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:02 PM UTC 24 |
474101149 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.3336911830 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:03 PM UTC 24 |
307341945 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.3707618554 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:03 PM UTC 24 |
138890352 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.1443004511 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:03 PM UTC 24 |
108149997 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.1175313883 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:03 PM UTC 24 |
520929962 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.809609923 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:03 PM UTC 24 |
261142528 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.3741559750 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:03 PM UTC 24 |
111373438 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2410899480 |
|
|
Sep 01 07:01:32 PM UTC 24 |
Sep 01 07:04:03 PM UTC 24 |
13474094066 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.144947926 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:03 PM UTC 24 |
581479591 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.79374351 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:03 PM UTC 24 |
186932314 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.3981175899 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:03 PM UTC 24 |
188657031 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.3078056455 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:03 PM UTC 24 |
350975963 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.572400947 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:04 PM UTC 24 |
1941103131 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.43104768 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:04 PM UTC 24 |
572383367 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.1809626749 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:04 PM UTC 24 |
419788531 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.2816112926 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:04 PM UTC 24 |
2404479640 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.3266333935 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:04 PM UTC 24 |
542664820 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.3875914944 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:04 PM UTC 24 |
2917160449 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.906653538 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:04 PM UTC 24 |
439587177 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.268665106 |
|
|
Sep 01 07:03:57 PM UTC 24 |
Sep 01 07:04:05 PM UTC 24 |
274803785 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.2192035867 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:05 PM UTC 24 |
2285603940 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.1657813206 |
|
|
Sep 01 07:01:02 PM UTC 24 |
Sep 01 07:04:14 PM UTC 24 |
24868482729 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.1277870684 |
|
|
Sep 01 07:02:07 PM UTC 24 |
Sep 01 07:04:22 PM UTC 24 |
13955021537 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.375378134 |
|
|
Sep 01 07:01:39 PM UTC 24 |
Sep 01 07:04:23 PM UTC 24 |
20499720311 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.2631529718 |
|
|
Sep 01 07:01:24 PM UTC 24 |
Sep 01 07:04:28 PM UTC 24 |
99681769125 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.2243427274 |
|
|
Sep 01 06:58:24 PM UTC 24 |
Sep 01 07:04:42 PM UTC 24 |
139919788308 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.2639669357 |
|
|
Sep 01 07:01:53 PM UTC 24 |
Sep 01 07:04:58 PM UTC 24 |
15708462791 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.2545535138 |
|
|
Sep 01 07:01:53 PM UTC 24 |
Sep 01 07:05:09 PM UTC 24 |
8523615035 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.769767811 |
|
|
Sep 01 07:01:19 PM UTC 24 |
Sep 01 07:05:30 PM UTC 24 |
39765227461 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.3586890989 |
|
|
Sep 01 06:53:55 PM UTC 24 |
Sep 01 07:25:42 PM UTC 24 |
150733364233 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.278866625 |
|
|
Sep 01 06:47:05 PM UTC 24 |
Sep 01 06:47:08 PM UTC 24 |
46674434 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.2953542244 |
|
|
Sep 01 06:47:05 PM UTC 24 |
Sep 01 06:47:08 PM UTC 24 |
36261300 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.618215746 |
|
|
Sep 01 06:47:05 PM UTC 24 |
Sep 01 06:47:08 PM UTC 24 |
66337014 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2889572401 |
|
|
Sep 01 06:47:03 PM UTC 24 |
Sep 01 06:47:10 PM UTC 24 |
108442235 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.381231726 |
|
|
Sep 01 06:47:06 PM UTC 24 |
Sep 01 06:47:10 PM UTC 24 |
72778788 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1982819549 |
|
|
Sep 01 06:47:06 PM UTC 24 |
Sep 01 06:47:10 PM UTC 24 |
159419769 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.2584068934 |
|
|
Sep 01 06:47:09 PM UTC 24 |
Sep 01 06:47:12 PM UTC 24 |
37575092 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1148473037 |
|
|
Sep 01 06:47:08 PM UTC 24 |
Sep 01 06:47:14 PM UTC 24 |
60156381 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.448562365 |
|
|
Sep 01 06:47:10 PM UTC 24 |
Sep 01 06:47:14 PM UTC 24 |
131478843 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3430221672 |
|
|
Sep 01 06:47:11 PM UTC 24 |
Sep 01 06:47:15 PM UTC 24 |
36787490 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.541959616 |
|
|
Sep 01 06:47:08 PM UTC 24 |
Sep 01 06:47:15 PM UTC 24 |
1073377961 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2324046051 |
|
|
Sep 01 06:47:12 PM UTC 24 |
Sep 01 06:47:16 PM UTC 24 |
264206504 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.716398168 |
|
|
Sep 01 06:47:08 PM UTC 24 |
Sep 01 06:47:17 PM UTC 24 |
1452334636 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1679635448 |
|
|
Sep 01 06:47:14 PM UTC 24 |
Sep 01 06:47:17 PM UTC 24 |
100925751 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.4208413949 |
|
|
Sep 01 06:47:08 PM UTC 24 |
Sep 01 06:47:19 PM UTC 24 |
123218433 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2869444256 |
|
|
Sep 01 06:47:09 PM UTC 24 |
Sep 01 06:47:20 PM UTC 24 |
636857070 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1002807697 |
|
|
Sep 01 06:47:16 PM UTC 24 |
Sep 01 06:47:21 PM UTC 24 |
72022170 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.4114825229 |
|
|
Sep 01 06:47:15 PM UTC 24 |
Sep 01 06:47:21 PM UTC 24 |
116457287 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1523921133 |
|
|
Sep 01 06:47:16 PM UTC 24 |
Sep 01 06:47:21 PM UTC 24 |
225995470 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.1697095547 |
|
|
Sep 01 06:47:18 PM UTC 24 |
Sep 01 06:47:21 PM UTC 24 |
69620519 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.98608865 |
|
|
Sep 01 06:47:19 PM UTC 24 |
Sep 01 06:47:23 PM UTC 24 |
70168173 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2912162050 |
|
|
Sep 01 06:47:21 PM UTC 24 |
Sep 01 06:47:25 PM UTC 24 |
52312859 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3672398468 |
|
|
Sep 01 06:47:17 PM UTC 24 |
Sep 01 06:47:25 PM UTC 24 |
303029858 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.734148693 |
|
|
Sep 01 06:47:22 PM UTC 24 |
Sep 01 06:47:26 PM UTC 24 |
69573434 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2967171246 |
|
|
Sep 01 06:47:21 PM UTC 24 |
Sep 01 06:47:26 PM UTC 24 |
97943756 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3798891634 |
|
|
Sep 01 06:47:24 PM UTC 24 |
Sep 01 06:47:28 PM UTC 24 |
136427187 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2513331100 |
|
|
Sep 01 06:47:15 PM UTC 24 |
Sep 01 06:47:30 PM UTC 24 |
392022583 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.2256367396 |
|
|
Sep 01 06:47:27 PM UTC 24 |
Sep 01 06:47:30 PM UTC 24 |
50102908 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1416981457 |
|
|
Sep 01 06:47:23 PM UTC 24 |
Sep 01 06:47:32 PM UTC 24 |
1886029146 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2738716077 |
|
|
Sep 01 06:47:29 PM UTC 24 |
Sep 01 06:47:32 PM UTC 24 |
128236843 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3586194912 |
|
|
Sep 01 06:47:26 PM UTC 24 |
Sep 01 06:47:33 PM UTC 24 |
106121256 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3130797590 |
|
|
Sep 01 06:47:26 PM UTC 24 |
Sep 01 06:47:33 PM UTC 24 |
110707447 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3896745788 |
|
|
Sep 01 06:47:32 PM UTC 24 |
Sep 01 06:47:35 PM UTC 24 |
40212241 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1474869734 |
|
|
Sep 01 06:47:22 PM UTC 24 |
Sep 01 06:47:36 PM UTC 24 |
838308630 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2988944000 |
|
|
Sep 01 06:47:32 PM UTC 24 |
Sep 01 06:47:36 PM UTC 24 |
559505451 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2464459220 |
|
|
Sep 01 06:47:32 PM UTC 24 |
Sep 01 06:47:37 PM UTC 24 |
181381748 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3853570799 |
|
|
Sep 01 06:47:52 PM UTC 24 |
Sep 01 06:47:55 PM UTC 24 |
78617257 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3952936901 |
|
|
Sep 01 06:47:05 PM UTC 24 |
Sep 01 06:47:38 PM UTC 24 |
2528797398 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1546233794 |
|
|
Sep 01 06:47:32 PM UTC 24 |
Sep 01 06:47:39 PM UTC 24 |
259949415 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.632557161 |
|
|
Sep 01 06:47:34 PM UTC 24 |
Sep 01 06:47:39 PM UTC 24 |
140394535 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.355643275 |
|
|
Sep 01 06:47:36 PM UTC 24 |
Sep 01 06:47:40 PM UTC 24 |
70943616 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2422908756 |
|
|
Sep 01 06:47:38 PM UTC 24 |
Sep 01 06:47:41 PM UTC 24 |
37836942 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.163011653 |
|
|
Sep 01 06:47:38 PM UTC 24 |
Sep 01 06:47:41 PM UTC 24 |
74024438 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2821147369 |
|
|
Sep 01 06:47:39 PM UTC 24 |
Sep 01 06:47:42 PM UTC 24 |
41712969 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3310910893 |
|
|
Sep 01 06:47:09 PM UTC 24 |
Sep 01 06:47:42 PM UTC 24 |
2842892630 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1498896913 |
|
|
Sep 01 06:47:39 PM UTC 24 |
Sep 01 06:47:43 PM UTC 24 |
125942642 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1803938989 |
|
|
Sep 01 06:47:34 PM UTC 24 |
Sep 01 06:47:45 PM UTC 24 |
304643581 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3477828659 |
|
|
Sep 01 06:47:34 PM UTC 24 |
Sep 01 06:47:45 PM UTC 24 |
1824527943 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.342084936 |
|
|
Sep 01 06:47:42 PM UTC 24 |
Sep 01 06:47:46 PM UTC 24 |
50752168 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1375771501 |
|
|
Sep 01 06:47:43 PM UTC 24 |
Sep 01 06:47:46 PM UTC 24 |
46171638 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.726623003 |
|
|
Sep 01 06:47:40 PM UTC 24 |
Sep 01 06:47:47 PM UTC 24 |
110618440 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3872947173 |
|
|
Sep 01 06:47:42 PM UTC 24 |
Sep 01 06:47:48 PM UTC 24 |
104391762 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3006246778 |
|
|
Sep 01 06:47:44 PM UTC 24 |
Sep 01 06:47:48 PM UTC 24 |
195945252 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3042206528 |
|
|
Sep 01 06:47:42 PM UTC 24 |
Sep 01 06:47:49 PM UTC 24 |
221806649 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.1875989648 |
|
|
Sep 01 06:47:44 PM UTC 24 |
Sep 01 06:47:49 PM UTC 24 |
74653022 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2758432229 |
|
|
Sep 01 06:47:18 PM UTC 24 |
Sep 01 06:47:49 PM UTC 24 |
9722038524 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1719316650 |
|
|
Sep 01 06:47:41 PM UTC 24 |
Sep 01 06:47:50 PM UTC 24 |
2006374980 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.4221541820 |
|
|
Sep 01 06:47:47 PM UTC 24 |
Sep 01 06:47:50 PM UTC 24 |
77573366 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2569713056 |
|
|
Sep 01 06:47:47 PM UTC 24 |
Sep 01 06:47:51 PM UTC 24 |
42023915 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3240258527 |
|
|
Sep 01 06:47:40 PM UTC 24 |
Sep 01 06:47:51 PM UTC 24 |
716970815 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1206276516 |
|
|
Sep 01 06:47:47 PM UTC 24 |
Sep 01 06:47:53 PM UTC 24 |
83912429 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2583920361 |
|
|
Sep 01 06:47:27 PM UTC 24 |
Sep 01 06:47:53 PM UTC 24 |
10364485562 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3082937942 |
|
|
Sep 01 06:47:50 PM UTC 24 |
Sep 01 06:47:53 PM UTC 24 |
47804045 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.3437536276 |
|
|
Sep 01 06:47:50 PM UTC 24 |
Sep 01 06:47:53 PM UTC 24 |
599849856 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.505079730 |
|
|
Sep 01 06:47:46 PM UTC 24 |
Sep 01 06:47:54 PM UTC 24 |
689702521 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.924637787 |
|
|
Sep 01 06:47:35 PM UTC 24 |
Sep 01 06:47:54 PM UTC 24 |
9744628875 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3374689069 |
|
|
Sep 01 06:47:50 PM UTC 24 |
Sep 01 06:47:54 PM UTC 24 |
77927906 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.1926687923 |
|
|
Sep 01 06:47:52 PM UTC 24 |
Sep 01 06:47:55 PM UTC 24 |
138415603 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3592481266 |
|
|
Sep 01 06:47:48 PM UTC 24 |
Sep 01 06:47:56 PM UTC 24 |
107444631 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.464872681 |
|
|
Sep 01 06:47:51 PM UTC 24 |
Sep 01 06:47:56 PM UTC 24 |
1745465033 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2865296312 |
|
|
Sep 01 06:47:42 PM UTC 24 |
Sep 01 06:47:57 PM UTC 24 |
640308731 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2013539365 |
|
|
Sep 01 06:47:48 PM UTC 24 |
Sep 01 06:47:57 PM UTC 24 |
251845971 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.1872525549 |
|
|
Sep 01 06:47:54 PM UTC 24 |
Sep 01 06:47:58 PM UTC 24 |
88085269 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.926939959 |
|
|
Sep 01 06:47:54 PM UTC 24 |
Sep 01 06:47:58 PM UTC 24 |
38431286 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2073782384 |
|
|
Sep 01 06:47:54 PM UTC 24 |
Sep 01 06:47:59 PM UTC 24 |
132407740 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.1112217145 |
|
|
Sep 01 06:47:51 PM UTC 24 |
Sep 01 06:47:59 PM UTC 24 |
378132136 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.3423390412 |
|
|
Sep 01 06:47:58 PM UTC 24 |
Sep 01 06:48:01 PM UTC 24 |
45698105 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2598647329 |
|
|
Sep 01 06:47:58 PM UTC 24 |
Sep 01 06:48:01 PM UTC 24 |
41314185 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3770276238 |
|
|
Sep 01 06:47:56 PM UTC 24 |
Sep 01 06:48:01 PM UTC 24 |
75582102 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3934777807 |
|
|
Sep 01 06:47:55 PM UTC 24 |
Sep 01 06:48:03 PM UTC 24 |
446969340 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.53407117 |
|
|
Sep 01 06:48:00 PM UTC 24 |
Sep 01 06:48:03 PM UTC 24 |
44155462 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3243220248 |
|
|
Sep 01 06:47:59 PM UTC 24 |
Sep 01 06:48:03 PM UTC 24 |
74933346 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.1510085148 |
|
|
Sep 01 06:47:53 PM UTC 24 |
Sep 01 06:48:04 PM UTC 24 |
1794283693 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2742611288 |
|
|
Sep 01 06:47:59 PM UTC 24 |
Sep 01 06:48:05 PM UTC 24 |
188277590 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1823977414 |
|
|
Sep 01 06:47:54 PM UTC 24 |
Sep 01 06:48:05 PM UTC 24 |
250645840 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.436729028 |
|
|
Sep 01 06:47:59 PM UTC 24 |
Sep 01 06:48:05 PM UTC 24 |
128501577 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.8818768 |
|
|
Sep 01 06:48:02 PM UTC 24 |
Sep 01 06:48:06 PM UTC 24 |
73793700 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1612980204 |
|
|
Sep 01 06:48:02 PM UTC 24 |
Sep 01 06:48:07 PM UTC 24 |
105965087 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.961990355 |
|
|
Sep 01 06:48:02 PM UTC 24 |
Sep 01 06:48:07 PM UTC 24 |
281669950 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.2029993849 |
|
|
Sep 01 06:48:04 PM UTC 24 |
Sep 01 06:48:08 PM UTC 24 |
130397895 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2643840134 |
|
|
Sep 01 06:48:04 PM UTC 24 |
Sep 01 06:48:08 PM UTC 24 |
42659228 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3094511419 |
|
|
Sep 01 06:47:48 PM UTC 24 |
Sep 01 06:48:08 PM UTC 24 |
1170984750 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.974969749 |
|
|
Sep 01 06:47:57 PM UTC 24 |
Sep 01 06:48:09 PM UTC 24 |
378142122 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1577098645 |
|
|
Sep 01 06:48:06 PM UTC 24 |
Sep 01 06:48:10 PM UTC 24 |
47968116 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3616206394 |
|
|
Sep 01 06:48:03 PM UTC 24 |
Sep 01 06:48:10 PM UTC 24 |
203366164 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.673886822 |
|
|
Sep 01 06:48:06 PM UTC 24 |
Sep 01 06:48:11 PM UTC 24 |
113505915 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.1635037571 |
|
|
Sep 01 06:48:08 PM UTC 24 |
Sep 01 06:48:12 PM UTC 24 |
132496782 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3442349237 |
|
|
Sep 01 06:48:08 PM UTC 24 |
Sep 01 06:48:12 PM UTC 24 |
622781810 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.2348339194 |
|
|
Sep 01 06:48:10 PM UTC 24 |
Sep 01 06:48:13 PM UTC 24 |
36553249 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.4004917975 |
|
|
Sep 01 06:48:09 PM UTC 24 |
Sep 01 06:48:13 PM UTC 24 |
93798932 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2645195868 |
|
|
Sep 01 06:48:11 PM UTC 24 |
Sep 01 06:48:14 PM UTC 24 |
39982789 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.890263059 |
|
|
Sep 01 06:48:09 PM UTC 24 |
Sep 01 06:48:15 PM UTC 24 |
102641543 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1847904568 |
|
|
Sep 01 06:47:51 PM UTC 24 |
Sep 01 06:48:15 PM UTC 24 |
1248690322 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1365573626 |
|
|
Sep 01 06:48:09 PM UTC 24 |
Sep 01 06:48:16 PM UTC 24 |
57890199 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.140333590 |
|
|
Sep 01 06:48:12 PM UTC 24 |
Sep 01 06:48:17 PM UTC 24 |
146587175 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.3464777224 |
|
|
Sep 01 06:48:14 PM UTC 24 |
Sep 01 06:48:17 PM UTC 24 |
139191350 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3797876214 |
|
|
Sep 01 06:48:14 PM UTC 24 |
Sep 01 06:48:17 PM UTC 24 |
82785033 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3772322494 |
|
|
Sep 01 06:48:11 PM UTC 24 |
Sep 01 06:48:18 PM UTC 24 |
1016984419 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2322481905 |
|
|
Sep 01 06:48:08 PM UTC 24 |
Sep 01 06:48:19 PM UTC 24 |
157373436 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1607989378 |
|
|
Sep 01 06:48:15 PM UTC 24 |
Sep 01 06:48:20 PM UTC 24 |
73804283 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.379079254 |
|
|
Sep 01 06:48:15 PM UTC 24 |
Sep 01 06:48:20 PM UTC 24 |
130916064 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.2385596793 |
|
|
Sep 01 06:48:18 PM UTC 24 |
Sep 01 06:48:21 PM UTC 24 |
568226800 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.76958834 |
|
|
Sep 01 06:48:13 PM UTC 24 |
Sep 01 06:48:21 PM UTC 24 |
441590357 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2369280834 |
|
|
Sep 01 06:48:19 PM UTC 24 |
Sep 01 06:48:22 PM UTC 24 |
96820840 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1499841491 |
|
|
Sep 01 06:48:15 PM UTC 24 |
Sep 01 06:48:23 PM UTC 24 |
110364159 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.572459336 |
|
|
Sep 01 06:48:19 PM UTC 24 |
Sep 01 06:48:23 PM UTC 24 |
101783070 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1054920134 |
|
|
Sep 01 06:48:04 PM UTC 24 |
Sep 01 06:48:23 PM UTC 24 |
1409636047 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4258562463 |
|
|
Sep 01 06:48:08 PM UTC 24 |
Sep 01 06:48:24 PM UTC 24 |
10492777149 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.4152144388 |
|
|
Sep 01 06:48:19 PM UTC 24 |
Sep 01 06:48:24 PM UTC 24 |
104744604 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3505804499 |
|
|
Sep 01 06:47:54 PM UTC 24 |
Sep 01 06:48:25 PM UTC 24 |
5261744739 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.1762751266 |
|
|
Sep 01 06:48:21 PM UTC 24 |
Sep 01 06:48:25 PM UTC 24 |
575736850 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3650072658 |
|
|
Sep 01 06:48:22 PM UTC 24 |
Sep 01 06:48:25 PM UTC 24 |
109491232 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1726363950 |
|
|
Sep 01 06:48:22 PM UTC 24 |
Sep 01 06:48:27 PM UTC 24 |
73231577 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.24498548 |
|
|
Sep 01 06:48:20 PM UTC 24 |
Sep 01 06:48:27 PM UTC 24 |
55611990 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3018597213 |
|
|
Sep 01 06:48:24 PM UTC 24 |
Sep 01 06:48:28 PM UTC 24 |
144539912 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.427516222 |
|
|
Sep 01 06:48:24 PM UTC 24 |
Sep 01 06:48:28 PM UTC 24 |
588212665 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.222804392 |
|
|
Sep 01 06:48:23 PM UTC 24 |
Sep 01 06:48:28 PM UTC 24 |
258163935 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1893509123 |
|
|
Sep 01 06:48:24 PM UTC 24 |
Sep 01 06:48:30 PM UTC 24 |
828243419 ps |