| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 94.78 | 93.81 | 96.18 | 95.85 | 90.93 | 97.10 | 96.34 | 93.28 |
| T1257 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3108890845 | Sep 01 06:48:26 PM UTC 24 | Sep 01 06:48:30 PM UTC 24 | 185234582 ps | ||
| T1258 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.641347279 | Sep 01 06:48:26 PM UTC 24 | Sep 01 06:48:31 PM UTC 24 | 156540588 ps | ||
| T1259 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.3663350471 | Sep 01 06:48:28 PM UTC 24 | Sep 01 06:48:31 PM UTC 24 | 50742125 ps | ||
| T1260 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1868252802 | Sep 01 06:48:28 PM UTC 24 | Sep 01 06:48:32 PM UTC 24 | 590064887 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.197246773 | Sep 01 06:48:17 PM UTC 24 | Sep 01 06:48:32 PM UTC 24 | 1215917746 ps | ||
| T1261 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.2023412462 | Sep 01 06:48:29 PM UTC 24 | Sep 01 06:48:32 PM UTC 24 | 94839451 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1041928153 | Sep 01 06:48:23 PM UTC 24 | Sep 01 06:48:33 PM UTC 24 | 270334876 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.2058654928 | Sep 01 06:48:30 PM UTC 24 | Sep 01 06:48:33 PM UTC 24 | 73120761 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2999241864 | Sep 01 06:48:29 PM UTC 24 | Sep 01 06:48:34 PM UTC 24 | 78669853 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3397846228 | Sep 01 06:48:29 PM UTC 24 | Sep 01 06:48:34 PM UTC 24 | 72733523 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.1179193494 | Sep 01 06:48:31 PM UTC 24 | Sep 01 06:48:35 PM UTC 24 | 49912419 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.2838620790 | Sep 01 06:48:32 PM UTC 24 | Sep 01 06:48:36 PM UTC 24 | 138144965 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.702690897 | Sep 01 06:48:32 PM UTC 24 | Sep 01 06:48:36 PM UTC 24 | 39839284 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.1125317267 | Sep 01 06:48:33 PM UTC 24 | Sep 01 06:48:36 PM UTC 24 | 42877724 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1200398882 | Sep 01 06:48:10 PM UTC 24 | Sep 01 06:48:36 PM UTC 24 | 2550017303 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.2382220470 | Sep 01 06:48:32 PM UTC 24 | Sep 01 06:48:36 PM UTC 24 | 87267226 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1825684352 | Sep 01 06:48:33 PM UTC 24 | Sep 01 06:48:36 PM UTC 24 | 530922888 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.14865769 | Sep 01 06:48:23 PM UTC 24 | Sep 01 06:48:36 PM UTC 24 | 645132071 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.4127595850 | Sep 01 06:48:34 PM UTC 24 | Sep 01 06:48:37 PM UTC 24 | 516867148 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.2900304546 | Sep 01 06:48:34 PM UTC 24 | Sep 01 06:48:37 PM UTC 24 | 76369115 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.2273850007 | Sep 01 06:48:35 PM UTC 24 | Sep 01 06:48:38 PM UTC 24 | 40026124 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.3857489133 | Sep 01 06:48:35 PM UTC 24 | Sep 01 06:48:38 PM UTC 24 | 58167504 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.1516795406 | Sep 01 06:48:35 PM UTC 24 | Sep 01 06:48:38 PM UTC 24 | 70944238 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.902498018 | Sep 01 06:48:36 PM UTC 24 | Sep 01 06:48:39 PM UTC 24 | 38000385 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.2486639832 | Sep 01 06:48:36 PM UTC 24 | Sep 01 06:48:40 PM UTC 24 | 568183873 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.4189343972 | Sep 01 06:48:37 PM UTC 24 | Sep 01 06:48:40 PM UTC 24 | 153558832 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.153200548 | Sep 01 06:48:37 PM UTC 24 | Sep 01 06:48:40 PM UTC 24 | 74753018 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.2382394929 | Sep 01 06:48:37 PM UTC 24 | Sep 01 06:48:41 PM UTC 24 | 42970418 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.833910840 | Sep 01 06:48:21 PM UTC 24 | Sep 01 06:48:41 PM UTC 24 | 2565079166 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.163811669 | Sep 01 06:48:37 PM UTC 24 | Sep 01 06:48:41 PM UTC 24 | 141984306 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.770498753 | Sep 01 06:48:37 PM UTC 24 | Sep 01 06:48:41 PM UTC 24 | 38504034 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.3321293211 | Sep 01 06:48:37 PM UTC 24 | Sep 01 06:48:41 PM UTC 24 | 565921935 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.1496713923 | Sep 01 06:48:39 PM UTC 24 | Sep 01 06:48:42 PM UTC 24 | 152627302 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.2320801778 | Sep 01 06:48:39 PM UTC 24 | Sep 01 06:48:42 PM UTC 24 | 96044550 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.333034656 | Sep 01 06:48:39 PM UTC 24 | Sep 01 06:48:42 PM UTC 24 | 57180544 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.1707945621 | Sep 01 06:48:38 PM UTC 24 | Sep 01 06:48:42 PM UTC 24 | 144816675 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.4154244125 | Sep 01 06:48:40 PM UTC 24 | Sep 01 06:48:43 PM UTC 24 | 72413627 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2667642848 | Sep 01 06:48:00 PM UTC 24 | Sep 01 06:48:43 PM UTC 24 | 4887115278 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.373660662 | Sep 01 06:48:13 PM UTC 24 | Sep 01 06:48:43 PM UTC 24 | 1196851365 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.4008216258 | Sep 01 06:48:40 PM UTC 24 | Sep 01 06:48:43 PM UTC 24 | 140164016 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.1307492299 | Sep 01 06:48:41 PM UTC 24 | Sep 01 06:48:44 PM UTC 24 | 132968655 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.63654739 | Sep 01 06:48:41 PM UTC 24 | Sep 01 06:48:44 PM UTC 24 | 71167230 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.808082101 | Sep 01 06:48:41 PM UTC 24 | Sep 01 06:48:44 PM UTC 24 | 59281088 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.920116151 | Sep 01 06:48:26 PM UTC 24 | Sep 01 06:48:49 PM UTC 24 | 4846884183 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2117980776 | Sep 01 06:47:57 PM UTC 24 | Sep 01 06:48:51 PM UTC 24 | 20007416818 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.306776363 | Sep 01 06:47:46 PM UTC 24 | Sep 01 06:48:52 PM UTC 24 | 19862572362 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.1403374659 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 247541480 ps |
| CPU time | 9.32 seconds |
| Started | Sep 01 06:48:45 PM UTC 24 |
| Finished | Sep 01 06:48:56 PM UTC 24 |
| Peak memory | 253556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403374659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1403374659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.516948704 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 9128368680 ps |
| CPU time | 64.75 seconds |
| Started | Sep 01 06:48:44 PM UTC 24 |
| Finished | Sep 01 06:49:51 PM UTC 24 |
| Peak memory | 257500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516948704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.516948704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.2519795807 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1092043341 ps |
| CPU time | 33.44 seconds |
| Started | Sep 01 06:49:08 PM UTC 24 |
| Finished | Sep 01 06:49:43 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519795807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.2519795807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.4285515925 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4161693616 ps |
| CPU time | 130.53 seconds |
| Started | Sep 01 06:49:12 PM UTC 24 |
| Finished | Sep 01 06:51:25 PM UTC 24 |
| Peak memory | 257868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4285515925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.otp_ctrl_stress_all_with_rand_reset.4285515925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.2048959816 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6740996976 ps |
| CPU time | 53.71 seconds |
| Started | Sep 01 06:49:12 PM UTC 24 |
| Finished | Sep 01 06:50:07 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048959816 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.2048959816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.3664303684 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 15557707803 ps |
| CPU time | 135.26 seconds |
| Started | Sep 01 06:52:16 PM UTC 24 |
| Finished | Sep 01 06:54:34 PM UTC 24 |
| Peak memory | 267704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664303684 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.3664303684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.2647797528 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 18597115590 ps |
| CPU time | 202.17 seconds |
| Started | Sep 01 06:49:45 PM UTC 24 |
| Finished | Sep 01 06:53:11 PM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647797528 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.2647797528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.3542055283 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 5664151785 ps |
| CPU time | 16.59 seconds |
| Started | Sep 01 06:48:53 PM UTC 24 |
| Finished | Sep 01 06:49:10 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542055283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.3542055283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.3775669234 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 165745457163 ps |
| CPU time | 244.27 seconds |
| Started | Sep 01 06:49:13 PM UTC 24 |
| Finished | Sep 01 06:53:21 PM UTC 24 |
| Peak memory | 287892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775669234 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3775669234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.1513320377 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 516513120 ps |
| CPU time | 5.28 seconds |
| Started | Sep 01 06:48:42 PM UTC 24 |
| Finished | Sep 01 06:48:49 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513320377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.1513320377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.91814441 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 23589017133 ps |
| CPU time | 81.81 seconds |
| Started | Sep 01 06:50:28 PM UTC 24 |
| Finished | Sep 01 06:51:52 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91814441 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.91814441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.3134839555 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 129261969 ps |
| CPU time | 3.98 seconds |
| Started | Sep 01 07:02:24 PM UTC 24 |
| Finished | Sep 01 07:02:29 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134839555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.3134839555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.1169820223 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2400048249 ps |
| CPU time | 3.99 seconds |
| Started | Sep 01 06:53:42 PM UTC 24 |
| Finished | Sep 01 06:53:47 PM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169820223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.1169820223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.2473307175 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 18847852913 ps |
| CPU time | 77.01 seconds |
| Started | Sep 01 06:48:44 PM UTC 24 |
| Finished | Sep 01 06:50:03 PM UTC 24 |
| Peak memory | 257592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473307175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.2473307175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.3217582830 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 11232196720 ps |
| CPU time | 184.19 seconds |
| Started | Sep 01 06:53:18 PM UTC 24 |
| Finished | Sep 01 06:56:26 PM UTC 24 |
| Peak memory | 267884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3217582830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.otp_ctrl_stress_all_with_rand_reset.3217582830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.2205138010 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 5004885218 ps |
| CPU time | 40.81 seconds |
| Started | Sep 01 06:49:25 PM UTC 24 |
| Finished | Sep 01 06:50:08 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205138010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.2205138010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3310910893 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2842892630 ps |
| CPU time | 31.62 seconds |
| Started | Sep 01 06:47:09 PM UTC 24 |
| Finished | Sep 01 06:47:42 PM UTC 24 |
| Peak memory | 256908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310910893 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.3310910893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.1603129563 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 23917384222 ps |
| CPU time | 370.12 seconds |
| Started | Sep 01 06:51:13 PM UTC 24 |
| Finished | Sep 01 06:57:29 PM UTC 24 |
| Peak memory | 271920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603129563 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.1603129563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.22150385 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2069246687 ps |
| CPU time | 25.88 seconds |
| Started | Sep 01 06:54:31 PM UTC 24 |
| Finished | Sep 01 06:54:59 PM UTC 24 |
| Peak memory | 253396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22150385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.22150385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.202320477 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 10975530726 ps |
| CPU time | 56.58 seconds |
| Started | Sep 01 06:49:25 PM UTC 24 |
| Finished | Sep 01 06:50:23 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202320477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.202320477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.1237600459 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 41645560520 ps |
| CPU time | 245.27 seconds |
| Started | Sep 01 06:53:40 PM UTC 24 |
| Finished | Sep 01 06:57:49 PM UTC 24 |
| Peak memory | 271804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237600459 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.1237600459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.941378512 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 46648566708 ps |
| CPU time | 204.35 seconds |
| Started | Sep 01 06:50:51 PM UTC 24 |
| Finished | Sep 01 06:54:19 PM UTC 24 |
| Peak memory | 255412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941378512 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.941378512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.2759768766 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 152582844 ps |
| CPU time | 5.74 seconds |
| Started | Sep 01 06:48:51 PM UTC 24 |
| Finished | Sep 01 06:48:58 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759768766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.2759768766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.2056268470 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 194845008 ps |
| CPU time | 4.42 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:50 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056268470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2056268470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1148473037 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 60156381 ps |
| CPU time | 4.65 seconds |
| Started | Sep 01 06:47:08 PM UTC 24 |
| Finished | Sep 01 06:47:14 PM UTC 24 |
| Peak memory | 252824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148473037 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.1148473037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.1654820868 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 19028209132 ps |
| CPU time | 174.39 seconds |
| Started | Sep 01 07:00:57 PM UTC 24 |
| Finished | Sep 01 07:03:55 PM UTC 24 |
| Peak memory | 267864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1654820868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 59.otp_ctrl_stress_all_with_rand_reset.1654820868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.2139594667 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 440913071 ps |
| CPU time | 5.12 seconds |
| Started | Sep 01 07:02:18 PM UTC 24 |
| Finished | Sep 01 07:02:24 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139594667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.2139594667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.3282989581 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 4908238348 ps |
| CPU time | 30.13 seconds |
| Started | Sep 01 06:49:33 PM UTC 24 |
| Finished | Sep 01 06:50:05 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282989581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.3282989581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.2046231705 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 219473011 ps |
| CPU time | 3.16 seconds |
| Started | Sep 01 06:50:53 PM UTC 24 |
| Finished | Sep 01 06:50:57 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046231705 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2046231705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.3896283989 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 14857600630 ps |
| CPU time | 258.31 seconds |
| Started | Sep 01 06:56:01 PM UTC 24 |
| Finished | Sep 01 07:00:23 PM UTC 24 |
| Peak memory | 268080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3896283989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.otp_ctrl_stress_all_with_rand_reset.3896283989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.408206148 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 287653181 ps |
| CPU time | 7.69 seconds |
| Started | Sep 01 06:50:34 PM UTC 24 |
| Finished | Sep 01 06:50:43 PM UTC 24 |
| Peak memory | 253532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408206148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.408206148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.2793561273 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2908994849 ps |
| CPU time | 28.7 seconds |
| Started | Sep 01 06:55:23 PM UTC 24 |
| Finished | Sep 01 06:55:54 PM UTC 24 |
| Peak memory | 255744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793561273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.2793561273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.2387279264 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 137120237 ps |
| CPU time | 5.62 seconds |
| Started | Sep 01 07:02:41 PM UTC 24 |
| Finished | Sep 01 07:02:48 PM UTC 24 |
| Peak memory | 253580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387279264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.2387279264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.2077060846 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3239810300 ps |
| CPU time | 25.45 seconds |
| Started | Sep 01 06:52:27 PM UTC 24 |
| Finished | Sep 01 06:52:54 PM UTC 24 |
| Peak memory | 253384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077060846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.2077060846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.4044104236 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1372033889 ps |
| CPU time | 4.05 seconds |
| Started | Sep 01 07:03:41 PM UTC 24 |
| Finished | Sep 01 07:03:46 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044104236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.4044104236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.2470765694 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 240991642 ps |
| CPU time | 6.58 seconds |
| Started | Sep 01 06:53:33 PM UTC 24 |
| Finished | Sep 01 06:53:41 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470765694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.2470765694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.3266333935 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 542664820 ps |
| CPU time | 5.32 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:04 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266333935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.3266333935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.1700131906 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 20010399190 ps |
| CPU time | 76.95 seconds |
| Started | Sep 01 06:52:37 PM UTC 24 |
| Finished | Sep 01 06:53:56 PM UTC 24 |
| Peak memory | 255512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700131906 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.1700131906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.3444340204 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 26448469204 ps |
| CPU time | 240.04 seconds |
| Started | Sep 01 06:52:53 PM UTC 24 |
| Finished | Sep 01 06:56:56 PM UTC 24 |
| Peak memory | 267968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444340204 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.3444340204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.2823437179 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 462966336 ps |
| CPU time | 4.71 seconds |
| Started | Sep 01 07:02:17 PM UTC 24 |
| Finished | Sep 01 07:02:23 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823437179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.2823437179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.1612744735 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 145795750 ps |
| CPU time | 5.49 seconds |
| Started | Sep 01 07:02:50 PM UTC 24 |
| Finished | Sep 01 07:02:57 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612744735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.1612744735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.2452547013 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 32146502438 ps |
| CPU time | 346.69 seconds |
| Started | Sep 01 06:52:01 PM UTC 24 |
| Finished | Sep 01 06:57:53 PM UTC 24 |
| Peak memory | 274028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452547013 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.2452547013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.711383745 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 65056111811 ps |
| CPU time | 239 seconds |
| Started | Sep 01 06:57:11 PM UTC 24 |
| Finished | Sep 01 07:01:14 PM UTC 24 |
| Peak memory | 269780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711383745 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.711383745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.111525788 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 519708727 ps |
| CPU time | 8.67 seconds |
| Started | Sep 01 06:48:45 PM UTC 24 |
| Finished | Sep 01 06:48:55 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111525788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.111525788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.4019736674 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1859040876 ps |
| CPU time | 25.93 seconds |
| Started | Sep 01 06:58:08 PM UTC 24 |
| Finished | Sep 01 06:58:36 PM UTC 24 |
| Peak memory | 255412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019736674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.4019736674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.19457358 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1512357725 ps |
| CPU time | 7.5 seconds |
| Started | Sep 01 06:50:18 PM UTC 24 |
| Finished | Sep 01 06:50:27 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19457358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.19457358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.568793475 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 27813045500 ps |
| CPU time | 82.01 seconds |
| Started | Sep 01 06:48:43 PM UTC 24 |
| Finished | Sep 01 06:50:08 PM UTC 24 |
| Peak memory | 253656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568793475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.568793475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.2371217691 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 24238163702 ps |
| CPU time | 195.36 seconds |
| Started | Sep 01 06:53:18 PM UTC 24 |
| Finished | Sep 01 06:56:37 PM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371217691 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.2371217691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.51856376 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 120055834 ps |
| CPU time | 6.11 seconds |
| Started | Sep 01 07:02:11 PM UTC 24 |
| Finished | Sep 01 07:02:18 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51856376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.51856376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.1016058917 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2502772230 ps |
| CPU time | 6 seconds |
| Started | Sep 01 06:58:08 PM UTC 24 |
| Finished | Sep 01 06:58:15 PM UTC 24 |
| Peak memory | 251336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016058917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.1016058917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.2451603630 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1861629828 ps |
| CPU time | 57.98 seconds |
| Started | Sep 01 06:48:56 PM UTC 24 |
| Finished | Sep 01 06:49:56 PM UTC 24 |
| Peak memory | 251332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451603630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.2451603630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.634732796 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 23306631505 ps |
| CPU time | 201.41 seconds |
| Started | Sep 01 06:55:14 PM UTC 24 |
| Finished | Sep 01 06:58:39 PM UTC 24 |
| Peak memory | 274036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=634732796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.634732796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.4108802857 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 13610231795 ps |
| CPU time | 41.47 seconds |
| Started | Sep 01 07:00:30 PM UTC 24 |
| Finished | Sep 01 07:01:13 PM UTC 24 |
| Peak memory | 257688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108802857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.4108802857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.3925439154 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 647125277 ps |
| CPU time | 13.07 seconds |
| Started | Sep 01 06:51:58 PM UTC 24 |
| Finished | Sep 01 06:52:12 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925439154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.3925439154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.1284492294 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 174958967 ps |
| CPU time | 6.22 seconds |
| Started | Sep 01 06:57:48 PM UTC 24 |
| Finished | Sep 01 06:57:56 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284492294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.1284492294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.400043522 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 19847291182 ps |
| CPU time | 198.11 seconds |
| Started | Sep 01 06:55:50 PM UTC 24 |
| Finished | Sep 01 06:59:11 PM UTC 24 |
| Peak memory | 290280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400043522 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.400043522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1847904568 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1248690322 ps |
| CPU time | 22.77 seconds |
| Started | Sep 01 06:47:51 PM UTC 24 |
| Finished | Sep 01 06:48:15 PM UTC 24 |
| Peak memory | 256796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847904568 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.1847904568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.2003278644 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1135693177 ps |
| CPU time | 20.66 seconds |
| Started | Sep 01 06:54:20 PM UTC 24 |
| Finished | Sep 01 06:54:42 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003278644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.2003278644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.2560660669 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 639187396 ps |
| CPU time | 6.86 seconds |
| Started | Sep 01 07:02:30 PM UTC 24 |
| Finished | Sep 01 07:02:38 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560660669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.2560660669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.672156906 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 927206348 ps |
| CPU time | 15.59 seconds |
| Started | Sep 01 06:56:20 PM UTC 24 |
| Finished | Sep 01 06:56:36 PM UTC 24 |
| Peak memory | 253368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672156906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.672156906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.1599674800 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 496050619 ps |
| CPU time | 5.43 seconds |
| Started | Sep 01 07:02:17 PM UTC 24 |
| Finished | Sep 01 07:02:23 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599674800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.1599674800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.560426676 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 205435150 ps |
| CPU time | 4.08 seconds |
| Started | Sep 01 07:03:49 PM UTC 24 |
| Finished | Sep 01 07:03:54 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560426676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.560426676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.3745584481 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 844190733 ps |
| CPU time | 20.69 seconds |
| Started | Sep 01 06:50:00 PM UTC 24 |
| Finished | Sep 01 06:50:22 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745584481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.3745584481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.875870952 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 470624962 ps |
| CPU time | 15.77 seconds |
| Started | Sep 01 06:59:35 PM UTC 24 |
| Finished | Sep 01 06:59:53 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875870952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.875870952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.1096286575 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 652867371 ps |
| CPU time | 9.51 seconds |
| Started | Sep 01 07:01:32 PM UTC 24 |
| Finished | Sep 01 07:01:42 PM UTC 24 |
| Peak memory | 251136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096286575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1096286575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.2051757924 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 15950267261 ps |
| CPU time | 105.42 seconds |
| Started | Sep 01 06:55:24 PM UTC 24 |
| Finished | Sep 01 06:57:12 PM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2051757924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.otp_ctrl_stress_all_with_rand_reset.2051757924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.507974210 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 215885802 ps |
| CPU time | 5.38 seconds |
| Started | Sep 01 07:01:02 PM UTC 24 |
| Finished | Sep 01 07:01:08 PM UTC 24 |
| Peak memory | 251268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507974210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.507974210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.381231726 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 72778788 ps |
| CPU time | 2.61 seconds |
| Started | Sep 01 06:47:06 PM UTC 24 |
| Finished | Sep 01 06:47:10 PM UTC 24 |
| Peak memory | 254728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381231726 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.381231726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.808615239 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 3429477435 ps |
| CPU time | 33.8 seconds |
| Started | Sep 01 06:50:06 PM UTC 24 |
| Finished | Sep 01 06:50:42 PM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808615239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.808615239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.709205157 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 537975322 ps |
| CPU time | 14.17 seconds |
| Started | Sep 01 06:50:23 PM UTC 24 |
| Finished | Sep 01 06:50:39 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709205157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.709205157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3094511419 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1170984750 ps |
| CPU time | 18.66 seconds |
| Started | Sep 01 06:47:48 PM UTC 24 |
| Finished | Sep 01 06:48:08 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094511419 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.3094511419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.4204788747 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2982685463 ps |
| CPU time | 24.17 seconds |
| Started | Sep 01 06:56:16 PM UTC 24 |
| Finished | Sep 01 06:56:41 PM UTC 24 |
| Peak memory | 250960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204788747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.4204788747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.2673280295 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 479588640 ps |
| CPU time | 11.97 seconds |
| Started | Sep 01 06:50:09 PM UTC 24 |
| Finished | Sep 01 06:50:22 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673280295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.2673280295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.2569287711 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 4139464909 ps |
| CPU time | 49.78 seconds |
| Started | Sep 01 06:51:06 PM UTC 24 |
| Finished | Sep 01 06:51:57 PM UTC 24 |
| Peak memory | 257844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569287711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2569287711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.1447580658 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3736357164 ps |
| CPU time | 33.55 seconds |
| Started | Sep 01 06:56:57 PM UTC 24 |
| Finished | Sep 01 06:57:32 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447580658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1447580658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.2712067748 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 853049889 ps |
| CPU time | 12.82 seconds |
| Started | Sep 01 06:51:00 PM UTC 24 |
| Finished | Sep 01 06:51:14 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712067748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.2712067748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.2731578046 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2202125478 ps |
| CPU time | 54.03 seconds |
| Started | Sep 01 06:56:01 PM UTC 24 |
| Finished | Sep 01 06:56:56 PM UTC 24 |
| Peak memory | 253404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731578046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.2731578046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.2646414170 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 455547925 ps |
| CPU time | 7.66 seconds |
| Started | Sep 01 06:54:03 PM UTC 24 |
| Finished | Sep 01 06:54:11 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646414170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.2646414170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.2095365569 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4223546158 ps |
| CPU time | 12.93 seconds |
| Started | Sep 01 06:54:42 PM UTC 24 |
| Finished | Sep 01 06:54:56 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095365569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.2095365569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.1468958307 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 192049731 ps |
| CPU time | 4.93 seconds |
| Started | Sep 01 07:02:13 PM UTC 24 |
| Finished | Sep 01 07:02:19 PM UTC 24 |
| Peak memory | 253008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468958307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.1468958307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.2826709241 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 92503885 ps |
| CPU time | 5.23 seconds |
| Started | Sep 01 06:54:13 PM UTC 24 |
| Finished | Sep 01 06:54:19 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826709241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2826709241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4258562463 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 10492777149 ps |
| CPU time | 14.06 seconds |
| Started | Sep 01 06:48:08 PM UTC 24 |
| Finished | Sep 01 06:48:24 PM UTC 24 |
| Peak memory | 257100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258562463 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.4258562463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.3276469751 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 744552962 ps |
| CPU time | 16.75 seconds |
| Started | Sep 01 06:48:55 PM UTC 24 |
| Finished | Sep 01 06:49:13 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276469751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.3276469751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.238184618 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 30698179318 ps |
| CPU time | 87.11 seconds |
| Started | Sep 01 07:00:50 PM UTC 24 |
| Finished | Sep 01 07:02:19 PM UTC 24 |
| Peak memory | 257652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=238184618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.238184618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.4099891414 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 8607791557 ps |
| CPU time | 86.53 seconds |
| Started | Sep 01 07:00:50 PM UTC 24 |
| Finished | Sep 01 07:02:18 PM UTC 24 |
| Peak memory | 284336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4099891414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 54.otp_ctrl_stress_all_with_rand_reset.4099891414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.3078056455 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 350975963 ps |
| CPU time | 5.46 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:03 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078056455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.3078056455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.3516037586 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 782687238 ps |
| CPU time | 3.24 seconds |
| Started | Sep 01 06:48:42 PM UTC 24 |
| Finished | Sep 01 06:48:47 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516037586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes t +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.3516037586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.871767957 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1054108193 ps |
| CPU time | 15.71 seconds |
| Started | Sep 01 06:50:00 PM UTC 24 |
| Finished | Sep 01 06:50:17 PM UTC 24 |
| Peak memory | 257780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871767957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.871767957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.1666169765 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 6768370045 ps |
| CPU time | 21.32 seconds |
| Started | Sep 01 06:55:36 PM UTC 24 |
| Finished | Sep 01 06:55:59 PM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666169765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1666169765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.4212862017 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 20123643160 ps |
| CPU time | 64.02 seconds |
| Started | Sep 01 06:53:53 PM UTC 24 |
| Finished | Sep 01 06:54:58 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212862017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.4212862017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.3960032547 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 2263862057 ps |
| CPU time | 6.14 seconds |
| Started | Sep 01 06:49:20 PM UTC 24 |
| Finished | Sep 01 06:49:27 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960032547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.3960032547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2758432229 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 9722038524 ps |
| CPU time | 29.57 seconds |
| Started | Sep 01 06:47:18 PM UTC 24 |
| Finished | Sep 01 06:47:49 PM UTC 24 |
| Peak memory | 256836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758432229 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.2758432229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.4243004541 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 966512889 ps |
| CPU time | 14.85 seconds |
| Started | Sep 01 06:53:20 PM UTC 24 |
| Finished | Sep 01 06:53:36 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243004541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.4243004541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.611174742 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 474753344 ps |
| CPU time | 5.54 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:44 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611174742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.611174742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.4087065717 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1349700345 ps |
| CPU time | 24.23 seconds |
| Started | Sep 01 06:57:48 PM UTC 24 |
| Finished | Sep 01 06:58:14 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087065717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.4087065717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.3796185218 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 740717967 ps |
| CPU time | 9.15 seconds |
| Started | Sep 01 06:49:20 PM UTC 24 |
| Finished | Sep 01 06:49:30 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796185218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.3796185218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.1311414702 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 17147973785 ps |
| CPU time | 157.98 seconds |
| Started | Sep 01 07:01:06 PM UTC 24 |
| Finished | Sep 01 07:03:47 PM UTC 24 |
| Peak memory | 270000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1311414702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 64.otp_ctrl_stress_all_with_rand_reset.1311414702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.2924006118 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1746259151 ps |
| CPU time | 43.04 seconds |
| Started | Sep 01 06:52:27 PM UTC 24 |
| Finished | Sep 01 06:53:12 PM UTC 24 |
| Peak memory | 257596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924006118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.2924006118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.3804310193 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 14854994843 ps |
| CPU time | 48.85 seconds |
| Started | Sep 01 06:52:51 PM UTC 24 |
| Finished | Sep 01 06:53:41 PM UTC 24 |
| Peak memory | 253448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804310193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.3804310193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.1059513353 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 8493939261 ps |
| CPU time | 21.95 seconds |
| Started | Sep 01 06:54:42 PM UTC 24 |
| Finished | Sep 01 06:55:05 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059513353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.1059513353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.4059150855 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2215052966 ps |
| CPU time | 5.84 seconds |
| Started | Sep 01 07:03:32 PM UTC 24 |
| Finished | Sep 01 07:03:40 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059150855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.4059150855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.810127744 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1461216684 ps |
| CPU time | 21.5 seconds |
| Started | Sep 01 06:48:43 PM UTC 24 |
| Finished | Sep 01 06:49:07 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810127744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.810127744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.4208413949 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 123218433 ps |
| CPU time | 9.41 seconds |
| Started | Sep 01 06:47:08 PM UTC 24 |
| Finished | Sep 01 06:47:19 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208413949 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.4208413949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1982819549 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 159419769 ps |
| CPU time | 2.99 seconds |
| Started | Sep 01 06:47:06 PM UTC 24 |
| Finished | Sep 01 06:47:10 PM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982819549 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.1982819549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.541959616 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1073377961 ps |
| CPU time | 5.57 seconds |
| Started | Sep 01 06:47:08 PM UTC 24 |
| Finished | Sep 01 06:47:15 PM UTC 24 |
| Peak memory | 258872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=541959616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr _mem_rw_with_rand_reset.541959616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.2953542244 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 36261300 ps |
| CPU time | 2.24 seconds |
| Started | Sep 01 06:47:05 PM UTC 24 |
| Finished | Sep 01 06:47:08 PM UTC 24 |
| Peak memory | 241716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953542244 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2953542244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.618215746 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 66337014 ps |
| CPU time | 2.09 seconds |
| Started | Sep 01 06:47:05 PM UTC 24 |
| Finished | Sep 01 06:47:08 PM UTC 24 |
| Peak memory | 241264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618215746 -assert nopostproc +U VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.618215746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.278866625 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 46674434 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 06:47:05 PM UTC 24 |
| Finished | Sep 01 06:47:08 PM UTC 24 |
| Peak memory | 240928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278866625 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.278866625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.716398168 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1452334636 ps |
| CPU time | 7.7 seconds |
| Started | Sep 01 06:47:08 PM UTC 24 |
| Finished | Sep 01 06:47:17 PM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716398168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.716398168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2889572401 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 108442235 ps |
| CPU time | 4.99 seconds |
| Started | Sep 01 06:47:03 PM UTC 24 |
| Finished | Sep 01 06:47:10 PM UTC 24 |
| Peak memory | 252888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889572401 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.2889572401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3952936901 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 2528797398 ps |
| CPU time | 31.33 seconds |
| Started | Sep 01 06:47:05 PM UTC 24 |
| Finished | Sep 01 06:47:38 PM UTC 24 |
| Peak memory | 258956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952936901 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.3952936901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.4114825229 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 116457287 ps |
| CPU time | 5.53 seconds |
| Started | Sep 01 06:47:15 PM UTC 24 |
| Finished | Sep 01 06:47:21 PM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114825229 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.4114825229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2513331100 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 392022583 ps |
| CPU time | 13.82 seconds |
| Started | Sep 01 06:47:15 PM UTC 24 |
| Finished | Sep 01 06:47:30 PM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513331100 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.2513331100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2324046051 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 264206504 ps |
| CPU time | 3.73 seconds |
| Started | Sep 01 06:47:12 PM UTC 24 |
| Finished | Sep 01 06:47:16 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324046051 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.2324046051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1523921133 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 225995470 ps |
| CPU time | 4.33 seconds |
| Started | Sep 01 06:47:16 PM UTC 24 |
| Finished | Sep 01 06:47:21 PM UTC 24 |
| Peak memory | 259036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1523921133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_cs r_mem_rw_with_rand_reset.1523921133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1679635448 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 100925751 ps |
| CPU time | 2.48 seconds |
| Started | Sep 01 06:47:14 PM UTC 24 |
| Finished | Sep 01 06:47:17 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679635448 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1679635448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.2584068934 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 37575092 ps |
| CPU time | 2.1 seconds |
| Started | Sep 01 06:47:09 PM UTC 24 |
| Finished | Sep 01 06:47:12 PM UTC 24 |
| Peak memory | 241708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584068934 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.2584068934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3430221672 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 36787490 ps |
| CPU time | 2.14 seconds |
| Started | Sep 01 06:47:11 PM UTC 24 |
| Finished | Sep 01 06:47:15 PM UTC 24 |
| Peak memory | 241200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430221672 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.3430221672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.448562365 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 131478843 ps |
| CPU time | 2.26 seconds |
| Started | Sep 01 06:47:10 PM UTC 24 |
| Finished | Sep 01 06:47:14 PM UTC 24 |
| Peak memory | 241432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448562365 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.448562365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1002807697 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 72022170 ps |
| CPU time | 3.48 seconds |
| Started | Sep 01 06:47:16 PM UTC 24 |
| Finished | Sep 01 06:47:21 PM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002807697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.1002807697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2869444256 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 636857070 ps |
| CPU time | 10.11 seconds |
| Started | Sep 01 06:47:09 PM UTC 24 |
| Finished | Sep 01 06:47:20 PM UTC 24 |
| Peak memory | 259000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869444256 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.2869444256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.436729028 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 128501577 ps |
| CPU time | 5.46 seconds |
| Started | Sep 01 06:47:59 PM UTC 24 |
| Finished | Sep 01 06:48:05 PM UTC 24 |
| Peak memory | 258884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=436729028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_cs r_mem_rw_with_rand_reset.436729028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2598647329 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 41314185 ps |
| CPU time | 2.49 seconds |
| Started | Sep 01 06:47:58 PM UTC 24 |
| Finished | Sep 01 06:48:01 PM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598647329 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.2598647329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.3423390412 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 45698105 ps |
| CPU time | 2.21 seconds |
| Started | Sep 01 06:47:58 PM UTC 24 |
| Finished | Sep 01 06:48:01 PM UTC 24 |
| Peak memory | 242656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423390412 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.3423390412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3243220248 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 74933346 ps |
| CPU time | 3.43 seconds |
| Started | Sep 01 06:47:59 PM UTC 24 |
| Finished | Sep 01 06:48:03 PM UTC 24 |
| Peak memory | 252712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243220248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.3243220248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.974969749 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 378142122 ps |
| CPU time | 11.66 seconds |
| Started | Sep 01 06:47:57 PM UTC 24 |
| Finished | Sep 01 06:48:09 PM UTC 24 |
| Peak memory | 259156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974969749 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.974969749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2117980776 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 20007416818 ps |
| CPU time | 52.41 seconds |
| Started | Sep 01 06:47:57 PM UTC 24 |
| Finished | Sep 01 06:48:51 PM UTC 24 |
| Peak memory | 256856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117980776 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.2117980776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.961990355 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 281669950 ps |
| CPU time | 3.88 seconds |
| Started | Sep 01 06:48:02 PM UTC 24 |
| Finished | Sep 01 06:48:07 PM UTC 24 |
| Peak memory | 258900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=961990355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_cs r_mem_rw_with_rand_reset.961990355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.8818768 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 73793700 ps |
| CPU time | 2.43 seconds |
| Started | Sep 01 06:48:02 PM UTC 24 |
| Finished | Sep 01 06:48:06 PM UTC 24 |
| Peak memory | 254812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8818768 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.8818768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.53407117 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 44155462 ps |
| CPU time | 2.13 seconds |
| Started | Sep 01 06:48:00 PM UTC 24 |
| Finished | Sep 01 06:48:03 PM UTC 24 |
| Peak memory | 242576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53407117 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.53407117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1612980204 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 105965087 ps |
| CPU time | 3.77 seconds |
| Started | Sep 01 06:48:02 PM UTC 24 |
| Finished | Sep 01 06:48:07 PM UTC 24 |
| Peak memory | 252728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612980204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.1612980204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2742611288 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 188277590 ps |
| CPU time | 4.61 seconds |
| Started | Sep 01 06:47:59 PM UTC 24 |
| Finished | Sep 01 06:48:05 PM UTC 24 |
| Peak memory | 258964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742611288 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.2742611288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2667642848 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4887115278 ps |
| CPU time | 41.41 seconds |
| Started | Sep 01 06:48:00 PM UTC 24 |
| Finished | Sep 01 06:48:43 PM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667642848 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.2667642848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.673886822 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 113505915 ps |
| CPU time | 4.5 seconds |
| Started | Sep 01 06:48:06 PM UTC 24 |
| Finished | Sep 01 06:48:11 PM UTC 24 |
| Peak memory | 258972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=673886822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_cs r_mem_rw_with_rand_reset.673886822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2643840134 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 42659228 ps |
| CPU time | 2.45 seconds |
| Started | Sep 01 06:48:04 PM UTC 24 |
| Finished | Sep 01 06:48:08 PM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643840134 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.2643840134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.2029993849 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 130397895 ps |
| CPU time | 2.39 seconds |
| Started | Sep 01 06:48:04 PM UTC 24 |
| Finished | Sep 01 06:48:08 PM UTC 24 |
| Peak memory | 241732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029993849 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2029993849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1577098645 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 47968116 ps |
| CPU time | 3.08 seconds |
| Started | Sep 01 06:48:06 PM UTC 24 |
| Finished | Sep 01 06:48:10 PM UTC 24 |
| Peak memory | 252824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577098645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.1577098645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3616206394 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 203366164 ps |
| CPU time | 5.75 seconds |
| Started | Sep 01 06:48:03 PM UTC 24 |
| Finished | Sep 01 06:48:10 PM UTC 24 |
| Peak memory | 259024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616206394 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3616206394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1054920134 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 1409636047 ps |
| CPU time | 17.47 seconds |
| Started | Sep 01 06:48:04 PM UTC 24 |
| Finished | Sep 01 06:48:23 PM UTC 24 |
| Peak memory | 256796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054920134 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.1054920134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.890263059 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 102641543 ps |
| CPU time | 4.97 seconds |
| Started | Sep 01 06:48:09 PM UTC 24 |
| Finished | Sep 01 06:48:15 PM UTC 24 |
| Peak memory | 259068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=890263059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_cs r_mem_rw_with_rand_reset.890263059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3442349237 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 622781810 ps |
| CPU time | 2.63 seconds |
| Started | Sep 01 06:48:08 PM UTC 24 |
| Finished | Sep 01 06:48:12 PM UTC 24 |
| Peak memory | 252652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442349237 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.3442349237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.1635037571 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 132496782 ps |
| CPU time | 2.16 seconds |
| Started | Sep 01 06:48:08 PM UTC 24 |
| Finished | Sep 01 06:48:12 PM UTC 24 |
| Peak memory | 241896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635037571 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1635037571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.4004917975 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 93798932 ps |
| CPU time | 3.82 seconds |
| Started | Sep 01 06:48:09 PM UTC 24 |
| Finished | Sep 01 06:48:13 PM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004917975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.4004917975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2322481905 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 157373436 ps |
| CPU time | 9.56 seconds |
| Started | Sep 01 06:48:08 PM UTC 24 |
| Finished | Sep 01 06:48:19 PM UTC 24 |
| Peak memory | 259156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322481905 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.2322481905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.140333590 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 146587175 ps |
| CPU time | 3.91 seconds |
| Started | Sep 01 06:48:12 PM UTC 24 |
| Finished | Sep 01 06:48:17 PM UTC 24 |
| Peak memory | 259068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=140333590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_cs r_mem_rw_with_rand_reset.140333590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2645195868 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 39982789 ps |
| CPU time | 2.33 seconds |
| Started | Sep 01 06:48:11 PM UTC 24 |
| Finished | Sep 01 06:48:14 PM UTC 24 |
| Peak memory | 252820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645195868 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.2645195868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.2348339194 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 36553249 ps |
| CPU time | 2.15 seconds |
| Started | Sep 01 06:48:10 PM UTC 24 |
| Finished | Sep 01 06:48:13 PM UTC 24 |
| Peak memory | 241676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348339194 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2348339194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3772322494 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 1016984419 ps |
| CPU time | 5.85 seconds |
| Started | Sep 01 06:48:11 PM UTC 24 |
| Finished | Sep 01 06:48:18 PM UTC 24 |
| Peak memory | 254676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772322494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.3772322494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1365573626 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 57890199 ps |
| CPU time | 5.95 seconds |
| Started | Sep 01 06:48:09 PM UTC 24 |
| Finished | Sep 01 06:48:16 PM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365573626 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.1365573626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1200398882 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2550017303 ps |
| CPU time | 24.81 seconds |
| Started | Sep 01 06:48:10 PM UTC 24 |
| Finished | Sep 01 06:48:36 PM UTC 24 |
| Peak memory | 252832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200398882 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.1200398882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1607989378 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 73804283 ps |
| CPU time | 3.17 seconds |
| Started | Sep 01 06:48:15 PM UTC 24 |
| Finished | Sep 01 06:48:20 PM UTC 24 |
| Peak memory | 256708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1607989378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_c sr_mem_rw_with_rand_reset.1607989378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3797876214 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 82785033 ps |
| CPU time | 2.23 seconds |
| Started | Sep 01 06:48:14 PM UTC 24 |
| Finished | Sep 01 06:48:17 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797876214 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3797876214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.3464777224 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 139191350 ps |
| CPU time | 2.17 seconds |
| Started | Sep 01 06:48:14 PM UTC 24 |
| Finished | Sep 01 06:48:17 PM UTC 24 |
| Peak memory | 242604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464777224 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.3464777224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.379079254 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 130916064 ps |
| CPU time | 3.59 seconds |
| Started | Sep 01 06:48:15 PM UTC 24 |
| Finished | Sep 01 06:48:20 PM UTC 24 |
| Peak memory | 252664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379079254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.379079254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.76958834 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 441590357 ps |
| CPU time | 7.06 seconds |
| Started | Sep 01 06:48:13 PM UTC 24 |
| Finished | Sep 01 06:48:21 PM UTC 24 |
| Peak memory | 258908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76958834 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.76958834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.373660662 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1196851365 ps |
| CPU time | 28.38 seconds |
| Started | Sep 01 06:48:13 PM UTC 24 |
| Finished | Sep 01 06:48:43 PM UTC 24 |
| Peak memory | 252820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373660662 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.373660662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.4152144388 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 104744604 ps |
| CPU time | 4.11 seconds |
| Started | Sep 01 06:48:19 PM UTC 24 |
| Finished | Sep 01 06:48:24 PM UTC 24 |
| Peak memory | 259076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4152144388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_c sr_mem_rw_with_rand_reset.4152144388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2369280834 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 96820840 ps |
| CPU time | 2.58 seconds |
| Started | Sep 01 06:48:19 PM UTC 24 |
| Finished | Sep 01 06:48:22 PM UTC 24 |
| Peak memory | 258784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369280834 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.2369280834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.2385596793 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 568226800 ps |
| CPU time | 2.62 seconds |
| Started | Sep 01 06:48:18 PM UTC 24 |
| Finished | Sep 01 06:48:21 PM UTC 24 |
| Peak memory | 241896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385596793 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.2385596793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.572459336 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 101783070 ps |
| CPU time | 3.09 seconds |
| Started | Sep 01 06:48:19 PM UTC 24 |
| Finished | Sep 01 06:48:23 PM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572459336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.572459336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1499841491 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 110364159 ps |
| CPU time | 6.22 seconds |
| Started | Sep 01 06:48:15 PM UTC 24 |
| Finished | Sep 01 06:48:23 PM UTC 24 |
| Peak memory | 258980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499841491 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1499841491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.197246773 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1215917746 ps |
| CPU time | 14.18 seconds |
| Started | Sep 01 06:48:17 PM UTC 24 |
| Finished | Sep 01 06:48:32 PM UTC 24 |
| Peak memory | 256796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197246773 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.197246773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.222804392 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 258163935 ps |
| CPU time | 4.01 seconds |
| Started | Sep 01 06:48:23 PM UTC 24 |
| Finished | Sep 01 06:48:28 PM UTC 24 |
| Peak memory | 258348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=222804392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_cs r_mem_rw_with_rand_reset.222804392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3650072658 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 109491232 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 06:48:22 PM UTC 24 |
| Finished | Sep 01 06:48:25 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650072658 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3650072658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.1762751266 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 575736850 ps |
| CPU time | 2.75 seconds |
| Started | Sep 01 06:48:21 PM UTC 24 |
| Finished | Sep 01 06:48:25 PM UTC 24 |
| Peak memory | 242604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762751266 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.1762751266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1726363950 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 73231577 ps |
| CPU time | 3.44 seconds |
| Started | Sep 01 06:48:22 PM UTC 24 |
| Finished | Sep 01 06:48:27 PM UTC 24 |
| Peak memory | 252892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726363950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.1726363950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.24498548 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 55611990 ps |
| CPU time | 5.81 seconds |
| Started | Sep 01 06:48:20 PM UTC 24 |
| Finished | Sep 01 06:48:27 PM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24498548 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.24498548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.833910840 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2565079166 ps |
| CPU time | 18.54 seconds |
| Started | Sep 01 06:48:21 PM UTC 24 |
| Finished | Sep 01 06:48:41 PM UTC 24 |
| Peak memory | 256868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833910840 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.833910840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3108890845 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 185234582 ps |
| CPU time | 3.75 seconds |
| Started | Sep 01 06:48:26 PM UTC 24 |
| Finished | Sep 01 06:48:30 PM UTC 24 |
| Peak memory | 256928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3108890845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_c sr_mem_rw_with_rand_reset.3108890845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3018597213 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 144539912 ps |
| CPU time | 2.19 seconds |
| Started | Sep 01 06:48:24 PM UTC 24 |
| Finished | Sep 01 06:48:28 PM UTC 24 |
| Peak memory | 254792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018597213 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.3018597213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.427516222 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 588212665 ps |
| CPU time | 2.85 seconds |
| Started | Sep 01 06:48:24 PM UTC 24 |
| Finished | Sep 01 06:48:28 PM UTC 24 |
| Peak memory | 242168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427516222 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.427516222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1893509123 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 828243419 ps |
| CPU time | 4.14 seconds |
| Started | Sep 01 06:48:24 PM UTC 24 |
| Finished | Sep 01 06:48:30 PM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893509123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.1893509123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1041928153 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 270334876 ps |
| CPU time | 8.25 seconds |
| Started | Sep 01 06:48:23 PM UTC 24 |
| Finished | Sep 01 06:48:33 PM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041928153 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.1041928153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.14865769 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 645132071 ps |
| CPU time | 11.83 seconds |
| Started | Sep 01 06:48:23 PM UTC 24 |
| Finished | Sep 01 06:48:36 PM UTC 24 |
| Peak memory | 256856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14865769 -assert nopostproc +UVM_TESTN AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.14865769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2999241864 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 78669853 ps |
| CPU time | 3.73 seconds |
| Started | Sep 01 06:48:29 PM UTC 24 |
| Finished | Sep 01 06:48:34 PM UTC 24 |
| Peak memory | 258884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2999241864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_c sr_mem_rw_with_rand_reset.2999241864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1868252802 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 590064887 ps |
| CPU time | 2.67 seconds |
| Started | Sep 01 06:48:28 PM UTC 24 |
| Finished | Sep 01 06:48:32 PM UTC 24 |
| Peak memory | 252636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868252802 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1868252802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.3663350471 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 50742125 ps |
| CPU time | 2.35 seconds |
| Started | Sep 01 06:48:28 PM UTC 24 |
| Finished | Sep 01 06:48:31 PM UTC 24 |
| Peak memory | 242472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663350471 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.3663350471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3397846228 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 72733523 ps |
| CPU time | 3.75 seconds |
| Started | Sep 01 06:48:29 PM UTC 24 |
| Finished | Sep 01 06:48:34 PM UTC 24 |
| Peak memory | 254872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397846228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.3397846228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.641347279 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 156540588 ps |
| CPU time | 4.42 seconds |
| Started | Sep 01 06:48:26 PM UTC 24 |
| Finished | Sep 01 06:48:31 PM UTC 24 |
| Peak memory | 252812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641347279 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.641347279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.920116151 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 4846884183 ps |
| CPU time | 22.35 seconds |
| Started | Sep 01 06:48:26 PM UTC 24 |
| Finished | Sep 01 06:48:49 PM UTC 24 |
| Peak memory | 256860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920116151 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.920116151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1416981457 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1886029146 ps |
| CPU time | 8.05 seconds |
| Started | Sep 01 06:47:23 PM UTC 24 |
| Finished | Sep 01 06:47:32 PM UTC 24 |
| Peak memory | 252832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416981457 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.1416981457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1474869734 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 838308630 ps |
| CPU time | 12.18 seconds |
| Started | Sep 01 06:47:22 PM UTC 24 |
| Finished | Sep 01 06:47:36 PM UTC 24 |
| Peak memory | 252548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474869734 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.1474869734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2967171246 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 97943756 ps |
| CPU time | 3.57 seconds |
| Started | Sep 01 06:47:21 PM UTC 24 |
| Finished | Sep 01 06:47:26 PM UTC 24 |
| Peak memory | 254756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967171246 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.2967171246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3586194912 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 106121256 ps |
| CPU time | 6.09 seconds |
| Started | Sep 01 06:47:26 PM UTC 24 |
| Finished | Sep 01 06:47:33 PM UTC 24 |
| Peak memory | 258668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3586194912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_cs r_mem_rw_with_rand_reset.3586194912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.734148693 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 69573434 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 06:47:22 PM UTC 24 |
| Finished | Sep 01 06:47:26 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734148693 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.734148693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.1697095547 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 69620519 ps |
| CPU time | 2.19 seconds |
| Started | Sep 01 06:47:18 PM UTC 24 |
| Finished | Sep 01 06:47:21 PM UTC 24 |
| Peak memory | 242656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697095547 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.1697095547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2912162050 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 52312859 ps |
| CPU time | 2.23 seconds |
| Started | Sep 01 06:47:21 PM UTC 24 |
| Finished | Sep 01 06:47:25 PM UTC 24 |
| Peak memory | 241152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912162050 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.2912162050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.98608865 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 70168173 ps |
| CPU time | 2.19 seconds |
| Started | Sep 01 06:47:19 PM UTC 24 |
| Finished | Sep 01 06:47:23 PM UTC 24 |
| Peak memory | 241732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98608865 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.98608865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3798891634 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 136427187 ps |
| CPU time | 3.62 seconds |
| Started | Sep 01 06:47:24 PM UTC 24 |
| Finished | Sep 01 06:47:28 PM UTC 24 |
| Peak memory | 252672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798891634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.3798891634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3672398468 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 303029858 ps |
| CPU time | 6.53 seconds |
| Started | Sep 01 06:47:17 PM UTC 24 |
| Finished | Sep 01 06:47:25 PM UTC 24 |
| Peak memory | 259200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672398468 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3672398468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.2023412462 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 94839451 ps |
| CPU time | 2.16 seconds |
| Started | Sep 01 06:48:29 PM UTC 24 |
| Finished | Sep 01 06:48:32 PM UTC 24 |
| Peak memory | 241972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023412462 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.2023412462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.2058654928 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 73120761 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 06:48:30 PM UTC 24 |
| Finished | Sep 01 06:48:33 PM UTC 24 |
| Peak memory | 242004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058654928 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2058654928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.1179193494 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 49912419 ps |
| CPU time | 2.28 seconds |
| Started | Sep 01 06:48:31 PM UTC 24 |
| Finished | Sep 01 06:48:35 PM UTC 24 |
| Peak memory | 242008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179193494 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1179193494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.702690897 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 39839284 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 06:48:32 PM UTC 24 |
| Finished | Sep 01 06:48:36 PM UTC 24 |
| Peak memory | 242656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702690897 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.702690897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.2838620790 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 138144965 ps |
| CPU time | 2.04 seconds |
| Started | Sep 01 06:48:32 PM UTC 24 |
| Finished | Sep 01 06:48:36 PM UTC 24 |
| Peak memory | 241836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838620790 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2838620790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.2382220470 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 87267226 ps |
| CPU time | 2.27 seconds |
| Started | Sep 01 06:48:32 PM UTC 24 |
| Finished | Sep 01 06:48:36 PM UTC 24 |
| Peak memory | 242476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382220470 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.2382220470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1825684352 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 530922888 ps |
| CPU time | 2.51 seconds |
| Started | Sep 01 06:48:33 PM UTC 24 |
| Finished | Sep 01 06:48:36 PM UTC 24 |
| Peak memory | 242460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825684352 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1825684352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.1125317267 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 42877724 ps |
| CPU time | 2.2 seconds |
| Started | Sep 01 06:48:33 PM UTC 24 |
| Finished | Sep 01 06:48:36 PM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125317267 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1125317267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.2900304546 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 76369115 ps |
| CPU time | 2.34 seconds |
| Started | Sep 01 06:48:34 PM UTC 24 |
| Finished | Sep 01 06:48:37 PM UTC 24 |
| Peak memory | 241716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900304546 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.2900304546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.4127595850 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 516867148 ps |
| CPU time | 2.23 seconds |
| Started | Sep 01 06:48:34 PM UTC 24 |
| Finished | Sep 01 06:48:37 PM UTC 24 |
| Peak memory | 242460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127595850 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.4127595850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1803938989 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 304643581 ps |
| CPU time | 9.66 seconds |
| Started | Sep 01 06:47:34 PM UTC 24 |
| Finished | Sep 01 06:47:45 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803938989 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.1803938989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1546233794 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 259949415 ps |
| CPU time | 5.4 seconds |
| Started | Sep 01 06:47:32 PM UTC 24 |
| Finished | Sep 01 06:47:39 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546233794 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.1546233794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2464459220 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 181381748 ps |
| CPU time | 3.65 seconds |
| Started | Sep 01 06:47:32 PM UTC 24 |
| Finished | Sep 01 06:47:37 PM UTC 24 |
| Peak memory | 254728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464459220 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.2464459220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2988944000 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 559505451 ps |
| CPU time | 2.83 seconds |
| Started | Sep 01 06:47:32 PM UTC 24 |
| Finished | Sep 01 06:47:36 PM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988944000 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.2988944000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.2256367396 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 50102908 ps |
| CPU time | 2.11 seconds |
| Started | Sep 01 06:47:27 PM UTC 24 |
| Finished | Sep 01 06:47:30 PM UTC 24 |
| Peak memory | 241696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256367396 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.2256367396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3896745788 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 40212241 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 06:47:32 PM UTC 24 |
| Finished | Sep 01 06:47:35 PM UTC 24 |
| Peak memory | 240532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896745788 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.3896745788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2738716077 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 128236843 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 06:47:29 PM UTC 24 |
| Finished | Sep 01 06:47:32 PM UTC 24 |
| Peak memory | 241728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738716077 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.2738716077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.632557161 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 140394535 ps |
| CPU time | 3.65 seconds |
| Started | Sep 01 06:47:34 PM UTC 24 |
| Finished | Sep 01 06:47:39 PM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632557161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.632557161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3130797590 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 110707447 ps |
| CPU time | 6.37 seconds |
| Started | Sep 01 06:47:26 PM UTC 24 |
| Finished | Sep 01 06:47:33 PM UTC 24 |
| Peak memory | 258684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130797590 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.3130797590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2583920361 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 10364485562 ps |
| CPU time | 24.68 seconds |
| Started | Sep 01 06:47:27 PM UTC 24 |
| Finished | Sep 01 06:47:53 PM UTC 24 |
| Peak memory | 256916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583920361 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.2583920361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.2273850007 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 40026124 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 06:48:35 PM UTC 24 |
| Finished | Sep 01 06:48:38 PM UTC 24 |
| Peak memory | 241192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273850007 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.2273850007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.3857489133 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 58167504 ps |
| CPU time | 2.17 seconds |
| Started | Sep 01 06:48:35 PM UTC 24 |
| Finished | Sep 01 06:48:38 PM UTC 24 |
| Peak memory | 242604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857489133 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.3857489133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.1516795406 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 70944238 ps |
| CPU time | 2.3 seconds |
| Started | Sep 01 06:48:35 PM UTC 24 |
| Finished | Sep 01 06:48:38 PM UTC 24 |
| Peak memory | 242464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516795406 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1516795406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.902498018 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 38000385 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 06:48:36 PM UTC 24 |
| Finished | Sep 01 06:48:39 PM UTC 24 |
| Peak memory | 241684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902498018 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.902498018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.2486639832 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 568183873 ps |
| CPU time | 3.02 seconds |
| Started | Sep 01 06:48:36 PM UTC 24 |
| Finished | Sep 01 06:48:40 PM UTC 24 |
| Peak memory | 242128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486639832 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.2486639832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.4189343972 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 153558832 ps |
| CPU time | 2.16 seconds |
| Started | Sep 01 06:48:37 PM UTC 24 |
| Finished | Sep 01 06:48:40 PM UTC 24 |
| Peak memory | 242572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189343972 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.4189343972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.2382394929 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 42970418 ps |
| CPU time | 2.28 seconds |
| Started | Sep 01 06:48:37 PM UTC 24 |
| Finished | Sep 01 06:48:41 PM UTC 24 |
| Peak memory | 241640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382394929 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.2382394929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.153200548 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 74753018 ps |
| CPU time | 2.27 seconds |
| Started | Sep 01 06:48:37 PM UTC 24 |
| Finished | Sep 01 06:48:40 PM UTC 24 |
| Peak memory | 241744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153200548 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.153200548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.163811669 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 141984306 ps |
| CPU time | 2.48 seconds |
| Started | Sep 01 06:48:37 PM UTC 24 |
| Finished | Sep 01 06:48:41 PM UTC 24 |
| Peak memory | 241724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163811669 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.163811669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.3321293211 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 565921935 ps |
| CPU time | 2.54 seconds |
| Started | Sep 01 06:48:37 PM UTC 24 |
| Finished | Sep 01 06:48:41 PM UTC 24 |
| Peak memory | 242132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321293211 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.3321293211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.726623003 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 110618440 ps |
| CPU time | 5.99 seconds |
| Started | Sep 01 06:47:40 PM UTC 24 |
| Finished | Sep 01 06:47:47 PM UTC 24 |
| Peak memory | 254760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726623003 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.726623003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3240258527 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 716970815 ps |
| CPU time | 10.44 seconds |
| Started | Sep 01 06:47:40 PM UTC 24 |
| Finished | Sep 01 06:47:51 PM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240258527 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.3240258527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1498896913 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 125942642 ps |
| CPU time | 3.07 seconds |
| Started | Sep 01 06:47:39 PM UTC 24 |
| Finished | Sep 01 06:47:43 PM UTC 24 |
| Peak memory | 254740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498896913 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.1498896913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3042206528 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 221806649 ps |
| CPU time | 5.12 seconds |
| Started | Sep 01 06:47:42 PM UTC 24 |
| Finished | Sep 01 06:47:49 PM UTC 24 |
| Peak memory | 258856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3042206528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_cs r_mem_rw_with_rand_reset.3042206528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2821147369 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 41712969 ps |
| CPU time | 2.2 seconds |
| Started | Sep 01 06:47:39 PM UTC 24 |
| Finished | Sep 01 06:47:42 PM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821147369 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.2821147369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.355643275 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 70943616 ps |
| CPU time | 2.38 seconds |
| Started | Sep 01 06:47:36 PM UTC 24 |
| Finished | Sep 01 06:47:40 PM UTC 24 |
| Peak memory | 241952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355643275 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.355643275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.163011653 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 74024438 ps |
| CPU time | 2.26 seconds |
| Started | Sep 01 06:47:38 PM UTC 24 |
| Finished | Sep 01 06:47:41 PM UTC 24 |
| Peak memory | 241152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163011653 -assert nopostproc +U VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.163011653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2422908756 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 37836942 ps |
| CPU time | 2.1 seconds |
| Started | Sep 01 06:47:38 PM UTC 24 |
| Finished | Sep 01 06:47:41 PM UTC 24 |
| Peak memory | 242196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422908756 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.2422908756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1719316650 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2006374980 ps |
| CPU time | 7.99 seconds |
| Started | Sep 01 06:47:41 PM UTC 24 |
| Finished | Sep 01 06:47:50 PM UTC 24 |
| Peak memory | 252728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719316650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.1719316650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3477828659 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 1824527943 ps |
| CPU time | 10.04 seconds |
| Started | Sep 01 06:47:34 PM UTC 24 |
| Finished | Sep 01 06:47:45 PM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477828659 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3477828659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.924637787 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 9744628875 ps |
| CPU time | 17 seconds |
| Started | Sep 01 06:47:35 PM UTC 24 |
| Finished | Sep 01 06:47:54 PM UTC 24 |
| Peak memory | 256968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924637787 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.924637787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.770498753 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 38504034 ps |
| CPU time | 2.14 seconds |
| Started | Sep 01 06:48:37 PM UTC 24 |
| Finished | Sep 01 06:48:41 PM UTC 24 |
| Peak memory | 241968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770498753 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.770498753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.1707945621 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 144816675 ps |
| CPU time | 2.44 seconds |
| Started | Sep 01 06:48:38 PM UTC 24 |
| Finished | Sep 01 06:48:42 PM UTC 24 |
| Peak memory | 242136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707945621 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.1707945621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.2320801778 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 96044550 ps |
| CPU time | 2.24 seconds |
| Started | Sep 01 06:48:39 PM UTC 24 |
| Finished | Sep 01 06:48:42 PM UTC 24 |
| Peak memory | 242476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320801778 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2320801778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.333034656 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 57180544 ps |
| CPU time | 2.39 seconds |
| Started | Sep 01 06:48:39 PM UTC 24 |
| Finished | Sep 01 06:48:42 PM UTC 24 |
| Peak memory | 241824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333034656 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.333034656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.1496713923 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 152627302 ps |
| CPU time | 2.2 seconds |
| Started | Sep 01 06:48:39 PM UTC 24 |
| Finished | Sep 01 06:48:42 PM UTC 24 |
| Peak memory | 242112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496713923 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.1496713923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.4154244125 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 72413627 ps |
| CPU time | 2.12 seconds |
| Started | Sep 01 06:48:40 PM UTC 24 |
| Finished | Sep 01 06:48:43 PM UTC 24 |
| Peak memory | 241996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154244125 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.4154244125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.4008216258 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 140164016 ps |
| CPU time | 2.42 seconds |
| Started | Sep 01 06:48:40 PM UTC 24 |
| Finished | Sep 01 06:48:43 PM UTC 24 |
| Peak memory | 242604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008216258 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.4008216258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.63654739 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 71167230 ps |
| CPU time | 2.3 seconds |
| Started | Sep 01 06:48:41 PM UTC 24 |
| Finished | Sep 01 06:48:44 PM UTC 24 |
| Peak memory | 241712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63654739 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.63654739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.1307492299 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 132968655 ps |
| CPU time | 2.19 seconds |
| Started | Sep 01 06:48:41 PM UTC 24 |
| Finished | Sep 01 06:48:44 PM UTC 24 |
| Peak memory | 241720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307492299 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.1307492299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.808082101 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 59281088 ps |
| CPU time | 2.24 seconds |
| Started | Sep 01 06:48:41 PM UTC 24 |
| Finished | Sep 01 06:48:44 PM UTC 24 |
| Peak memory | 241680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808082101 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.808082101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.1875989648 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 74653022 ps |
| CPU time | 4.26 seconds |
| Started | Sep 01 06:47:44 PM UTC 24 |
| Finished | Sep 01 06:47:49 PM UTC 24 |
| Peak memory | 258876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1875989648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_cs r_mem_rw_with_rand_reset.1875989648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1375771501 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 46171638 ps |
| CPU time | 2.48 seconds |
| Started | Sep 01 06:47:43 PM UTC 24 |
| Finished | Sep 01 06:47:46 PM UTC 24 |
| Peak memory | 254676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375771501 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.1375771501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.342084936 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 50752168 ps |
| CPU time | 2.32 seconds |
| Started | Sep 01 06:47:42 PM UTC 24 |
| Finished | Sep 01 06:47:46 PM UTC 24 |
| Peak memory | 242464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342084936 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.342084936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3006246778 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 195945252 ps |
| CPU time | 3.57 seconds |
| Started | Sep 01 06:47:44 PM UTC 24 |
| Finished | Sep 01 06:47:48 PM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006246778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.3006246778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3872947173 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 104391762 ps |
| CPU time | 4.4 seconds |
| Started | Sep 01 06:47:42 PM UTC 24 |
| Finished | Sep 01 06:47:48 PM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872947173 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.3872947173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2865296312 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 640308731 ps |
| CPU time | 13.24 seconds |
| Started | Sep 01 06:47:42 PM UTC 24 |
| Finished | Sep 01 06:47:57 PM UTC 24 |
| Peak memory | 256972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865296312 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.2865296312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3592481266 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 107444631 ps |
| CPU time | 6.23 seconds |
| Started | Sep 01 06:47:48 PM UTC 24 |
| Finished | Sep 01 06:47:56 PM UTC 24 |
| Peak memory | 258876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3592481266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_cs r_mem_rw_with_rand_reset.3592481266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2569713056 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 42023915 ps |
| CPU time | 2.51 seconds |
| Started | Sep 01 06:47:47 PM UTC 24 |
| Finished | Sep 01 06:47:51 PM UTC 24 |
| Peak memory | 254756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569713056 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2569713056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.4221541820 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 77573366 ps |
| CPU time | 2.31 seconds |
| Started | Sep 01 06:47:47 PM UTC 24 |
| Finished | Sep 01 06:47:50 PM UTC 24 |
| Peak memory | 241736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221541820 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.4221541820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1206276516 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 83912429 ps |
| CPU time | 4.5 seconds |
| Started | Sep 01 06:47:47 PM UTC 24 |
| Finished | Sep 01 06:47:53 PM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206276516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.1206276516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.505079730 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 689702521 ps |
| CPU time | 6.79 seconds |
| Started | Sep 01 06:47:46 PM UTC 24 |
| Finished | Sep 01 06:47:54 PM UTC 24 |
| Peak memory | 258952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505079730 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.505079730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.306776363 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 19862572362 ps |
| CPU time | 63.5 seconds |
| Started | Sep 01 06:47:46 PM UTC 24 |
| Finished | Sep 01 06:48:52 PM UTC 24 |
| Peak memory | 259032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306776363 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.306776363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.464872681 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 1745465033 ps |
| CPU time | 4.5 seconds |
| Started | Sep 01 06:47:51 PM UTC 24 |
| Finished | Sep 01 06:47:56 PM UTC 24 |
| Peak memory | 258936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=464872681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr _mem_rw_with_rand_reset.464872681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3082937942 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 47804045 ps |
| CPU time | 2.57 seconds |
| Started | Sep 01 06:47:50 PM UTC 24 |
| Finished | Sep 01 06:47:53 PM UTC 24 |
| Peak memory | 252716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082937942 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3082937942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.3437536276 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 599849856 ps |
| CPU time | 2.98 seconds |
| Started | Sep 01 06:47:50 PM UTC 24 |
| Finished | Sep 01 06:47:53 PM UTC 24 |
| Peak memory | 242472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437536276 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3437536276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3374689069 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 77927906 ps |
| CPU time | 3.82 seconds |
| Started | Sep 01 06:47:50 PM UTC 24 |
| Finished | Sep 01 06:47:54 PM UTC 24 |
| Peak memory | 252832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374689069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.3374689069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2013539365 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 251845971 ps |
| CPU time | 8 seconds |
| Started | Sep 01 06:47:48 PM UTC 24 |
| Finished | Sep 01 06:47:57 PM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013539365 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.2013539365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2073782384 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 132407740 ps |
| CPU time | 3.47 seconds |
| Started | Sep 01 06:47:54 PM UTC 24 |
| Finished | Sep 01 06:47:59 PM UTC 24 |
| Peak memory | 259016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2073782384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_cs r_mem_rw_with_rand_reset.2073782384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3853570799 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 78617257 ps |
| CPU time | 2.49 seconds |
| Started | Sep 01 06:47:52 PM UTC 24 |
| Finished | Sep 01 06:47:55 PM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853570799 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.3853570799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.1926687923 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 138415603 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 06:47:52 PM UTC 24 |
| Finished | Sep 01 06:47:55 PM UTC 24 |
| Peak memory | 241744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926687923 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.1926687923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.1510085148 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 1794283693 ps |
| CPU time | 9.87 seconds |
| Started | Sep 01 06:47:53 PM UTC 24 |
| Finished | Sep 01 06:48:04 PM UTC 24 |
| Peak memory | 254804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510085148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.1510085148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.1112217145 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 378132136 ps |
| CPU time | 7.11 seconds |
| Started | Sep 01 06:47:51 PM UTC 24 |
| Finished | Sep 01 06:47:59 PM UTC 24 |
| Peak memory | 259000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112217145 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.1112217145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3770276238 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 75582102 ps |
| CPU time | 3.82 seconds |
| Started | Sep 01 06:47:56 PM UTC 24 |
| Finished | Sep 01 06:48:01 PM UTC 24 |
| Peak memory | 258980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3770276238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_cs r_mem_rw_with_rand_reset.3770276238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.926939959 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 38431286 ps |
| CPU time | 2.34 seconds |
| Started | Sep 01 06:47:54 PM UTC 24 |
| Finished | Sep 01 06:47:58 PM UTC 24 |
| Peak memory | 252720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926939959 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.926939959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.1872525549 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 88085269 ps |
| CPU time | 2.39 seconds |
| Started | Sep 01 06:47:54 PM UTC 24 |
| Finished | Sep 01 06:47:58 PM UTC 24 |
| Peak memory | 242020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872525549 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1872525549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3934777807 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 446969340 ps |
| CPU time | 6.14 seconds |
| Started | Sep 01 06:47:55 PM UTC 24 |
| Finished | Sep 01 06:48:03 PM UTC 24 |
| Peak memory | 252732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934777807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.3934777807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1823977414 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 250645840 ps |
| CPU time | 9.39 seconds |
| Started | Sep 01 06:47:54 PM UTC 24 |
| Finished | Sep 01 06:48:05 PM UTC 24 |
| Peak memory | 259080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823977414 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.1823977414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3505804499 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5261744739 ps |
| CPU time | 29 seconds |
| Started | Sep 01 06:47:54 PM UTC 24 |
| Finished | Sep 01 06:48:25 PM UTC 24 |
| Peak memory | 256924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505804499 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.3505804499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.3181629561 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 54395723 ps |
| CPU time | 2.36 seconds |
| Started | Sep 01 06:48:50 PM UTC 24 |
| Finished | Sep 01 06:48:54 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181629561 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.3181629561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.1277499536 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 252274051 ps |
| CPU time | 16.71 seconds |
| Started | Sep 01 06:48:44 PM UTC 24 |
| Finished | Sep 01 06:49:02 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277499536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.1277499536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.3139692240 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2768349023 ps |
| CPU time | 39.08 seconds |
| Started | Sep 01 06:48:44 PM UTC 24 |
| Finished | Sep 01 06:49:25 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139692240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3139692240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.1662892785 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 5924255319 ps |
| CPU time | 21.66 seconds |
| Started | Sep 01 06:48:42 PM UTC 24 |
| Finished | Sep 01 06:49:06 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662892785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.1662892785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.1232470587 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2450146456 ps |
| CPU time | 6.14 seconds |
| Started | Sep 01 06:48:43 PM UTC 24 |
| Finished | Sep 01 06:48:51 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232470587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.1232470587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.3643639428 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 709782484 ps |
| CPU time | 26.33 seconds |
| Started | Sep 01 06:48:42 PM UTC 24 |
| Finished | Sep 01 06:49:11 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643639428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.3643639428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.3547348905 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 154565225312 ps |
| CPU time | 390.14 seconds |
| Started | Sep 01 06:48:50 PM UTC 24 |
| Finished | Sep 01 06:55:26 PM UTC 24 |
| Peak memory | 287928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547348905 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.3547348905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.789660120 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 556830863 ps |
| CPU time | 6.58 seconds |
| Started | Sep 01 06:48:42 PM UTC 24 |
| Finished | Sep 01 06:48:51 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789660120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.789660120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.1909510983 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 18354112459 ps |
| CPU time | 203.82 seconds |
| Started | Sep 01 06:48:45 PM UTC 24 |
| Finished | Sep 01 06:52:13 PM UTC 24 |
| Peak memory | 257964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1909510983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.otp_ctrl_stress_all_with_rand_reset.1909510983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.3817135388 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6694962407 ps |
| CPU time | 70.68 seconds |
| Started | Sep 01 06:48:45 PM UTC 24 |
| Finished | Sep 01 06:49:58 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817135388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.3817135388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.678013296 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 589788614 ps |
| CPU time | 2.96 seconds |
| Started | Sep 01 06:49:14 PM UTC 24 |
| Finished | Sep 01 06:49:18 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678013296 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.678013296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.3682616595 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 11347158040 ps |
| CPU time | 73.4 seconds |
| Started | Sep 01 06:48:53 PM UTC 24 |
| Finished | Sep 01 06:50:08 PM UTC 24 |
| Peak memory | 253492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682616595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.3682616595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.755474175 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2346670030 ps |
| CPU time | 24.12 seconds |
| Started | Sep 01 06:48:59 PM UTC 24 |
| Finished | Sep 01 06:49:25 PM UTC 24 |
| Peak memory | 253496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755474175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.755474175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.625247516 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7063651322 ps |
| CPU time | 33.26 seconds |
| Started | Sep 01 06:48:57 PM UTC 24 |
| Finished | Sep 01 06:49:32 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625247516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.625247516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.3811963094 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2106351508 ps |
| CPU time | 16.51 seconds |
| Started | Sep 01 06:49:04 PM UTC 24 |
| Finished | Sep 01 06:49:22 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811963094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.3811963094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.4050625664 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3263746120 ps |
| CPU time | 12.45 seconds |
| Started | Sep 01 06:49:05 PM UTC 24 |
| Finished | Sep 01 06:49:18 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050625664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.4050625664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.1632882064 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 240573046 ps |
| CPU time | 4.46 seconds |
| Started | Sep 01 06:49:07 PM UTC 24 |
| Finished | Sep 01 06:49:12 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632882064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.1632882064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.1065214613 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 352221009 ps |
| CPU time | 11.64 seconds |
| Started | Sep 01 06:48:51 PM UTC 24 |
| Finished | Sep 01 06:49:04 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065214613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.1065214613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.290234001 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 343629506 ps |
| CPU time | 2.99 seconds |
| Started | Sep 01 06:52:37 PM UTC 24 |
| Finished | Sep 01 06:52:41 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290234001 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.290234001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.2059264412 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1653275545 ps |
| CPU time | 39.94 seconds |
| Started | Sep 01 06:52:27 PM UTC 24 |
| Finished | Sep 01 06:53:09 PM UTC 24 |
| Peak memory | 255484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059264412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.2059264412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.1615037448 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 3095035163 ps |
| CPU time | 39.21 seconds |
| Started | Sep 01 06:52:27 PM UTC 24 |
| Finished | Sep 01 06:53:08 PM UTC 24 |
| Peak memory | 251364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615037448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.1615037448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.308352007 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1809457611 ps |
| CPU time | 5.5 seconds |
| Started | Sep 01 06:52:21 PM UTC 24 |
| Finished | Sep 01 06:52:27 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308352007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.308352007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.3058240680 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1306502210 ps |
| CPU time | 42.83 seconds |
| Started | Sep 01 06:52:27 PM UTC 24 |
| Finished | Sep 01 06:53:12 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058240680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.3058240680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.4066913448 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 141198625 ps |
| CPU time | 6.62 seconds |
| Started | Sep 01 06:52:27 PM UTC 24 |
| Finished | Sep 01 06:52:35 PM UTC 24 |
| Peak memory | 251104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066913448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.4066913448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.3537892498 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2638261751 ps |
| CPU time | 25.39 seconds |
| Started | Sep 01 06:52:22 PM UTC 24 |
| Finished | Sep 01 06:52:49 PM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537892498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.3537892498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.2275697588 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 899133509 ps |
| CPU time | 9.53 seconds |
| Started | Sep 01 06:52:28 PM UTC 24 |
| Finished | Sep 01 06:52:39 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275697588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.2275697588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.828178440 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 278287499 ps |
| CPU time | 10.44 seconds |
| Started | Sep 01 06:52:21 PM UTC 24 |
| Finished | Sep 01 06:52:32 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828178440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.828178440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.954089135 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1680802209 ps |
| CPU time | 33 seconds |
| Started | Sep 01 06:52:33 PM UTC 24 |
| Finished | Sep 01 06:53:08 PM UTC 24 |
| Peak memory | 253652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954089135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.954089135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.4022539376 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 487816528 ps |
| CPU time | 7.23 seconds |
| Started | Sep 01 07:02:07 PM UTC 24 |
| Finished | Sep 01 07:02:15 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022539376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.4022539376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.1241555949 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 982899895 ps |
| CPU time | 14.07 seconds |
| Started | Sep 01 07:02:10 PM UTC 24 |
| Finished | Sep 01 07:02:26 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241555949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.1241555949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.3550212272 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 82714939 ps |
| CPU time | 4.16 seconds |
| Started | Sep 01 07:02:10 PM UTC 24 |
| Finished | Sep 01 07:02:16 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550212272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3550212272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.350209109 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 1525506077 ps |
| CPU time | 25.25 seconds |
| Started | Sep 01 07:02:10 PM UTC 24 |
| Finished | Sep 01 07:02:37 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350209109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.350209109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.3884266286 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 223256847 ps |
| CPU time | 9.59 seconds |
| Started | Sep 01 07:02:11 PM UTC 24 |
| Finished | Sep 01 07:02:21 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884266286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.3884266286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.300054425 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 306194323 ps |
| CPU time | 5.92 seconds |
| Started | Sep 01 07:02:13 PM UTC 24 |
| Finished | Sep 01 07:02:20 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300054425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.300054425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.200705300 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2550485728 ps |
| CPU time | 10.71 seconds |
| Started | Sep 01 07:02:13 PM UTC 24 |
| Finished | Sep 01 07:02:25 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200705300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.200705300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.280235937 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 2023081707 ps |
| CPU time | 16.24 seconds |
| Started | Sep 01 07:02:15 PM UTC 24 |
| Finished | Sep 01 07:02:32 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280235937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.280235937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.912425800 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 94809256 ps |
| CPU time | 4.45 seconds |
| Started | Sep 01 07:02:15 PM UTC 24 |
| Finished | Sep 01 07:02:20 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912425800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.912425800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.3619704488 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 1001660040 ps |
| CPU time | 32.96 seconds |
| Started | Sep 01 07:02:15 PM UTC 24 |
| Finished | Sep 01 07:02:49 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619704488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3619704488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.744887248 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 104512505 ps |
| CPU time | 3.24 seconds |
| Started | Sep 01 07:02:17 PM UTC 24 |
| Finished | Sep 01 07:02:21 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744887248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.744887248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.3817914337 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 168532906 ps |
| CPU time | 4.73 seconds |
| Started | Sep 01 07:02:17 PM UTC 24 |
| Finished | Sep 01 07:02:23 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817914337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.3817914337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.2919185000 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 7150957425 ps |
| CPU time | 14.01 seconds |
| Started | Sep 01 07:02:22 PM UTC 24 |
| Finished | Sep 01 07:02:37 PM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919185000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.2919185000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.3747202495 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 354497203 ps |
| CPU time | 3.5 seconds |
| Started | Sep 01 07:02:22 PM UTC 24 |
| Finished | Sep 01 07:02:26 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747202495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.3747202495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.2233403644 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 17160399875 ps |
| CPU time | 60.07 seconds |
| Started | Sep 01 07:02:22 PM UTC 24 |
| Finished | Sep 01 07:03:24 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233403644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2233403644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.3313843198 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 131029985 ps |
| CPU time | 3.08 seconds |
| Started | Sep 01 06:52:53 PM UTC 24 |
| Finished | Sep 01 06:52:57 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313843198 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.3313843198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.2813405801 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 5135645511 ps |
| CPU time | 52.64 seconds |
| Started | Sep 01 06:52:51 PM UTC 24 |
| Finished | Sep 01 06:53:45 PM UTC 24 |
| Peak memory | 257588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813405801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2813405801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.1133829006 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 8881348269 ps |
| CPU time | 28.36 seconds |
| Started | Sep 01 06:52:44 PM UTC 24 |
| Finished | Sep 01 06:53:14 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133829006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1133829006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.1230137543 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 3565534379 ps |
| CPU time | 11.08 seconds |
| Started | Sep 01 06:52:41 PM UTC 24 |
| Finished | Sep 01 06:52:54 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230137543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.1230137543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.4279136149 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1431721849 ps |
| CPU time | 8.43 seconds |
| Started | Sep 01 06:52:39 PM UTC 24 |
| Finished | Sep 01 06:52:48 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279136149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.4279136149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.2498216456 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1885391970 ps |
| CPU time | 29.2 seconds |
| Started | Sep 01 06:52:51 PM UTC 24 |
| Finished | Sep 01 06:53:21 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498216456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.2498216456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.4020439546 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 953960692 ps |
| CPU time | 17.29 seconds |
| Started | Sep 01 06:52:51 PM UTC 24 |
| Finished | Sep 01 06:53:09 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020439546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.4020439546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.3860741747 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 294073344 ps |
| CPU time | 7.58 seconds |
| Started | Sep 01 06:52:40 PM UTC 24 |
| Finished | Sep 01 06:52:49 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860741747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.3860741747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.2032920147 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 805906655 ps |
| CPU time | 16.99 seconds |
| Started | Sep 01 06:52:40 PM UTC 24 |
| Finished | Sep 01 06:52:59 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032920147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.2032920147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.1920826457 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 187946337 ps |
| CPU time | 8.12 seconds |
| Started | Sep 01 06:52:51 PM UTC 24 |
| Finished | Sep 01 06:53:00 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920826457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1920826457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.3649864958 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 243758504 ps |
| CPU time | 4.36 seconds |
| Started | Sep 01 06:52:37 PM UTC 24 |
| Finished | Sep 01 06:52:43 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649864958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.3649864958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.2177243761 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 232031155 ps |
| CPU time | 5.52 seconds |
| Started | Sep 01 07:02:22 PM UTC 24 |
| Finished | Sep 01 07:02:29 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177243761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2177243761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.1687941251 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 577579058 ps |
| CPU time | 5.79 seconds |
| Started | Sep 01 07:02:22 PM UTC 24 |
| Finished | Sep 01 07:02:29 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687941251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.1687941251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.2662644210 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 266269252 ps |
| CPU time | 4.31 seconds |
| Started | Sep 01 07:02:22 PM UTC 24 |
| Finished | Sep 01 07:02:28 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662644210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.2662644210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.4052420629 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 3344111011 ps |
| CPU time | 16.05 seconds |
| Started | Sep 01 07:02:22 PM UTC 24 |
| Finished | Sep 01 07:02:40 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052420629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.4052420629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.838805376 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 325818409 ps |
| CPU time | 4.4 seconds |
| Started | Sep 01 07:02:22 PM UTC 24 |
| Finished | Sep 01 07:02:28 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838805376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.838805376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.3007128757 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 1528439807 ps |
| CPU time | 4.28 seconds |
| Started | Sep 01 07:02:22 PM UTC 24 |
| Finished | Sep 01 07:02:28 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007128757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3007128757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.232465634 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 126621177 ps |
| CPU time | 5.28 seconds |
| Started | Sep 01 07:02:24 PM UTC 24 |
| Finished | Sep 01 07:02:30 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232465634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.232465634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.3165886963 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 238778652 ps |
| CPU time | 6.56 seconds |
| Started | Sep 01 07:02:24 PM UTC 24 |
| Finished | Sep 01 07:02:32 PM UTC 24 |
| Peak memory | 257304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165886963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.3165886963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.2826814090 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 10110638401 ps |
| CPU time | 33.7 seconds |
| Started | Sep 01 07:02:24 PM UTC 24 |
| Finished | Sep 01 07:02:59 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826814090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.2826814090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.2270061604 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 2033126993 ps |
| CPU time | 6.26 seconds |
| Started | Sep 01 07:02:24 PM UTC 24 |
| Finished | Sep 01 07:02:32 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270061604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.2270061604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.2972672790 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 233240192 ps |
| CPU time | 7.18 seconds |
| Started | Sep 01 07:02:27 PM UTC 24 |
| Finished | Sep 01 07:02:35 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972672790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.2972672790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.1895967601 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2286342197 ps |
| CPU time | 5.01 seconds |
| Started | Sep 01 07:02:27 PM UTC 24 |
| Finished | Sep 01 07:02:33 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895967601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.1895967601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.3801930699 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 157896039 ps |
| CPU time | 8.15 seconds |
| Started | Sep 01 07:02:27 PM UTC 24 |
| Finished | Sep 01 07:02:37 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801930699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.3801930699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.620300918 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 233555527 ps |
| CPU time | 5.68 seconds |
| Started | Sep 01 07:02:27 PM UTC 24 |
| Finished | Sep 01 07:02:34 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620300918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.620300918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.1002291422 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 135304022 ps |
| CPU time | 3.01 seconds |
| Started | Sep 01 07:02:27 PM UTC 24 |
| Finished | Sep 01 07:02:31 PM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002291422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.1002291422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.520856855 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 329890615 ps |
| CPU time | 5.3 seconds |
| Started | Sep 01 07:02:29 PM UTC 24 |
| Finished | Sep 01 07:02:35 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520856855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.520856855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.2131802811 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 631268986 ps |
| CPU time | 8.54 seconds |
| Started | Sep 01 07:02:29 PM UTC 24 |
| Finished | Sep 01 07:02:38 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131802811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2131802811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.4030509890 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 582318953 ps |
| CPU time | 4.99 seconds |
| Started | Sep 01 07:02:29 PM UTC 24 |
| Finished | Sep 01 07:02:35 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030509890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.4030509890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.484282307 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 2408212845 ps |
| CPU time | 7.07 seconds |
| Started | Sep 01 07:02:29 PM UTC 24 |
| Finished | Sep 01 07:02:37 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484282307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.484282307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.4079007480 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 332523557 ps |
| CPU time | 2.88 seconds |
| Started | Sep 01 06:53:11 PM UTC 24 |
| Finished | Sep 01 06:53:15 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079007480 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.4079007480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.3857019102 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 176764806 ps |
| CPU time | 5.49 seconds |
| Started | Sep 01 06:53:01 PM UTC 24 |
| Finished | Sep 01 06:53:08 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857019102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.3857019102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.552031130 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 743517139 ps |
| CPU time | 15.25 seconds |
| Started | Sep 01 06:53:00 PM UTC 24 |
| Finished | Sep 01 06:53:17 PM UTC 24 |
| Peak memory | 251132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552031130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.552031130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.983593920 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 817870884 ps |
| CPU time | 9.57 seconds |
| Started | Sep 01 06:52:59 PM UTC 24 |
| Finished | Sep 01 06:53:10 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983593920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.983593920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.1122392641 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 153155082 ps |
| CPU time | 6.18 seconds |
| Started | Sep 01 06:52:55 PM UTC 24 |
| Finished | Sep 01 06:53:02 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122392641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1122392641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.934589004 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 221167477 ps |
| CPU time | 7.95 seconds |
| Started | Sep 01 06:53:03 PM UTC 24 |
| Finished | Sep 01 06:53:12 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934589004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.934589004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.4227614099 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 342023220 ps |
| CPU time | 5.2 seconds |
| Started | Sep 01 06:53:03 PM UTC 24 |
| Finished | Sep 01 06:53:09 PM UTC 24 |
| Peak memory | 257436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227614099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.4227614099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.928395730 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 770506425 ps |
| CPU time | 23.62 seconds |
| Started | Sep 01 06:52:57 PM UTC 24 |
| Finished | Sep 01 06:53:22 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928395730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.928395730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.3261795629 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 277566656 ps |
| CPU time | 10.44 seconds |
| Started | Sep 01 06:52:57 PM UTC 24 |
| Finished | Sep 01 06:53:09 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261795629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.3261795629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.2499987837 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 294012856 ps |
| CPU time | 8.54 seconds |
| Started | Sep 01 06:53:07 PM UTC 24 |
| Finished | Sep 01 06:53:17 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499987837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2499987837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.2439895815 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 505831896 ps |
| CPU time | 17.31 seconds |
| Started | Sep 01 06:52:55 PM UTC 24 |
| Finished | Sep 01 06:53:14 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439895815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2439895815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.1390103962 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 7016381201 ps |
| CPU time | 20.02 seconds |
| Started | Sep 01 06:53:11 PM UTC 24 |
| Finished | Sep 01 06:53:33 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390103962 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.1390103962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.204076925 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 8366864225 ps |
| CPU time | 24.45 seconds |
| Started | Sep 01 06:53:09 PM UTC 24 |
| Finished | Sep 01 06:53:35 PM UTC 24 |
| Peak memory | 253460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204076925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.204076925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.1351850132 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 101175862 ps |
| CPU time | 5.49 seconds |
| Started | Sep 01 07:02:30 PM UTC 24 |
| Finished | Sep 01 07:02:37 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351850132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.1351850132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.1494649984 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 97516392 ps |
| CPU time | 4.16 seconds |
| Started | Sep 01 07:02:31 PM UTC 24 |
| Finished | Sep 01 07:02:36 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494649984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.1494649984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.4029484244 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 7580160188 ps |
| CPU time | 15.9 seconds |
| Started | Sep 01 07:02:33 PM UTC 24 |
| Finished | Sep 01 07:02:51 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029484244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.4029484244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.1276927132 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 248265416 ps |
| CPU time | 5.3 seconds |
| Started | Sep 01 07:02:33 PM UTC 24 |
| Finished | Sep 01 07:02:40 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276927132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.1276927132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.1893252288 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 498246636 ps |
| CPU time | 3.97 seconds |
| Started | Sep 01 07:02:33 PM UTC 24 |
| Finished | Sep 01 07:02:39 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893252288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.1893252288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.627936082 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 211900630 ps |
| CPU time | 4.43 seconds |
| Started | Sep 01 07:02:33 PM UTC 24 |
| Finished | Sep 01 07:02:39 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627936082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.627936082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.1108570410 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 812475837 ps |
| CPU time | 6.54 seconds |
| Started | Sep 01 07:02:33 PM UTC 24 |
| Finished | Sep 01 07:02:42 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108570410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.1108570410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.1745733272 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 264912567 ps |
| CPU time | 4.58 seconds |
| Started | Sep 01 07:02:35 PM UTC 24 |
| Finished | Sep 01 07:02:42 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745733272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.1745733272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.576733260 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 1818060787 ps |
| CPU time | 4.88 seconds |
| Started | Sep 01 07:02:35 PM UTC 24 |
| Finished | Sep 01 07:02:42 PM UTC 24 |
| Peak memory | 251044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576733260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.576733260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.3169392518 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 175937009 ps |
| CPU time | 5.28 seconds |
| Started | Sep 01 07:02:35 PM UTC 24 |
| Finished | Sep 01 07:02:43 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169392518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.3169392518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.2069597196 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 656578573 ps |
| CPU time | 21 seconds |
| Started | Sep 01 07:02:39 PM UTC 24 |
| Finished | Sep 01 07:03:02 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069597196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.2069597196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.728872055 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 323976359 ps |
| CPU time | 3.66 seconds |
| Started | Sep 01 07:02:39 PM UTC 24 |
| Finished | Sep 01 07:02:44 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728872055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.728872055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.306112967 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 1790628899 ps |
| CPU time | 18.78 seconds |
| Started | Sep 01 07:02:39 PM UTC 24 |
| Finished | Sep 01 07:02:59 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306112967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.306112967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.3362778117 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 232805955 ps |
| CPU time | 4.78 seconds |
| Started | Sep 01 07:02:39 PM UTC 24 |
| Finished | Sep 01 07:02:45 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362778117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.3362778117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.868127930 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 415995629 ps |
| CPU time | 6.7 seconds |
| Started | Sep 01 07:02:39 PM UTC 24 |
| Finished | Sep 01 07:02:47 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868127930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.868127930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.1623442671 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 193529561 ps |
| CPU time | 5.55 seconds |
| Started | Sep 01 07:02:39 PM UTC 24 |
| Finished | Sep 01 07:02:46 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623442671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.1623442671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.145433968 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 603019949 ps |
| CPU time | 8.06 seconds |
| Started | Sep 01 07:02:39 PM UTC 24 |
| Finished | Sep 01 07:02:49 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145433968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.145433968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.1404826237 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1747243033 ps |
| CPU time | 5.58 seconds |
| Started | Sep 01 07:02:39 PM UTC 24 |
| Finished | Sep 01 07:02:46 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404826237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.1404826237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.3654080611 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 119648928 ps |
| CPU time | 4.99 seconds |
| Started | Sep 01 07:02:39 PM UTC 24 |
| Finished | Sep 01 07:02:46 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654080611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.3654080611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.39086678 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 92929346 ps |
| CPU time | 2.7 seconds |
| Started | Sep 01 06:53:19 PM UTC 24 |
| Finished | Sep 01 06:53:22 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39086678 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.39086678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.1754892450 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 572170723 ps |
| CPU time | 12.11 seconds |
| Started | Sep 01 06:53:18 PM UTC 24 |
| Finished | Sep 01 06:53:31 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754892450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.1754892450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.4132107856 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 274878905 ps |
| CPU time | 10.23 seconds |
| Started | Sep 01 06:53:18 PM UTC 24 |
| Finished | Sep 01 06:53:29 PM UTC 24 |
| Peak memory | 250708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132107856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.4132107856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.2442969809 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 409716583 ps |
| CPU time | 10.36 seconds |
| Started | Sep 01 06:53:18 PM UTC 24 |
| Finished | Sep 01 06:53:29 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442969809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.2442969809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.3684222815 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 553816082 ps |
| CPU time | 5.13 seconds |
| Started | Sep 01 06:53:11 PM UTC 24 |
| Finished | Sep 01 06:53:18 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684222815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.3684222815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.259640588 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 24104754587 ps |
| CPU time | 60.25 seconds |
| Started | Sep 01 06:53:18 PM UTC 24 |
| Finished | Sep 01 06:54:20 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259640588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.259640588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.2799454725 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 404097130 ps |
| CPU time | 14.91 seconds |
| Started | Sep 01 06:53:18 PM UTC 24 |
| Finished | Sep 01 06:53:34 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799454725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.2799454725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.2188359173 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 527768672 ps |
| CPU time | 11.13 seconds |
| Started | Sep 01 06:53:12 PM UTC 24 |
| Finished | Sep 01 06:53:24 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188359173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.2188359173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.948646108 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 347224571 ps |
| CPU time | 11.78 seconds |
| Started | Sep 01 06:53:12 PM UTC 24 |
| Finished | Sep 01 06:53:24 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948646108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.948646108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.595682954 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 121338850 ps |
| CPU time | 5.96 seconds |
| Started | Sep 01 06:53:18 PM UTC 24 |
| Finished | Sep 01 06:53:25 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595682954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.595682954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.4015664315 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1395641583 ps |
| CPU time | 6.32 seconds |
| Started | Sep 01 06:53:11 PM UTC 24 |
| Finished | Sep 01 06:53:19 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015664315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.4015664315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.1171848973 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 7335620989 ps |
| CPU time | 20.63 seconds |
| Started | Sep 01 06:53:18 PM UTC 24 |
| Finished | Sep 01 06:53:40 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171848973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.1171848973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.2746171707 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 2694042326 ps |
| CPU time | 6.57 seconds |
| Started | Sep 01 07:02:40 PM UTC 24 |
| Finished | Sep 01 07:02:47 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746171707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.2746171707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.2310452279 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 309921417 ps |
| CPU time | 11.03 seconds |
| Started | Sep 01 07:02:40 PM UTC 24 |
| Finished | Sep 01 07:02:52 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310452279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2310452279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.187646452 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 2011672018 ps |
| CPU time | 4.11 seconds |
| Started | Sep 01 07:02:40 PM UTC 24 |
| Finished | Sep 01 07:02:45 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187646452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.187646452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.1634070993 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 430549734 ps |
| CPU time | 9.31 seconds |
| Started | Sep 01 07:02:40 PM UTC 24 |
| Finished | Sep 01 07:02:50 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634070993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.1634070993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.1356451194 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 791622231 ps |
| CPU time | 19.01 seconds |
| Started | Sep 01 07:02:41 PM UTC 24 |
| Finished | Sep 01 07:03:02 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356451194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.1356451194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.2022770577 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 305951863 ps |
| CPU time | 5.17 seconds |
| Started | Sep 01 07:02:41 PM UTC 24 |
| Finished | Sep 01 07:02:48 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022770577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.2022770577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.8741085 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 732880421 ps |
| CPU time | 13.45 seconds |
| Started | Sep 01 07:02:42 PM UTC 24 |
| Finished | Sep 01 07:02:56 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8741085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.8741085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.168712435 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 452780069 ps |
| CPU time | 5.76 seconds |
| Started | Sep 01 07:02:42 PM UTC 24 |
| Finished | Sep 01 07:02:49 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168712435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.168712435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.130822877 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 1372705490 ps |
| CPU time | 12.01 seconds |
| Started | Sep 01 07:02:43 PM UTC 24 |
| Finished | Sep 01 07:02:56 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130822877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.130822877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.341391753 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 261618468 ps |
| CPU time | 4.2 seconds |
| Started | Sep 01 07:02:43 PM UTC 24 |
| Finished | Sep 01 07:02:49 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341391753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.341391753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.3843116431 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 264733023 ps |
| CPU time | 7.36 seconds |
| Started | Sep 01 07:02:43 PM UTC 24 |
| Finished | Sep 01 07:02:52 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843116431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.3843116431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.3616772995 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 125033324 ps |
| CPU time | 3.77 seconds |
| Started | Sep 01 07:02:43 PM UTC 24 |
| Finished | Sep 01 07:02:48 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616772995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.3616772995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.4264586717 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 683568033 ps |
| CPU time | 13.02 seconds |
| Started | Sep 01 07:02:45 PM UTC 24 |
| Finished | Sep 01 07:02:59 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264586717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.4264586717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.1323075953 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2665392292 ps |
| CPU time | 5.87 seconds |
| Started | Sep 01 07:02:45 PM UTC 24 |
| Finished | Sep 01 07:02:52 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323075953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.1323075953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.3393580520 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 550396188 ps |
| CPU time | 8.18 seconds |
| Started | Sep 01 07:02:45 PM UTC 24 |
| Finished | Sep 01 07:02:54 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393580520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.3393580520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.1123783980 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 1855094349 ps |
| CPU time | 7.65 seconds |
| Started | Sep 01 07:02:47 PM UTC 24 |
| Finished | Sep 01 07:02:55 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123783980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.1123783980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.1308926626 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 572657780 ps |
| CPU time | 12.62 seconds |
| Started | Sep 01 07:02:47 PM UTC 24 |
| Finished | Sep 01 07:03:01 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308926626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.1308926626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.4148991472 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 286461843 ps |
| CPU time | 4.35 seconds |
| Started | Sep 01 07:02:47 PM UTC 24 |
| Finished | Sep 01 07:02:52 PM UTC 24 |
| Peak memory | 253392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148991472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.4148991472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.3897375459 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 116419174 ps |
| CPU time | 4.84 seconds |
| Started | Sep 01 07:02:50 PM UTC 24 |
| Finished | Sep 01 07:02:56 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897375459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.3897375459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.3480111811 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 97487891 ps |
| CPU time | 2.67 seconds |
| Started | Sep 01 06:53:30 PM UTC 24 |
| Finished | Sep 01 06:53:34 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480111811 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.3480111811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.156348889 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 784778728 ps |
| CPU time | 12.25 seconds |
| Started | Sep 01 06:53:23 PM UTC 24 |
| Finished | Sep 01 06:53:37 PM UTC 24 |
| Peak memory | 253752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156348889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.156348889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.3876246805 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 651384207 ps |
| CPU time | 22.21 seconds |
| Started | Sep 01 06:53:23 PM UTC 24 |
| Finished | Sep 01 06:53:47 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876246805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.3876246805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.1468230692 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2345686657 ps |
| CPU time | 11.02 seconds |
| Started | Sep 01 06:53:23 PM UTC 24 |
| Finished | Sep 01 06:53:35 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468230692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.1468230692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.1389060552 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 133689389 ps |
| CPU time | 5.61 seconds |
| Started | Sep 01 06:53:20 PM UTC 24 |
| Finished | Sep 01 06:53:27 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389060552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.1389060552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.1108587953 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 900852937 ps |
| CPU time | 11.99 seconds |
| Started | Sep 01 06:53:25 PM UTC 24 |
| Finished | Sep 01 06:53:38 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108587953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1108587953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.657906266 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 872863081 ps |
| CPU time | 23.49 seconds |
| Started | Sep 01 06:53:26 PM UTC 24 |
| Finished | Sep 01 06:53:51 PM UTC 24 |
| Peak memory | 253332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657906266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.657906266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.25886595 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1572767790 ps |
| CPU time | 24.87 seconds |
| Started | Sep 01 06:53:23 PM UTC 24 |
| Finished | Sep 01 06:53:49 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25886595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.25886595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.1070288820 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 3816555015 ps |
| CPU time | 13.49 seconds |
| Started | Sep 01 06:53:26 PM UTC 24 |
| Finished | Sep 01 06:53:41 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070288820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.1070288820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.3982389657 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 3447255177 ps |
| CPU time | 14.23 seconds |
| Started | Sep 01 06:53:19 PM UTC 24 |
| Finished | Sep 01 06:53:34 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982389657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.3982389657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.2924959446 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 7371978100 ps |
| CPU time | 78.06 seconds |
| Started | Sep 01 06:53:28 PM UTC 24 |
| Finished | Sep 01 06:54:48 PM UTC 24 |
| Peak memory | 255676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924959446 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.2924959446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.3197727473 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1875742010 ps |
| CPU time | 78.91 seconds |
| Started | Sep 01 06:53:28 PM UTC 24 |
| Finished | Sep 01 06:54:49 PM UTC 24 |
| Peak memory | 257496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3197727473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.otp_ctrl_stress_all_with_rand_reset.3197727473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.47692380 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 4352995655 ps |
| CPU time | 66.46 seconds |
| Started | Sep 01 06:53:28 PM UTC 24 |
| Finished | Sep 01 06:54:36 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47692380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.47692380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.3035960404 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2174232334 ps |
| CPU time | 5.87 seconds |
| Started | Sep 01 07:02:50 PM UTC 24 |
| Finished | Sep 01 07:02:57 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035960404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.3035960404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.3929621486 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 169504319 ps |
| CPU time | 5.22 seconds |
| Started | Sep 01 07:02:50 PM UTC 24 |
| Finished | Sep 01 07:02:56 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929621486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.3929621486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.4008743077 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 603570143 ps |
| CPU time | 6.38 seconds |
| Started | Sep 01 07:02:50 PM UTC 24 |
| Finished | Sep 01 07:02:57 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008743077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.4008743077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.2880301051 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 331087915 ps |
| CPU time | 8.53 seconds |
| Started | Sep 01 07:02:50 PM UTC 24 |
| Finished | Sep 01 07:02:59 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880301051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.2880301051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.305156159 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 385135075 ps |
| CPU time | 4.4 seconds |
| Started | Sep 01 07:02:50 PM UTC 24 |
| Finished | Sep 01 07:02:55 PM UTC 24 |
| Peak memory | 253364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305156159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.305156159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.3368833158 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 477388506 ps |
| CPU time | 3.92 seconds |
| Started | Sep 01 07:02:50 PM UTC 24 |
| Finished | Sep 01 07:02:55 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368833158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.3368833158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.1644117021 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 143395110 ps |
| CPU time | 4.59 seconds |
| Started | Sep 01 07:02:50 PM UTC 24 |
| Finished | Sep 01 07:02:56 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644117021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.1644117021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.3721692776 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 5740416078 ps |
| CPU time | 26.54 seconds |
| Started | Sep 01 07:02:50 PM UTC 24 |
| Finished | Sep 01 07:03:18 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721692776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3721692776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.3342027518 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 376540296 ps |
| CPU time | 11.9 seconds |
| Started | Sep 01 07:02:50 PM UTC 24 |
| Finished | Sep 01 07:03:03 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342027518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.3342027518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.3141084462 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 197285254 ps |
| CPU time | 4.08 seconds |
| Started | Sep 01 07:02:52 PM UTC 24 |
| Finished | Sep 01 07:02:58 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141084462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.3141084462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.688286859 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 773181540 ps |
| CPU time | 10.72 seconds |
| Started | Sep 01 07:02:52 PM UTC 24 |
| Finished | Sep 01 07:03:04 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688286859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.688286859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.2751576159 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 429361624 ps |
| CPU time | 5.69 seconds |
| Started | Sep 01 07:02:52 PM UTC 24 |
| Finished | Sep 01 07:02:59 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751576159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2751576159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.3470100909 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 8230477417 ps |
| CPU time | 19.59 seconds |
| Started | Sep 01 07:02:52 PM UTC 24 |
| Finished | Sep 01 07:03:13 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470100909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.3470100909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.1029289412 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 2382070640 ps |
| CPU time | 7.07 seconds |
| Started | Sep 01 07:02:55 PM UTC 24 |
| Finished | Sep 01 07:03:03 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029289412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.1029289412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.3954513669 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 113849532 ps |
| CPU time | 4.95 seconds |
| Started | Sep 01 07:02:55 PM UTC 24 |
| Finished | Sep 01 07:03:01 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954513669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.3954513669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.47789405 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 246941279 ps |
| CPU time | 4.32 seconds |
| Started | Sep 01 07:02:55 PM UTC 24 |
| Finished | Sep 01 07:03:00 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47789405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.47789405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.1952228702 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 1777557649 ps |
| CPU time | 24.87 seconds |
| Started | Sep 01 07:02:55 PM UTC 24 |
| Finished | Sep 01 07:03:21 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952228702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.1952228702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.4020085984 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 190254934 ps |
| CPU time | 5.89 seconds |
| Started | Sep 01 07:02:55 PM UTC 24 |
| Finished | Sep 01 07:03:02 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020085984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.4020085984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.3396307390 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 1535162614 ps |
| CPU time | 9.12 seconds |
| Started | Sep 01 07:02:57 PM UTC 24 |
| Finished | Sep 01 07:03:08 PM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396307390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.3396307390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.2044455233 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 74075367 ps |
| CPU time | 2.95 seconds |
| Started | Sep 01 06:53:42 PM UTC 24 |
| Finished | Sep 01 06:53:46 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044455233 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.2044455233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.3392270840 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 691740363 ps |
| CPU time | 16.54 seconds |
| Started | Sep 01 06:53:36 PM UTC 24 |
| Finished | Sep 01 06:53:54 PM UTC 24 |
| Peak memory | 253364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392270840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.3392270840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.3372397316 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 512332849 ps |
| CPU time | 21.16 seconds |
| Started | Sep 01 06:53:35 PM UTC 24 |
| Finished | Sep 01 06:53:57 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372397316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.3372397316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.1633090101 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 3884788386 ps |
| CPU time | 47.39 seconds |
| Started | Sep 01 06:53:35 PM UTC 24 |
| Finished | Sep 01 06:54:24 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633090101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.1633090101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.1195737571 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 964640998 ps |
| CPU time | 19.38 seconds |
| Started | Sep 01 06:53:36 PM UTC 24 |
| Finished | Sep 01 06:53:57 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195737571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1195737571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.3330010914 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1373623550 ps |
| CPU time | 23.21 seconds |
| Started | Sep 01 06:53:36 PM UTC 24 |
| Finished | Sep 01 06:54:01 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330010914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.3330010914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.2196662639 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 88119900 ps |
| CPU time | 5.49 seconds |
| Started | Sep 01 06:53:33 PM UTC 24 |
| Finished | Sep 01 06:53:40 PM UTC 24 |
| Peak memory | 251088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196662639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.2196662639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.1496461276 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 427879654 ps |
| CPU time | 16.13 seconds |
| Started | Sep 01 06:53:33 PM UTC 24 |
| Finished | Sep 01 06:53:51 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496461276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.1496461276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.2774985613 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1169389078 ps |
| CPU time | 14.07 seconds |
| Started | Sep 01 06:53:38 PM UTC 24 |
| Finished | Sep 01 06:53:53 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774985613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.2774985613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.2205944951 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 4319219842 ps |
| CPU time | 9.94 seconds |
| Started | Sep 01 06:53:30 PM UTC 24 |
| Finished | Sep 01 06:53:41 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205944951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2205944951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.4007643368 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 64997639587 ps |
| CPU time | 231.44 seconds |
| Started | Sep 01 06:53:38 PM UTC 24 |
| Finished | Sep 01 06:57:33 PM UTC 24 |
| Peak memory | 274096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4007643368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.otp_ctrl_stress_all_with_rand_reset.4007643368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.1760060633 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 457971462 ps |
| CPU time | 17.66 seconds |
| Started | Sep 01 06:53:38 PM UTC 24 |
| Finished | Sep 01 06:53:57 PM UTC 24 |
| Peak memory | 251040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760060633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.1760060633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.3163394696 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 2261205997 ps |
| CPU time | 6.25 seconds |
| Started | Sep 01 07:02:57 PM UTC 24 |
| Finished | Sep 01 07:03:05 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163394696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.3163394696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.1534303747 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 9873217358 ps |
| CPU time | 26.52 seconds |
| Started | Sep 01 07:02:57 PM UTC 24 |
| Finished | Sep 01 07:03:25 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534303747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.1534303747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.1904041738 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 269527277 ps |
| CPU time | 4.72 seconds |
| Started | Sep 01 07:02:57 PM UTC 24 |
| Finished | Sep 01 07:03:03 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904041738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.1904041738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.4094826873 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 310948132 ps |
| CPU time | 8.79 seconds |
| Started | Sep 01 07:02:57 PM UTC 24 |
| Finished | Sep 01 07:03:07 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094826873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.4094826873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.764114286 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 220047469 ps |
| CPU time | 5.2 seconds |
| Started | Sep 01 07:02:57 PM UTC 24 |
| Finished | Sep 01 07:03:04 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764114286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.764114286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.781422607 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 290740979 ps |
| CPU time | 5.72 seconds |
| Started | Sep 01 07:02:57 PM UTC 24 |
| Finished | Sep 01 07:03:05 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781422607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.781422607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.2996220905 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 1592327844 ps |
| CPU time | 4.32 seconds |
| Started | Sep 01 07:02:58 PM UTC 24 |
| Finished | Sep 01 07:03:03 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996220905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.2996220905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.2889909742 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 1805674149 ps |
| CPU time | 4.86 seconds |
| Started | Sep 01 07:02:58 PM UTC 24 |
| Finished | Sep 01 07:03:04 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889909742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.2889909742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.229852559 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 258338032 ps |
| CPU time | 3.49 seconds |
| Started | Sep 01 07:03:04 PM UTC 24 |
| Finished | Sep 01 07:03:09 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229852559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.229852559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.1039526591 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 203940969 ps |
| CPU time | 9.1 seconds |
| Started | Sep 01 07:03:04 PM UTC 24 |
| Finished | Sep 01 07:03:14 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039526591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.1039526591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.526152506 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 2317650156 ps |
| CPU time | 5.63 seconds |
| Started | Sep 01 07:03:04 PM UTC 24 |
| Finished | Sep 01 07:03:11 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526152506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.526152506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.95996097 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 1096618865 ps |
| CPU time | 13.57 seconds |
| Started | Sep 01 07:03:04 PM UTC 24 |
| Finished | Sep 01 07:03:19 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95996097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.95996097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.2200616292 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 453820834 ps |
| CPU time | 5.85 seconds |
| Started | Sep 01 07:03:04 PM UTC 24 |
| Finished | Sep 01 07:03:11 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200616292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.2200616292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.1170955534 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 3387658668 ps |
| CPU time | 25.75 seconds |
| Started | Sep 01 07:03:04 PM UTC 24 |
| Finished | Sep 01 07:03:31 PM UTC 24 |
| Peak memory | 251240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170955534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.1170955534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.3398103928 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 489605401 ps |
| CPU time | 5.11 seconds |
| Started | Sep 01 07:03:04 PM UTC 24 |
| Finished | Sep 01 07:03:11 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398103928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.3398103928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.446703087 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 350164844 ps |
| CPU time | 4.9 seconds |
| Started | Sep 01 07:03:04 PM UTC 24 |
| Finished | Sep 01 07:03:11 PM UTC 24 |
| Peak memory | 253088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446703087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.446703087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.3290540222 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 188224816 ps |
| CPU time | 6.83 seconds |
| Started | Sep 01 07:03:04 PM UTC 24 |
| Finished | Sep 01 07:03:12 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290540222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.3290540222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.826942750 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 7125178148 ps |
| CPU time | 14.95 seconds |
| Started | Sep 01 07:03:05 PM UTC 24 |
| Finished | Sep 01 07:03:21 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826942750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.826942750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.715740471 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 838065607 ps |
| CPU time | 6.65 seconds |
| Started | Sep 01 07:03:05 PM UTC 24 |
| Finished | Sep 01 07:03:12 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715740471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.715740471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.2235580254 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 330633703 ps |
| CPU time | 4.14 seconds |
| Started | Sep 01 07:03:05 PM UTC 24 |
| Finished | Sep 01 07:03:10 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235580254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.2235580254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.4287924994 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 180192839 ps |
| CPU time | 2.87 seconds |
| Started | Sep 01 06:54:00 PM UTC 24 |
| Finished | Sep 01 06:54:04 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287924994 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.4287924994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.3539540426 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 2816930711 ps |
| CPU time | 27.99 seconds |
| Started | Sep 01 06:53:48 PM UTC 24 |
| Finished | Sep 01 06:54:17 PM UTC 24 |
| Peak memory | 257788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539540426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.3539540426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.1504532494 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 657130994 ps |
| CPU time | 8.24 seconds |
| Started | Sep 01 06:53:47 PM UTC 24 |
| Finished | Sep 01 06:53:56 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504532494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1504532494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.2389976597 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 12455871161 ps |
| CPU time | 35.29 seconds |
| Started | Sep 01 06:53:47 PM UTC 24 |
| Finished | Sep 01 06:54:23 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389976597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.2389976597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.1630091456 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1861785313 ps |
| CPU time | 29.63 seconds |
| Started | Sep 01 06:53:48 PM UTC 24 |
| Finished | Sep 01 06:54:19 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630091456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.1630091456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.181992097 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2310035823 ps |
| CPU time | 39.65 seconds |
| Started | Sep 01 06:53:51 PM UTC 24 |
| Finished | Sep 01 06:54:32 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181992097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.181992097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.3235497740 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 383789853 ps |
| CPU time | 12.28 seconds |
| Started | Sep 01 06:53:44 PM UTC 24 |
| Finished | Sep 01 06:53:57 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235497740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.3235497740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.1593336193 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1683045625 ps |
| CPU time | 36.34 seconds |
| Started | Sep 01 06:53:44 PM UTC 24 |
| Finished | Sep 01 06:54:22 PM UTC 24 |
| Peak memory | 253532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593336193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.1593336193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.1075971370 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 486420401 ps |
| CPU time | 4.87 seconds |
| Started | Sep 01 06:53:53 PM UTC 24 |
| Finished | Sep 01 06:53:58 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075971370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.1075971370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.2222553096 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 860783003 ps |
| CPU time | 16.62 seconds |
| Started | Sep 01 06:53:42 PM UTC 24 |
| Finished | Sep 01 06:54:00 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222553096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2222553096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.3586890989 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 150733364233 ps |
| CPU time | 1884.78 seconds |
| Started | Sep 01 06:53:55 PM UTC 24 |
| Finished | Sep 01 07:25:42 PM UTC 24 |
| Peak memory | 273744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586890989 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.3586890989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.3040950476 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 175221457 ps |
| CPU time | 6.07 seconds |
| Started | Sep 01 07:03:05 PM UTC 24 |
| Finished | Sep 01 07:03:12 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040950476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.3040950476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.1287578730 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 366380559 ps |
| CPU time | 5.39 seconds |
| Started | Sep 01 07:03:05 PM UTC 24 |
| Finished | Sep 01 07:03:11 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287578730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.1287578730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.3779833803 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 94563677 ps |
| CPU time | 4.12 seconds |
| Started | Sep 01 07:03:05 PM UTC 24 |
| Finished | Sep 01 07:03:10 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779833803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3779833803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.3826850720 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 749475421 ps |
| CPU time | 22.03 seconds |
| Started | Sep 01 07:03:05 PM UTC 24 |
| Finished | Sep 01 07:03:28 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826850720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.3826850720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.2006786076 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 126874896 ps |
| CPU time | 5.78 seconds |
| Started | Sep 01 07:03:05 PM UTC 24 |
| Finished | Sep 01 07:03:12 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006786076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.2006786076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.3803348526 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 446256374 ps |
| CPU time | 11.17 seconds |
| Started | Sep 01 07:03:05 PM UTC 24 |
| Finished | Sep 01 07:03:17 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803348526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.3803348526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.2153390689 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 1675633330 ps |
| CPU time | 6.4 seconds |
| Started | Sep 01 07:03:05 PM UTC 24 |
| Finished | Sep 01 07:03:13 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153390689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.2153390689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.931586176 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 611338568 ps |
| CPU time | 5.97 seconds |
| Started | Sep 01 07:03:05 PM UTC 24 |
| Finished | Sep 01 07:03:12 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931586176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.931586176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.357700647 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 203099570 ps |
| CPU time | 5.34 seconds |
| Started | Sep 01 07:03:09 PM UTC 24 |
| Finished | Sep 01 07:03:16 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357700647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.357700647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.591383491 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 886900500 ps |
| CPU time | 7.88 seconds |
| Started | Sep 01 07:03:09 PM UTC 24 |
| Finished | Sep 01 07:03:18 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591383491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.591383491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.616144805 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 171559146 ps |
| CPU time | 3.84 seconds |
| Started | Sep 01 07:03:09 PM UTC 24 |
| Finished | Sep 01 07:03:14 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616144805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.616144805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.3986981660 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 1082217956 ps |
| CPU time | 13.41 seconds |
| Started | Sep 01 07:03:09 PM UTC 24 |
| Finished | Sep 01 07:03:24 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986981660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3986981660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.782409172 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 298344929 ps |
| CPU time | 5.21 seconds |
| Started | Sep 01 07:03:09 PM UTC 24 |
| Finished | Sep 01 07:03:16 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782409172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.782409172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.1366208380 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 3663569898 ps |
| CPU time | 16.53 seconds |
| Started | Sep 01 07:03:09 PM UTC 24 |
| Finished | Sep 01 07:03:27 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366208380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.1366208380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.2102703293 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 140526542 ps |
| CPU time | 4.31 seconds |
| Started | Sep 01 07:03:09 PM UTC 24 |
| Finished | Sep 01 07:03:15 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102703293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.2102703293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.1489615042 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 118335521 ps |
| CPU time | 3.23 seconds |
| Started | Sep 01 07:03:09 PM UTC 24 |
| Finished | Sep 01 07:03:14 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489615042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.1489615042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.3437242360 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 231773426 ps |
| CPU time | 4.19 seconds |
| Started | Sep 01 07:03:09 PM UTC 24 |
| Finished | Sep 01 07:03:15 PM UTC 24 |
| Peak memory | 253520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437242360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.3437242360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.1345782426 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 572172639 ps |
| CPU time | 11.24 seconds |
| Started | Sep 01 07:03:10 PM UTC 24 |
| Finished | Sep 01 07:03:22 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345782426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.1345782426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.1258359648 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 476025648 ps |
| CPU time | 4.6 seconds |
| Started | Sep 01 07:03:12 PM UTC 24 |
| Finished | Sep 01 07:03:18 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258359648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.1258359648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.1116986418 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 5548511052 ps |
| CPU time | 17.94 seconds |
| Started | Sep 01 07:03:12 PM UTC 24 |
| Finished | Sep 01 07:03:32 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116986418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.1116986418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.604697205 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 785637971 ps |
| CPU time | 4.33 seconds |
| Started | Sep 01 06:54:11 PM UTC 24 |
| Finished | Sep 01 06:54:17 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604697205 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.604697205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.3198219020 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 7680078875 ps |
| CPU time | 19.75 seconds |
| Started | Sep 01 06:54:01 PM UTC 24 |
| Finished | Sep 01 06:54:22 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198219020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.3198219020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.3781414457 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2261132384 ps |
| CPU time | 38.14 seconds |
| Started | Sep 01 06:54:01 PM UTC 24 |
| Finished | Sep 01 06:54:41 PM UTC 24 |
| Peak memory | 253668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781414457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.3781414457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.2121656458 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 732411721 ps |
| CPU time | 21.4 seconds |
| Started | Sep 01 06:54:01 PM UTC 24 |
| Finished | Sep 01 06:54:24 PM UTC 24 |
| Peak memory | 257660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121656458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.2121656458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.2356716076 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 259363606 ps |
| CPU time | 6.31 seconds |
| Started | Sep 01 06:54:00 PM UTC 24 |
| Finished | Sep 01 06:54:08 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356716076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.2356716076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.108723553 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 325133804 ps |
| CPU time | 12.26 seconds |
| Started | Sep 01 06:54:03 PM UTC 24 |
| Finished | Sep 01 06:54:16 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108723553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.108723553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.836914582 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 776231746 ps |
| CPU time | 21.92 seconds |
| Started | Sep 01 06:54:03 PM UTC 24 |
| Finished | Sep 01 06:54:26 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836914582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.836914582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.3921915312 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 241830483 ps |
| CPU time | 8.81 seconds |
| Started | Sep 01 06:54:01 PM UTC 24 |
| Finished | Sep 01 06:54:11 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921915312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3921915312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.2636021689 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 829112652 ps |
| CPU time | 13.26 seconds |
| Started | Sep 01 06:54:00 PM UTC 24 |
| Finished | Sep 01 06:54:15 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636021689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.2636021689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.1682279811 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 763895178 ps |
| CPU time | 8.85 seconds |
| Started | Sep 01 06:54:00 PM UTC 24 |
| Finished | Sep 01 06:54:10 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682279811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.1682279811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.3842433044 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 4393854526 ps |
| CPU time | 28.73 seconds |
| Started | Sep 01 06:54:09 PM UTC 24 |
| Finished | Sep 01 06:54:39 PM UTC 24 |
| Peak memory | 253500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842433044 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.3842433044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.4276282169 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 4172715062 ps |
| CPU time | 33.91 seconds |
| Started | Sep 01 06:54:03 PM UTC 24 |
| Finished | Sep 01 06:54:38 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276282169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.4276282169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.2022825503 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 580744420 ps |
| CPU time | 7.5 seconds |
| Started | Sep 01 07:03:12 PM UTC 24 |
| Finished | Sep 01 07:03:20 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022825503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.2022825503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.2912853002 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 391015936 ps |
| CPU time | 15.6 seconds |
| Started | Sep 01 07:03:12 PM UTC 24 |
| Finished | Sep 01 07:03:29 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912853002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.2912853002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.2951716981 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 134353939 ps |
| CPU time | 4.74 seconds |
| Started | Sep 01 07:03:12 PM UTC 24 |
| Finished | Sep 01 07:03:18 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951716981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.2951716981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.4083836584 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 1853519436 ps |
| CPU time | 12.38 seconds |
| Started | Sep 01 07:03:12 PM UTC 24 |
| Finished | Sep 01 07:03:26 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083836584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.4083836584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.2273922002 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 2321271503 ps |
| CPU time | 7.43 seconds |
| Started | Sep 01 07:03:12 PM UTC 24 |
| Finished | Sep 01 07:03:21 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273922002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.2273922002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.1383337826 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 11762635310 ps |
| CPU time | 31.32 seconds |
| Started | Sep 01 07:03:14 PM UTC 24 |
| Finished | Sep 01 07:03:47 PM UTC 24 |
| Peak memory | 257396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383337826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1383337826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.2750365470 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 144728936 ps |
| CPU time | 3.84 seconds |
| Started | Sep 01 07:03:14 PM UTC 24 |
| Finished | Sep 01 07:03:19 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750365470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.2750365470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.581674867 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 4465277189 ps |
| CPU time | 35.57 seconds |
| Started | Sep 01 07:03:14 PM UTC 24 |
| Finished | Sep 01 07:03:51 PM UTC 24 |
| Peak memory | 253292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581674867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.581674867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.2592690617 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 272088200 ps |
| CPU time | 3.59 seconds |
| Started | Sep 01 07:03:14 PM UTC 24 |
| Finished | Sep 01 07:03:19 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592690617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.2592690617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.385692473 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 649498276 ps |
| CPU time | 16.28 seconds |
| Started | Sep 01 07:03:14 PM UTC 24 |
| Finished | Sep 01 07:03:32 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385692473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.385692473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.3669206496 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 170676323 ps |
| CPU time | 5.12 seconds |
| Started | Sep 01 07:03:14 PM UTC 24 |
| Finished | Sep 01 07:03:20 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669206496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.3669206496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.695538078 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 1299539334 ps |
| CPU time | 16.48 seconds |
| Started | Sep 01 07:03:14 PM UTC 24 |
| Finished | Sep 01 07:03:32 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695538078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.695538078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.1150896074 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 2224898424 ps |
| CPU time | 6.12 seconds |
| Started | Sep 01 07:03:14 PM UTC 24 |
| Finished | Sep 01 07:03:22 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150896074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.1150896074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.2688070466 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 3556231082 ps |
| CPU time | 13.44 seconds |
| Started | Sep 01 07:03:17 PM UTC 24 |
| Finished | Sep 01 07:03:31 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688070466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2688070466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.3692858880 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 146425551 ps |
| CPU time | 3.57 seconds |
| Started | Sep 01 07:03:17 PM UTC 24 |
| Finished | Sep 01 07:03:22 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692858880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.3692858880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.2742484932 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 416211011 ps |
| CPU time | 12.74 seconds |
| Started | Sep 01 07:03:17 PM UTC 24 |
| Finished | Sep 01 07:03:31 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742484932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.2742484932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.1136127564 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 2159735913 ps |
| CPU time | 7.6 seconds |
| Started | Sep 01 07:03:17 PM UTC 24 |
| Finished | Sep 01 07:03:26 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136127564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.1136127564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.535609084 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 571223836 ps |
| CPU time | 10.75 seconds |
| Started | Sep 01 07:03:17 PM UTC 24 |
| Finished | Sep 01 07:03:29 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535609084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.535609084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.4241661216 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 233316999 ps |
| CPU time | 5.67 seconds |
| Started | Sep 01 07:03:17 PM UTC 24 |
| Finished | Sep 01 07:03:24 PM UTC 24 |
| Peak memory | 251268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241661216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.4241661216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.4078343504 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 3391734045 ps |
| CPU time | 11.91 seconds |
| Started | Sep 01 07:03:17 PM UTC 24 |
| Finished | Sep 01 07:03:30 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078343504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.4078343504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.1098358333 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 738236722 ps |
| CPU time | 3.29 seconds |
| Started | Sep 01 06:54:25 PM UTC 24 |
| Finished | Sep 01 06:54:29 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098358333 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.1098358333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.2056198024 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 705485917 ps |
| CPU time | 17.95 seconds |
| Started | Sep 01 06:54:18 PM UTC 24 |
| Finished | Sep 01 06:54:38 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056198024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.2056198024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.828232600 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 977131249 ps |
| CPU time | 40.73 seconds |
| Started | Sep 01 06:54:18 PM UTC 24 |
| Finished | Sep 01 06:55:01 PM UTC 24 |
| Peak memory | 253632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828232600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.828232600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.976952663 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 12011515268 ps |
| CPU time | 23.39 seconds |
| Started | Sep 01 06:54:17 PM UTC 24 |
| Finished | Sep 01 06:54:42 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976952663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.976952663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.255605968 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1889844775 ps |
| CPU time | 44.28 seconds |
| Started | Sep 01 06:54:20 PM UTC 24 |
| Finished | Sep 01 06:55:06 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255605968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.255605968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.2039018891 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 522910252 ps |
| CPU time | 13.06 seconds |
| Started | Sep 01 06:54:17 PM UTC 24 |
| Finished | Sep 01 06:54:31 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039018891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.2039018891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.659804753 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 683522675 ps |
| CPU time | 20.09 seconds |
| Started | Sep 01 06:54:17 PM UTC 24 |
| Finished | Sep 01 06:54:38 PM UTC 24 |
| Peak memory | 250908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659804753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.659804753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.3516420477 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2454959284 ps |
| CPU time | 9.57 seconds |
| Started | Sep 01 06:54:25 PM UTC 24 |
| Finished | Sep 01 06:54:35 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516420477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.3516420477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.3460114041 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 924849500 ps |
| CPU time | 13.21 seconds |
| Started | Sep 01 06:54:12 PM UTC 24 |
| Finished | Sep 01 06:54:26 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460114041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.3460114041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.364105720 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 54308984277 ps |
| CPU time | 342.11 seconds |
| Started | Sep 01 06:54:25 PM UTC 24 |
| Finished | Sep 01 07:00:12 PM UTC 24 |
| Peak memory | 314992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364105720 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.364105720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.2577587918 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 54639543494 ps |
| CPU time | 139.53 seconds |
| Started | Sep 01 06:54:25 PM UTC 24 |
| Finished | Sep 01 06:56:47 PM UTC 24 |
| Peak memory | 272304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2577587918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.otp_ctrl_stress_all_with_rand_reset.2577587918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.3348919091 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 5370133653 ps |
| CPU time | 11.89 seconds |
| Started | Sep 01 06:54:25 PM UTC 24 |
| Finished | Sep 01 06:54:38 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348919091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.3348919091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.774115026 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 367413704 ps |
| CPU time | 5.01 seconds |
| Started | Sep 01 07:03:17 PM UTC 24 |
| Finished | Sep 01 07:03:23 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774115026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.774115026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.1910666616 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 191555180 ps |
| CPU time | 5.9 seconds |
| Started | Sep 01 07:03:17 PM UTC 24 |
| Finished | Sep 01 07:03:24 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910666616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.1910666616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.2810087819 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 209120753 ps |
| CPU time | 6 seconds |
| Started | Sep 01 07:03:22 PM UTC 24 |
| Finished | Sep 01 07:03:29 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810087819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.2810087819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.1947106709 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 494353091 ps |
| CPU time | 7.7 seconds |
| Started | Sep 01 07:03:22 PM UTC 24 |
| Finished | Sep 01 07:03:31 PM UTC 24 |
| Peak memory | 250744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947106709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.1947106709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.1896392836 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 149647593 ps |
| CPU time | 5.06 seconds |
| Started | Sep 01 07:03:22 PM UTC 24 |
| Finished | Sep 01 07:03:28 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896392836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.1896392836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.1562474875 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 2526782884 ps |
| CPU time | 7.07 seconds |
| Started | Sep 01 07:03:22 PM UTC 24 |
| Finished | Sep 01 07:03:30 PM UTC 24 |
| Peak memory | 250800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562474875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.1562474875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.2018508495 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 1960312712 ps |
| CPU time | 6.68 seconds |
| Started | Sep 01 07:03:22 PM UTC 24 |
| Finished | Sep 01 07:03:30 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018508495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2018508495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.3741331454 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 1581822421 ps |
| CPU time | 24.52 seconds |
| Started | Sep 01 07:03:22 PM UTC 24 |
| Finished | Sep 01 07:03:48 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741331454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.3741331454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.3612282001 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 122602751 ps |
| CPU time | 3.78 seconds |
| Started | Sep 01 07:03:22 PM UTC 24 |
| Finished | Sep 01 07:03:27 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612282001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.3612282001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.1523019674 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 159288711 ps |
| CPU time | 3.51 seconds |
| Started | Sep 01 07:03:22 PM UTC 24 |
| Finished | Sep 01 07:03:27 PM UTC 24 |
| Peak memory | 251100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523019674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.1523019674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.4187490251 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 279963370 ps |
| CPU time | 5.07 seconds |
| Started | Sep 01 07:03:22 PM UTC 24 |
| Finished | Sep 01 07:03:29 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187490251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.4187490251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.2730192369 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 4970311854 ps |
| CPU time | 21.59 seconds |
| Started | Sep 01 07:03:23 PM UTC 24 |
| Finished | Sep 01 07:03:45 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730192369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.2730192369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.3085515565 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 208609300 ps |
| CPU time | 6.21 seconds |
| Started | Sep 01 07:03:23 PM UTC 24 |
| Finished | Sep 01 07:03:30 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085515565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.3085515565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.2101718389 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 366537985 ps |
| CPU time | 6.2 seconds |
| Started | Sep 01 07:03:23 PM UTC 24 |
| Finished | Sep 01 07:03:30 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101718389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.2101718389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.349335953 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 136882010 ps |
| CPU time | 5.3 seconds |
| Started | Sep 01 07:03:23 PM UTC 24 |
| Finished | Sep 01 07:03:29 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349335953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.349335953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.3506883415 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 3562899829 ps |
| CPU time | 10.7 seconds |
| Started | Sep 01 07:03:23 PM UTC 24 |
| Finished | Sep 01 07:03:35 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506883415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.3506883415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.3964164915 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 116477826 ps |
| CPU time | 4.58 seconds |
| Started | Sep 01 07:03:25 PM UTC 24 |
| Finished | Sep 01 07:03:31 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964164915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.3964164915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.3537360495 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 185861911 ps |
| CPU time | 7.38 seconds |
| Started | Sep 01 07:03:25 PM UTC 24 |
| Finished | Sep 01 07:03:34 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537360495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.3537360495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.4213220067 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 268805333 ps |
| CPU time | 5.04 seconds |
| Started | Sep 01 07:03:25 PM UTC 24 |
| Finished | Sep 01 07:03:31 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213220067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.4213220067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.2346679063 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 102763902 ps |
| CPU time | 4.63 seconds |
| Started | Sep 01 07:03:25 PM UTC 24 |
| Finished | Sep 01 07:03:31 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346679063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.2346679063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.1509964800 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 307056980 ps |
| CPU time | 4.12 seconds |
| Started | Sep 01 06:54:42 PM UTC 24 |
| Finished | Sep 01 06:54:47 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509964800 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.1509964800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.299902941 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1108527461 ps |
| CPU time | 37.56 seconds |
| Started | Sep 01 06:54:30 PM UTC 24 |
| Finished | Sep 01 06:55:09 PM UTC 24 |
| Peak memory | 255268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299902941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.299902941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.157093080 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 10397541520 ps |
| CPU time | 38.88 seconds |
| Started | Sep 01 06:54:28 PM UTC 24 |
| Finished | Sep 01 06:55:08 PM UTC 24 |
| Peak memory | 257532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157093080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.157093080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.320586661 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 420775358 ps |
| CPU time | 5.34 seconds |
| Started | Sep 01 06:54:27 PM UTC 24 |
| Finished | Sep 01 06:54:34 PM UTC 24 |
| Peak memory | 251528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320586661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.320586661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.199010831 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2012895793 ps |
| CPU time | 54.31 seconds |
| Started | Sep 01 06:54:33 PM UTC 24 |
| Finished | Sep 01 06:55:29 PM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199010831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.199010831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.1344360593 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1241789649 ps |
| CPU time | 45.65 seconds |
| Started | Sep 01 06:54:33 PM UTC 24 |
| Finished | Sep 01 06:55:20 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344360593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.1344360593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.1872557957 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1496764670 ps |
| CPU time | 15.19 seconds |
| Started | Sep 01 06:54:28 PM UTC 24 |
| Finished | Sep 01 06:54:44 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872557957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.1872557957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.135906414 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 804450514 ps |
| CPU time | 13.88 seconds |
| Started | Sep 01 06:54:27 PM UTC 24 |
| Finished | Sep 01 06:54:43 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135906414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.135906414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.3293468044 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 183500924 ps |
| CPU time | 5.64 seconds |
| Started | Sep 01 06:54:25 PM UTC 24 |
| Finished | Sep 01 06:54:32 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293468044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.3293468044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.712543114 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 11084558400 ps |
| CPU time | 172.2 seconds |
| Started | Sep 01 06:54:42 PM UTC 24 |
| Finished | Sep 01 06:57:37 PM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712543114 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.712543114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.3797151709 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2508841290 ps |
| CPU time | 26.58 seconds |
| Started | Sep 01 06:54:42 PM UTC 24 |
| Finished | Sep 01 06:55:10 PM UTC 24 |
| Peak memory | 253676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797151709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3797151709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.1990511671 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 620854015 ps |
| CPU time | 5.85 seconds |
| Started | Sep 01 07:03:25 PM UTC 24 |
| Finished | Sep 01 07:03:32 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990511671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1990511671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.2801619676 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 235906447 ps |
| CPU time | 6.87 seconds |
| Started | Sep 01 07:03:26 PM UTC 24 |
| Finished | Sep 01 07:03:33 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801619676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.2801619676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.629292451 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 176980859 ps |
| CPU time | 3.67 seconds |
| Started | Sep 01 07:03:26 PM UTC 24 |
| Finished | Sep 01 07:03:30 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629292451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.629292451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.46237942 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2642475453 ps |
| CPU time | 12.51 seconds |
| Started | Sep 01 07:03:28 PM UTC 24 |
| Finished | Sep 01 07:03:42 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46237942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.46237942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.3846028670 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 499724314 ps |
| CPU time | 3.98 seconds |
| Started | Sep 01 07:03:28 PM UTC 24 |
| Finished | Sep 01 07:03:33 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846028670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.3846028670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.1953604172 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 454435455 ps |
| CPU time | 7.48 seconds |
| Started | Sep 01 07:03:28 PM UTC 24 |
| Finished | Sep 01 07:03:37 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953604172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.1953604172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.3654981076 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 395222245 ps |
| CPU time | 4.98 seconds |
| Started | Sep 01 07:03:28 PM UTC 24 |
| Finished | Sep 01 07:03:34 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654981076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.3654981076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.257024705 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 904475006 ps |
| CPU time | 11.36 seconds |
| Started | Sep 01 07:03:28 PM UTC 24 |
| Finished | Sep 01 07:03:41 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257024705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.257024705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.2783049734 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 2668319837 ps |
| CPU time | 6.06 seconds |
| Started | Sep 01 07:03:28 PM UTC 24 |
| Finished | Sep 01 07:03:36 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783049734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.2783049734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.4204693510 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 201193167 ps |
| CPU time | 4.33 seconds |
| Started | Sep 01 07:03:32 PM UTC 24 |
| Finished | Sep 01 07:03:38 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204693510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.4204693510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.3798031420 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 624624973 ps |
| CPU time | 4.12 seconds |
| Started | Sep 01 07:03:32 PM UTC 24 |
| Finished | Sep 01 07:03:37 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798031420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.3798031420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.3440192683 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 288315051 ps |
| CPU time | 6.79 seconds |
| Started | Sep 01 07:03:32 PM UTC 24 |
| Finished | Sep 01 07:03:40 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440192683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.3440192683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.3179545661 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 400938097 ps |
| CPU time | 5.8 seconds |
| Started | Sep 01 07:03:32 PM UTC 24 |
| Finished | Sep 01 07:03:39 PM UTC 24 |
| Peak memory | 251328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179545661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.3179545661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.2215502489 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 1540056998 ps |
| CPU time | 6.59 seconds |
| Started | Sep 01 07:03:32 PM UTC 24 |
| Finished | Sep 01 07:03:40 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215502489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.2215502489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.3805941087 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 4347458461 ps |
| CPU time | 8.85 seconds |
| Started | Sep 01 07:03:32 PM UTC 24 |
| Finished | Sep 01 07:03:43 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805941087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.3805941087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.1545772636 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 97997056 ps |
| CPU time | 3.48 seconds |
| Started | Sep 01 07:03:33 PM UTC 24 |
| Finished | Sep 01 07:03:37 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545772636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1545772636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.842480142 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 349402195 ps |
| CPU time | 9.99 seconds |
| Started | Sep 01 07:03:33 PM UTC 24 |
| Finished | Sep 01 07:03:44 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842480142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.842480142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.1647074114 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 545682507 ps |
| CPU time | 4.75 seconds |
| Started | Sep 01 07:03:33 PM UTC 24 |
| Finished | Sep 01 07:03:39 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647074114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.1647074114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.1493627159 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 191275706 ps |
| CPU time | 4.52 seconds |
| Started | Sep 01 07:03:33 PM UTC 24 |
| Finished | Sep 01 07:03:38 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493627159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1493627159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.533317014 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 937236194 ps |
| CPU time | 4.4 seconds |
| Started | Sep 01 06:49:53 PM UTC 24 |
| Finished | Sep 01 06:49:58 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533317014 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.533317014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.3095123908 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 806160745 ps |
| CPU time | 22.78 seconds |
| Started | Sep 01 06:49:28 PM UTC 24 |
| Finished | Sep 01 06:49:52 PM UTC 24 |
| Peak memory | 253368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095123908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.3095123908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.2403234878 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 885741150 ps |
| CPU time | 29.65 seconds |
| Started | Sep 01 06:49:27 PM UTC 24 |
| Finished | Sep 01 06:49:58 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403234878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.2403234878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.1872386061 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1346420598 ps |
| CPU time | 16.81 seconds |
| Started | Sep 01 06:49:27 PM UTC 24 |
| Finished | Sep 01 06:49:45 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872386061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1872386061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.1984221624 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 6766765742 ps |
| CPU time | 47.92 seconds |
| Started | Sep 01 06:49:31 PM UTC 24 |
| Finished | Sep 01 06:50:21 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984221624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.1984221624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.4042198619 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 252837290 ps |
| CPU time | 5.76 seconds |
| Started | Sep 01 06:49:25 PM UTC 24 |
| Finished | Sep 01 06:49:32 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042198619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.4042198619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.2762492137 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 316960359 ps |
| CPU time | 8.45 seconds |
| Started | Sep 01 06:49:33 PM UTC 24 |
| Finished | Sep 01 06:49:43 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762492137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.2762492137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.476665677 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 41825200378 ps |
| CPU time | 216.92 seconds |
| Started | Sep 01 06:49:46 PM UTC 24 |
| Finished | Sep 01 06:53:27 PM UTC 24 |
| Peak memory | 302208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476665677 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.476665677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.2912125316 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 33889064371 ps |
| CPU time | 251.9 seconds |
| Started | Sep 01 06:49:45 PM UTC 24 |
| Finished | Sep 01 06:54:01 PM UTC 24 |
| Peak memory | 268200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2912125316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.otp_ctrl_stress_all_with_rand_reset.2912125316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.1523279123 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 990375094 ps |
| CPU time | 13.68 seconds |
| Started | Sep 01 06:49:42 PM UTC 24 |
| Finished | Sep 01 06:49:57 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523279123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.1523279123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.2371704614 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 101637806 ps |
| CPU time | 3.31 seconds |
| Started | Sep 01 06:54:50 PM UTC 24 |
| Finished | Sep 01 06:54:55 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371704614 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.2371704614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.3474891255 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 4857711847 ps |
| CPU time | 30.08 seconds |
| Started | Sep 01 06:54:42 PM UTC 24 |
| Finished | Sep 01 06:55:14 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474891255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.3474891255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.2804337108 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1477087286 ps |
| CPU time | 43.74 seconds |
| Started | Sep 01 06:54:42 PM UTC 24 |
| Finished | Sep 01 06:55:27 PM UTC 24 |
| Peak memory | 257404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804337108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.2804337108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.1886286862 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 257355299 ps |
| CPU time | 4.94 seconds |
| Started | Sep 01 06:54:42 PM UTC 24 |
| Finished | Sep 01 06:54:48 PM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886286862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.1886286862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.1319361117 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 251274872 ps |
| CPU time | 5.43 seconds |
| Started | Sep 01 06:54:42 PM UTC 24 |
| Finished | Sep 01 06:54:48 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319361117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.1319361117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.4072747331 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 28424747671 ps |
| CPU time | 37.54 seconds |
| Started | Sep 01 06:54:44 PM UTC 24 |
| Finished | Sep 01 06:55:23 PM UTC 24 |
| Peak memory | 257564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072747331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.4072747331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.3931371906 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1153545496 ps |
| CPU time | 40.25 seconds |
| Started | Sep 01 06:54:44 PM UTC 24 |
| Finished | Sep 01 06:55:26 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931371906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.3931371906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.1654678298 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 205018895 ps |
| CPU time | 8.95 seconds |
| Started | Sep 01 06:54:42 PM UTC 24 |
| Finished | Sep 01 06:54:52 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654678298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.1654678298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.281180522 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 132426415 ps |
| CPU time | 5.58 seconds |
| Started | Sep 01 06:54:44 PM UTC 24 |
| Finished | Sep 01 06:54:51 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281180522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.281180522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.3691185877 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 388790288 ps |
| CPU time | 10.54 seconds |
| Started | Sep 01 06:54:42 PM UTC 24 |
| Finished | Sep 01 06:54:54 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691185877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.3691185877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.2100657827 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 120396692988 ps |
| CPU time | 253.37 seconds |
| Started | Sep 01 06:54:48 PM UTC 24 |
| Finished | Sep 01 06:59:05 PM UTC 24 |
| Peak memory | 273944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100657827 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.2100657827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.1115399456 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 16385500175 ps |
| CPU time | 124.99 seconds |
| Started | Sep 01 06:54:45 PM UTC 24 |
| Finished | Sep 01 06:56:53 PM UTC 24 |
| Peak memory | 267832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1115399456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.otp_ctrl_stress_all_with_rand_reset.1115399456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.2327868758 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 794498672 ps |
| CPU time | 16.12 seconds |
| Started | Sep 01 06:54:44 PM UTC 24 |
| Finished | Sep 01 06:55:02 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327868758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.2327868758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.1729852523 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 1706227168 ps |
| CPU time | 5.33 seconds |
| Started | Sep 01 07:03:33 PM UTC 24 |
| Finished | Sep 01 07:03:39 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729852523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.1729852523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.2117139669 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 1803505486 ps |
| CPU time | 6.68 seconds |
| Started | Sep 01 07:03:33 PM UTC 24 |
| Finished | Sep 01 07:03:41 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117139669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.2117139669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.725394738 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 500202095 ps |
| CPU time | 5.54 seconds |
| Started | Sep 01 07:03:33 PM UTC 24 |
| Finished | Sep 01 07:03:40 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725394738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.725394738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.3347371225 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 250624851 ps |
| CPU time | 4.1 seconds |
| Started | Sep 01 07:03:33 PM UTC 24 |
| Finished | Sep 01 07:03:38 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347371225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.3347371225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.154325816 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 464177676 ps |
| CPU time | 6.59 seconds |
| Started | Sep 01 07:03:33 PM UTC 24 |
| Finished | Sep 01 07:03:41 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154325816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.154325816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.412342259 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 203067514 ps |
| CPU time | 4.98 seconds |
| Started | Sep 01 07:03:33 PM UTC 24 |
| Finished | Sep 01 07:03:39 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412342259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.412342259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.1610929843 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 286855571 ps |
| CPU time | 6.97 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:45 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610929843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.1610929843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.4284018537 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 142986915 ps |
| CPU time | 4.31 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:42 PM UTC 24 |
| Peak memory | 250880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284018537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.4284018537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.3158280867 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 119325685 ps |
| CPU time | 5.95 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:44 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158280867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3158280867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.2264153691 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 313957577 ps |
| CPU time | 3.62 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:41 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264153691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.2264153691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.580892014 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 818673721 ps |
| CPU time | 3.98 seconds |
| Started | Sep 01 06:55:03 PM UTC 24 |
| Finished | Sep 01 06:55:08 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580892014 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.580892014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.1749872545 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1651840346 ps |
| CPU time | 14.08 seconds |
| Started | Sep 01 06:54:56 PM UTC 24 |
| Finished | Sep 01 06:55:11 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749872545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.1749872545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.1046164586 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 4367491864 ps |
| CPU time | 41.16 seconds |
| Started | Sep 01 06:54:55 PM UTC 24 |
| Finished | Sep 01 06:55:37 PM UTC 24 |
| Peak memory | 257596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046164586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.1046164586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.3891260294 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1590378139 ps |
| CPU time | 33.32 seconds |
| Started | Sep 01 06:54:53 PM UTC 24 |
| Finished | Sep 01 06:55:28 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891260294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.3891260294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.1024078988 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 378071669 ps |
| CPU time | 6.49 seconds |
| Started | Sep 01 06:54:50 PM UTC 24 |
| Finished | Sep 01 06:54:58 PM UTC 24 |
| Peak memory | 253272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024078988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.1024078988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.344278387 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 10864046620 ps |
| CPU time | 22.26 seconds |
| Started | Sep 01 06:54:57 PM UTC 24 |
| Finished | Sep 01 06:55:20 PM UTC 24 |
| Peak memory | 255516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344278387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.344278387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.3778688314 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1125078528 ps |
| CPU time | 19 seconds |
| Started | Sep 01 06:55:00 PM UTC 24 |
| Finished | Sep 01 06:55:20 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778688314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.3778688314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.2418258328 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 527808468 ps |
| CPU time | 16.17 seconds |
| Started | Sep 01 06:54:52 PM UTC 24 |
| Finished | Sep 01 06:55:10 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418258328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.2418258328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.698655392 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 183734952 ps |
| CPU time | 6.76 seconds |
| Started | Sep 01 06:54:52 PM UTC 24 |
| Finished | Sep 01 06:55:00 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698655392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.698655392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.3335642815 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 640537527 ps |
| CPU time | 7.58 seconds |
| Started | Sep 01 06:55:00 PM UTC 24 |
| Finished | Sep 01 06:55:08 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335642815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.3335642815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.2975673629 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1011661901 ps |
| CPU time | 9.01 seconds |
| Started | Sep 01 06:54:50 PM UTC 24 |
| Finished | Sep 01 06:55:00 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975673629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.2975673629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.2558536311 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 26532838780 ps |
| CPU time | 206.99 seconds |
| Started | Sep 01 06:55:03 PM UTC 24 |
| Finished | Sep 01 06:58:33 PM UTC 24 |
| Peak memory | 257564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558536311 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.2558536311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.4127035963 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 5437095111 ps |
| CPU time | 60.64 seconds |
| Started | Sep 01 06:55:00 PM UTC 24 |
| Finished | Sep 01 06:56:02 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127035963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.4127035963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.3723506287 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 683740923 ps |
| CPU time | 5.5 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:43 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723506287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.3723506287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.2006091533 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 646007145 ps |
| CPU time | 4.38 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:42 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006091533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2006091533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.2741688183 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 284250686 ps |
| CPU time | 4.32 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:42 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741688183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.2741688183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.3222239556 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 199414600 ps |
| CPU time | 4.11 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:42 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222239556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.3222239556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.1701898867 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 114940737 ps |
| CPU time | 3.31 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:41 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701898867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.1701898867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.61751087 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 123801594 ps |
| CPU time | 4.5 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:43 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61751087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.61751087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.2934075796 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 443633877 ps |
| CPU time | 4.69 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:43 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934075796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.2934075796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.1720609194 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 571533643 ps |
| CPU time | 5.16 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:43 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720609194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.1720609194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.629297648 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 2040116716 ps |
| CPU time | 7.01 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:45 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629297648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.629297648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.3046548729 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 259076028 ps |
| CPU time | 4.49 seconds |
| Started | Sep 01 06:55:14 PM UTC 24 |
| Finished | Sep 01 06:55:20 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046548729 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.3046548729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.1316423584 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1800155916 ps |
| CPU time | 14.34 seconds |
| Started | Sep 01 06:55:14 PM UTC 24 |
| Finished | Sep 01 06:55:30 PM UTC 24 |
| Peak memory | 253348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316423584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.1316423584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.547044395 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1115311540 ps |
| CPU time | 39.16 seconds |
| Started | Sep 01 06:55:09 PM UTC 24 |
| Finished | Sep 01 06:55:49 PM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547044395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.547044395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.454962820 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 840688485 ps |
| CPU time | 9.01 seconds |
| Started | Sep 01 06:55:09 PM UTC 24 |
| Finished | Sep 01 06:55:19 PM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454962820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.454962820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.1699824542 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 2105952440 ps |
| CPU time | 11.57 seconds |
| Started | Sep 01 06:55:03 PM UTC 24 |
| Finished | Sep 01 06:55:15 PM UTC 24 |
| Peak memory | 251396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699824542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1699824542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.2498932950 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 907745670 ps |
| CPU time | 22.8 seconds |
| Started | Sep 01 06:55:14 PM UTC 24 |
| Finished | Sep 01 06:55:38 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498932950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2498932950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.1235438704 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1315126996 ps |
| CPU time | 40.43 seconds |
| Started | Sep 01 06:55:14 PM UTC 24 |
| Finished | Sep 01 06:55:56 PM UTC 24 |
| Peak memory | 257720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235438704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.1235438704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.2146601424 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 7608445340 ps |
| CPU time | 22.62 seconds |
| Started | Sep 01 06:55:09 PM UTC 24 |
| Finished | Sep 01 06:55:33 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146601424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.2146601424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.3105713489 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 5262520017 ps |
| CPU time | 17.68 seconds |
| Started | Sep 01 06:55:07 PM UTC 24 |
| Finished | Sep 01 06:55:26 PM UTC 24 |
| Peak memory | 253336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105713489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.3105713489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.1299111181 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 130102448 ps |
| CPU time | 5.92 seconds |
| Started | Sep 01 06:55:14 PM UTC 24 |
| Finished | Sep 01 06:55:21 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299111181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1299111181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.1275359203 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 314331354 ps |
| CPU time | 9.13 seconds |
| Started | Sep 01 06:55:03 PM UTC 24 |
| Finished | Sep 01 06:55:13 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275359203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.1275359203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.1829976308 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 16324844887 ps |
| CPU time | 105.08 seconds |
| Started | Sep 01 06:55:14 PM UTC 24 |
| Finished | Sep 01 06:57:02 PM UTC 24 |
| Peak memory | 273940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829976308 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.1829976308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.3504153212 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1984474215 ps |
| CPU time | 32.47 seconds |
| Started | Sep 01 06:55:14 PM UTC 24 |
| Finished | Sep 01 06:55:48 PM UTC 24 |
| Peak memory | 257716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504153212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.3504153212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.299230635 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 176319551 ps |
| CPU time | 4.68 seconds |
| Started | Sep 01 07:03:37 PM UTC 24 |
| Finished | Sep 01 07:03:43 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299230635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.299230635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.484179549 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 152983259 ps |
| CPU time | 4.48 seconds |
| Started | Sep 01 07:03:40 PM UTC 24 |
| Finished | Sep 01 07:03:46 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484179549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.484179549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.3098506011 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 147974984 ps |
| CPU time | 3.54 seconds |
| Started | Sep 01 07:03:40 PM UTC 24 |
| Finished | Sep 01 07:03:45 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098506011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3098506011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.1776369953 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 610345503 ps |
| CPU time | 4.88 seconds |
| Started | Sep 01 07:03:40 PM UTC 24 |
| Finished | Sep 01 07:03:46 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776369953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.1776369953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.1473205583 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 156161509 ps |
| CPU time | 3.51 seconds |
| Started | Sep 01 07:03:40 PM UTC 24 |
| Finished | Sep 01 07:03:45 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473205583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1473205583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.452441065 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 172795458 ps |
| CPU time | 3.21 seconds |
| Started | Sep 01 07:03:40 PM UTC 24 |
| Finished | Sep 01 07:03:45 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452441065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.452441065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.3860731986 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 703839527 ps |
| CPU time | 4.61 seconds |
| Started | Sep 01 07:03:40 PM UTC 24 |
| Finished | Sep 01 07:03:46 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860731986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.3860731986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.1850423388 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 655220281 ps |
| CPU time | 6.52 seconds |
| Started | Sep 01 07:03:41 PM UTC 24 |
| Finished | Sep 01 07:03:48 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850423388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.1850423388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.1616347056 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 131841894 ps |
| CPU time | 3.82 seconds |
| Started | Sep 01 07:03:41 PM UTC 24 |
| Finished | Sep 01 07:03:45 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616347056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1616347056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.350988362 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 134807675 ps |
| CPU time | 4.74 seconds |
| Started | Sep 01 07:03:41 PM UTC 24 |
| Finished | Sep 01 07:03:46 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350988362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.350988362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.2866161564 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 800921439 ps |
| CPU time | 2.45 seconds |
| Started | Sep 01 06:55:26 PM UTC 24 |
| Finished | Sep 01 06:55:30 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866161564 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.2866161564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.1699648921 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 5207877446 ps |
| CPU time | 34.2 seconds |
| Started | Sep 01 06:55:23 PM UTC 24 |
| Finished | Sep 01 06:56:00 PM UTC 24 |
| Peak memory | 255476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699648921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.1699648921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.719121679 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 1049156752 ps |
| CPU time | 32.62 seconds |
| Started | Sep 01 06:55:23 PM UTC 24 |
| Finished | Sep 01 06:55:58 PM UTC 24 |
| Peak memory | 253220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719121679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.719121679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.1597251594 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1837366651 ps |
| CPU time | 31.35 seconds |
| Started | Sep 01 06:55:23 PM UTC 24 |
| Finished | Sep 01 06:55:57 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597251594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.1597251594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.307935893 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 90066348 ps |
| CPU time | 4.92 seconds |
| Started | Sep 01 06:55:16 PM UTC 24 |
| Finished | Sep 01 06:55:22 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307935893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.307935893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.1052882913 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 461478558 ps |
| CPU time | 9.83 seconds |
| Started | Sep 01 06:55:24 PM UTC 24 |
| Finished | Sep 01 06:55:35 PM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052882913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.1052882913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.733152239 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 360574195 ps |
| CPU time | 11.1 seconds |
| Started | Sep 01 06:55:23 PM UTC 24 |
| Finished | Sep 01 06:55:36 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733152239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.733152239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.3887781055 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 237634363 ps |
| CPU time | 10 seconds |
| Started | Sep 01 06:55:16 PM UTC 24 |
| Finished | Sep 01 06:55:27 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887781055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.3887781055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.329206564 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 3781953952 ps |
| CPU time | 10.41 seconds |
| Started | Sep 01 06:55:24 PM UTC 24 |
| Finished | Sep 01 06:55:35 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329206564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.329206564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.324999752 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 453624551 ps |
| CPU time | 10.7 seconds |
| Started | Sep 01 06:55:15 PM UTC 24 |
| Finished | Sep 01 06:55:26 PM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324999752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.324999752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.1146844082 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 10918693395 ps |
| CPU time | 83.55 seconds |
| Started | Sep 01 06:55:25 PM UTC 24 |
| Finished | Sep 01 06:56:52 PM UTC 24 |
| Peak memory | 255580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146844082 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.1146844082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.2590169709 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1636176344 ps |
| CPU time | 16.34 seconds |
| Started | Sep 01 06:55:24 PM UTC 24 |
| Finished | Sep 01 06:55:42 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590169709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.2590169709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.1160674665 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 171621348 ps |
| CPU time | 3.59 seconds |
| Started | Sep 01 07:03:41 PM UTC 24 |
| Finished | Sep 01 07:03:45 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160674665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.1160674665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.2725320774 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 445415224 ps |
| CPU time | 3.67 seconds |
| Started | Sep 01 07:03:41 PM UTC 24 |
| Finished | Sep 01 07:03:45 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725320774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.2725320774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.2454061821 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 163331242 ps |
| CPU time | 4.12 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:50 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454061821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2454061821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.4255798842 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 251243859 ps |
| CPU time | 3.51 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:49 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255798842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.4255798842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.3245351170 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 430908700 ps |
| CPU time | 4.4 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:50 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245351170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.3245351170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.2561698582 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 388216291 ps |
| CPU time | 4.82 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:51 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561698582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.2561698582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1917254063 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 1463893604 ps |
| CPU time | 4.48 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:51 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917254063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.1917254063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.3819261557 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 120472941 ps |
| CPU time | 3.8 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:50 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819261557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.3819261557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.1121346953 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 45639469 ps |
| CPU time | 2.43 seconds |
| Started | Sep 01 06:55:36 PM UTC 24 |
| Finished | Sep 01 06:55:40 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121346953 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.1121346953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.3841970147 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 893828507 ps |
| CPU time | 16.29 seconds |
| Started | Sep 01 06:55:32 PM UTC 24 |
| Finished | Sep 01 06:55:49 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841970147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.3841970147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.2914144273 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3139797474 ps |
| CPU time | 37.71 seconds |
| Started | Sep 01 06:55:32 PM UTC 24 |
| Finished | Sep 01 06:56:11 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914144273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.2914144273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.2913308557 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 3332735758 ps |
| CPU time | 18.44 seconds |
| Started | Sep 01 06:55:32 PM UTC 24 |
| Finished | Sep 01 06:55:52 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913308557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.2913308557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.2745303584 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 420650669 ps |
| CPU time | 3.38 seconds |
| Started | Sep 01 06:55:28 PM UTC 24 |
| Finished | Sep 01 06:55:33 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745303584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.2745303584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.1129394822 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 11110094083 ps |
| CPU time | 84.31 seconds |
| Started | Sep 01 06:55:32 PM UTC 24 |
| Finished | Sep 01 06:56:58 PM UTC 24 |
| Peak memory | 269916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129394822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.1129394822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.1166190629 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 12017454203 ps |
| CPU time | 33.26 seconds |
| Started | Sep 01 06:55:32 PM UTC 24 |
| Finished | Sep 01 06:56:07 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166190629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.1166190629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.1613554727 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1854705229 ps |
| CPU time | 6.96 seconds |
| Started | Sep 01 06:55:29 PM UTC 24 |
| Finished | Sep 01 06:55:37 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613554727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1613554727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.4121499154 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1016399829 ps |
| CPU time | 28.19 seconds |
| Started | Sep 01 06:55:29 PM UTC 24 |
| Finished | Sep 01 06:55:59 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121499154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.4121499154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.2093088237 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 2231599061 ps |
| CPU time | 11.89 seconds |
| Started | Sep 01 06:55:33 PM UTC 24 |
| Finished | Sep 01 06:55:46 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093088237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.2093088237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.2799891468 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 131987179 ps |
| CPU time | 5.25 seconds |
| Started | Sep 01 06:55:26 PM UTC 24 |
| Finished | Sep 01 06:55:33 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799891468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.2799891468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.2492232301 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1372341972 ps |
| CPU time | 16.12 seconds |
| Started | Sep 01 06:55:36 PM UTC 24 |
| Finished | Sep 01 06:55:54 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492232301 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.2492232301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.365368915 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4256326922 ps |
| CPU time | 87.5 seconds |
| Started | Sep 01 06:55:35 PM UTC 24 |
| Finished | Sep 01 06:57:04 PM UTC 24 |
| Peak memory | 257880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=365368915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.365368915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.722855555 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2435044219 ps |
| CPU time | 12.03 seconds |
| Started | Sep 01 06:55:35 PM UTC 24 |
| Finished | Sep 01 06:55:48 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722855555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.722855555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.82735579 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 123346244 ps |
| CPU time | 4.51 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:51 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82735579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.82735579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.1042105902 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 247032262 ps |
| CPU time | 4.01 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:50 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042105902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.1042105902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.905595976 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 177324843 ps |
| CPU time | 4.91 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:51 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905595976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.905595976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.1032317735 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 384679902 ps |
| CPU time | 4.83 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:51 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032317735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1032317735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.2221833767 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 345745151 ps |
| CPU time | 4.41 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:51 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221833767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.2221833767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.381359496 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 292526891 ps |
| CPU time | 3.75 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:50 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381359496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.381359496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.2499038823 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 185193823 ps |
| CPU time | 3.79 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:50 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499038823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.2499038823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3423317548 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 143405172 ps |
| CPU time | 3.73 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:50 PM UTC 24 |
| Peak memory | 251128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423317548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.3423317548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.4007624114 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 289532821 ps |
| CPU time | 4.42 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:51 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007624114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.4007624114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.2423415441 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 206470318 ps |
| CPU time | 3.5 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:50 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423415441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.2423415441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.789821817 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 148278162 ps |
| CPU time | 2.84 seconds |
| Started | Sep 01 06:55:50 PM UTC 24 |
| Finished | Sep 01 06:55:54 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789821817 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.789821817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.3712980296 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 128559098 ps |
| CPU time | 5.45 seconds |
| Started | Sep 01 06:55:41 PM UTC 24 |
| Finished | Sep 01 06:55:47 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712980296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.3712980296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.2088320881 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 2293865498 ps |
| CPU time | 26.11 seconds |
| Started | Sep 01 06:55:40 PM UTC 24 |
| Finished | Sep 01 06:56:08 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088320881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.2088320881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.2964172425 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 1187211798 ps |
| CPU time | 30.73 seconds |
| Started | Sep 01 06:55:40 PM UTC 24 |
| Finished | Sep 01 06:56:13 PM UTC 24 |
| Peak memory | 253692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964172425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.2964172425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.1375877426 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 121241906 ps |
| CPU time | 5.18 seconds |
| Started | Sep 01 06:55:40 PM UTC 24 |
| Finished | Sep 01 06:55:47 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375877426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1375877426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.1127318438 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2381223473 ps |
| CPU time | 29.14 seconds |
| Started | Sep 01 06:55:43 PM UTC 24 |
| Finished | Sep 01 06:56:14 PM UTC 24 |
| Peak memory | 257532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127318438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.1127318438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.3623199218 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 15534538339 ps |
| CPU time | 42.47 seconds |
| Started | Sep 01 06:55:48 PM UTC 24 |
| Finished | Sep 01 06:56:32 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623199218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.3623199218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.1963160966 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 416318850 ps |
| CPU time | 24.53 seconds |
| Started | Sep 01 06:55:40 PM UTC 24 |
| Finished | Sep 01 06:56:07 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963160966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.1963160966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.1766491678 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 758372457 ps |
| CPU time | 17.21 seconds |
| Started | Sep 01 06:55:40 PM UTC 24 |
| Finished | Sep 01 06:55:59 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766491678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.1766491678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.3749524468 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 668705117 ps |
| CPU time | 10.08 seconds |
| Started | Sep 01 06:55:48 PM UTC 24 |
| Finished | Sep 01 06:56:00 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749524468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.3749524468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.913921686 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11626480101 ps |
| CPU time | 85.94 seconds |
| Started | Sep 01 06:55:50 PM UTC 24 |
| Finished | Sep 01 06:57:18 PM UTC 24 |
| Peak memory | 274136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=913921686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.913921686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.1664980517 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2137095122 ps |
| CPU time | 37.83 seconds |
| Started | Sep 01 06:55:48 PM UTC 24 |
| Finished | Sep 01 06:56:28 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664980517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.1664980517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.670862857 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 339963283 ps |
| CPU time | 3.68 seconds |
| Started | Sep 01 07:03:45 PM UTC 24 |
| Finished | Sep 01 07:03:50 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670862857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.670862857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.1766604412 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 154643248 ps |
| CPU time | 3.87 seconds |
| Started | Sep 01 07:03:49 PM UTC 24 |
| Finished | Sep 01 07:03:54 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766604412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1766604412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.292121742 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 361798541 ps |
| CPU time | 4.13 seconds |
| Started | Sep 01 07:03:49 PM UTC 24 |
| Finished | Sep 01 07:03:54 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292121742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.292121742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.2214307940 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 500707337 ps |
| CPU time | 4.28 seconds |
| Started | Sep 01 07:03:49 PM UTC 24 |
| Finished | Sep 01 07:03:55 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214307940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.2214307940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.3222692271 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 109033759 ps |
| CPU time | 2.84 seconds |
| Started | Sep 01 07:03:49 PM UTC 24 |
| Finished | Sep 01 07:03:53 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222692271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.3222692271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.576214337 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 414160309 ps |
| CPU time | 3.36 seconds |
| Started | Sep 01 07:03:49 PM UTC 24 |
| Finished | Sep 01 07:03:54 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576214337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.576214337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.3409931671 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 2643803355 ps |
| CPU time | 5.64 seconds |
| Started | Sep 01 07:03:49 PM UTC 24 |
| Finished | Sep 01 07:03:56 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409931671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.3409931671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.1810378009 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 189527744 ps |
| CPU time | 3.5 seconds |
| Started | Sep 01 07:03:49 PM UTC 24 |
| Finished | Sep 01 07:03:54 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810378009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.1810378009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.3264236861 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 2656690087 ps |
| CPU time | 5.19 seconds |
| Started | Sep 01 07:03:49 PM UTC 24 |
| Finished | Sep 01 07:03:56 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264236861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.3264236861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.2964652836 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 69615006 ps |
| CPU time | 2.77 seconds |
| Started | Sep 01 06:56:02 PM UTC 24 |
| Finished | Sep 01 06:56:06 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964652836 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2964652836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.1906246137 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 262756633 ps |
| CPU time | 9.57 seconds |
| Started | Sep 01 06:55:58 PM UTC 24 |
| Finished | Sep 01 06:56:08 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906246137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.1906246137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.3114130257 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1123797719 ps |
| CPU time | 13.18 seconds |
| Started | Sep 01 06:55:56 PM UTC 24 |
| Finished | Sep 01 06:56:10 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114130257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.3114130257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.1528876264 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 734201727 ps |
| CPU time | 19.4 seconds |
| Started | Sep 01 06:55:56 PM UTC 24 |
| Finished | Sep 01 06:56:16 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528876264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.1528876264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.1870198423 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2177428666 ps |
| CPU time | 7.27 seconds |
| Started | Sep 01 06:55:54 PM UTC 24 |
| Finished | Sep 01 06:56:02 PM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870198423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.1870198423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.2421592684 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 2656934616 ps |
| CPU time | 32.06 seconds |
| Started | Sep 01 06:55:58 PM UTC 24 |
| Finished | Sep 01 06:56:31 PM UTC 24 |
| Peak memory | 253488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421592684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.2421592684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.4269754046 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 16183507731 ps |
| CPU time | 66.96 seconds |
| Started | Sep 01 06:56:00 PM UTC 24 |
| Finished | Sep 01 06:57:09 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269754046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.4269754046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.1882317413 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 313186357 ps |
| CPU time | 5.03 seconds |
| Started | Sep 01 06:55:55 PM UTC 24 |
| Finished | Sep 01 06:56:02 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882317413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.1882317413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.3613518484 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 491758185 ps |
| CPU time | 17.11 seconds |
| Started | Sep 01 06:55:54 PM UTC 24 |
| Finished | Sep 01 06:56:12 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613518484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3613518484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.3781399567 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 441840053 ps |
| CPU time | 9.06 seconds |
| Started | Sep 01 06:56:00 PM UTC 24 |
| Finished | Sep 01 06:56:11 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781399567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.3781399567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.2125558065 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 260904648 ps |
| CPU time | 10.85 seconds |
| Started | Sep 01 06:55:54 PM UTC 24 |
| Finished | Sep 01 06:56:06 PM UTC 24 |
| Peak memory | 257436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125558065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2125558065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.687746028 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 13897044460 ps |
| CPU time | 146.85 seconds |
| Started | Sep 01 06:56:01 PM UTC 24 |
| Finished | Sep 01 06:58:30 PM UTC 24 |
| Peak memory | 271828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687746028 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.687746028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.1639184476 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 177390822 ps |
| CPU time | 3.93 seconds |
| Started | Sep 01 07:03:50 PM UTC 24 |
| Finished | Sep 01 07:03:55 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639184476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.1639184476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.3545498092 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 319895302 ps |
| CPU time | 3.98 seconds |
| Started | Sep 01 07:03:50 PM UTC 24 |
| Finished | Sep 01 07:03:55 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545498092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.3545498092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.3363769916 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 117887829 ps |
| CPU time | 4.54 seconds |
| Started | Sep 01 07:03:50 PM UTC 24 |
| Finished | Sep 01 07:03:55 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363769916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.3363769916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.576305583 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 1652054055 ps |
| CPU time | 5.13 seconds |
| Started | Sep 01 07:03:50 PM UTC 24 |
| Finished | Sep 01 07:03:56 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576305583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.576305583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.3095008172 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 151353065 ps |
| CPU time | 4.2 seconds |
| Started | Sep 01 07:03:50 PM UTC 24 |
| Finished | Sep 01 07:03:55 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095008172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.3095008172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.842027118 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 281511650 ps |
| CPU time | 3.76 seconds |
| Started | Sep 01 07:03:50 PM UTC 24 |
| Finished | Sep 01 07:03:55 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842027118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.842027118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.4180514544 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 374943373 ps |
| CPU time | 4.35 seconds |
| Started | Sep 01 07:03:50 PM UTC 24 |
| Finished | Sep 01 07:03:55 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180514544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.4180514544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.2668779702 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 600392894 ps |
| CPU time | 4.91 seconds |
| Started | Sep 01 07:03:50 PM UTC 24 |
| Finished | Sep 01 07:03:56 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668779702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.2668779702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.874377430 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 203719911 ps |
| CPU time | 3.9 seconds |
| Started | Sep 01 07:03:50 PM UTC 24 |
| Finished | Sep 01 07:03:55 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874377430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.874377430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.1431486626 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 420180973 ps |
| CPU time | 3.69 seconds |
| Started | Sep 01 07:03:50 PM UTC 24 |
| Finished | Sep 01 07:03:55 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431486626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.1431486626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.453600576 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 680117192 ps |
| CPU time | 4.2 seconds |
| Started | Sep 01 06:56:14 PM UTC 24 |
| Finished | Sep 01 06:56:19 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453600576 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.453600576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.2158058875 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 6588827116 ps |
| CPU time | 26.9 seconds |
| Started | Sep 01 06:56:09 PM UTC 24 |
| Finished | Sep 01 06:56:38 PM UTC 24 |
| Peak memory | 253660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158058875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.2158058875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.863041259 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 5568738158 ps |
| CPU time | 42.37 seconds |
| Started | Sep 01 06:56:09 PM UTC 24 |
| Finished | Sep 01 06:56:53 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863041259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.863041259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.1913095785 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 1465000523 ps |
| CPU time | 6.24 seconds |
| Started | Sep 01 06:56:07 PM UTC 24 |
| Finished | Sep 01 06:56:14 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913095785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.1913095785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.556476354 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 537230184 ps |
| CPU time | 5.8 seconds |
| Started | Sep 01 06:56:03 PM UTC 24 |
| Finished | Sep 01 06:56:09 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556476354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.556476354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.1670895386 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 13327234514 ps |
| CPU time | 32.65 seconds |
| Started | Sep 01 06:56:09 PM UTC 24 |
| Finished | Sep 01 06:56:43 PM UTC 24 |
| Peak memory | 255448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670895386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.1670895386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.3576565224 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1341053266 ps |
| CPU time | 36.55 seconds |
| Started | Sep 01 06:56:09 PM UTC 24 |
| Finished | Sep 01 06:56:48 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576565224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.3576565224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.2237563496 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1168759174 ps |
| CPU time | 20.72 seconds |
| Started | Sep 01 06:56:07 PM UTC 24 |
| Finished | Sep 01 06:56:29 PM UTC 24 |
| Peak memory | 253392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237563496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.2237563496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.3181828847 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 468054630 ps |
| CPU time | 12.45 seconds |
| Started | Sep 01 06:56:04 PM UTC 24 |
| Finished | Sep 01 06:56:18 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181828847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.3181828847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.2138583747 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 784698203 ps |
| CPU time | 7.56 seconds |
| Started | Sep 01 06:56:11 PM UTC 24 |
| Finished | Sep 01 06:56:20 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138583747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.2138583747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.4210888760 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 565334562 ps |
| CPU time | 9.3 seconds |
| Started | Sep 01 06:56:02 PM UTC 24 |
| Finished | Sep 01 06:56:13 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210888760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.4210888760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.1912106908 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 7321014080 ps |
| CPU time | 47.68 seconds |
| Started | Sep 01 06:56:13 PM UTC 24 |
| Finished | Sep 01 06:57:03 PM UTC 24 |
| Peak memory | 254948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912106908 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.1912106908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.730800472 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 964308374 ps |
| CPU time | 16.67 seconds |
| Started | Sep 01 06:56:11 PM UTC 24 |
| Finished | Sep 01 06:56:29 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730800472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.730800472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.2568700714 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 112895878 ps |
| CPU time | 3.36 seconds |
| Started | Sep 01 07:03:50 PM UTC 24 |
| Finished | Sep 01 07:03:54 PM UTC 24 |
| Peak memory | 253264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568700714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2568700714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.2917434652 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 1651666959 ps |
| CPU time | 6.49 seconds |
| Started | Sep 01 07:03:50 PM UTC 24 |
| Finished | Sep 01 07:03:58 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917434652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.2917434652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.569142377 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 283857952 ps |
| CPU time | 3.53 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:01 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569142377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.569142377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.79374351 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 186932314 ps |
| CPU time | 5.27 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:03 PM UTC 24 |
| Peak memory | 251020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79374351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.79374351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.729498815 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 474101149 ps |
| CPU time | 4.34 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:02 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729498815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.729498815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.2799169035 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 116613281 ps |
| CPU time | 3.66 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:02 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799169035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.2799169035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.1175313883 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 520929962 ps |
| CPU time | 4.62 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:03 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175313883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.1175313883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.4075512804 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 295093396 ps |
| CPU time | 4.32 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:02 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075512804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.4075512804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.3875914944 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 2917160449 ps |
| CPU time | 6.12 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:04 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875914944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.3875914944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.3759156254 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 111589348 ps |
| CPU time | 2.87 seconds |
| Started | Sep 01 06:56:31 PM UTC 24 |
| Finished | Sep 01 06:56:35 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759156254 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.3759156254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.2270789145 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 1203091679 ps |
| CPU time | 30.6 seconds |
| Started | Sep 01 06:56:19 PM UTC 24 |
| Finished | Sep 01 06:56:50 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270789145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.2270789145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.2430112803 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1926484607 ps |
| CPU time | 35.4 seconds |
| Started | Sep 01 06:56:17 PM UTC 24 |
| Finished | Sep 01 06:56:54 PM UTC 24 |
| Peak memory | 253688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430112803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.2430112803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.4117996026 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 208409059 ps |
| CPU time | 6.37 seconds |
| Started | Sep 01 06:56:16 PM UTC 24 |
| Finished | Sep 01 06:56:23 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117996026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.4117996026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.2887277599 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 24914630045 ps |
| CPU time | 51.52 seconds |
| Started | Sep 01 06:56:23 PM UTC 24 |
| Finished | Sep 01 06:57:16 PM UTC 24 |
| Peak memory | 268156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887277599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.2887277599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.1321665964 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1849515433 ps |
| CPU time | 39.81 seconds |
| Started | Sep 01 06:56:23 PM UTC 24 |
| Finished | Sep 01 06:57:04 PM UTC 24 |
| Peak memory | 253624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321665964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.1321665964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.2516890038 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 713674012 ps |
| CPU time | 29.41 seconds |
| Started | Sep 01 06:56:16 PM UTC 24 |
| Finished | Sep 01 06:56:47 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516890038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.2516890038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.637988653 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1109504918 ps |
| CPU time | 15.66 seconds |
| Started | Sep 01 06:56:23 PM UTC 24 |
| Finished | Sep 01 06:56:40 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637988653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.637988653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.39282743 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 133631775 ps |
| CPU time | 5.53 seconds |
| Started | Sep 01 06:56:14 PM UTC 24 |
| Finished | Sep 01 06:56:20 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39282743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.39282743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.2693321196 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 22722565283 ps |
| CPU time | 132.29 seconds |
| Started | Sep 01 06:56:29 PM UTC 24 |
| Finished | Sep 01 06:58:44 PM UTC 24 |
| Peak memory | 257424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693321196 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.2693321196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.1450062553 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1217598613 ps |
| CPU time | 35.53 seconds |
| Started | Sep 01 06:56:24 PM UTC 24 |
| Finished | Sep 01 06:57:01 PM UTC 24 |
| Peak memory | 253620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450062553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.1450062553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.958508440 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 450282667 ps |
| CPU time | 3.64 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:02 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958508440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.958508440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.3741559750 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 111373438 ps |
| CPU time | 4.6 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:03 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741559750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.3741559750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.899138472 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 1927535982 ps |
| CPU time | 5.54 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:04 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899138472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.899138472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.144947926 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 581479591 ps |
| CPU time | 4.69 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:03 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144947926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.144947926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.3202423549 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 128886354 ps |
| CPU time | 3.79 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:02 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202423549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3202423549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.3336911830 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 307341945 ps |
| CPU time | 4.19 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:03 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336911830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.3336911830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.43104768 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 572383367 ps |
| CPU time | 5.11 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:04 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43104768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.43104768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.3707618554 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 138890352 ps |
| CPU time | 4.16 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:03 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707618554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.3707618554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.2816112926 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 2404479640 ps |
| CPU time | 5.3 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:04 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816112926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.2816112926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.1443004511 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 108149997 ps |
| CPU time | 4.16 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:03 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443004511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.1443004511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.1301928405 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 198135227 ps |
| CPU time | 2.86 seconds |
| Started | Sep 01 06:56:45 PM UTC 24 |
| Finished | Sep 01 06:56:49 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301928405 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.1301928405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.2481512854 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 699222063 ps |
| CPU time | 9.26 seconds |
| Started | Sep 01 06:56:43 PM UTC 24 |
| Finished | Sep 01 06:56:53 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481512854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.2481512854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.4034583256 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1265871350 ps |
| CPU time | 22.63 seconds |
| Started | Sep 01 06:56:43 PM UTC 24 |
| Finished | Sep 01 06:57:07 PM UTC 24 |
| Peak memory | 251104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034583256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.4034583256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.630022844 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 2412302429 ps |
| CPU time | 33.61 seconds |
| Started | Sep 01 06:56:38 PM UTC 24 |
| Finished | Sep 01 06:57:13 PM UTC 24 |
| Peak memory | 253500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630022844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.630022844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.4192636557 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 265279822 ps |
| CPU time | 5.96 seconds |
| Started | Sep 01 06:56:33 PM UTC 24 |
| Finished | Sep 01 06:56:40 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192636557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.4192636557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.3167501209 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1169467827 ps |
| CPU time | 14.55 seconds |
| Started | Sep 01 06:56:43 PM UTC 24 |
| Finished | Sep 01 06:56:59 PM UTC 24 |
| Peak memory | 253620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167501209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.3167501209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.3765307784 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 19607136278 ps |
| CPU time | 82.95 seconds |
| Started | Sep 01 06:56:43 PM UTC 24 |
| Finished | Sep 01 06:58:08 PM UTC 24 |
| Peak memory | 251104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765307784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.3765307784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.1401989894 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 107120725 ps |
| CPU time | 4.35 seconds |
| Started | Sep 01 06:56:36 PM UTC 24 |
| Finished | Sep 01 06:56:42 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401989894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.1401989894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.2904035254 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1155911629 ps |
| CPU time | 20.6 seconds |
| Started | Sep 01 06:56:34 PM UTC 24 |
| Finished | Sep 01 06:56:56 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904035254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.2904035254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.1733676123 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1065741219 ps |
| CPU time | 13.06 seconds |
| Started | Sep 01 06:56:43 PM UTC 24 |
| Finished | Sep 01 06:56:58 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733676123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.1733676123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.1268512717 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 144498133 ps |
| CPU time | 7.09 seconds |
| Started | Sep 01 06:56:31 PM UTC 24 |
| Finished | Sep 01 06:56:39 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268512717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1268512717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.2964672535 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 6396046399 ps |
| CPU time | 76.34 seconds |
| Started | Sep 01 06:56:43 PM UTC 24 |
| Finished | Sep 01 06:58:02 PM UTC 24 |
| Peak memory | 253376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964672535 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.2964672535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.2348711137 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 10521509158 ps |
| CPU time | 23.75 seconds |
| Started | Sep 01 06:56:43 PM UTC 24 |
| Finished | Sep 01 06:57:08 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348711137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.2348711137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.1809626749 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 419788531 ps |
| CPU time | 5.1 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:04 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809626749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.1809626749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.906653538 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 439587177 ps |
| CPU time | 5.91 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:04 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906653538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.906653538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.1594859940 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 233829684 ps |
| CPU time | 3.6 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:02 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594859940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1594859940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.268665106 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 274803785 ps |
| CPU time | 5.78 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:05 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268665106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.268665106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.572400947 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 1941103131 ps |
| CPU time | 4.8 seconds |
| Started | Sep 01 07:03:57 PM UTC 24 |
| Finished | Sep 01 07:04:04 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572400947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.572400947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.3212391943 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 514728723 ps |
| CPU time | 4.99 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:04 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212391943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.3212391943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.2192035867 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 2285603940 ps |
| CPU time | 6.16 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:05 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192035867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.2192035867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.809609923 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 261142528 ps |
| CPU time | 3.94 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:03 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809609923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.809609923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.3981175899 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 188657031 ps |
| CPU time | 4.45 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:03 PM UTC 24 |
| Peak memory | 253588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981175899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.3981175899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.744511732 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 769321984 ps |
| CPU time | 3.45 seconds |
| Started | Sep 01 06:50:11 PM UTC 24 |
| Finished | Sep 01 06:50:16 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744511732 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.744511732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.2781350828 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 500096635 ps |
| CPU time | 8.32 seconds |
| Started | Sep 01 06:49:58 PM UTC 24 |
| Finished | Sep 01 06:50:07 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781350828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.2781350828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.3215290306 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 421304193 ps |
| CPU time | 12.97 seconds |
| Started | Sep 01 06:50:05 PM UTC 24 |
| Finished | Sep 01 06:50:19 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215290306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.3215290306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.203010063 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2934070862 ps |
| CPU time | 31.22 seconds |
| Started | Sep 01 06:50:02 PM UTC 24 |
| Finished | Sep 01 06:50:35 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203010063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.203010063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.3531542927 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 10014354265 ps |
| CPU time | 26.48 seconds |
| Started | Sep 01 06:50:00 PM UTC 24 |
| Finished | Sep 01 06:50:28 PM UTC 24 |
| Peak memory | 253852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531542927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.3531542927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.3615360841 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 269994836 ps |
| CPU time | 6 seconds |
| Started | Sep 01 06:49:58 PM UTC 24 |
| Finished | Sep 01 06:50:05 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615360841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.3615360841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.4133319789 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 219484791 ps |
| CPU time | 12.52 seconds |
| Started | Sep 01 06:50:07 PM UTC 24 |
| Finished | Sep 01 06:50:20 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133319789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.4133319789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.3514069912 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 188064640 ps |
| CPU time | 4.53 seconds |
| Started | Sep 01 06:50:09 PM UTC 24 |
| Finished | Sep 01 06:50:15 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514069912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3514069912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.4163829057 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 11075625555 ps |
| CPU time | 249.69 seconds |
| Started | Sep 01 06:50:11 PM UTC 24 |
| Finished | Sep 01 06:54:25 PM UTC 24 |
| Peak memory | 298156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163829057 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.4163829057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.3851523284 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 5268929705 ps |
| CPU time | 17.61 seconds |
| Started | Sep 01 06:49:53 PM UTC 24 |
| Finished | Sep 01 06:50:12 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851523284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.3851523284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.559852590 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 25882912321 ps |
| CPU time | 74.07 seconds |
| Started | Sep 01 06:50:09 PM UTC 24 |
| Finished | Sep 01 06:51:25 PM UTC 24 |
| Peak memory | 267800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=559852590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.559852590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.2168807925 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 47084962 ps |
| CPU time | 2.36 seconds |
| Started | Sep 01 06:57:03 PM UTC 24 |
| Finished | Sep 01 06:57:06 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168807925 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.2168807925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.4098511327 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 829625173 ps |
| CPU time | 24.79 seconds |
| Started | Sep 01 06:56:53 PM UTC 24 |
| Finished | Sep 01 06:57:20 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098511327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.4098511327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.2039420858 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 5772839866 ps |
| CPU time | 37.37 seconds |
| Started | Sep 01 06:56:52 PM UTC 24 |
| Finished | Sep 01 06:57:31 PM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039420858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2039420858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.4097960090 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 2220782015 ps |
| CPU time | 10.82 seconds |
| Started | Sep 01 06:56:52 PM UTC 24 |
| Finished | Sep 01 06:57:04 PM UTC 24 |
| Peak memory | 253336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097960090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.4097960090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.3765355733 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1053989179 ps |
| CPU time | 9.47 seconds |
| Started | Sep 01 06:56:57 PM UTC 24 |
| Finished | Sep 01 06:57:07 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765355733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.3765355733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.236846216 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 5435265839 ps |
| CPU time | 21.36 seconds |
| Started | Sep 01 06:56:57 PM UTC 24 |
| Finished | Sep 01 06:57:20 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236846216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.236846216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.755183465 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 261092158 ps |
| CPU time | 7.54 seconds |
| Started | Sep 01 06:56:52 PM UTC 24 |
| Finished | Sep 01 06:57:01 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755183465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.755183465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.3183356055 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1072495852 ps |
| CPU time | 17.92 seconds |
| Started | Sep 01 06:56:52 PM UTC 24 |
| Finished | Sep 01 06:57:11 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183356055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3183356055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.646290853 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 2047388506 ps |
| CPU time | 6.87 seconds |
| Started | Sep 01 06:56:57 PM UTC 24 |
| Finished | Sep 01 06:57:05 PM UTC 24 |
| Peak memory | 257616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646290853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.646290853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.4026843205 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 307805955 ps |
| CPU time | 7.82 seconds |
| Started | Sep 01 06:56:48 PM UTC 24 |
| Finished | Sep 01 06:56:57 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026843205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.4026843205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.669584263 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 17442192929 ps |
| CPU time | 213.18 seconds |
| Started | Sep 01 06:57:03 PM UTC 24 |
| Finished | Sep 01 07:00:40 PM UTC 24 |
| Peak memory | 257812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669584263 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.669584263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.656524258 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 402962658 ps |
| CPU time | 15.69 seconds |
| Started | Sep 01 06:56:57 PM UTC 24 |
| Finished | Sep 01 06:57:14 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656524258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.656524258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.267910291 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 48855485 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 06:57:11 PM UTC 24 |
| Finished | Sep 01 06:57:14 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267910291 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.267910291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.3508981927 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 6400775931 ps |
| CPU time | 14.9 seconds |
| Started | Sep 01 06:57:11 PM UTC 24 |
| Finished | Sep 01 06:57:27 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508981927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3508981927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.4203524164 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 692563451 ps |
| CPU time | 23.21 seconds |
| Started | Sep 01 06:57:03 PM UTC 24 |
| Finished | Sep 01 06:57:28 PM UTC 24 |
| Peak memory | 253372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203524164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.4203524164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.3644020390 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1428652726 ps |
| CPU time | 17.63 seconds |
| Started | Sep 01 06:57:03 PM UTC 24 |
| Finished | Sep 01 06:57:22 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644020390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.3644020390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.4272657858 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2514429201 ps |
| CPU time | 8.57 seconds |
| Started | Sep 01 06:57:03 PM UTC 24 |
| Finished | Sep 01 06:57:13 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272657858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.4272657858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.615869674 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1889265009 ps |
| CPU time | 31.81 seconds |
| Started | Sep 01 06:57:11 PM UTC 24 |
| Finished | Sep 01 06:57:44 PM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615869674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.615869674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.819534023 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 384431798 ps |
| CPU time | 14.59 seconds |
| Started | Sep 01 06:57:11 PM UTC 24 |
| Finished | Sep 01 06:57:27 PM UTC 24 |
| Peak memory | 253616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819534023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.819534023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.3195059209 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 378237118 ps |
| CPU time | 12.31 seconds |
| Started | Sep 01 06:57:03 PM UTC 24 |
| Finished | Sep 01 06:57:17 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195059209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.3195059209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.2204940331 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 497281847 ps |
| CPU time | 6.61 seconds |
| Started | Sep 01 06:57:03 PM UTC 24 |
| Finished | Sep 01 06:57:11 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204940331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.2204940331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.3615511985 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 204362401 ps |
| CPU time | 8.1 seconds |
| Started | Sep 01 06:57:11 PM UTC 24 |
| Finished | Sep 01 06:57:20 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615511985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.3615511985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.129090831 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 366079178 ps |
| CPU time | 6.62 seconds |
| Started | Sep 01 06:57:03 PM UTC 24 |
| Finished | Sep 01 06:57:11 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129090831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.129090831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.686809074 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 7443134625 ps |
| CPU time | 66.69 seconds |
| Started | Sep 01 06:57:11 PM UTC 24 |
| Finished | Sep 01 06:58:19 PM UTC 24 |
| Peak memory | 253456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686809074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.686809074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.1595978816 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 56396183 ps |
| CPU time | 2.82 seconds |
| Started | Sep 01 06:57:18 PM UTC 24 |
| Finished | Sep 01 06:57:22 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595978816 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.1595978816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.2082635797 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 25092850696 ps |
| CPU time | 57.14 seconds |
| Started | Sep 01 06:57:14 PM UTC 24 |
| Finished | Sep 01 06:58:13 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082635797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.2082635797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.924241112 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 3130498544 ps |
| CPU time | 19.79 seconds |
| Started | Sep 01 06:57:14 PM UTC 24 |
| Finished | Sep 01 06:57:35 PM UTC 24 |
| Peak memory | 253284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924241112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.924241112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.2969677059 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 2342190480 ps |
| CPU time | 26.09 seconds |
| Started | Sep 01 06:57:13 PM UTC 24 |
| Finished | Sep 01 06:57:41 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969677059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.2969677059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.4149557370 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 108296495 ps |
| CPU time | 4.61 seconds |
| Started | Sep 01 06:57:11 PM UTC 24 |
| Finished | Sep 01 06:57:17 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149557370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.4149557370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.4038751814 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 11679208203 ps |
| CPU time | 40.96 seconds |
| Started | Sep 01 06:57:14 PM UTC 24 |
| Finished | Sep 01 06:57:56 PM UTC 24 |
| Peak memory | 257820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038751814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.4038751814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.846454090 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 14593415548 ps |
| CPU time | 40.97 seconds |
| Started | Sep 01 06:57:16 PM UTC 24 |
| Finished | Sep 01 06:57:59 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846454090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.846454090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.2061831840 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 742766431 ps |
| CPU time | 15.47 seconds |
| Started | Sep 01 06:57:13 PM UTC 24 |
| Finished | Sep 01 06:57:30 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061831840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.2061831840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.3382438572 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2621983047 ps |
| CPU time | 10.37 seconds |
| Started | Sep 01 06:57:11 PM UTC 24 |
| Finished | Sep 01 06:57:23 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382438572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.3382438572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.4169084382 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 341800945 ps |
| CPU time | 9.21 seconds |
| Started | Sep 01 06:57:16 PM UTC 24 |
| Finished | Sep 01 06:57:26 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169084382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.4169084382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.2666054719 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 511334230 ps |
| CPU time | 8.84 seconds |
| Started | Sep 01 06:57:11 PM UTC 24 |
| Finished | Sep 01 06:57:21 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666054719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.2666054719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.2639547069 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 11810076616 ps |
| CPU time | 115.4 seconds |
| Started | Sep 01 06:57:18 PM UTC 24 |
| Finished | Sep 01 06:59:16 PM UTC 24 |
| Peak memory | 257472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639547069 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.2639547069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.3766702372 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 948733113 ps |
| CPU time | 22.41 seconds |
| Started | Sep 01 06:57:16 PM UTC 24 |
| Finished | Sep 01 06:57:40 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766702372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.3766702372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.2725107639 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 65405939 ps |
| CPU time | 3.13 seconds |
| Started | Sep 01 06:57:48 PM UTC 24 |
| Finished | Sep 01 06:57:52 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725107639 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.2725107639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.3388333641 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2532325902 ps |
| CPU time | 19.5 seconds |
| Started | Sep 01 06:57:24 PM UTC 24 |
| Finished | Sep 01 06:57:45 PM UTC 24 |
| Peak memory | 250856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388333641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.3388333641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.3428338327 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2494072359 ps |
| CPU time | 13.8 seconds |
| Started | Sep 01 06:57:22 PM UTC 24 |
| Finished | Sep 01 06:57:37 PM UTC 24 |
| Peak memory | 253348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428338327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.3428338327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.187379444 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 3808319343 ps |
| CPU time | 32.63 seconds |
| Started | Sep 01 06:57:22 PM UTC 24 |
| Finished | Sep 01 06:57:56 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187379444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.187379444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.239972537 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 757093027 ps |
| CPU time | 8.27 seconds |
| Started | Sep 01 06:57:22 PM UTC 24 |
| Finished | Sep 01 06:57:31 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239972537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.239972537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.1767926609 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 14102186182 ps |
| CPU time | 38.84 seconds |
| Started | Sep 01 06:57:24 PM UTC 24 |
| Finished | Sep 01 06:58:04 PM UTC 24 |
| Peak memory | 253404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767926609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.1767926609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.1777456256 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 904439647 ps |
| CPU time | 11.54 seconds |
| Started | Sep 01 06:57:24 PM UTC 24 |
| Finished | Sep 01 06:57:37 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777456256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.1777456256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.3192780692 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 188444444 ps |
| CPU time | 7.07 seconds |
| Started | Sep 01 06:57:22 PM UTC 24 |
| Finished | Sep 01 06:57:30 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192780692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3192780692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.408961301 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2525432706 ps |
| CPU time | 24.54 seconds |
| Started | Sep 01 06:57:22 PM UTC 24 |
| Finished | Sep 01 06:57:48 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408961301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.408961301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.3834132788 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 939792064 ps |
| CPU time | 11.11 seconds |
| Started | Sep 01 06:57:28 PM UTC 24 |
| Finished | Sep 01 06:57:40 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834132788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.3834132788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.477950563 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1382706538 ps |
| CPU time | 18.5 seconds |
| Started | Sep 01 06:57:18 PM UTC 24 |
| Finished | Sep 01 06:57:38 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477950563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.477950563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.869856906 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 24557589246 ps |
| CPU time | 232.69 seconds |
| Started | Sep 01 06:57:29 PM UTC 24 |
| Finished | Sep 01 07:01:26 PM UTC 24 |
| Peak memory | 269780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869856906 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.869856906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.2383857934 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 51691138476 ps |
| CPU time | 186.97 seconds |
| Started | Sep 01 06:57:28 PM UTC 24 |
| Finished | Sep 01 07:00:38 PM UTC 24 |
| Peak memory | 274032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2383857934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.otp_ctrl_stress_all_with_rand_reset.2383857934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.3294163378 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 22055565988 ps |
| CPU time | 43.79 seconds |
| Started | Sep 01 06:57:28 PM UTC 24 |
| Finished | Sep 01 06:58:13 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294163378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.3294163378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.1418036412 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 98975070 ps |
| CPU time | 2.52 seconds |
| Started | Sep 01 06:57:49 PM UTC 24 |
| Finished | Sep 01 06:57:52 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418036412 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.1418036412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.1759368618 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 644608114 ps |
| CPU time | 15.48 seconds |
| Started | Sep 01 06:57:48 PM UTC 24 |
| Finished | Sep 01 06:58:05 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759368618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1759368618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.939662765 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 103970870 ps |
| CPU time | 4.43 seconds |
| Started | Sep 01 06:57:48 PM UTC 24 |
| Finished | Sep 01 06:57:54 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939662765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.939662765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.2705952431 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 206393816 ps |
| CPU time | 4.84 seconds |
| Started | Sep 01 06:57:48 PM UTC 24 |
| Finished | Sep 01 06:57:54 PM UTC 24 |
| Peak memory | 253572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705952431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.2705952431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.1181365514 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 23158127128 ps |
| CPU time | 53.81 seconds |
| Started | Sep 01 06:57:48 PM UTC 24 |
| Finished | Sep 01 06:58:44 PM UTC 24 |
| Peak memory | 267748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181365514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.1181365514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.4007334805 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 3329390640 ps |
| CPU time | 40.86 seconds |
| Started | Sep 01 06:57:48 PM UTC 24 |
| Finished | Sep 01 06:58:31 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007334805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.4007334805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.573412140 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 701678599 ps |
| CPU time | 23.04 seconds |
| Started | Sep 01 06:57:48 PM UTC 24 |
| Finished | Sep 01 06:58:12 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573412140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.573412140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.4017821839 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 462909907 ps |
| CPU time | 10.68 seconds |
| Started | Sep 01 06:57:48 PM UTC 24 |
| Finished | Sep 01 06:58:00 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017821839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.4017821839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.1325283485 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 5456067416 ps |
| CPU time | 15.27 seconds |
| Started | Sep 01 06:57:48 PM UTC 24 |
| Finished | Sep 01 06:58:04 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325283485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1325283485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.263857127 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 64179064638 ps |
| CPU time | 195.41 seconds |
| Started | Sep 01 06:57:49 PM UTC 24 |
| Finished | Sep 01 07:01:07 PM UTC 24 |
| Peak memory | 257724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263857127 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.263857127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.3371984784 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 4434368737 ps |
| CPU time | 29.42 seconds |
| Started | Sep 01 06:57:48 PM UTC 24 |
| Finished | Sep 01 06:58:19 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371984784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.3371984784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.1466451376 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 65240653 ps |
| CPU time | 2.95 seconds |
| Started | Sep 01 06:58:08 PM UTC 24 |
| Finished | Sep 01 06:58:12 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466451376 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.1466451376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.2035931126 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2051141623 ps |
| CPU time | 26.58 seconds |
| Started | Sep 01 06:57:57 PM UTC 24 |
| Finished | Sep 01 06:58:25 PM UTC 24 |
| Peak memory | 253668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035931126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.2035931126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.3433617923 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 397297442 ps |
| CPU time | 22.49 seconds |
| Started | Sep 01 06:57:57 PM UTC 24 |
| Finished | Sep 01 06:58:21 PM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433617923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.3433617923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.2248762665 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 3037020684 ps |
| CPU time | 38.06 seconds |
| Started | Sep 01 06:57:57 PM UTC 24 |
| Finished | Sep 01 06:58:36 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248762665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.2248762665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.3027303736 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 189697340 ps |
| CPU time | 7.4 seconds |
| Started | Sep 01 06:57:49 PM UTC 24 |
| Finished | Sep 01 06:57:57 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027303736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.3027303736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.4210752803 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 6244573294 ps |
| CPU time | 40.18 seconds |
| Started | Sep 01 06:57:57 PM UTC 24 |
| Finished | Sep 01 06:58:39 PM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210752803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.4210752803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.1476538565 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 791677475 ps |
| CPU time | 30.98 seconds |
| Started | Sep 01 06:57:57 PM UTC 24 |
| Finished | Sep 01 06:58:29 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476538565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1476538565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.2887043610 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1757020063 ps |
| CPU time | 8.25 seconds |
| Started | Sep 01 06:57:57 PM UTC 24 |
| Finished | Sep 01 06:58:06 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887043610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.2887043610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.876733134 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 12187665255 ps |
| CPU time | 52.59 seconds |
| Started | Sep 01 06:57:57 PM UTC 24 |
| Finished | Sep 01 06:58:51 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876733134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.876733134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.3710852179 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 5289539414 ps |
| CPU time | 22.54 seconds |
| Started | Sep 01 06:57:57 PM UTC 24 |
| Finished | Sep 01 06:58:21 PM UTC 24 |
| Peak memory | 257492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710852179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.3710852179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.1404359277 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 138131631 ps |
| CPU time | 5.55 seconds |
| Started | Sep 01 06:57:49 PM UTC 24 |
| Finished | Sep 01 06:57:55 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404359277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1404359277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.1038842922 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 119772156172 ps |
| CPU time | 213.65 seconds |
| Started | Sep 01 06:58:08 PM UTC 24 |
| Finished | Sep 01 07:01:45 PM UTC 24 |
| Peak memory | 286172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038842922 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.1038842922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.704894742 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 15303133467 ps |
| CPU time | 59.2 seconds |
| Started | Sep 01 06:57:57 PM UTC 24 |
| Finished | Sep 01 06:58:58 PM UTC 24 |
| Peak memory | 257532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704894742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.704894742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.171006537 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 88294264 ps |
| CPU time | 2.29 seconds |
| Started | Sep 01 06:58:16 PM UTC 24 |
| Finished | Sep 01 06:58:19 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171006537 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.171006537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.82928949 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 2562992362 ps |
| CPU time | 30.26 seconds |
| Started | Sep 01 06:58:08 PM UTC 24 |
| Finished | Sep 01 06:58:40 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82928949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.82928949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.3452542410 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1727237151 ps |
| CPU time | 17.97 seconds |
| Started | Sep 01 06:58:08 PM UTC 24 |
| Finished | Sep 01 06:58:28 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452542410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.3452542410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.2798395430 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1781101980 ps |
| CPU time | 32.66 seconds |
| Started | Sep 01 06:58:08 PM UTC 24 |
| Finished | Sep 01 06:58:42 PM UTC 24 |
| Peak memory | 255644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798395430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.2798395430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.1653735500 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 155980224 ps |
| CPU time | 6.91 seconds |
| Started | Sep 01 06:58:08 PM UTC 24 |
| Finished | Sep 01 06:58:16 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653735500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1653735500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.3006580702 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2307216103 ps |
| CPU time | 12.78 seconds |
| Started | Sep 01 06:58:08 PM UTC 24 |
| Finished | Sep 01 06:58:22 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006580702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3006580702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.2940054410 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 466914643 ps |
| CPU time | 8.43 seconds |
| Started | Sep 01 06:58:08 PM UTC 24 |
| Finished | Sep 01 06:58:18 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940054410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.2940054410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.611214612 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 461625813 ps |
| CPU time | 9.74 seconds |
| Started | Sep 01 06:58:08 PM UTC 24 |
| Finished | Sep 01 06:58:19 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611214612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.611214612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.3766355744 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 6589071115 ps |
| CPU time | 25.44 seconds |
| Started | Sep 01 06:58:08 PM UTC 24 |
| Finished | Sep 01 06:58:35 PM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766355744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3766355744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.1767262400 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 12645695051 ps |
| CPU time | 98.18 seconds |
| Started | Sep 01 06:58:16 PM UTC 24 |
| Finished | Sep 01 06:59:56 PM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767262400 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.1767262400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.914733384 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 4796064633 ps |
| CPU time | 32.42 seconds |
| Started | Sep 01 06:58:10 PM UTC 24 |
| Finished | Sep 01 06:58:44 PM UTC 24 |
| Peak memory | 253684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914733384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.914733384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.3788540238 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 154757282 ps |
| CPU time | 2.88 seconds |
| Started | Sep 01 06:58:26 PM UTC 24 |
| Finished | Sep 01 06:58:30 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788540238 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.3788540238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.3353271400 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 683745738 ps |
| CPU time | 11.37 seconds |
| Started | Sep 01 06:58:21 PM UTC 24 |
| Finished | Sep 01 06:58:33 PM UTC 24 |
| Peak memory | 251580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353271400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.3353271400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.2264297603 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 209269974 ps |
| CPU time | 13.89 seconds |
| Started | Sep 01 06:58:20 PM UTC 24 |
| Finished | Sep 01 06:58:36 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264297603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.2264297603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.2586849035 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 12490141782 ps |
| CPU time | 57.39 seconds |
| Started | Sep 01 06:58:19 PM UTC 24 |
| Finished | Sep 01 06:59:18 PM UTC 24 |
| Peak memory | 253496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586849035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.2586849035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.3261185343 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 204382797 ps |
| CPU time | 5.31 seconds |
| Started | Sep 01 06:58:16 PM UTC 24 |
| Finished | Sep 01 06:58:22 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261185343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3261185343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.2982589552 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 2578505189 ps |
| CPU time | 37.19 seconds |
| Started | Sep 01 06:58:21 PM UTC 24 |
| Finished | Sep 01 06:58:59 PM UTC 24 |
| Peak memory | 257884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982589552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.2982589552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.2386158777 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 4147463045 ps |
| CPU time | 40.47 seconds |
| Started | Sep 01 06:58:24 PM UTC 24 |
| Finished | Sep 01 06:59:06 PM UTC 24 |
| Peak memory | 253688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386158777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.2386158777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.4252640087 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 347110996 ps |
| CPU time | 17.11 seconds |
| Started | Sep 01 06:58:17 PM UTC 24 |
| Finished | Sep 01 06:58:36 PM UTC 24 |
| Peak memory | 257552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252640087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.4252640087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.4073286578 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1277577413 ps |
| CPU time | 29.24 seconds |
| Started | Sep 01 06:58:16 PM UTC 24 |
| Finished | Sep 01 06:58:47 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073286578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.4073286578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.2629674151 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 2897404604 ps |
| CPU time | 9.28 seconds |
| Started | Sep 01 06:58:24 PM UTC 24 |
| Finished | Sep 01 06:58:35 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629674151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.2629674151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.303072294 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 537345751 ps |
| CPU time | 7.49 seconds |
| Started | Sep 01 06:58:16 PM UTC 24 |
| Finished | Sep 01 06:58:25 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303072294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.303072294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.2243427274 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 139919788308 ps |
| CPU time | 371.98 seconds |
| Started | Sep 01 06:58:24 PM UTC 24 |
| Finished | Sep 01 07:04:42 PM UTC 24 |
| Peak memory | 267712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243427274 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.2243427274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.219893479 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2961834783 ps |
| CPU time | 143.18 seconds |
| Started | Sep 01 06:58:24 PM UTC 24 |
| Finished | Sep 01 07:00:50 PM UTC 24 |
| Peak memory | 257600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=219893479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.219893479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.1629200444 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1997834481 ps |
| CPU time | 19.63 seconds |
| Started | Sep 01 06:58:24 PM UTC 24 |
| Finished | Sep 01 06:58:45 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629200444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.1629200444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.3437767852 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 830601988 ps |
| CPU time | 3.36 seconds |
| Started | Sep 01 06:58:45 PM UTC 24 |
| Finished | Sep 01 06:58:50 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437767852 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.3437767852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.595508508 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 745094758 ps |
| CPU time | 26.5 seconds |
| Started | Sep 01 06:58:36 PM UTC 24 |
| Finished | Sep 01 06:59:04 PM UTC 24 |
| Peak memory | 253688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595508508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.595508508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.1799387021 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 731690004 ps |
| CPU time | 22.73 seconds |
| Started | Sep 01 06:58:36 PM UTC 24 |
| Finished | Sep 01 06:59:00 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799387021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.1799387021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.1276501423 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 666050952 ps |
| CPU time | 19.32 seconds |
| Started | Sep 01 06:58:31 PM UTC 24 |
| Finished | Sep 01 06:58:52 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276501423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.1276501423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.1700670834 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 119139656 ps |
| CPU time | 6.55 seconds |
| Started | Sep 01 06:58:29 PM UTC 24 |
| Finished | Sep 01 06:58:37 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700670834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.1700670834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.473104342 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 1098451083 ps |
| CPU time | 40.98 seconds |
| Started | Sep 01 06:58:36 PM UTC 24 |
| Finished | Sep 01 06:59:19 PM UTC 24 |
| Peak memory | 255388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473104342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.473104342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.2938324906 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 587185857 ps |
| CPU time | 27.42 seconds |
| Started | Sep 01 06:58:36 PM UTC 24 |
| Finished | Sep 01 06:59:05 PM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938324906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.2938324906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.4271339691 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 423762415 ps |
| CPU time | 11.94 seconds |
| Started | Sep 01 06:58:31 PM UTC 24 |
| Finished | Sep 01 06:58:44 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271339691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.4271339691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.4040142832 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2718170844 ps |
| CPU time | 17.65 seconds |
| Started | Sep 01 06:58:29 PM UTC 24 |
| Finished | Sep 01 06:58:48 PM UTC 24 |
| Peak memory | 257688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040142832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.4040142832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.1637168790 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 246835808 ps |
| CPU time | 6.92 seconds |
| Started | Sep 01 06:58:36 PM UTC 24 |
| Finished | Sep 01 06:58:45 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637168790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1637168790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.1243698411 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 1548329376 ps |
| CPU time | 11.6 seconds |
| Started | Sep 01 06:58:26 PM UTC 24 |
| Finished | Sep 01 06:58:39 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243698411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1243698411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.3525446367 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 17057250252 ps |
| CPU time | 169.95 seconds |
| Started | Sep 01 06:58:45 PM UTC 24 |
| Finished | Sep 01 07:01:39 PM UTC 24 |
| Peak memory | 257472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525446367 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.3525446367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.3535730957 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 76953716494 ps |
| CPU time | 194.9 seconds |
| Started | Sep 01 06:58:45 PM UTC 24 |
| Finished | Sep 01 07:02:04 PM UTC 24 |
| Peak memory | 284332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3535730957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.otp_ctrl_stress_all_with_rand_reset.3535730957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.1894229206 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 889017225 ps |
| CPU time | 24.61 seconds |
| Started | Sep 01 06:58:45 PM UTC 24 |
| Finished | Sep 01 06:59:11 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894229206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.1894229206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.3579955092 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 54433650 ps |
| CPU time | 2.72 seconds |
| Started | Sep 01 06:58:52 PM UTC 24 |
| Finished | Sep 01 06:58:56 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579955092 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.3579955092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.882505588 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 4838862257 ps |
| CPU time | 29.03 seconds |
| Started | Sep 01 06:58:46 PM UTC 24 |
| Finished | Sep 01 06:59:16 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882505588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.882505588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.1471928410 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 9152163812 ps |
| CPU time | 37.18 seconds |
| Started | Sep 01 06:58:46 PM UTC 24 |
| Finished | Sep 01 06:59:24 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471928410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1471928410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.3177379193 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 634087808 ps |
| CPU time | 27.06 seconds |
| Started | Sep 01 06:58:46 PM UTC 24 |
| Finished | Sep 01 06:59:14 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177379193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.3177379193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.805008560 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1502764151 ps |
| CPU time | 9.87 seconds |
| Started | Sep 01 06:58:46 PM UTC 24 |
| Finished | Sep 01 06:58:57 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805008560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.805008560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.1933030560 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 4616153002 ps |
| CPU time | 26.13 seconds |
| Started | Sep 01 06:58:46 PM UTC 24 |
| Finished | Sep 01 06:59:13 PM UTC 24 |
| Peak memory | 255476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933030560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.1933030560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.3930516130 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 550924015 ps |
| CPU time | 18.04 seconds |
| Started | Sep 01 06:58:46 PM UTC 24 |
| Finished | Sep 01 06:59:05 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930516130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.3930516130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.1327978097 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 353868095 ps |
| CPU time | 6.8 seconds |
| Started | Sep 01 06:58:46 PM UTC 24 |
| Finished | Sep 01 06:58:53 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327978097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.1327978097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.727938897 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1771708029 ps |
| CPU time | 18.19 seconds |
| Started | Sep 01 06:58:46 PM UTC 24 |
| Finished | Sep 01 06:59:05 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727938897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.727938897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.4115788545 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 162057886 ps |
| CPU time | 8.91 seconds |
| Started | Sep 01 06:58:52 PM UTC 24 |
| Finished | Sep 01 06:59:02 PM UTC 24 |
| Peak memory | 250940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115788545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.4115788545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.2754124999 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1566491850 ps |
| CPU time | 5.02 seconds |
| Started | Sep 01 06:58:45 PM UTC 24 |
| Finished | Sep 01 06:58:52 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754124999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.2754124999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.3924263993 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 9386265275 ps |
| CPU time | 86.25 seconds |
| Started | Sep 01 06:58:52 PM UTC 24 |
| Finished | Sep 01 07:00:21 PM UTC 24 |
| Peak memory | 257884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924263993 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.3924263993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.115839410 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 2442514359 ps |
| CPU time | 76.31 seconds |
| Started | Sep 01 06:58:52 PM UTC 24 |
| Finished | Sep 01 07:00:10 PM UTC 24 |
| Peak memory | 257316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=115839410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.115839410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.793553183 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 2936025798 ps |
| CPU time | 33.99 seconds |
| Started | Sep 01 06:58:52 PM UTC 24 |
| Finished | Sep 01 06:59:28 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793553183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.793553183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.1039159854 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 208051185 ps |
| CPU time | 3.01 seconds |
| Started | Sep 01 06:50:30 PM UTC 24 |
| Finished | Sep 01 06:50:34 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039159854 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.1039159854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.677063616 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 788414075 ps |
| CPU time | 16.1 seconds |
| Started | Sep 01 06:50:16 PM UTC 24 |
| Finished | Sep 01 06:50:33 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677063616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.677063616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.1249035521 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1590132379 ps |
| CPU time | 28.49 seconds |
| Started | Sep 01 06:50:22 PM UTC 24 |
| Finished | Sep 01 06:50:52 PM UTC 24 |
| Peak memory | 257440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249035521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1249035521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.2485973952 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1761090829 ps |
| CPU time | 24.88 seconds |
| Started | Sep 01 06:50:22 PM UTC 24 |
| Finished | Sep 01 06:50:48 PM UTC 24 |
| Peak memory | 251580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485973952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2485973952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.2807684503 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 782153637 ps |
| CPU time | 10.21 seconds |
| Started | Sep 01 06:50:20 PM UTC 24 |
| Finished | Sep 01 06:50:32 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807684503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.2807684503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.3896711180 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 215051364 ps |
| CPU time | 4.44 seconds |
| Started | Sep 01 06:50:16 PM UTC 24 |
| Finished | Sep 01 06:50:21 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896711180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.3896711180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.2676861700 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 243239117 ps |
| CPU time | 5.95 seconds |
| Started | Sep 01 06:50:22 PM UTC 24 |
| Finished | Sep 01 06:50:29 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676861700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.2676861700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.2839016222 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 225512163 ps |
| CPU time | 13.96 seconds |
| Started | Sep 01 06:50:23 PM UTC 24 |
| Finished | Sep 01 06:50:39 PM UTC 24 |
| Peak memory | 257408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839016222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.2839016222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.2937559231 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 3204903883 ps |
| CPU time | 22.25 seconds |
| Started | Sep 01 06:50:17 PM UTC 24 |
| Finished | Sep 01 06:50:41 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937559231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2937559231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.1604132104 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 155056544977 ps |
| CPU time | 204.2 seconds |
| Started | Sep 01 06:50:30 PM UTC 24 |
| Finished | Sep 01 06:53:58 PM UTC 24 |
| Peak memory | 289916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604132104 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1604132104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.1194304616 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1366875509 ps |
| CPU time | 12.84 seconds |
| Started | Sep 01 06:50:13 PM UTC 24 |
| Finished | Sep 01 06:50:27 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194304616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1194304616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.3167706037 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1134383205 ps |
| CPU time | 25.47 seconds |
| Started | Sep 01 06:50:25 PM UTC 24 |
| Finished | Sep 01 06:50:52 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167706037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.3167706037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.3928204488 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 41502828 ps |
| CPU time | 2.44 seconds |
| Started | Sep 01 06:59:03 PM UTC 24 |
| Finished | Sep 01 06:59:06 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928204488 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.3928204488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.3011940630 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 675125571 ps |
| CPU time | 17.07 seconds |
| Started | Sep 01 06:58:55 PM UTC 24 |
| Finished | Sep 01 06:59:13 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011940630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.3011940630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.21308381 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 681581015 ps |
| CPU time | 11.4 seconds |
| Started | Sep 01 06:58:55 PM UTC 24 |
| Finished | Sep 01 06:59:07 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21308381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.21308381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.645160362 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 3897232460 ps |
| CPU time | 14.57 seconds |
| Started | Sep 01 06:58:53 PM UTC 24 |
| Finished | Sep 01 06:59:08 PM UTC 24 |
| Peak memory | 253496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645160362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.645160362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.2513560856 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 2454846367 ps |
| CPU time | 6.81 seconds |
| Started | Sep 01 06:58:52 PM UTC 24 |
| Finished | Sep 01 06:59:00 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513560856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.2513560856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.2342271910 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1916258526 ps |
| CPU time | 23.02 seconds |
| Started | Sep 01 06:58:55 PM UTC 24 |
| Finished | Sep 01 06:59:19 PM UTC 24 |
| Peak memory | 253376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342271910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.2342271910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.3247085857 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 783648203 ps |
| CPU time | 22.53 seconds |
| Started | Sep 01 06:58:57 PM UTC 24 |
| Finished | Sep 01 06:59:21 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247085857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.3247085857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.2314779719 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 1740089442 ps |
| CPU time | 16.67 seconds |
| Started | Sep 01 06:58:53 PM UTC 24 |
| Finished | Sep 01 06:59:11 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314779719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.2314779719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.182520111 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2470820570 ps |
| CPU time | 23.66 seconds |
| Started | Sep 01 06:58:52 PM UTC 24 |
| Finished | Sep 01 06:59:18 PM UTC 24 |
| Peak memory | 257492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182520111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.182520111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.1621861747 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 278769187 ps |
| CPU time | 4.02 seconds |
| Started | Sep 01 06:58:58 PM UTC 24 |
| Finished | Sep 01 06:59:03 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621861747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.1621861747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.3472208083 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 3830024957 ps |
| CPU time | 14.89 seconds |
| Started | Sep 01 06:58:52 PM UTC 24 |
| Finished | Sep 01 06:59:09 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472208083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3472208083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.1223397124 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 52157768355 ps |
| CPU time | 160.54 seconds |
| Started | Sep 01 06:59:03 PM UTC 24 |
| Finished | Sep 01 07:01:46 PM UTC 24 |
| Peak memory | 267804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223397124 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.1223397124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.1406333541 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3916632351 ps |
| CPU time | 26.59 seconds |
| Started | Sep 01 06:58:59 PM UTC 24 |
| Finished | Sep 01 06:59:27 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406333541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.1406333541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.1747861995 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 92215533 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 06:59:20 PM UTC 24 |
| Finished | Sep 01 06:59:24 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747861995 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1747861995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.635290042 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10289092354 ps |
| CPU time | 17.39 seconds |
| Started | Sep 01 06:59:08 PM UTC 24 |
| Finished | Sep 01 06:59:26 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635290042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.635290042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.901469107 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1247384079 ps |
| CPU time | 37.19 seconds |
| Started | Sep 01 06:59:08 PM UTC 24 |
| Finished | Sep 01 06:59:46 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901469107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.901469107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.718758629 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1112810248 ps |
| CPU time | 20.13 seconds |
| Started | Sep 01 06:59:07 PM UTC 24 |
| Finished | Sep 01 06:59:29 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718758629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.718758629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.1990161443 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 222628001 ps |
| CPU time | 6.81 seconds |
| Started | Sep 01 06:59:04 PM UTC 24 |
| Finished | Sep 01 06:59:12 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990161443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.1990161443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.2148966884 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 1011388513 ps |
| CPU time | 35.35 seconds |
| Started | Sep 01 06:59:20 PM UTC 24 |
| Finished | Sep 01 06:59:57 PM UTC 24 |
| Peak memory | 257584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148966884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2148966884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.2052449150 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 3667392094 ps |
| CPU time | 8.98 seconds |
| Started | Sep 01 06:59:20 PM UTC 24 |
| Finished | Sep 01 06:59:30 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052449150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.2052449150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.2540749838 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 148520277 ps |
| CPU time | 5.68 seconds |
| Started | Sep 01 06:59:07 PM UTC 24 |
| Finished | Sep 01 06:59:14 PM UTC 24 |
| Peak memory | 251036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540749838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.2540749838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.1518508981 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 617191670 ps |
| CPU time | 20.75 seconds |
| Started | Sep 01 06:59:07 PM UTC 24 |
| Finished | Sep 01 06:59:29 PM UTC 24 |
| Peak memory | 257244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518508981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.1518508981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.1492146101 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 280505099 ps |
| CPU time | 9.64 seconds |
| Started | Sep 01 06:59:20 PM UTC 24 |
| Finished | Sep 01 06:59:31 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492146101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.1492146101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.511645803 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 1384709612 ps |
| CPU time | 14.65 seconds |
| Started | Sep 01 06:59:04 PM UTC 24 |
| Finished | Sep 01 06:59:20 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511645803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.511645803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.2638354759 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 7354943137 ps |
| CPU time | 105.03 seconds |
| Started | Sep 01 06:59:20 PM UTC 24 |
| Finished | Sep 01 07:01:08 PM UTC 24 |
| Peak memory | 257564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638354759 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.2638354759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.3270375151 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 809801765 ps |
| CPU time | 31.72 seconds |
| Started | Sep 01 06:59:20 PM UTC 24 |
| Finished | Sep 01 06:59:54 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270375151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.3270375151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.4228879135 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 197830284 ps |
| CPU time | 4.73 seconds |
| Started | Sep 01 06:59:25 PM UTC 24 |
| Finished | Sep 01 06:59:31 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228879135 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.4228879135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.3209600445 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1859105437 ps |
| CPU time | 31.71 seconds |
| Started | Sep 01 06:59:21 PM UTC 24 |
| Finished | Sep 01 06:59:54 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209600445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.3209600445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.856632084 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1882494870 ps |
| CPU time | 37.22 seconds |
| Started | Sep 01 06:59:21 PM UTC 24 |
| Finished | Sep 01 07:00:00 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856632084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.856632084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.1456479802 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 8600986716 ps |
| CPU time | 26.14 seconds |
| Started | Sep 01 06:59:21 PM UTC 24 |
| Finished | Sep 01 06:59:48 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456479802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.1456479802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.2038921439 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 132034482 ps |
| CPU time | 4.75 seconds |
| Started | Sep 01 06:59:21 PM UTC 24 |
| Finished | Sep 01 06:59:26 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038921439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.2038921439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.2789070395 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1154764740 ps |
| CPU time | 25.71 seconds |
| Started | Sep 01 06:59:21 PM UTC 24 |
| Finished | Sep 01 06:59:48 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789070395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.2789070395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.2155314656 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 1780864353 ps |
| CPU time | 35.65 seconds |
| Started | Sep 01 06:59:21 PM UTC 24 |
| Finished | Sep 01 06:59:58 PM UTC 24 |
| Peak memory | 257592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155314656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.2155314656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.1162415100 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 1194344176 ps |
| CPU time | 27.28 seconds |
| Started | Sep 01 06:59:21 PM UTC 24 |
| Finished | Sep 01 06:59:49 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162415100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1162415100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.2548188699 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 415694595 ps |
| CPU time | 5.19 seconds |
| Started | Sep 01 06:59:21 PM UTC 24 |
| Finished | Sep 01 06:59:27 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548188699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.2548188699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.991310160 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 980901832 ps |
| CPU time | 7.61 seconds |
| Started | Sep 01 06:59:21 PM UTC 24 |
| Finished | Sep 01 06:59:30 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991310160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.991310160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.4232771439 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 2153190720 ps |
| CPU time | 6.52 seconds |
| Started | Sep 01 06:59:21 PM UTC 24 |
| Finished | Sep 01 06:59:28 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232771439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.4232771439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.2389034721 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 324465459 ps |
| CPU time | 6.32 seconds |
| Started | Sep 01 06:59:25 PM UTC 24 |
| Finished | Sep 01 06:59:33 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389034721 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.2389034721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.3263334588 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 16003472110 ps |
| CPU time | 117.9 seconds |
| Started | Sep 01 06:59:25 PM UTC 24 |
| Finished | Sep 01 07:01:26 PM UTC 24 |
| Peak memory | 257708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3263334588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.otp_ctrl_stress_all_with_rand_reset.3263334588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.1982686347 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 6313331573 ps |
| CPU time | 35.15 seconds |
| Started | Sep 01 06:59:21 PM UTC 24 |
| Finished | Sep 01 06:59:58 PM UTC 24 |
| Peak memory | 257780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982686347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.1982686347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.145136689 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 145174245 ps |
| CPU time | 3.33 seconds |
| Started | Sep 01 06:59:33 PM UTC 24 |
| Finished | Sep 01 06:59:37 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145136689 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.145136689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.473434449 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 1021536904 ps |
| CPU time | 16.91 seconds |
| Started | Sep 01 06:59:29 PM UTC 24 |
| Finished | Sep 01 06:59:47 PM UTC 24 |
| Peak memory | 257656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473434449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.473434449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.2730600607 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 3014849878 ps |
| CPU time | 47.49 seconds |
| Started | Sep 01 06:59:29 PM UTC 24 |
| Finished | Sep 01 07:00:18 PM UTC 24 |
| Peak memory | 261796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730600607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.2730600607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.4146440198 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1706462706 ps |
| CPU time | 20.23 seconds |
| Started | Sep 01 06:59:29 PM UTC 24 |
| Finished | Sep 01 06:59:50 PM UTC 24 |
| Peak memory | 257724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146440198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.4146440198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.2988491104 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1919784334 ps |
| CPU time | 7.43 seconds |
| Started | Sep 01 06:59:25 PM UTC 24 |
| Finished | Sep 01 06:59:34 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988491104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.2988491104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.313674412 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 310784603 ps |
| CPU time | 10.38 seconds |
| Started | Sep 01 06:59:29 PM UTC 24 |
| Finished | Sep 01 06:59:41 PM UTC 24 |
| Peak memory | 257440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313674412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.313674412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.133329934 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1409479931 ps |
| CPU time | 19.48 seconds |
| Started | Sep 01 06:59:32 PM UTC 24 |
| Finished | Sep 01 06:59:53 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133329934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.133329934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.3560633704 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 103246369 ps |
| CPU time | 4.51 seconds |
| Started | Sep 01 06:59:29 PM UTC 24 |
| Finished | Sep 01 06:59:34 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560633704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.3560633704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.1114459329 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 483323133 ps |
| CPU time | 11.86 seconds |
| Started | Sep 01 06:59:29 PM UTC 24 |
| Finished | Sep 01 06:59:42 PM UTC 24 |
| Peak memory | 257652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114459329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.1114459329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.3709779078 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 148042117 ps |
| CPU time | 7.14 seconds |
| Started | Sep 01 06:59:33 PM UTC 24 |
| Finished | Sep 01 06:59:41 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709779078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.3709779078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.229481267 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 497788911 ps |
| CPU time | 13.38 seconds |
| Started | Sep 01 06:59:25 PM UTC 24 |
| Finished | Sep 01 06:59:40 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229481267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.229481267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.1538046362 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 11185147564 ps |
| CPU time | 87.22 seconds |
| Started | Sep 01 06:59:33 PM UTC 24 |
| Finished | Sep 01 07:01:02 PM UTC 24 |
| Peak memory | 288304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538046362 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.1538046362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.1340125528 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 9628912348 ps |
| CPU time | 31.69 seconds |
| Started | Sep 01 06:59:33 PM UTC 24 |
| Finished | Sep 01 07:00:06 PM UTC 24 |
| Peak memory | 253264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340125528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.1340125528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.17188408 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 89240852 ps |
| CPU time | 2.67 seconds |
| Started | Sep 01 06:59:47 PM UTC 24 |
| Finished | Sep 01 06:59:51 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17188408 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.17188408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.1200946722 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 5596489372 ps |
| CPU time | 15.01 seconds |
| Started | Sep 01 06:59:42 PM UTC 24 |
| Finished | Sep 01 06:59:58 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200946722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.1200946722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.341929725 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 5866858706 ps |
| CPU time | 34.1 seconds |
| Started | Sep 01 06:59:42 PM UTC 24 |
| Finished | Sep 01 07:00:18 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341929725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.341929725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.3130185556 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2858206952 ps |
| CPU time | 17.25 seconds |
| Started | Sep 01 06:59:36 PM UTC 24 |
| Finished | Sep 01 06:59:54 PM UTC 24 |
| Peak memory | 253476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130185556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.3130185556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.3233743760 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 111001149 ps |
| CPU time | 5.02 seconds |
| Started | Sep 01 06:59:33 PM UTC 24 |
| Finished | Sep 01 06:59:39 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233743760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.3233743760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.2136483409 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 627262509 ps |
| CPU time | 17.65 seconds |
| Started | Sep 01 06:59:42 PM UTC 24 |
| Finished | Sep 01 07:00:01 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136483409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2136483409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.4173264571 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3993586596 ps |
| CPU time | 29.28 seconds |
| Started | Sep 01 06:59:42 PM UTC 24 |
| Finished | Sep 01 07:00:13 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173264571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.4173264571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.2403283917 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 7792996653 ps |
| CPU time | 28.31 seconds |
| Started | Sep 01 06:59:34 PM UTC 24 |
| Finished | Sep 01 07:00:04 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403283917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.2403283917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.3552769677 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 1850492585 ps |
| CPU time | 9.24 seconds |
| Started | Sep 01 06:59:42 PM UTC 24 |
| Finished | Sep 01 06:59:53 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552769677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3552769677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.2782032133 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 287863056 ps |
| CPU time | 8.15 seconds |
| Started | Sep 01 06:59:33 PM UTC 24 |
| Finished | Sep 01 06:59:42 PM UTC 24 |
| Peak memory | 257428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782032133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.2782032133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.2034559387 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 19452091636 ps |
| CPU time | 55.61 seconds |
| Started | Sep 01 06:59:44 PM UTC 24 |
| Finished | Sep 01 07:00:41 PM UTC 24 |
| Peak memory | 253376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034559387 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.2034559387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.1396268846 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 10839745016 ps |
| CPU time | 91.74 seconds |
| Started | Sep 01 06:59:44 PM UTC 24 |
| Finished | Sep 01 07:01:18 PM UTC 24 |
| Peak memory | 257816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1396268846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.otp_ctrl_stress_all_with_rand_reset.1396268846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.1141740491 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 979203467 ps |
| CPU time | 28.47 seconds |
| Started | Sep 01 06:59:42 PM UTC 24 |
| Finished | Sep 01 07:00:12 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141740491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.1141740491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.2229974440 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 47482880 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 06:59:58 PM UTC 24 |
| Finished | Sep 01 07:00:01 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229974440 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.2229974440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.3139370951 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 467371318 ps |
| CPU time | 8.46 seconds |
| Started | Sep 01 06:59:54 PM UTC 24 |
| Finished | Sep 01 07:00:04 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139370951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.3139370951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.2828255147 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 12437169932 ps |
| CPU time | 52.81 seconds |
| Started | Sep 01 06:59:52 PM UTC 24 |
| Finished | Sep 01 07:00:47 PM UTC 24 |
| Peak memory | 253240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828255147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.2828255147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.1300004012 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 8366801841 ps |
| CPU time | 17.8 seconds |
| Started | Sep 01 06:59:52 PM UTC 24 |
| Finished | Sep 01 07:00:11 PM UTC 24 |
| Peak memory | 253408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300004012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1300004012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.4112733801 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 94543905 ps |
| CPU time | 4.63 seconds |
| Started | Sep 01 06:59:50 PM UTC 24 |
| Finished | Sep 01 06:59:56 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112733801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.4112733801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.2423045306 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 663725480 ps |
| CPU time | 4.99 seconds |
| Started | Sep 01 06:59:54 PM UTC 24 |
| Finished | Sep 01 07:00:00 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423045306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.2423045306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.65916425 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 357351747 ps |
| CPU time | 17.75 seconds |
| Started | Sep 01 06:59:58 PM UTC 24 |
| Finished | Sep 01 07:00:17 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65916425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.65916425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.3547192540 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3456704343 ps |
| CPU time | 14.91 seconds |
| Started | Sep 01 06:59:52 PM UTC 24 |
| Finished | Sep 01 07:00:09 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547192540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3547192540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.914385248 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 1342340973 ps |
| CPU time | 23.18 seconds |
| Started | Sep 01 06:59:52 PM UTC 24 |
| Finished | Sep 01 07:00:17 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914385248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.914385248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.4183140011 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 265285553 ps |
| CPU time | 5.9 seconds |
| Started | Sep 01 06:59:58 PM UTC 24 |
| Finished | Sep 01 07:00:05 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183140011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.4183140011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.4164176891 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 4206845317 ps |
| CPU time | 11.07 seconds |
| Started | Sep 01 06:59:50 PM UTC 24 |
| Finished | Sep 01 07:00:02 PM UTC 24 |
| Peak memory | 253404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164176891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.4164176891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.3372694680 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 24424073086 ps |
| CPU time | 73.82 seconds |
| Started | Sep 01 06:59:58 PM UTC 24 |
| Finished | Sep 01 07:01:14 PM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372694680 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.3372694680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.3198595538 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 423989714 ps |
| CPU time | 6.41 seconds |
| Started | Sep 01 06:59:58 PM UTC 24 |
| Finished | Sep 01 07:00:06 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198595538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.3198595538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.3048758615 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 96563780 ps |
| CPU time | 2.68 seconds |
| Started | Sep 01 07:00:09 PM UTC 24 |
| Finished | Sep 01 07:00:13 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048758615 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.3048758615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.3115364805 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 33793927623 ps |
| CPU time | 58.91 seconds |
| Started | Sep 01 07:00:06 PM UTC 24 |
| Finished | Sep 01 07:01:07 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115364805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.3115364805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.1916568653 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 263390919 ps |
| CPU time | 19.98 seconds |
| Started | Sep 01 07:00:06 PM UTC 24 |
| Finished | Sep 01 07:00:28 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916568653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.1916568653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.448956352 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1654257355 ps |
| CPU time | 17.7 seconds |
| Started | Sep 01 07:00:06 PM UTC 24 |
| Finished | Sep 01 07:00:25 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448956352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.448956352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.4291128987 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 756221360 ps |
| CPU time | 7.06 seconds |
| Started | Sep 01 07:00:06 PM UTC 24 |
| Finished | Sep 01 07:00:14 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291128987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.4291128987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.4161842703 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 816561197 ps |
| CPU time | 24.97 seconds |
| Started | Sep 01 07:00:06 PM UTC 24 |
| Finished | Sep 01 07:00:33 PM UTC 24 |
| Peak memory | 257596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161842703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.4161842703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.3589144181 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 911242623 ps |
| CPU time | 10.39 seconds |
| Started | Sep 01 07:00:06 PM UTC 24 |
| Finished | Sep 01 07:00:18 PM UTC 24 |
| Peak memory | 253336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589144181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.3589144181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.3660547905 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 575914176 ps |
| CPU time | 5.11 seconds |
| Started | Sep 01 07:00:06 PM UTC 24 |
| Finished | Sep 01 07:00:12 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660547905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.3660547905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.3789372824 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 446552143 ps |
| CPU time | 13.5 seconds |
| Started | Sep 01 07:00:06 PM UTC 24 |
| Finished | Sep 01 07:00:21 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789372824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3789372824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.3281156507 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 306500989 ps |
| CPU time | 6.41 seconds |
| Started | Sep 01 07:00:06 PM UTC 24 |
| Finished | Sep 01 07:00:14 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281156507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.3281156507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.4220052329 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 423799456 ps |
| CPU time | 12.38 seconds |
| Started | Sep 01 07:00:06 PM UTC 24 |
| Finished | Sep 01 07:00:20 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220052329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.4220052329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.2978363804 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 19120699044 ps |
| CPU time | 96.91 seconds |
| Started | Sep 01 07:00:09 PM UTC 24 |
| Finished | Sep 01 07:01:48 PM UTC 24 |
| Peak memory | 267852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978363804 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.2978363804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.1446405865 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 338817040 ps |
| CPU time | 6.45 seconds |
| Started | Sep 01 07:00:06 PM UTC 24 |
| Finished | Sep 01 07:00:14 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446405865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.1446405865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.328992294 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 681571893 ps |
| CPU time | 3.96 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:00:25 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328992294 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.328992294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.757780172 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1841448493 ps |
| CPU time | 30.93 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:00:52 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757780172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.757780172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.2394592541 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1084727192 ps |
| CPU time | 19.67 seconds |
| Started | Sep 01 07:00:12 PM UTC 24 |
| Finished | Sep 01 07:00:33 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394592541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.2394592541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.2129213506 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 21443209764 ps |
| CPU time | 198.96 seconds |
| Started | Sep 01 07:00:12 PM UTC 24 |
| Finished | Sep 01 07:03:35 PM UTC 24 |
| Peak memory | 253368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129213506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.2129213506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.3826990221 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 2038216785 ps |
| CPU time | 5.3 seconds |
| Started | Sep 01 07:00:09 PM UTC 24 |
| Finished | Sep 01 07:00:16 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826990221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.3826990221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.2449320545 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 1549509015 ps |
| CPU time | 22.76 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:00:44 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449320545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.2449320545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.1087598338 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 682428411 ps |
| CPU time | 9.94 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:00:31 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087598338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.1087598338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.3434546918 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 128977608 ps |
| CPU time | 5.58 seconds |
| Started | Sep 01 07:00:11 PM UTC 24 |
| Finished | Sep 01 07:00:17 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434546918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.3434546918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.2225445591 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 2492148793 ps |
| CPU time | 18.95 seconds |
| Started | Sep 01 07:00:10 PM UTC 24 |
| Finished | Sep 01 07:00:30 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225445591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.2225445591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.3792665522 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 976136422 ps |
| CPU time | 8.65 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:00:30 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792665522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.3792665522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.1329505265 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 417125972 ps |
| CPU time | 8.93 seconds |
| Started | Sep 01 07:00:09 PM UTC 24 |
| Finished | Sep 01 07:00:19 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329505265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1329505265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.3317486958 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 19937112518 ps |
| CPU time | 98.75 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:02:01 PM UTC 24 |
| Peak memory | 253492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317486958 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.3317486958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.1649165383 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1496609527 ps |
| CPU time | 37.59 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:00:59 PM UTC 24 |
| Peak memory | 257532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1649165383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.otp_ctrl_stress_all_with_rand_reset.1649165383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.3443771035 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 156360048 ps |
| CPU time | 4.09 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:00:25 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443771035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.3443771035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.728191965 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 205832957 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 07:00:30 PM UTC 24 |
| Finished | Sep 01 07:00:32 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728191965 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.728191965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.1520428225 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 844169250 ps |
| CPU time | 12.38 seconds |
| Started | Sep 01 07:00:24 PM UTC 24 |
| Finished | Sep 01 07:00:38 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520428225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.1520428225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.3460249339 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 5259524000 ps |
| CPU time | 32.93 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:00:55 PM UTC 24 |
| Peak memory | 251556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460249339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.3460249339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.2586468099 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 768464549 ps |
| CPU time | 19.85 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:00:42 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586468099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.2586468099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.381303655 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 454727468 ps |
| CPU time | 5.54 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:00:27 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381303655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.381303655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.3873905982 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 948743126 ps |
| CPU time | 22.44 seconds |
| Started | Sep 01 07:00:24 PM UTC 24 |
| Finished | Sep 01 07:00:48 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873905982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.3873905982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.1185501716 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 1598685082 ps |
| CPU time | 25.99 seconds |
| Started | Sep 01 07:00:24 PM UTC 24 |
| Finished | Sep 01 07:00:52 PM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185501716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.1185501716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.1559648373 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 195393635 ps |
| CPU time | 6.62 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:00:28 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559648373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.1559648373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.2935439554 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 922726921 ps |
| CPU time | 29.06 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:00:51 PM UTC 24 |
| Peak memory | 257364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935439554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.2935439554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.2504246888 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 682199248 ps |
| CPU time | 11.61 seconds |
| Started | Sep 01 07:00:25 PM UTC 24 |
| Finished | Sep 01 07:00:37 PM UTC 24 |
| Peak memory | 250544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504246888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.2504246888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.1702309151 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 405353330 ps |
| CPU time | 7.64 seconds |
| Started | Sep 01 07:00:20 PM UTC 24 |
| Finished | Sep 01 07:00:29 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702309151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.1702309151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.3033586649 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 5943305172 ps |
| CPU time | 56.09 seconds |
| Started | Sep 01 07:00:25 PM UTC 24 |
| Finished | Sep 01 07:01:22 PM UTC 24 |
| Peak memory | 268056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033586649 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.3033586649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3222502696 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 2219774735 ps |
| CPU time | 72.35 seconds |
| Started | Sep 01 07:00:25 PM UTC 24 |
| Finished | Sep 01 07:01:39 PM UTC 24 |
| Peak memory | 257708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3222502696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.otp_ctrl_stress_all_with_rand_reset.3222502696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.139305601 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 1741647361 ps |
| CPU time | 11.11 seconds |
| Started | Sep 01 07:00:25 PM UTC 24 |
| Finished | Sep 01 07:00:37 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139305601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.139305601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.1060767774 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 220314358 ps |
| CPU time | 3.1 seconds |
| Started | Sep 01 07:00:36 PM UTC 24 |
| Finished | Sep 01 07:00:40 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060767774 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.1060767774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.683026522 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 592054001 ps |
| CPU time | 17.43 seconds |
| Started | Sep 01 07:00:30 PM UTC 24 |
| Finished | Sep 01 07:00:49 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683026522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.683026522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.1930168758 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 9871123905 ps |
| CPU time | 29.54 seconds |
| Started | Sep 01 07:00:30 PM UTC 24 |
| Finished | Sep 01 07:01:01 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930168758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.1930168758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.3105296599 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 122811024 ps |
| CPU time | 6.42 seconds |
| Started | Sep 01 07:00:30 PM UTC 24 |
| Finished | Sep 01 07:00:37 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105296599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.3105296599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.3257072927 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 15501891883 ps |
| CPU time | 30.36 seconds |
| Started | Sep 01 07:00:34 PM UTC 24 |
| Finished | Sep 01 07:01:06 PM UTC 24 |
| Peak memory | 255796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257072927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.3257072927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.1671526006 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 1610553720 ps |
| CPU time | 12.32 seconds |
| Started | Sep 01 07:00:34 PM UTC 24 |
| Finished | Sep 01 07:00:47 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671526006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.1671526006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.62976205 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1383063261 ps |
| CPU time | 20.64 seconds |
| Started | Sep 01 07:00:30 PM UTC 24 |
| Finished | Sep 01 07:00:52 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62976205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.62976205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.4062774937 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1501115713 ps |
| CPU time | 17.21 seconds |
| Started | Sep 01 07:00:30 PM UTC 24 |
| Finished | Sep 01 07:00:48 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062774937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.4062774937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.4244689817 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 480122089 ps |
| CPU time | 5.77 seconds |
| Started | Sep 01 07:00:34 PM UTC 24 |
| Finished | Sep 01 07:00:41 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244689817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.4244689817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.2690686291 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 2413330422 ps |
| CPU time | 10.85 seconds |
| Started | Sep 01 07:00:30 PM UTC 24 |
| Finished | Sep 01 07:00:42 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690686291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2690686291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.1391582398 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 11414575629 ps |
| CPU time | 77.62 seconds |
| Started | Sep 01 07:00:34 PM UTC 24 |
| Finished | Sep 01 07:01:54 PM UTC 24 |
| Peak memory | 255472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391582398 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.1391582398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.696229514 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 19563680049 ps |
| CPU time | 21.02 seconds |
| Started | Sep 01 07:00:34 PM UTC 24 |
| Finished | Sep 01 07:00:56 PM UTC 24 |
| Peak memory | 257556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696229514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.696229514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.1965365438 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 8620436157 ps |
| CPU time | 20.53 seconds |
| Started | Sep 01 06:50:36 PM UTC 24 |
| Finished | Sep 01 06:50:58 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965365438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.1965365438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.3379125409 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1095909852 ps |
| CPU time | 20.96 seconds |
| Started | Sep 01 06:50:42 PM UTC 24 |
| Finished | Sep 01 06:51:04 PM UTC 24 |
| Peak memory | 253688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379125409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.3379125409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.1963242915 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1646369833 ps |
| CPU time | 56.88 seconds |
| Started | Sep 01 06:50:41 PM UTC 24 |
| Finished | Sep 01 06:51:39 PM UTC 24 |
| Peak memory | 261468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963242915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1963242915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.1052283973 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 442833659 ps |
| CPU time | 9.72 seconds |
| Started | Sep 01 06:50:41 PM UTC 24 |
| Finished | Sep 01 06:50:51 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052283973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.1052283973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.775875248 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 3327803738 ps |
| CPU time | 58.66 seconds |
| Started | Sep 01 06:50:43 PM UTC 24 |
| Finished | Sep 01 06:51:44 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775875248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.775875248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.553000802 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 165186368 ps |
| CPU time | 9.22 seconds |
| Started | Sep 01 06:50:44 PM UTC 24 |
| Finished | Sep 01 06:50:55 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553000802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.553000802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.3919354516 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 543059080 ps |
| CPU time | 6.81 seconds |
| Started | Sep 01 06:50:39 PM UTC 24 |
| Finished | Sep 01 06:50:47 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919354516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.3919354516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.2147387086 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 4473611623 ps |
| CPU time | 21.52 seconds |
| Started | Sep 01 06:50:36 PM UTC 24 |
| Finished | Sep 01 06:50:59 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147387086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.2147387086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.4164118475 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1898501485 ps |
| CPU time | 8.77 seconds |
| Started | Sep 01 06:50:48 PM UTC 24 |
| Finished | Sep 01 06:50:58 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164118475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.4164118475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.251602162 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1301931205 ps |
| CPU time | 14.09 seconds |
| Started | Sep 01 06:50:32 PM UTC 24 |
| Finished | Sep 01 06:50:48 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251602162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.251602162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.2651564880 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7786644708 ps |
| CPU time | 144.74 seconds |
| Started | Sep 01 06:50:49 PM UTC 24 |
| Finished | Sep 01 06:53:17 PM UTC 24 |
| Peak memory | 267880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2651564880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.otp_ctrl_stress_all_with_rand_reset.2651564880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.3057587483 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 7490142423 ps |
| CPU time | 13.23 seconds |
| Started | Sep 01 06:50:49 PM UTC 24 |
| Finished | Sep 01 06:51:04 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057587483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.3057587483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.3422002869 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 1895406926 ps |
| CPU time | 10.11 seconds |
| Started | Sep 01 07:00:36 PM UTC 24 |
| Finished | Sep 01 07:00:47 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422002869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.3422002869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.738050879 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 1873112113 ps |
| CPU time | 27.33 seconds |
| Started | Sep 01 07:00:39 PM UTC 24 |
| Finished | Sep 01 07:01:07 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738050879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.738050879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.2130706456 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 130701743 ps |
| CPU time | 6.67 seconds |
| Started | Sep 01 07:00:39 PM UTC 24 |
| Finished | Sep 01 07:00:46 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130706456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.2130706456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.4283273487 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 926721382 ps |
| CPU time | 13.26 seconds |
| Started | Sep 01 07:00:41 PM UTC 24 |
| Finished | Sep 01 07:00:56 PM UTC 24 |
| Peak memory | 250596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283273487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.4283273487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.1407138974 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3910005210 ps |
| CPU time | 78.18 seconds |
| Started | Sep 01 07:00:41 PM UTC 24 |
| Finished | Sep 01 07:02:02 PM UTC 24 |
| Peak memory | 257840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1407138974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 51.otp_ctrl_stress_all_with_rand_reset.1407138974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.883592271 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 142548813 ps |
| CPU time | 5.36 seconds |
| Started | Sep 01 07:00:42 PM UTC 24 |
| Finished | Sep 01 07:00:48 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883592271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.883592271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.1160734890 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 173634299 ps |
| CPU time | 6.86 seconds |
| Started | Sep 01 07:00:42 PM UTC 24 |
| Finished | Sep 01 07:00:50 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160734890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.1160734890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.3769513251 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 2211711930 ps |
| CPU time | 34.88 seconds |
| Started | Sep 01 07:00:49 PM UTC 24 |
| Finished | Sep 01 07:01:26 PM UTC 24 |
| Peak memory | 257684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3769513251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 52.otp_ctrl_stress_all_with_rand_reset.3769513251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.1782724653 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 213622970 ps |
| CPU time | 4.7 seconds |
| Started | Sep 01 07:00:49 PM UTC 24 |
| Finished | Sep 01 07:00:55 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782724653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.1782724653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.1559001751 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 252399737 ps |
| CPU time | 8.75 seconds |
| Started | Sep 01 07:00:49 PM UTC 24 |
| Finished | Sep 01 07:00:59 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559001751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.1559001751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.4221421529 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 207696587 ps |
| CPU time | 6.44 seconds |
| Started | Sep 01 07:00:50 PM UTC 24 |
| Finished | Sep 01 07:00:57 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221421529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.4221421529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.1985213131 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 281181033 ps |
| CPU time | 8.62 seconds |
| Started | Sep 01 07:00:50 PM UTC 24 |
| Finished | Sep 01 07:00:59 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985213131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.1985213131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.3137636195 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 136334615 ps |
| CPU time | 6.42 seconds |
| Started | Sep 01 07:00:50 PM UTC 24 |
| Finished | Sep 01 07:00:57 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137636195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.3137636195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.4146166048 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 214572393 ps |
| CPU time | 5.16 seconds |
| Started | Sep 01 07:00:50 PM UTC 24 |
| Finished | Sep 01 07:00:56 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146166048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.4146166048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.736990409 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 1940450679 ps |
| CPU time | 9.12 seconds |
| Started | Sep 01 07:00:57 PM UTC 24 |
| Finished | Sep 01 07:01:07 PM UTC 24 |
| Peak memory | 253272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736990409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.736990409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.4088756437 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 353216030 ps |
| CPU time | 9.65 seconds |
| Started | Sep 01 07:00:57 PM UTC 24 |
| Finished | Sep 01 07:01:08 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088756437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.4088756437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.2749577267 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 1520540184 ps |
| CPU time | 64.84 seconds |
| Started | Sep 01 07:00:57 PM UTC 24 |
| Finished | Sep 01 07:02:03 PM UTC 24 |
| Peak memory | 257560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2749577267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 56.otp_ctrl_stress_all_with_rand_reset.2749577267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.1207884231 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 142676733 ps |
| CPU time | 5.03 seconds |
| Started | Sep 01 07:00:57 PM UTC 24 |
| Finished | Sep 01 07:01:03 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207884231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1207884231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.1739608879 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 77643794 ps |
| CPU time | 3.98 seconds |
| Started | Sep 01 07:00:57 PM UTC 24 |
| Finished | Sep 01 07:01:02 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739608879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1739608879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.2589112463 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 334624224 ps |
| CPU time | 3.8 seconds |
| Started | Sep 01 07:00:57 PM UTC 24 |
| Finished | Sep 01 07:01:02 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589112463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.2589112463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.901805531 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 4429324708 ps |
| CPU time | 17.96 seconds |
| Started | Sep 01 07:00:57 PM UTC 24 |
| Finished | Sep 01 07:01:16 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901805531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.901805531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.337384814 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 95506995 ps |
| CPU time | 5.08 seconds |
| Started | Sep 01 07:00:57 PM UTC 24 |
| Finished | Sep 01 07:01:04 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337384814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.337384814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.559058617 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 230576766 ps |
| CPU time | 5.44 seconds |
| Started | Sep 01 07:00:57 PM UTC 24 |
| Finished | Sep 01 07:01:04 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559058617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.559058617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.3291479704 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 929749543 ps |
| CPU time | 3.53 seconds |
| Started | Sep 01 06:51:16 PM UTC 24 |
| Finished | Sep 01 06:51:20 PM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291479704 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.3291479704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.128325111 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 6231600341 ps |
| CPU time | 35.67 seconds |
| Started | Sep 01 06:50:56 PM UTC 24 |
| Finished | Sep 01 06:51:34 PM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128325111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.128325111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.2406238178 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1818859735 ps |
| CPU time | 40.85 seconds |
| Started | Sep 01 06:51:00 PM UTC 24 |
| Finished | Sep 01 06:51:42 PM UTC 24 |
| Peak memory | 255472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406238178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.2406238178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.3213019339 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2019941063 ps |
| CPU time | 41.57 seconds |
| Started | Sep 01 06:50:59 PM UTC 24 |
| Finished | Sep 01 06:51:42 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213019339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.3213019339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.626965759 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 104409955 ps |
| CPU time | 5.8 seconds |
| Started | Sep 01 06:50:53 PM UTC 24 |
| Finished | Sep 01 06:51:00 PM UTC 24 |
| Peak memory | 253276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626965759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.626965759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.4058737133 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 854771481 ps |
| CPU time | 17.73 seconds |
| Started | Sep 01 06:51:01 PM UTC 24 |
| Finished | Sep 01 06:51:21 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058737133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.4058737133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.2591737267 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 8908808796 ps |
| CPU time | 35.71 seconds |
| Started | Sep 01 06:51:01 PM UTC 24 |
| Finished | Sep 01 06:51:39 PM UTC 24 |
| Peak memory | 257496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591737267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.2591737267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.3269739687 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1403070660 ps |
| CPU time | 16.42 seconds |
| Started | Sep 01 06:50:59 PM UTC 24 |
| Finished | Sep 01 06:51:16 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269739687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.3269739687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.2210429847 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 800799478 ps |
| CPU time | 10.72 seconds |
| Started | Sep 01 06:50:59 PM UTC 24 |
| Finished | Sep 01 06:51:10 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210429847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.2210429847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.2401150327 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2521468932 ps |
| CPU time | 7.27 seconds |
| Started | Sep 01 06:51:05 PM UTC 24 |
| Finished | Sep 01 06:51:13 PM UTC 24 |
| Peak memory | 251608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401150327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.2401150327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.2954663392 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 269095301 ps |
| CPU time | 5.22 seconds |
| Started | Sep 01 06:50:53 PM UTC 24 |
| Finished | Sep 01 06:50:59 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954663392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.2954663392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.1842400912 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 424130684 ps |
| CPU time | 4.41 seconds |
| Started | Sep 01 07:00:57 PM UTC 24 |
| Finished | Sep 01 07:01:03 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842400912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.1842400912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.4046831987 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 548684650 ps |
| CPU time | 5.82 seconds |
| Started | Sep 01 07:00:57 PM UTC 24 |
| Finished | Sep 01 07:01:04 PM UTC 24 |
| Peak memory | 250700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046831987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.4046831987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.2645124503 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 247950572 ps |
| CPU time | 3.77 seconds |
| Started | Sep 01 07:00:57 PM UTC 24 |
| Finished | Sep 01 07:01:02 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645124503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.2645124503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.2086224867 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 157621868 ps |
| CPU time | 4.8 seconds |
| Started | Sep 01 07:01:01 PM UTC 24 |
| Finished | Sep 01 07:01:08 PM UTC 24 |
| Peak memory | 253048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086224867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.2086224867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.3916774508 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 158538314 ps |
| CPU time | 5.03 seconds |
| Started | Sep 01 07:01:01 PM UTC 24 |
| Finished | Sep 01 07:01:08 PM UTC 24 |
| Peak memory | 253276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916774508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.3916774508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.2649626762 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 397333631 ps |
| CPU time | 4.57 seconds |
| Started | Sep 01 07:01:02 PM UTC 24 |
| Finished | Sep 01 07:01:08 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649626762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.2649626762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.2547817786 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 3265716125 ps |
| CPU time | 132.99 seconds |
| Started | Sep 01 07:01:02 PM UTC 24 |
| Finished | Sep 01 07:03:18 PM UTC 24 |
| Peak memory | 257596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2547817786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 62.otp_ctrl_stress_all_with_rand_reset.2547817786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.618902611 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 132386179 ps |
| CPU time | 3.9 seconds |
| Started | Sep 01 07:01:02 PM UTC 24 |
| Finished | Sep 01 07:01:07 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618902611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.618902611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.2367268031 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 1104412087 ps |
| CPU time | 17.45 seconds |
| Started | Sep 01 07:01:02 PM UTC 24 |
| Finished | Sep 01 07:01:21 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367268031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.2367268031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.1657813206 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 24868482729 ps |
| CPU time | 188.65 seconds |
| Started | Sep 01 07:01:02 PM UTC 24 |
| Finished | Sep 01 07:04:14 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1657813206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 63.otp_ctrl_stress_all_with_rand_reset.1657813206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.3777777655 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 120408443 ps |
| CPU time | 7.99 seconds |
| Started | Sep 01 07:01:06 PM UTC 24 |
| Finished | Sep 01 07:01:16 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777777655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.3777777655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.3533632688 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 139273912 ps |
| CPU time | 5.34 seconds |
| Started | Sep 01 07:01:06 PM UTC 24 |
| Finished | Sep 01 07:01:13 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533632688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3533632688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.3256407899 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 2018870379 ps |
| CPU time | 18.86 seconds |
| Started | Sep 01 07:01:07 PM UTC 24 |
| Finished | Sep 01 07:01:27 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256407899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3256407899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.958310812 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 16697995757 ps |
| CPU time | 154.76 seconds |
| Started | Sep 01 07:01:07 PM UTC 24 |
| Finished | Sep 01 07:03:44 PM UTC 24 |
| Peak memory | 272020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=958310812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.958310812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.1156647162 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 116468014 ps |
| CPU time | 4.95 seconds |
| Started | Sep 01 07:01:07 PM UTC 24 |
| Finished | Sep 01 07:01:13 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156647162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.1156647162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.647457533 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 3765963612 ps |
| CPU time | 11.82 seconds |
| Started | Sep 01 07:01:07 PM UTC 24 |
| Finished | Sep 01 07:01:20 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647457533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.647457533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.3676532816 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 6284895006 ps |
| CPU time | 84.63 seconds |
| Started | Sep 01 07:01:07 PM UTC 24 |
| Finished | Sep 01 07:02:34 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3676532816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 66.otp_ctrl_stress_all_with_rand_reset.3676532816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.38598539 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 417331575 ps |
| CPU time | 5.51 seconds |
| Started | Sep 01 07:01:07 PM UTC 24 |
| Finished | Sep 01 07:01:13 PM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38598539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.38598539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.403981656 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 14273430698 ps |
| CPU time | 42.33 seconds |
| Started | Sep 01 07:01:07 PM UTC 24 |
| Finished | Sep 01 07:01:51 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403981656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.403981656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.4033453164 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 5847735719 ps |
| CPU time | 52.56 seconds |
| Started | Sep 01 07:01:07 PM UTC 24 |
| Finished | Sep 01 07:02:01 PM UTC 24 |
| Peak memory | 257560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4033453164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 67.otp_ctrl_stress_all_with_rand_reset.4033453164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.1033260625 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 414160472 ps |
| CPU time | 4.52 seconds |
| Started | Sep 01 07:01:18 PM UTC 24 |
| Finished | Sep 01 07:01:24 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033260625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.1033260625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.3495100256 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 8936837767 ps |
| CPU time | 26.64 seconds |
| Started | Sep 01 07:01:18 PM UTC 24 |
| Finished | Sep 01 07:01:47 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495100256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.3495100256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.2279077902 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 557295541 ps |
| CPU time | 4.7 seconds |
| Started | Sep 01 07:01:18 PM UTC 24 |
| Finished | Sep 01 07:01:24 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279077902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.2279077902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.1262518910 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1767916231 ps |
| CPU time | 15.3 seconds |
| Started | Sep 01 07:01:18 PM UTC 24 |
| Finished | Sep 01 07:01:35 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262518910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.1262518910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.4232278617 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 62031953 ps |
| CPU time | 2.87 seconds |
| Started | Sep 01 06:51:42 PM UTC 24 |
| Finished | Sep 01 06:51:46 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232278617 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.4232278617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.2291539990 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2179823942 ps |
| CPU time | 23.16 seconds |
| Started | Sep 01 06:51:21 PM UTC 24 |
| Finished | Sep 01 06:51:45 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291539990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.2291539990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.2961068382 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 476175272 ps |
| CPU time | 15.07 seconds |
| Started | Sep 01 06:51:36 PM UTC 24 |
| Finished | Sep 01 06:51:52 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961068382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.2961068382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.126408064 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 360050430 ps |
| CPU time | 28.34 seconds |
| Started | Sep 01 06:51:27 PM UTC 24 |
| Finished | Sep 01 06:51:57 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126408064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.126408064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.1254709794 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 16417734125 ps |
| CPU time | 52.29 seconds |
| Started | Sep 01 06:51:27 PM UTC 24 |
| Finished | Sep 01 06:52:21 PM UTC 24 |
| Peak memory | 253692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254709794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.1254709794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.430012459 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 385013553 ps |
| CPU time | 5.4 seconds |
| Started | Sep 01 06:51:20 PM UTC 24 |
| Finished | Sep 01 06:51:26 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430012459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.430012459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.3253888290 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 3373235418 ps |
| CPU time | 29.14 seconds |
| Started | Sep 01 06:51:36 PM UTC 24 |
| Finished | Sep 01 06:52:06 PM UTC 24 |
| Peak memory | 257632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253888290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.3253888290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.798659553 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 4395758027 ps |
| CPU time | 31.46 seconds |
| Started | Sep 01 06:51:38 PM UTC 24 |
| Finished | Sep 01 06:52:11 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798659553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.798659553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.1454702429 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 153972056 ps |
| CPU time | 9.67 seconds |
| Started | Sep 01 06:51:27 PM UTC 24 |
| Finished | Sep 01 06:51:38 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454702429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.1454702429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.3613676915 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 636391516 ps |
| CPU time | 12.15 seconds |
| Started | Sep 01 06:51:22 PM UTC 24 |
| Finished | Sep 01 06:51:35 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613676915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.3613676915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.4274605354 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 552987427 ps |
| CPU time | 14 seconds |
| Started | Sep 01 06:51:38 PM UTC 24 |
| Finished | Sep 01 06:51:53 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274605354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.4274605354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.1225757686 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 4111614476 ps |
| CPU time | 17.62 seconds |
| Started | Sep 01 06:51:17 PM UTC 24 |
| Finished | Sep 01 06:51:36 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225757686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1225757686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.3964011190 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 9852303228 ps |
| CPU time | 107.95 seconds |
| Started | Sep 01 06:51:40 PM UTC 24 |
| Finished | Sep 01 06:53:30 PM UTC 24 |
| Peak memory | 257556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964011190 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.3964011190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.2185731632 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 907621536 ps |
| CPU time | 14.34 seconds |
| Started | Sep 01 06:51:38 PM UTC 24 |
| Finished | Sep 01 06:51:54 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185731632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2185731632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.3830238521 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 188716537 ps |
| CPU time | 5.31 seconds |
| Started | Sep 01 07:01:19 PM UTC 24 |
| Finished | Sep 01 07:01:25 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830238521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.3830238521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.1728786387 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 254630364 ps |
| CPU time | 5.7 seconds |
| Started | Sep 01 07:01:19 PM UTC 24 |
| Finished | Sep 01 07:01:26 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728786387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.1728786387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.769767811 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 39765227461 ps |
| CPU time | 247.19 seconds |
| Started | Sep 01 07:01:19 PM UTC 24 |
| Finished | Sep 01 07:05:30 PM UTC 24 |
| Peak memory | 288348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=769767811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.769767811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.2741011017 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 255300334 ps |
| CPU time | 5.84 seconds |
| Started | Sep 01 07:01:19 PM UTC 24 |
| Finished | Sep 01 07:01:26 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741011017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.2741011017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.501692028 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 420734268 ps |
| CPU time | 5.41 seconds |
| Started | Sep 01 07:01:19 PM UTC 24 |
| Finished | Sep 01 07:01:26 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501692028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.501692028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2913553730 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 15922085158 ps |
| CPU time | 149.61 seconds |
| Started | Sep 01 07:01:19 PM UTC 24 |
| Finished | Sep 01 07:03:51 PM UTC 24 |
| Peak memory | 269936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2913553730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 71.otp_ctrl_stress_all_with_rand_reset.2913553730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.696718620 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 702499207 ps |
| CPU time | 6.07 seconds |
| Started | Sep 01 07:01:19 PM UTC 24 |
| Finished | Sep 01 07:01:26 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696718620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.696718620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.624716313 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 173222864 ps |
| CPU time | 6.76 seconds |
| Started | Sep 01 07:01:19 PM UTC 24 |
| Finished | Sep 01 07:01:27 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624716313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.624716313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.64025547 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 7054715723 ps |
| CPU time | 81.92 seconds |
| Started | Sep 01 07:01:19 PM UTC 24 |
| Finished | Sep 01 07:02:43 PM UTC 24 |
| Peak memory | 259652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=64025547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.64025547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.1687591830 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 253737783 ps |
| CPU time | 5.32 seconds |
| Started | Sep 01 07:01:19 PM UTC 24 |
| Finished | Sep 01 07:01:26 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687591830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.1687591830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.4100224464 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 4911156517 ps |
| CPU time | 10.88 seconds |
| Started | Sep 01 07:01:19 PM UTC 24 |
| Finished | Sep 01 07:01:31 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100224464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.4100224464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.2631529718 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 99681769125 ps |
| CPU time | 180.28 seconds |
| Started | Sep 01 07:01:24 PM UTC 24 |
| Finished | Sep 01 07:04:28 PM UTC 24 |
| Peak memory | 284308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2631529718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 73.otp_ctrl_stress_all_with_rand_reset.2631529718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.1936076025 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 311072666 ps |
| CPU time | 4.55 seconds |
| Started | Sep 01 07:01:24 PM UTC 24 |
| Finished | Sep 01 07:01:30 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936076025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.1936076025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.1544396091 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 350519164 ps |
| CPU time | 12.27 seconds |
| Started | Sep 01 07:01:24 PM UTC 24 |
| Finished | Sep 01 07:01:38 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544396091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1544396091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.962166274 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1210228984 ps |
| CPU time | 53.43 seconds |
| Started | Sep 01 07:01:24 PM UTC 24 |
| Finished | Sep 01 07:02:19 PM UTC 24 |
| Peak memory | 257536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=962166274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.962166274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.63545757 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 137699374 ps |
| CPU time | 4.99 seconds |
| Started | Sep 01 07:01:24 PM UTC 24 |
| Finished | Sep 01 07:01:30 PM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63545757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.63545757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.1709898484 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 821132019 ps |
| CPU time | 9.26 seconds |
| Started | Sep 01 07:01:24 PM UTC 24 |
| Finished | Sep 01 07:01:35 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709898484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.1709898484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.3125800267 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 118685522 ps |
| CPU time | 4.79 seconds |
| Started | Sep 01 07:01:31 PM UTC 24 |
| Finished | Sep 01 07:01:37 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125800267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.3125800267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.1629769211 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 3191077521 ps |
| CPU time | 8.77 seconds |
| Started | Sep 01 07:01:31 PM UTC 24 |
| Finished | Sep 01 07:01:41 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629769211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.1629769211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.1701560504 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2277388975 ps |
| CPU time | 60.36 seconds |
| Started | Sep 01 07:01:31 PM UTC 24 |
| Finished | Sep 01 07:02:33 PM UTC 24 |
| Peak memory | 257852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1701560504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 76.otp_ctrl_stress_all_with_rand_reset.1701560504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.1580958536 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 147744039 ps |
| CPU time | 6.12 seconds |
| Started | Sep 01 07:01:31 PM UTC 24 |
| Finished | Sep 01 07:01:39 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580958536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.1580958536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.141703584 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1963680805 ps |
| CPU time | 9.37 seconds |
| Started | Sep 01 07:01:31 PM UTC 24 |
| Finished | Sep 01 07:01:42 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141703584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.141703584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.2411983342 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 395896136 ps |
| CPU time | 5.45 seconds |
| Started | Sep 01 07:01:32 PM UTC 24 |
| Finished | Sep 01 07:01:38 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411983342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.2411983342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.2855816097 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1573992035 ps |
| CPU time | 7.5 seconds |
| Started | Sep 01 07:01:32 PM UTC 24 |
| Finished | Sep 01 07:01:40 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855816097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2855816097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.2741880993 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 4579844058 ps |
| CPU time | 13.51 seconds |
| Started | Sep 01 07:01:32 PM UTC 24 |
| Finished | Sep 01 07:01:47 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741880993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.2741880993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2410899480 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 13474094066 ps |
| CPU time | 148.1 seconds |
| Started | Sep 01 07:01:32 PM UTC 24 |
| Finished | Sep 01 07:04:03 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2410899480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 79.otp_ctrl_stress_all_with_rand_reset.2410899480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.1168032925 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 165847635 ps |
| CPU time | 3.32 seconds |
| Started | Sep 01 06:52:01 PM UTC 24 |
| Finished | Sep 01 06:52:05 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168032925 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.1168032925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.565321786 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 420215674 ps |
| CPU time | 12.65 seconds |
| Started | Sep 01 06:51:46 PM UTC 24 |
| Finished | Sep 01 06:51:59 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565321786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.565321786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.2972355441 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 289200903 ps |
| CPU time | 4.16 seconds |
| Started | Sep 01 06:51:54 PM UTC 24 |
| Finished | Sep 01 06:51:59 PM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972355441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2972355441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.1811053296 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 5290742965 ps |
| CPU time | 53.33 seconds |
| Started | Sep 01 06:51:54 PM UTC 24 |
| Finished | Sep 01 06:52:48 PM UTC 24 |
| Peak memory | 259516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811053296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.1811053296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.1617290962 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 307842714 ps |
| CPU time | 5.99 seconds |
| Started | Sep 01 06:51:50 PM UTC 24 |
| Finished | Sep 01 06:51:57 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617290962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.1617290962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.1122913322 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1595525664 ps |
| CPU time | 4.28 seconds |
| Started | Sep 01 06:51:44 PM UTC 24 |
| Finished | Sep 01 06:51:49 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122913322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.1122913322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.3672931313 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 284693141 ps |
| CPU time | 9.86 seconds |
| Started | Sep 01 06:51:55 PM UTC 24 |
| Finished | Sep 01 06:52:06 PM UTC 24 |
| Peak memory | 253200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672931313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.3672931313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.1248420949 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1524763591 ps |
| CPU time | 42.6 seconds |
| Started | Sep 01 06:51:55 PM UTC 24 |
| Finished | Sep 01 06:52:39 PM UTC 24 |
| Peak memory | 253436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248420949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.1248420949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.380201137 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 583334105 ps |
| CPU time | 12.64 seconds |
| Started | Sep 01 06:51:47 PM UTC 24 |
| Finished | Sep 01 06:52:01 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380201137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.380201137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.2864727560 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1699743590 ps |
| CPU time | 9.62 seconds |
| Started | Sep 01 06:51:46 PM UTC 24 |
| Finished | Sep 01 06:51:57 PM UTC 24 |
| Peak memory | 253200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864727560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.2864727560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.1506083965 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 394343198 ps |
| CPU time | 17.09 seconds |
| Started | Sep 01 06:51:44 PM UTC 24 |
| Finished | Sep 01 06:52:02 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506083965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.1506083965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.3519754144 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 17271801330 ps |
| CPU time | 46.43 seconds |
| Started | Sep 01 06:52:01 PM UTC 24 |
| Finished | Sep 01 06:52:49 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519754144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.3519754144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.3965996165 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 2398248468 ps |
| CPU time | 11.92 seconds |
| Started | Sep 01 07:01:32 PM UTC 24 |
| Finished | Sep 01 07:01:45 PM UTC 24 |
| Peak memory | 251364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965996165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3965996165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.3670929613 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 1991186808 ps |
| CPU time | 17.86 seconds |
| Started | Sep 01 07:01:32 PM UTC 24 |
| Finished | Sep 01 07:01:51 PM UTC 24 |
| Peak memory | 257320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670929613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.3670929613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.4084041155 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 513150541 ps |
| CPU time | 6.36 seconds |
| Started | Sep 01 07:01:32 PM UTC 24 |
| Finished | Sep 01 07:01:40 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084041155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.4084041155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.1641449875 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 2373515543 ps |
| CPU time | 8.05 seconds |
| Started | Sep 01 07:01:32 PM UTC 24 |
| Finished | Sep 01 07:01:41 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641449875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.1641449875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.41133599 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 445220766 ps |
| CPU time | 8.19 seconds |
| Started | Sep 01 07:01:37 PM UTC 24 |
| Finished | Sep 01 07:01:47 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41133599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.41133599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.1026249034 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 224673684 ps |
| CPU time | 7.07 seconds |
| Started | Sep 01 07:01:37 PM UTC 24 |
| Finished | Sep 01 07:01:46 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026249034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.1026249034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.3669042903 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 5199875637 ps |
| CPU time | 90.28 seconds |
| Started | Sep 01 07:01:37 PM UTC 24 |
| Finished | Sep 01 07:03:10 PM UTC 24 |
| Peak memory | 274096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3669042903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 82.otp_ctrl_stress_all_with_rand_reset.3669042903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.2736271267 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 396257379 ps |
| CPU time | 4.21 seconds |
| Started | Sep 01 07:01:39 PM UTC 24 |
| Finished | Sep 01 07:01:44 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736271267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.2736271267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.1896798688 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 82339332 ps |
| CPU time | 4.04 seconds |
| Started | Sep 01 07:01:39 PM UTC 24 |
| Finished | Sep 01 07:01:44 PM UTC 24 |
| Peak memory | 257300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896798688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.1896798688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.375378134 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 20499720311 ps |
| CPU time | 160.88 seconds |
| Started | Sep 01 07:01:39 PM UTC 24 |
| Finished | Sep 01 07:04:23 PM UTC 24 |
| Peak memory | 267840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=375378134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.375378134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.4210131182 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 395346995 ps |
| CPU time | 4.99 seconds |
| Started | Sep 01 07:01:43 PM UTC 24 |
| Finished | Sep 01 07:01:50 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210131182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.4210131182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.3891151347 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1613518045 ps |
| CPU time | 6.48 seconds |
| Started | Sep 01 07:01:44 PM UTC 24 |
| Finished | Sep 01 07:01:51 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891151347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3891151347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.3090176649 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 191228467 ps |
| CPU time | 5.46 seconds |
| Started | Sep 01 07:01:44 PM UTC 24 |
| Finished | Sep 01 07:01:50 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090176649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.3090176649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.1035917008 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 2398445594 ps |
| CPU time | 9.6 seconds |
| Started | Sep 01 07:01:44 PM UTC 24 |
| Finished | Sep 01 07:01:54 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035917008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.1035917008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.1380457622 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 140680918 ps |
| CPU time | 5.43 seconds |
| Started | Sep 01 07:01:44 PM UTC 24 |
| Finished | Sep 01 07:01:50 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380457622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.1380457622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.4074481375 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 238299158 ps |
| CPU time | 8.54 seconds |
| Started | Sep 01 07:01:44 PM UTC 24 |
| Finished | Sep 01 07:01:54 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074481375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.4074481375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.545318841 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 6422561119 ps |
| CPU time | 57.68 seconds |
| Started | Sep 01 07:01:44 PM UTC 24 |
| Finished | Sep 01 07:02:43 PM UTC 24 |
| Peak memory | 257688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=545318841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.545318841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/86.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.2554172458 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 374877184 ps |
| CPU time | 5.66 seconds |
| Started | Sep 01 07:01:44 PM UTC 24 |
| Finished | Sep 01 07:01:51 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554172458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.2554172458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.2660222808 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 175289617 ps |
| CPU time | 9.92 seconds |
| Started | Sep 01 07:01:44 PM UTC 24 |
| Finished | Sep 01 07:01:55 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660222808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.2660222808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.1666938740 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 126606734 ps |
| CPU time | 3.98 seconds |
| Started | Sep 01 07:01:45 PM UTC 24 |
| Finished | Sep 01 07:01:50 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666938740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.1666938740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.1352730414 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2548455139 ps |
| CPU time | 12.71 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:02:07 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352730414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.1352730414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.252031524 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 13574321658 ps |
| CPU time | 53.2 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:02:48 PM UTC 24 |
| Peak memory | 268084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=252031524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.252031524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/88.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.964403068 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 101081028 ps |
| CPU time | 4.64 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:01:58 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964403068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.964403068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.3875859859 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 1031480945 ps |
| CPU time | 15.27 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:02:09 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875859859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.3875859859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.3837794684 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 8971284409 ps |
| CPU time | 102.9 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:03:38 PM UTC 24 |
| Peak memory | 274264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3837794684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 89.otp_ctrl_stress_all_with_rand_reset.3837794684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.2458932780 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 691638472 ps |
| CPU time | 3.24 seconds |
| Started | Sep 01 06:52:19 PM UTC 24 |
| Finished | Sep 01 06:52:24 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458932780 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.2458932780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.2912728200 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 16048008186 ps |
| CPU time | 57.61 seconds |
| Started | Sep 01 06:52:02 PM UTC 24 |
| Finished | Sep 01 06:53:01 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912728200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.2912728200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.1117478578 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2886227832 ps |
| CPU time | 8.04 seconds |
| Started | Sep 01 06:52:09 PM UTC 24 |
| Finished | Sep 01 06:52:18 PM UTC 24 |
| Peak memory | 257400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117478578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.1117478578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.1980972069 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 806799992 ps |
| CPU time | 28.17 seconds |
| Started | Sep 01 06:52:08 PM UTC 24 |
| Finished | Sep 01 06:52:37 PM UTC 24 |
| Peak memory | 251268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980972069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.1980972069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.3303128602 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 341668265 ps |
| CPU time | 14.57 seconds |
| Started | Sep 01 06:52:07 PM UTC 24 |
| Finished | Sep 01 06:52:22 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303128602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.3303128602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.2281132806 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 129982410 ps |
| CPU time | 6.09 seconds |
| Started | Sep 01 06:52:01 PM UTC 24 |
| Finished | Sep 01 06:52:08 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281132806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.2281132806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.1498643457 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 177067655 ps |
| CPU time | 5.69 seconds |
| Started | Sep 01 06:52:13 PM UTC 24 |
| Finished | Sep 01 06:52:20 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498643457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.1498643457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.378728100 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3597216844 ps |
| CPU time | 34.33 seconds |
| Started | Sep 01 06:52:13 PM UTC 24 |
| Finished | Sep 01 06:52:49 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378728100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.378728100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.4198789520 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3935629635 ps |
| CPU time | 11.3 seconds |
| Started | Sep 01 06:52:07 PM UTC 24 |
| Finished | Sep 01 06:52:19 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198789520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.4198789520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.906938170 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1500201003 ps |
| CPU time | 30.29 seconds |
| Started | Sep 01 06:52:03 PM UTC 24 |
| Finished | Sep 01 06:52:35 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906938170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.906938170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.3369569692 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 164453526 ps |
| CPU time | 7.34 seconds |
| Started | Sep 01 06:52:15 PM UTC 24 |
| Finished | Sep 01 06:52:23 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369569692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3369569692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.592378727 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 504916498 ps |
| CPU time | 10.94 seconds |
| Started | Sep 01 06:52:01 PM UTC 24 |
| Finished | Sep 01 06:52:13 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592378727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.592378727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.1243109307 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 17416047088 ps |
| CPU time | 117.81 seconds |
| Started | Sep 01 06:52:15 PM UTC 24 |
| Finished | Sep 01 06:54:15 PM UTC 24 |
| Peak memory | 267880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1243109307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.otp_ctrl_stress_all_with_rand_reset.1243109307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.3428835256 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2091475429 ps |
| CPU time | 34.46 seconds |
| Started | Sep 01 06:52:15 PM UTC 24 |
| Finished | Sep 01 06:52:51 PM UTC 24 |
| Peak memory | 257296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428835256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.3428835256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.3835896846 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2496835299 ps |
| CPU time | 7.91 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:02:02 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835896846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.3835896846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.1310267674 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 633262626 ps |
| CPU time | 18.39 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:02:13 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310267674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.1310267674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.2545535138 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 8523615035 ps |
| CPU time | 192.16 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:05:09 PM UTC 24 |
| Peak memory | 274008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2545535138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 90.otp_ctrl_stress_all_with_rand_reset.2545535138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/90.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.875248968 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 425607301 ps |
| CPU time | 5.75 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:02:00 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875248968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.875248968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.794771278 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 218158544 ps |
| CPU time | 6.41 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:02:01 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794771278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.794771278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.2100700188 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 681490515 ps |
| CPU time | 5.26 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:02:00 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100700188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2100700188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.3819393318 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 414157506 ps |
| CPU time | 13.16 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:02:08 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819393318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3819393318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.2639669357 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 15708462791 ps |
| CPU time | 181.4 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:04:58 PM UTC 24 |
| Peak memory | 274096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2639669357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 92.otp_ctrl_stress_all_with_rand_reset.2639669357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.4089159985 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1613565467 ps |
| CPU time | 6.14 seconds |
| Started | Sep 01 07:01:53 PM UTC 24 |
| Finished | Sep 01 07:02:01 PM UTC 24 |
| Peak memory | 253272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089159985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.4089159985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.618384850 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 569048098 ps |
| CPU time | 12.58 seconds |
| Started | Sep 01 07:01:56 PM UTC 24 |
| Finished | Sep 01 07:02:10 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618384850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.618384850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1366362600 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 8262721407 ps |
| CPU time | 109.92 seconds |
| Started | Sep 01 07:01:56 PM UTC 24 |
| Finished | Sep 01 07:03:48 PM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1366362600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 93.otp_ctrl_stress_all_with_rand_reset.1366362600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/93.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.3379328514 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 130856379 ps |
| CPU time | 5.79 seconds |
| Started | Sep 01 07:01:56 PM UTC 24 |
| Finished | Sep 01 07:02:03 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379328514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.3379328514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.800064886 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 145708923 ps |
| CPU time | 5.36 seconds |
| Started | Sep 01 07:01:56 PM UTC 24 |
| Finished | Sep 01 07:02:03 PM UTC 24 |
| Peak memory | 251088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800064886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.800064886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2046916011 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 7158897731 ps |
| CPU time | 53.69 seconds |
| Started | Sep 01 07:01:56 PM UTC 24 |
| Finished | Sep 01 07:02:51 PM UTC 24 |
| Peak memory | 257684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2046916011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 94.otp_ctrl_stress_all_with_rand_reset.2046916011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.1349303004 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 192999297 ps |
| CPU time | 4.46 seconds |
| Started | Sep 01 07:01:56 PM UTC 24 |
| Finished | Sep 01 07:02:02 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349303004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.1349303004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.209721515 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 3251679227 ps |
| CPU time | 7.91 seconds |
| Started | Sep 01 07:01:58 PM UTC 24 |
| Finished | Sep 01 07:02:06 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209721515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.209721515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.3736459746 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 334876743 ps |
| CPU time | 5.93 seconds |
| Started | Sep 01 07:02:01 PM UTC 24 |
| Finished | Sep 01 07:02:08 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736459746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.3736459746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.2653966911 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 2983126569 ps |
| CPU time | 20.75 seconds |
| Started | Sep 01 07:02:01 PM UTC 24 |
| Finished | Sep 01 07:02:23 PM UTC 24 |
| Peak memory | 253292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653966911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.2653966911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.37130852 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 15134448737 ps |
| CPU time | 87.68 seconds |
| Started | Sep 01 07:02:01 PM UTC 24 |
| Finished | Sep 01 07:03:31 PM UTC 24 |
| Peak memory | 267844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=37130852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.37130852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.3580721506 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 254732022 ps |
| CPU time | 5.28 seconds |
| Started | Sep 01 07:02:06 PM UTC 24 |
| Finished | Sep 01 07:02:13 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580721506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.3580721506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.18649844 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 94495393 ps |
| CPU time | 3.5 seconds |
| Started | Sep 01 07:02:06 PM UTC 24 |
| Finished | Sep 01 07:02:11 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18649844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.18649844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.310868165 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 4985396521 ps |
| CPU time | 114.72 seconds |
| Started | Sep 01 07:02:07 PM UTC 24 |
| Finished | Sep 01 07:04:04 PM UTC 24 |
| Peak memory | 267956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=310868165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.310868165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.3440288398 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 191951750 ps |
| CPU time | 4.81 seconds |
| Started | Sep 01 07:02:07 PM UTC 24 |
| Finished | Sep 01 07:02:13 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440288398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.3440288398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.195336685 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 220070799 ps |
| CPU time | 6.91 seconds |
| Started | Sep 01 07:02:07 PM UTC 24 |
| Finished | Sep 01 07:02:15 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195336685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.195336685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.2792156609 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 8268490896 ps |
| CPU time | 65.06 seconds |
| Started | Sep 01 07:02:07 PM UTC 24 |
| Finished | Sep 01 07:03:14 PM UTC 24 |
| Peak memory | 257944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2792156609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 98.otp_ctrl_stress_all_with_rand_reset.2792156609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.2252889056 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 2047713531 ps |
| CPU time | 7.42 seconds |
| Started | Sep 01 07:02:07 PM UTC 24 |
| Finished | Sep 01 07:02:15 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252889056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2252889056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.35663111 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 243469193 ps |
| CPU time | 10.08 seconds |
| Started | Sep 01 07:02:07 PM UTC 24 |
| Finished | Sep 01 07:02:18 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35663111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.35663111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.1277870684 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 13955021537 ps |
| CPU time | 132.46 seconds |
| Started | Sep 01 07:02:07 PM UTC 24 |
| Finished | Sep 01 07:04:22 PM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1277870684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 99.otp_ctrl_stress_all_with_rand_reset.1277870684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |