Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4232982	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2473515

1

T1

11

T2

129

T3

529

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5632156	1			T1	4		T2	362		T3	3093
values[0x0]	505512	1			T1	6		T2	79		T3	81
values[0x1]	568829	1			T1	9		T2	100		T3	69

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3130679	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3575818

1

T1

12

T2

248

T3

1362

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24880	1			T3	22		T12	24		T44	1
valid_sources[0x01]	24228	1			T3	13		T11	1		T5	8
valid_sources[0x02]	21451	1			T3	10		T5	4		T12	6
valid_sources[0x03]	23126	1			T2	59		T3	20		T5	12
valid_sources[0x04]	23465	1			T2	4		T3	19		T12	15
valid_sources[0x05]	32258	1			T1	19		T3	14		T5	1
valid_sources[0x06]	29431	1			T3	21		T5	23		T12	14
valid_sources[0x07]	22194	1			T3	17		T5	30		T12	14
valid_sources[0x08]	26081	1			T3	7		T5	5		T12	16
valid_sources[0x09]	38147	1			T3	9		T5	20		T12	13
valid_sources[0x0a]	27696	1			T3	12		T5	13		T12	16
valid_sources[0x0b]	25783	1			T3	11		T12	14		T13	1
valid_sources[0x0c]	26374	1			T3	12		T5	13		T12	25
valid_sources[0x0d]	23751	1			T3	9		T5	1		T12	11
valid_sources[0x0e]	22747	1			T3	12		T5	6		T12	15
valid_sources[0x0f]	21944	1			T2	27		T3	12		T12	26
valid_sources[0x10]	22919	1			T3	15		T11	3		T12	17
valid_sources[0x11]	24379	1			T3	8		T5	3		T12	8
valid_sources[0x12]	24821	1			T3	21		T5	1		T12	15
valid_sources[0x13]	26327	1			T3	7		T5	3		T12	16
valid_sources[0x14]	23213	1			T3	18		T12	17		T44	8
valid_sources[0x15]	30989	1			T3	16		T5	9		T12	10
valid_sources[0x16]	33862	1			T3	12		T5	1		T12	16
valid_sources[0x17]	22539	1			T3	10		T5	15		T12	15
valid_sources[0x18]	28137	1			T3	6		T12	11		T24	5
valid_sources[0x19]	21695	1			T3	10		T5	16		T12	29
valid_sources[0x1a]	22262	1			T3	16		T5	2		T12	21
valid_sources[0x1b]	23014	1			T3	10		T5	4		T12	15
valid_sources[0x1c]	22959	1			T3	5		T12	15		T44	2
valid_sources[0x1d]	20884	1			T3	8		T11	1		T5	3
valid_sources[0x1e]	33721	1			T3	20		T12	24		T44	1
valid_sources[0x1f]	23822	1			T3	16		T12	15		T6	4
valid_sources[0x20]	26815	1			T3	10		T5	18		T12	18
valid_sources[0x21]	25570	1			T3	10		T11	1		T5	17
valid_sources[0x22]	21480	1			T3	9		T5	21		T12	16
valid_sources[0x23]	21964	1			T3	10		T5	10		T12	12
valid_sources[0x24]	25301	1			T3	12		T12	19		T31	15
valid_sources[0x25]	34566	1			T2	2		T3	11		T11	1
valid_sources[0x26]	37438	1			T3	10		T5	25		T12	12
valid_sources[0x27]	22195	1			T3	15		T5	7		T12	19
valid_sources[0x28]	25915	1			T2	9		T3	7		T5	13
valid_sources[0x29]	24891	1			T3	15		T5	2		T12	12
valid_sources[0x2a]	21967	1			T3	13		T5	5		T12	16
valid_sources[0x2b]	26623	1			T3	9		T12	27		T6	1
valid_sources[0x2c]	26053	1			T2	14		T3	15		T12	5
valid_sources[0x2d]	28845	1			T3	13		T5	3		T12	17
valid_sources[0x2e]	30541	1			T3	11		T5	1		T12	25
valid_sources[0x2f]	24102	1			T3	15		T5	16		T12	10
valid_sources[0x30]	23092	1			T3	15		T12	22		T24	4
valid_sources[0x31]	32176	1			T3	9		T11	2		T12	18
valid_sources[0x32]	23571	1			T3	9		T5	21		T12	20
valid_sources[0x33]	21730	1			T3	8		T11	1		T12	12
valid_sources[0x34]	21537	1			T3	11		T5	2		T10	95
valid_sources[0x35]	21736	1			T3	13		T5	5		T12	21
valid_sources[0x36]	30708	1			T3	17		T11	2		T12	21
valid_sources[0x37]	23173	1			T2	66		T3	15		T5	12
valid_sources[0x38]	27520	1			T3	11		T12	17		T6	3
valid_sources[0x39]	22357	1			T3	15		T5	7		T12	13
valid_sources[0x3a]	22002	1			T3	16		T5	12		T12	6
valid_sources[0x3b]	24517	1			T3	16		T5	1		T12	9
valid_sources[0x3c]	21306	1			T2	3		T3	19		T12	20
valid_sources[0x3d]	22125	1			T3	8		T12	14		T6	1
valid_sources[0x3e]	21189	1			T3	9		T5	1		T12	15
valid_sources[0x3f]	27632	1			T3	16		T5	33		T12	15
valid_sources[0x40]	27850	1			T3	14		T5	4		T12	17
valid_sources[0x41]	24011	1			T2	42		T3	12		T12	14
valid_sources[0x42]	21684	1			T2	11		T3	7		T11	1
valid_sources[0x43]	24355	1			T3	9		T11	2		T12	21
valid_sources[0x44]	40869	1			T3	19		T5	13		T12	13
valid_sources[0x45]	23688	1			T3	8		T5	5		T12	16
valid_sources[0x46]	21848	1			T3	14		T12	17		T6	1
valid_sources[0x47]	31790	1			T3	16		T12	26		T13	3
valid_sources[0x48]	22643	1			T3	11		T5	1		T12	15
valid_sources[0x49]	22903	1			T3	12		T5	6		T12	17
valid_sources[0x4a]	23563	1			T3	13		T5	11		T12	20
valid_sources[0x4b]	23182	1			T2	29		T3	12		T5	9
valid_sources[0x4c]	25880	1			T3	18		T5	27		T12	21
valid_sources[0x4d]	21186	1			T2	6		T3	14		T5	16
valid_sources[0x4e]	20871	1			T3	15		T12	15		T24	2
valid_sources[0x4f]	26170	1			T2	18		T3	16		T11	1
valid_sources[0x50]	25807	1			T3	17		T11	1		T12	16
valid_sources[0x51]	25070	1			T2	2		T3	12		T5	1
valid_sources[0x52]	25246	1			T3	12		T5	7		T12	9
valid_sources[0x53]	26585	1			T3	16		T5	2		T12	13
valid_sources[0x54]	27773	1			T3	6		T5	9		T12	14
valid_sources[0x55]	23535	1			T3	17		T12	10		T44	2
valid_sources[0x56]	24933	1			T3	8		T5	2		T12	9
valid_sources[0x57]	22102	1			T3	12		T5	7		T12	12
valid_sources[0x58]	21353	1			T3	11		T11	1		T12	12
valid_sources[0x59]	21550	1			T3	10		T5	3		T12	21
valid_sources[0x5a]	28665	1			T2	1		T3	4		T12	10
valid_sources[0x5b]	21811	1			T3	11		T5	16		T12	11
valid_sources[0x5c]	39311	1			T3	7		T12	11		T31	2
valid_sources[0x5d]	27771	1			T3	16		T12	34		T24	6
valid_sources[0x5e]	21099	1			T2	18		T3	10		T11	1
valid_sources[0x5f]	25498	1			T3	7		T5	2		T12	16
valid_sources[0x60]	22422	1			T3	8		T5	6		T12	18
valid_sources[0x61]	21385	1			T3	9		T12	13		T31	1
valid_sources[0x62]	24062	1			T3	11		T5	13		T12	15
valid_sources[0x63]	36250	1			T3	16		T5	37		T12	8
valid_sources[0x64]	22425	1			T3	11		T5	4		T12	15
valid_sources[0x65]	30147	1			T3	15		T12	11		T44	2
valid_sources[0x66]	32982	1			T3	16		T11	1		T12	18
valid_sources[0x67]	37868	1			T3	22		T5	8		T12	18
valid_sources[0x68]	22918	1			T3	9		T5	11		T12	14
valid_sources[0x69]	22339	1			T2	5		T3	12		T12	10
valid_sources[0x6a]	114058	1			T3	9		T12	17		T44	9
valid_sources[0x6b]	27121	1			T3	13		T5	4		T12	16
valid_sources[0x6c]	46752	1			T3	9		T5	2		T12	28
valid_sources[0x6d]	22596	1			T3	10		T4	370		T12	17
valid_sources[0x6e]	21718	1			T3	10		T5	6		T12	8
valid_sources[0x6f]	32383	1			T3	14		T5	10		T12	15
valid_sources[0x70]	26200	1			T3	15		T5	6		T12	21
valid_sources[0x71]	23244	1			T3	14		T5	4		T12	6
valid_sources[0x72]	39908	1			T2	5		T3	10		T11	1
valid_sources[0x73]	31533	1			T3	9		T5	4		T12	13
valid_sources[0x74]	29344	1			T2	29		T3	13		T5	2
valid_sources[0x75]	22738	1			T3	16		T5	32		T12	18
valid_sources[0x76]	30309	1			T3	13		T11	1		T5	6
valid_sources[0x77]	21663	1			T2	10		T3	15		T5	11
valid_sources[0x78]	29382	1			T2	15		T3	17		T11	1
valid_sources[0x79]	29760	1			T3	11		T12	15		T13	12
valid_sources[0x7a]	29863	1			T3	12		T5	16		T12	19
valid_sources[0x7b]	22746	1			T3	17		T5	2		T12	10
valid_sources[0x7c]	21777	1			T3	12		T5	11		T12	22
valid_sources[0x7d]	27540	1			T3	13		T12	27		T44	18
valid_sources[0x7e]	22795	1			T3	16		T12	19		T6	4
valid_sources[0x7f]	26553	1			T3	14		T10	3		T12	17
valid_sources[0x80]	26604	1			T3	10		T5	14		T12	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1963097

1

T1

3

T2

56

T3

464

values[0x0]

all_enables

biggest_size

285672

1

T1

5

T2

39

T3

44

values[0x1]

all_enables

biggest_size

224746

1

T1

3

T2

34

T3

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26989	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

514601

1

T3

40

T4

80

T5

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	173964	1			T3	20		T4	40		T5	10
values[0x0]	178559	1			T3	10		T4	20		T5	1
values[0x1]	189067	1			T3	10		T4	20		T5	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14988	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

526602

1

T3

40

T4

80

T5

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2441	1			T91	1		T124	1		T125	1
valid_sources[0x01]	2489	1			T17	1		T124	2		T125	3
valid_sources[0x02]	1769	1			T78	1		T19	1		T125	1
valid_sources[0x03]	1837	1			T34	1		T91	1		T92	1
valid_sources[0x04]	1921	1			T4	3		T10	1		T95	1
valid_sources[0x05]	1833	1			T135	1		T92	1		T124	3
valid_sources[0x06]	1977	1			T4	3		T99	2		T125	1
valid_sources[0x07]	2510	1			T4	1		T95	2		T78	1
valid_sources[0x08]	2619	1			T4	2		T135	2		T19	4
valid_sources[0x09]	2233	1			T34	2		T91	3		T17	2
valid_sources[0x0a]	2392	1			T92	2		T18	2		T124	1
valid_sources[0x0b]	2368	1			T91	1		T17	1		T92	1
valid_sources[0x0c]	2961	1			T10	1		T17	1		T124	2
valid_sources[0x0d]	2255	1			T99	1		T125	1		T132	9
valid_sources[0x0e]	2016	1			T4	2		T92	4		T125	1
valid_sources[0x0f]	2043	1			T125	1		T105	1		T154	1
valid_sources[0x10]	1942	1			T34	1		T17	1		T92	2
valid_sources[0x11]	2067	1			T92	1		T18	2		T19	2
valid_sources[0x12]	1840	1			T4	1		T124	2		T99	4
valid_sources[0x13]	1996	1			T232	2		T312	1		T9	9
valid_sources[0x14]	1655	1			T34	1		T124	1		T126	1
valid_sources[0x15]	2225	1			T91	4		T99	1		T154	1
valid_sources[0x16]	1887	1			T34	1		T18	1		T124	1
valid_sources[0x17]	2223	1			T4	6		T124	1		T99	1
valid_sources[0x18]	2170	1			T91	2		T92	1		T78	1
valid_sources[0x19]	2101	1			T134	1		T99	1		T154	1
valid_sources[0x1a]	2272	1			T204	2		T181	3		T60	1
valid_sources[0x1b]	2354	1			T126	1		T127	2		T175	200
valid_sources[0x1c]	1939	1			T130	1		T99	2		T125	1
valid_sources[0x1d]	2284	1			T135	1		T92	2		T125	2
valid_sources[0x1e]	1780	1			T4	1		T34	1		T92	1
valid_sources[0x1f]	1767	1			T4	1		T91	1		T92	4
valid_sources[0x20]	2489	1			T124	2		T99	3		T125	1
valid_sources[0x21]	2270	1			T17	1		T92	1		T124	3
valid_sources[0x22]	3091	1			T95	2		T92	1		T19	1
valid_sources[0x23]	1879	1			T34	1		T99	1		T125	2
valid_sources[0x24]	2374	1			T92	1		T126	1		T104	3
valid_sources[0x25]	1688	1			T17	3		T92	1		T99	2
valid_sources[0x26]	2093	1			T10	1		T34	1		T135	1
valid_sources[0x27]	2110	1			T17	4		T92	3		T126	1
valid_sources[0x28]	2162	1			T135	1		T17	1		T19	2
valid_sources[0x29]	1716	1			T34	1		T135	1		T92	1
valid_sources[0x2a]	3630	1			T18	1		T19	12		T99	1
valid_sources[0x2b]	1900	1			T95	4		T18	1		T204	1
valid_sources[0x2c]	2014	1			T105	2		T70	1		T14	14
valid_sources[0x2d]	2881	1			T135	1		T95	3		T17	2
valid_sources[0x2e]	2064	1			T99	1		T154	1		T14	42
valid_sources[0x2f]	2362	1			T99	1		T104	1		T127	2
valid_sources[0x30]	1764	1			T34	1		T78	1		T105	1
valid_sources[0x31]	1901	1			T5	1		T92	3		T18	1
valid_sources[0x32]	2218	1			T91	1		T125	2		T154	2
valid_sources[0x33]	2395	1			T4	1		T136	40		T125	1
valid_sources[0x34]	2347	1			T4	2		T99	2		T125	1
valid_sources[0x35]	2961	1			T34	1		T135	1		T124	1
valid_sources[0x36]	1622	1			T134	1		T135	1		T17	1
valid_sources[0x37]	2632	1			T95	5		T19	1		T105	3
valid_sources[0x38]	1796	1			T92	1		T130	1		T127	2
valid_sources[0x39]	1918	1			T135	2		T17	1		T124	2
valid_sources[0x3a]	2483	1			T99	4		T287	5		T70	3
valid_sources[0x3b]	1708	1			T34	1		T91	1		T92	1
valid_sources[0x3c]	2258	1			T124	1		T154	2		T104	1
valid_sources[0x3d]	1989	1			T92	1		T124	2		T99	2
valid_sources[0x3e]	1964	1			T92	1		T19	1		T99	1
valid_sources[0x3f]	1641	1			T92	1		T125	2		T154	3
valid_sources[0x40]	2062	1			T10	1		T17	1		T92	2
valid_sources[0x41]	1998	1			T34	1		T92	2		T78	2
valid_sources[0x42]	2014	1			T105	2		T154	4		T132	1
valid_sources[0x43]	2340	1			T95	1		T92	1		T19	4
valid_sources[0x44]	1891	1			T34	1		T17	2		T124	3
valid_sources[0x45]	1756	1			T10	1		T92	1		T18	1
valid_sources[0x46]	1861	1			T91	1		T18	2		T19	1
valid_sources[0x47]	2358	1			T4	1		T91	1		T105	1
valid_sources[0x48]	2216	1			T34	1		T17	2		T19	4
valid_sources[0x49]	1898	1			T92	2		T78	1		T125	1
valid_sources[0x4a]	2025	1			T4	1		T95	1		T18	1
valid_sources[0x4b]	1782	1			T95	1		T105	1		T126	2
valid_sources[0x4c]	1905	1			T4	1		T10	1		T95	1
valid_sources[0x4d]	2098	1			T91	1		T92	2		T124	2
valid_sources[0x4e]	1875	1			T10	1		T130	2		T19	6
valid_sources[0x4f]	1927	1			T34	1		T92	1		T154	1
valid_sources[0x50]	1753	1			T34	1		T92	1		T18	1
valid_sources[0x51]	2052	1			T95	4		T92	1		T124	2
valid_sources[0x52]	1983	1			T99	1		T154	3		T137	2
valid_sources[0x53]	1876	1			T5	1		T92	2		T18	1
valid_sources[0x54]	1927	1			T92	6		T78	1		T99	1
valid_sources[0x55]	1985	1			T34	1		T91	4		T17	1
valid_sources[0x56]	2036	1			T34	1		T91	1		T17	1
valid_sources[0x57]	1703	1			T95	7		T99	1		T154	1
valid_sources[0x58]	2039	1			T99	1		T105	2		T104	2
valid_sources[0x59]	1933	1			T34	1		T91	4		T95	2
valid_sources[0x5a]	3226	1			T95	2		T99	2		T154	1
valid_sources[0x5b]	1885	1			T91	1		T124	2		T127	1
valid_sources[0x5c]	2015	1			T92	2		T18	1		T78	1
valid_sources[0x5d]	2271	1			T91	2		T95	6		T154	2
valid_sources[0x5e]	2207	1			T17	2		T19	4		T125	2
valid_sources[0x5f]	1790	1			T10	1		T134	1		T92	4
valid_sources[0x60]	1538	1			T4	2		T91	2		T17	1
valid_sources[0x61]	2462	1			T34	1		T92	1		T78	1
valid_sources[0x62]	2420	1			T5	1		T78	1		T124	1
valid_sources[0x63]	2470	1			T4	2		T92	2		T99	4
valid_sources[0x64]	2096	1			T95	3		T92	1		T78	1
valid_sources[0x65]	1725	1			T4	1		T5	2		T92	1
valid_sources[0x66]	2045	1			T4	1		T92	3		T105	4
valid_sources[0x67]	2112	1			T34	1		T105	1		T137	2
valid_sources[0x68]	2245	1			T92	2		T130	1		T124	1
valid_sources[0x69]	2329	1			T130	3		T105	1		T126	3
valid_sources[0x6a]	2142	1			T17	2		T92	1		T130	1
valid_sources[0x6b]	2357	1			T92	2		T105	4		T127	1
valid_sources[0x6c]	2123	1			T99	1		T125	1		T105	2
valid_sources[0x6d]	2143	1			T92	2		T105	2		T104	1
valid_sources[0x6e]	1947	1			T4	3		T92	1		T99	1
valid_sources[0x6f]	2446	1			T124	1		T105	1		T126	1
valid_sources[0x70]	2725	1			T134	1		T95	1		T125	1
valid_sources[0x71]	2323	1			T34	1		T124	1		T99	2
valid_sources[0x72]	1810	1			T91	1		T95	2		T17	1
valid_sources[0x73]	1823	1			T92	1		T18	2		T99	1
valid_sources[0x74]	2028	1			T134	1		T17	4		T78	1
valid_sources[0x75]	1953	1			T34	1		T124	1		T126	1
valid_sources[0x76]	2146	1			T4	1		T34	1		T95	2
valid_sources[0x77]	2575	1			T5	1		T92	1		T154	1
valid_sources[0x78]	2391	1			T17	1		T19	1		T125	2
valid_sources[0x79]	2592	1			T91	2		T105	1		T154	3
valid_sources[0x7a]	2134	1			T10	1		T34	2		T18	8
valid_sources[0x7b]	1941	1			T4	3		T34	1		T92	3
valid_sources[0x7c]	2573	1			T95	3		T17	2		T92	3
valid_sources[0x7d]	2166	1			T17	1		T92	3		T130	3
valid_sources[0x7e]	2574	1			T91	2		T95	2		T92	2
valid_sources[0x7f]	2007	1			T17	1		T125	1		T132	7
valid_sources[0x80]	1795	1			T34	1		T17	2		T18	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

160097

1

T3

20

T4

40

T5

10

values[0x0]

all_enables

biggest_size

176970

1

T3

10

T4

20

T5

1

values[0x1]

all_enables

biggest_size

177534

1

T3

10

T4

20

T5

9