Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5015602

1

T1

8

T2

412

T3

2714

full_word

2520683

1

T1

11

T2

129

T3

529

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7535955	1			T1	19		T2	541		T3	3243
auto[TlIntgErrCmd]	105	1			T300	7		T301	6		T302	5
auto[TlIntgErrData]	120	1			T300	7		T301	11		T302	1
auto[TlIntgErrBoth]	105	1			T300	6		T301	3		T302	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5689149

1

T1

4

T2

362

T3

3093

auto[1]

1847136

1

T1

15

T2

179

T3

150

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3720131	1			T1	1		T2	306		T3	2629
auto[TlIntgErrNone]	partial	auto[1]	1295173	1			T1	7		T2	106		T3	85
auto[TlIntgErrNone]	full_word	auto[0]	1968866	1			T1	3		T2	56		T3	464
auto[TlIntgErrNone]	full_word	auto[1]	551785	1			T1	8		T2	73		T3	65
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T300	2		T301	3		T302	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T300	5		T301	3		T302	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T404	1		T411	1		T412	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T302	1		T413	1		T414	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T300	5		T301	7		T408	1
auto[TlIntgErrData]	partial	auto[1]	52	1			T300	2		T301	4		T302	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T415	1		T409	1		T411	2
auto[TlIntgErrData]	full_word	auto[1]	3	1			T405	2		T311	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T300	3		T301	3		T302	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T300	2		T408	1		T416	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T300	1		T416	1		T311	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T302	1		T416	1		T405	1