Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4445529	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2446940

1

T1

6

T2

74

T3

221

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5804617	1			T1	4		T2	566		T3	454
values[0x0]	512637	1			T1	9		T2	13		T3	134
values[0x1]	575215	1			T1	6		T2	12		T3	123

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3269270	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3623199

1

T1

7

T2

241

T3

346

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30444	1			T10	1		T4	2		T13	1
valid_sources[0x01]	34897	1			T3	1		T4	6		T14	5
valid_sources[0x02]	28975	1			T3	4		T4	6		T13	1
valid_sources[0x03]	21107	1			T4	5		T14	2		T95	22
valid_sources[0x04]	29643	1			T4	3		T13	8		T5	1
valid_sources[0x05]	40734	1			T3	1		T4	2		T13	6
valid_sources[0x06]	22579	1			T3	4		T4	1		T13	2
valid_sources[0x07]	20883	1			T2	17		T3	5		T4	6
valid_sources[0x08]	24217	1			T2	18		T3	10		T4	2
valid_sources[0x09]	45269	1			T3	4		T4	2		T12	1
valid_sources[0x0a]	21384	1			T4	4		T13	6		T5	2
valid_sources[0x0b]	21463	1			T3	1		T4	6		T14	3
valid_sources[0x0c]	20585	1			T3	4		T4	5		T14	2
valid_sources[0x0d]	22847	1			T3	2		T4	1		T13	1
valid_sources[0x0e]	21612	1			T10	1		T4	1		T14	3
valid_sources[0x0f]	24370	1			T4	6		T13	7		T14	2
valid_sources[0x10]	42718	1			T3	10		T4	5		T13	1
valid_sources[0x11]	24880	1			T3	6		T4	5		T13	2
valid_sources[0x12]	25311	1			T1	1		T3	8		T4	5
valid_sources[0x13]	29124	1			T4	3		T14	1		T5	3
valid_sources[0x14]	23241	1			T3	12		T10	1		T4	4
valid_sources[0x15]	40982	1			T3	8		T10	1		T4	3
valid_sources[0x16]	21545	1			T1	3		T3	14		T4	5
valid_sources[0x17]	21598	1			T3	19		T4	9		T13	3
valid_sources[0x18]	21295	1			T4	4		T13	1		T5	4
valid_sources[0x19]	28865	1			T2	73		T3	7		T4	4
valid_sources[0x1a]	21499	1			T2	10		T3	4		T13	1
valid_sources[0x1b]	31419	1			T4	3		T13	3		T14	1
valid_sources[0x1c]	26055	1			T3	4		T4	4		T13	7
valid_sources[0x1d]	23882	1			T3	5		T4	2		T14	1
valid_sources[0x1e]	20435	1			T3	8		T4	3		T12	3
valid_sources[0x1f]	34977	1			T4	3		T13	5		T14	3
valid_sources[0x20]	21707	1			T4	5		T13	1		T14	1
valid_sources[0x21]	24238	1			T4	1		T13	4		T5	8
valid_sources[0x22]	21638	1			T3	4		T10	1		T4	3
valid_sources[0x23]	32543	1			T4	5		T5	1		T95	19
valid_sources[0x24]	22741	1			T3	10		T4	8		T13	2
valid_sources[0x25]	27643	1			T3	6		T4	3		T13	2
valid_sources[0x26]	23402	1			T3	3		T10	1		T4	3
valid_sources[0x27]	28073	1			T3	2		T10	1		T4	4
valid_sources[0x28]	22205	1			T4	3		T13	5		T14	2
valid_sources[0x29]	25107	1			T4	2		T14	2		T5	2
valid_sources[0x2a]	20043	1			T4	6		T13	3		T5	3
valid_sources[0x2b]	23489	1			T3	1		T4	3		T14	4
valid_sources[0x2c]	27699	1			T3	1		T4	3		T5	4
valid_sources[0x2d]	29332	1			T4	6		T13	4		T95	4
valid_sources[0x2e]	20869	1			T10	1		T4	1		T5	11
valid_sources[0x2f]	20553	1			T3	2		T4	3		T14	2
valid_sources[0x30]	20436	1			T10	2		T4	4		T5	4
valid_sources[0x31]	24317	1			T4	1		T14	3		T34	6
valid_sources[0x32]	38529	1			T4	3		T5	3		T95	28
valid_sources[0x33]	27529	1			T3	10		T10	1		T4	3
valid_sources[0x34]	29894	1			T4	7		T13	4		T14	2
valid_sources[0x35]	21411	1			T3	3		T10	1		T4	3
valid_sources[0x36]	21811	1			T3	2		T4	4		T14	1
valid_sources[0x37]	20331	1			T3	6		T4	2		T14	5
valid_sources[0x38]	22342	1			T3	1		T10	1		T14	2
valid_sources[0x39]	21481	1			T3	1		T4	1		T14	1
valid_sources[0x3a]	31097	1			T10	2		T4	6		T12	3
valid_sources[0x3b]	24463	1			T4	4		T13	3		T14	4
valid_sources[0x3c]	27496	1			T10	1		T4	5		T14	2
valid_sources[0x3d]	28345	1			T3	7		T4	3		T14	3
valid_sources[0x3e]	20819	1			T3	4		T4	3		T12	7
valid_sources[0x3f]	24429	1			T3	4		T4	3		T13	4
valid_sources[0x40]	24928	1			T4	3		T13	2		T14	3
valid_sources[0x41]	22525	1			T10	1		T4	2		T5	2
valid_sources[0x42]	22392	1			T3	3		T4	2		T14	1
valid_sources[0x43]	20743	1			T1	5		T14	1		T5	10
valid_sources[0x44]	24272	1			T3	1		T4	5		T13	1
valid_sources[0x45]	62823	1			T3	4		T6	943		T4	3
valid_sources[0x46]	28206	1			T4	3		T14	3		T34	10
valid_sources[0x47]	44682	1			T3	6		T10	2		T4	6
valid_sources[0x48]	25841	1			T3	2		T4	5		T14	5
valid_sources[0x49]	22539	1			T3	10		T4	2		T12	10
valid_sources[0x4a]	37218	1			T10	3		T4	2		T14	1
valid_sources[0x4b]	21145	1			T4	2		T13	4		T14	1
valid_sources[0x4c]	23465	1			T3	5		T4	4		T12	1
valid_sources[0x4d]	33789	1			T2	3		T4	4		T14	1
valid_sources[0x4e]	21846	1			T4	4		T5	3		T95	4
valid_sources[0x4f]	34967	1			T10	1		T4	5		T13	7
valid_sources[0x50]	21796	1			T4	4		T13	2		T14	1
valid_sources[0x51]	20915	1			T3	1		T10	1		T4	4
valid_sources[0x52]	23872	1			T3	5		T4	2		T5	3
valid_sources[0x53]	20661	1			T10	1		T4	2		T13	4
valid_sources[0x54]	36200	1			T4	3		T13	2		T95	2
valid_sources[0x55]	21631	1			T3	8		T10	1		T4	3
valid_sources[0x56]	28428	1			T3	2		T4	2		T13	3
valid_sources[0x57]	21210	1			T3	11		T10	1		T4	5
valid_sources[0x58]	23819	1			T3	2		T4	4		T13	3
valid_sources[0x59]	29860	1			T13	1		T5	5		T95	16
valid_sources[0x5a]	20780	1			T3	4		T4	3		T13	1
valid_sources[0x5b]	25074	1			T3	2		T4	7		T14	1
valid_sources[0x5c]	23083	1			T2	8		T3	2		T4	2
valid_sources[0x5d]	25412	1			T2	10		T4	4		T14	3
valid_sources[0x5e]	27800	1			T3	1		T4	2		T12	17
valid_sources[0x5f]	22114	1			T3	6		T4	2		T14	3
valid_sources[0x60]	20181	1			T3	2		T4	5		T14	2
valid_sources[0x61]	23678	1			T3	1		T4	5		T13	2
valid_sources[0x62]	37654	1			T3	3		T4	1		T13	10
valid_sources[0x63]	21842	1			T4	2		T13	8		T14	1
valid_sources[0x64]	20301	1			T3	1		T4	3		T14	1
valid_sources[0x65]	20899	1			T3	1		T4	4		T13	6
valid_sources[0x66]	26164	1			T3	1		T4	8		T13	6
valid_sources[0x67]	26728	1			T3	9		T4	6		T14	2
valid_sources[0x68]	23093	1			T2	83		T10	3		T4	3
valid_sources[0x69]	23665	1			T10	1		T4	3		T14	1
valid_sources[0x6a]	22551	1			T3	2		T4	2		T11	1175
valid_sources[0x6b]	28230	1			T3	3		T4	4		T13	6
valid_sources[0x6c]	20377	1			T4	1		T14	3		T5	3
valid_sources[0x6d]	35173	1			T3	2		T4	4		T14	3
valid_sources[0x6e]	35718	1			T4	3		T13	5		T14	2
valid_sources[0x6f]	28970	1			T2	11		T3	5		T4	3
valid_sources[0x70]	25227	1			T3	6		T4	6		T13	1
valid_sources[0x71]	21095	1			T3	3		T14	2		T5	5
valid_sources[0x72]	22611	1			T3	1		T10	1		T4	3
valid_sources[0x73]	20010	1			T3	4		T4	5		T14	2
valid_sources[0x74]	20246	1			T3	5		T4	2		T13	1
valid_sources[0x75]	25265	1			T3	5		T4	3		T5	4
valid_sources[0x76]	49865	1			T4	5		T13	2		T5	4
valid_sources[0x77]	22741	1			T4	2		T14	3		T5	3
valid_sources[0x78]	27995	1			T3	11		T4	2		T14	5
valid_sources[0x79]	22306	1			T3	2		T10	1		T4	3
valid_sources[0x7a]	24811	1			T10	1		T4	7		T13	3
valid_sources[0x7b]	24865	1			T1	2		T3	16		T4	1
valid_sources[0x7c]	34294	1			T4	7		T13	4		T14	1
valid_sources[0x7d]	24032	1			T3	3		T4	5		T12	2
valid_sources[0x7e]	24001	1			T3	17		T4	2		T13	5
valid_sources[0x7f]	21727	1			T3	1		T4	4		T13	8
valid_sources[0x80]	21634	1			T4	4		T13	2		T14	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1931501

1

T1

2

T2

66

T3

118

values[0x0]

all_enables

biggest_size

289255

1

T1

3

T2

4

T3

62

values[0x1]

all_enables

biggest_size

226184

1

T1

1

T2

4

T3

41

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26022	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

523342

1

T2

20

T6

220

T4

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	174500	1			T2	10		T6	110		T4	10
values[0x0]	182229	1			T2	4		T6	50		T4	3
values[0x1]	192635	1			T2	6		T6	60		T4	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14175	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

535189

1

T2

20

T6

220

T4

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1845	1			T90	1		T124	2		T96	1
valid_sources[0x01]	2905	1			T166	1		T184	17		T121	1
valid_sources[0x02]	2439	1			T35	1		T121	2		T481	1
valid_sources[0x03]	2346	1			T14	16		T34	2		T137	1
valid_sources[0x04]	2386	1			T34	1		T89	2		T117	1
valid_sources[0x05]	2107	1			T2	3		T166	1		T181	2
valid_sources[0x06]	2068	1			T4	20		T95	1		T35	1
valid_sources[0x07]	1997	1			T8	1		T123	1		T130	1
valid_sources[0x08]	2087	1			T13	5		T35	1		T119	1
valid_sources[0x09]	1757	1			T93	1		T115	1		T121	4
valid_sources[0x0a]	2018	1			T34	1		T36	1		T18	2
valid_sources[0x0b]	1665	1			T122	1		T123	2		T124	2
valid_sources[0x0c]	1987	1			T35	1		T89	2		T119	1
valid_sources[0x0d]	2199	1			T36	1		T143	1		T181	1
valid_sources[0x0e]	1919	1			T95	1		T34	1		T36	1
valid_sources[0x0f]	2430	1			T36	1		T180	1		T90	1
valid_sources[0x10]	2306	1			T93	4		T36	1		T166	1
valid_sources[0x11]	2085	1			T34	1		T20	1		T166	1
valid_sources[0x12]	2098	1			T128	1		T180	5		T278	1
valid_sources[0x13]	1875	1			T34	2		T89	6		T121	1
valid_sources[0x14]	3113	1			T36	2		T121	1		T130	1
valid_sources[0x15]	1840	1			T36	1		T166	2		T123	1
valid_sources[0x16]	1999	1			T7	2		T166	1		T121	3
valid_sources[0x17]	3232	1			T34	1		T93	5		T128	3
valid_sources[0x18]	1834	1			T95	1		T36	1		T115	1
valid_sources[0x19]	2455	1			T89	10		T116	3		T122	3
valid_sources[0x1a]	2040	1			T35	1		T119	1		T166	7
valid_sources[0x1b]	2294	1			T137	1		T92	160		T126	1
valid_sources[0x1c]	1785	1			T95	1		T35	1		T7	1
valid_sources[0x1d]	2015	1			T34	1		T129	6		T128	1
valid_sources[0x1e]	1786	1			T36	1		T90	1		T122	5
valid_sources[0x1f]	2131	1			T128	1		T119	1		T123	1
valid_sources[0x20]	1963	1			T35	1		T128	2		T119	1
valid_sources[0x21]	2104	1			T35	1		T7	1		T9	1
valid_sources[0x22]	2121	1			T34	1		T7	5		T90	1
valid_sources[0x23]	2336	1			T95	9		T8	1		T89	5
valid_sources[0x24]	1920	1			T34	1		T128	1		T166	1
valid_sources[0x25]	2098	1			T34	1		T137	1		T120	2
valid_sources[0x26]	1975	1			T128	1		T22	2		T18	2
valid_sources[0x27]	2383	1			T115	1		T183	1		T121	2
valid_sources[0x28]	1776	1			T35	1		T36	1		T120	2
valid_sources[0x29]	1877	1			T13	4		T117	1		T18	3
valid_sources[0x2a]	2409	1			T34	1		T166	4		T123	1
valid_sources[0x2b]	1966	1			T128	1		T116	6		T121	1
valid_sources[0x2c]	1971	1			T34	1		T129	12		T128	1
valid_sources[0x2d]	2332	1			T93	1		T90	3		T122	1
valid_sources[0x2e]	2269	1			T35	1		T36	1		T120	2
valid_sources[0x2f]	2086	1			T93	2		T36	1		T117	1
valid_sources[0x30]	1689	1			T135	20		T20	10		T121	1
valid_sources[0x31]	1682	1			T36	2		T166	5		T123	1
valid_sources[0x32]	2177	1			T166	1		T121	1		T123	2
valid_sources[0x33]	2304	1			T14	2		T34	1		T20	7
valid_sources[0x34]	1795	1			T137	1		T126	1		T36	1
valid_sources[0x35]	2086	1			T35	1		T36	1		T115	1
valid_sources[0x36]	2119	1			T2	2		T36	1		T115	1
valid_sources[0x37]	3070	1			T89	1		T119	1		T22	1
valid_sources[0x38]	2053	1			T129	9		T89	2		T166	2
valid_sources[0x39]	1828	1			T34	1		T115	1		T166	1
valid_sources[0x3a]	1847	1			T95	2		T128	1		T36	1
valid_sources[0x3b]	2225	1			T121	1		T181	1		T87	1
valid_sources[0x3c]	1867	1			T2	3		T126	1		T166	3
valid_sources[0x3d]	2348	1			T35	1		T93	2		T115	1
valid_sources[0x3e]	1810	1			T34	1		T36	1		T90	1
valid_sources[0x3f]	1953	1			T36	1		T121	1		T123	1
valid_sources[0x40]	1918	1			T128	1		T36	1		T115	2
valid_sources[0x41]	1948	1			T20	2		T128	1		T166	4
valid_sources[0x42]	2454	1			T126	1		T180	1		T121	2
valid_sources[0x43]	2712	1			T35	2		T22	1		T166	2
valid_sources[0x44]	1899	1			T121	1		T90	2		T122	4
valid_sources[0x45]	2175	1			T34	1		T36	1		T89	2
valid_sources[0x46]	2236	1			T95	2		T126	1		T166	2
valid_sources[0x47]	1882	1			T34	1		T35	1		T36	1
valid_sources[0x48]	2901	1			T34	1		T18	1		T130	1
valid_sources[0x49]	2430	1			T36	2		T89	3		T180	1
valid_sources[0x4a]	2398	1			T14	4		T35	2		T7	2
valid_sources[0x4b]	1939	1			T95	3		T115	1		T119	1
valid_sources[0x4c]	2004	1			T93	5		T124	2		T131	2
valid_sources[0x4d]	2091	1			T35	1		T36	1		T121	1
valid_sources[0x4e]	2400	1			T34	1		T115	1		T22	1
valid_sources[0x4f]	2226	1			T34	2		T93	1		T115	1
valid_sources[0x50]	1791	1			T35	1		T20	1		T89	10
valid_sources[0x51]	2112	1			T34	1		T93	1		T128	1
valid_sources[0x52]	1824	1			T34	2		T119	1		T22	1
valid_sources[0x53]	2596	1			T6	220		T34	1		T122	1
valid_sources[0x54]	2125	1			T128	1		T119	1		T124	1
valid_sources[0x55]	2539	1			T22	1		T122	1		T123	1
valid_sources[0x56]	2619	1			T34	1		T36	1		T89	1
valid_sources[0x57]	2367	1			T34	1		T93	1		T115	1
valid_sources[0x58]	2330	1			T34	1		T93	4		T18	2
valid_sources[0x59]	1841	1			T34	1		T93	7		T126	3
valid_sources[0x5a]	2091	1			T93	2		T89	1		T122	2
valid_sources[0x5b]	1736	1			T34	1		T128	1		T36	2
valid_sources[0x5c]	1644	1			T34	1		T166	5		T90	1
valid_sources[0x5d]	2035	1			T34	2		T137	1		T93	2
valid_sources[0x5e]	2573	1			T34	1		T90	1		T122	2
valid_sources[0x5f]	2219	1			T126	2		T120	1		T122	1
valid_sources[0x60]	2182	1			T128	1		T118	2		T166	6
valid_sources[0x61]	1852	1			T137	1		T36	1		T89	1
valid_sources[0x62]	1803	1			T22	1		T90	1		T122	2
valid_sources[0x63]	1988	1			T14	3		T126	1		T102	59
valid_sources[0x64]	2545	1			T34	1		T20	2		T36	1
valid_sources[0x65]	2027	1			T34	1		T126	2		T89	10
valid_sources[0x66]	1749	1			T93	4		T123	1		T96	1
valid_sources[0x67]	1910	1			T93	1		T180	4		T121	3
valid_sources[0x68]	1899	1			T93	2		T180	2		T121	2
valid_sources[0x69]	2099	1			T34	3		T116	3		T120	2
valid_sources[0x6a]	2031	1			T34	1		T124	2		T125	1
valid_sources[0x6b]	2170	1			T22	1		T18	4		T90	1
valid_sources[0x6c]	2475	1			T34	3		T93	1		T121	2
valid_sources[0x6d]	1979	1			T34	2		T137	1		T36	1
valid_sources[0x6e]	2300	1			T35	1		T128	1		T36	3
valid_sources[0x6f]	1967	1			T35	1		T7	2		T22	1
valid_sources[0x70]	2492	1			T93	8		T115	1		T22	1
valid_sources[0x71]	2085	1			T34	2		T8	3		T36	1
valid_sources[0x72]	2012	1			T34	1		T35	1		T129	2
valid_sources[0x73]	2195	1			T34	2		T119	1		T120	1
valid_sources[0x74]	2200	1			T126	1		T180	7		T121	2
valid_sources[0x75]	2029	1			T34	1		T93	1		T128	1
valid_sources[0x76]	2377	1			T89	6		T121	1		T122	2
valid_sources[0x77]	2034	1			T93	3		T240	20		T121	6
valid_sources[0x78]	2318	1			T95	10		T34	1		T93	2
valid_sources[0x79]	1762	1			T34	1		T126	1		T89	1
valid_sources[0x7a]	1664	1			T14	9		T34	1		T36	1
valid_sources[0x7b]	3117	1			T34	2		T126	1		T9	1
valid_sources[0x7c]	1860	1			T93	5		T124	2		T130	2
valid_sources[0x7d]	2145	1			T34	1		T128	1		T117	1
valid_sources[0x7e]	2418	1			T128	1		T36	1		T89	8
valid_sources[0x7f]	2703	1			T95	3		T36	1		T183	1
valid_sources[0x80]	2397	1			T93	1		T36	1		T166	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

161545

1

T2

10

T6

110

T4

10

values[0x0]

all_enables

biggest_size

180808

1

T2

4

T6

50

T4

3

values[0x1]

all_enables

biggest_size

180989

1

T2

6

T6

60

T4

7