Line Coverage for Instance : tb.dut.u_scrmbl_mtx
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 192 | 144 | 75.00 |
| CONT_ASSIGN | 62 | 0 | 0 | |
| CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 112 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 126 | 0 | 0 | |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 148 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 0 | 0 | |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 150 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 0 | 0 | |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 151 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 0 | 0 | |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 160 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 0 | 0 | |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 161 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 0 | 0 | |
| CONT_ASSIGN | 163 | 0 | 0 | |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 0 | 0 | |
| CONT_ASSIGN | 163 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 0 | 0 | |
| CONT_ASSIGN | 163 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 163 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 164 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 164 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| ALWAYS | 191 | 3 | 3 | 100.00 |
61 logic unused_req_chk;
62 unreachable assign unused_req_chk = req_chk_i;
63
64 `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
65
66 // this case is basically just a bypass
67 if (N == 1) begin : gen_degenerate_case
68
69 assign valid_o = req_i[0];
70 assign data_o = data_i[0];
71 assign gnt_o[0] = valid_o & ready_i;
72 assign idx_o = '0;
73
74 end else begin : gen_normal_case
75
76 // align to powers of 2 for simplicity
77 // a full binary tree with N levels has 2**N + 2**N-1 nodes
78 logic [2**(IdxW+1)-2:0] req_tree;
79 logic [2**(IdxW+1)-2:0] prio_tree;
80 logic [2**(IdxW+1)-2:0] sel_tree;
81 logic [2**(IdxW+1)-2:0] mask_tree;
82 logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree;
83 logic [2**(IdxW+1)-2:0][DW-1:0] data_tree;
84 logic [N-1:0] prio_mask_d, prio_mask_q;
85
86 for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree
87 //
88 // level+1 C0 C1 <- "Base1" points to the first node on "level+1",
89 // \ / these nodes are the children of the nodes one level below
90 // level Pa <- "Base0", points to the first node on "level",
91 // these nodes are the parents of the nodes one level above
92 //
93 // hence we have the following indices for the Pa, C0, C1 nodes:
94 // Pa = 2**level - 1 + offset = Base0 + offset
95 // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset
96 // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1
97 //
98 localparam int Base0 = (2**level)-1;
99 localparam int Base1 = (2**(level+1))-1;
100
101 for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level
102 localparam int Pa = Base0 + offset;
103 localparam int C0 = Base1 + 2*offset;
104 localparam int C1 = Base1 + 2*offset + 1;
105
106 // this assigns the gated interrupt source signals, their
107 // corresponding IDs and priorities to the tree leafs
108 if (level == IdxW) begin : gen_leafs
109 if (offset < N) begin : gen_assign
110 // forward path (requests and data)
111 // all requests inputs are assigned to the request tree
112 7/14 ==> assign req_tree[Pa] = req_i[offset];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
113 // we basically split the incoming request vector into two halves with the following
114 // priority assignment. the prio_mask_q register contains a prefix sum that has been
115 // computed using the last winning index, and hence masks out all requests at offsets
116 // lower or equal the previously granted index. hence, all higher indices are considered
117 // first in the arbitration tree nodes below, before considering the lower indices.
118 14/14 assign prio_tree[Pa] = req_i[offset] & prio_mask_q[offset];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
119 // input for the index muxes (used to compute the winner index)
120 assign idx_tree[Pa] = offset;
121 // input for the data muxes
122 7/14 ==> assign data_tree[Pa] = data_i[offset];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
123
124 // backward path (grants and prefix sum)
125 // grant if selected, ready and request asserted
126 unreachable assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i;
127 // only update mask if there is a valid request
128 14/14 assign prio_mask_d[offset] = (|req_i) ?
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
129 mask_tree[Pa] | sel_tree[Pa] & ~ready_i :
130 prio_mask_q[offset];
131 end else begin : gen_tie_off
132 // forward path
133 assign req_tree[Pa] = '0;
134 assign prio_tree[Pa] = '0;
135 assign idx_tree[Pa] = '0;
136 assign data_tree[Pa] = '0;
137 logic unused_sigs;
138 2/2 assign unused_sigs = ^{mask_tree[Pa],
Tests: T1 T2 T3 | T1 T2 T3
139 sel_tree[Pa]};
140 end
141 // this creates the node assignments
142 end else begin : gen_nodes
143 // local helper variable
144 logic sel;
145
146 // forward path (requests and data)
147 // each node looks at its two children, and selects the one with higher priority
148 11/14(1 unreachable) ==> assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
149 // propagate requests
150 11/14(1 unreachable) ==> assign req_tree[Pa] = req_tree[C0] | req_tree[C1];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
151 11/14(1 unreachable) ==> assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
152 // data and index muxes
153 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
154 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
155 8/15 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
156 11/15 ==> assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
157
158 // backward path (grants and prefix sum)
159 // this propagates the selction index back and computes a hot one mask
160 11/14(1 unreachable) ==> assign sel_tree[C0] = sel_tree[Pa] & ~sel;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
161 12/15 ==> assign sel_tree[C1] = sel_tree[Pa] & sel;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
162 // this performs a prefix sum for masking the input requests in the next cycle
163 8/11(4 unreachable) ==> assign mask_tree[C0] = mask_tree[Pa];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
164 10/15 ==> assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
165 end
166 end : gen_level
167 end : gen_tree
168
169 // the results can be found at the tree root
170 if (EnDataPort) begin : gen_data_port
171 1/1 assign data_o = data_tree[0];
Tests: T1 T2 T3
172 end else begin : gen_no_dataport
173 logic [DW-1:0] unused_data;
174 assign unused_data = data_tree[0];
175 assign data_o = '1;
176 end
177
178 // This index is unused.
179 logic unused_prio_tree;
180 1/1 assign unused_prio_tree = prio_tree[0];
Tests: T1 T2 T3
181
182 1/1 assign idx_o = idx_tree[0];
Tests: T1 T2 T3
183 1/1 assign valid_o = req_tree[0];
Tests: T1 T2 T3
184
185 // the select tree computes a hot one signal that indicates which request is currently selected
186 assign sel_tree[0] = 1'b1;
187 // the mask tree is basically a prefix sum of the hot one select signal computed above
188 assign mask_tree[0] = 1'b0;
189
190 always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg
191 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
192 1/1 prio_mask_q <= '0;
Tests: T1 T2 T3
193 end else begin
194 1/1 prio_mask_q <= prio_mask_d;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_scrmbl_mtx
| Total | Covered | Percent |
|---|
| Conditions | 362 | 360 | 99.45 |
| Logical | 362 | 360 | 99.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Branch Coverage for Instance : tb.dut.u_scrmbl_mtx
| Line No. | Total | Covered | Percent |
| Branches |
|
74 |
74 |
100.00 |
| TERNARY |
155 |
2 |
2 |
100.00 |
| TERNARY |
156 |
2 |
2 |
100.00 |
| TERNARY |
155 |
1 |
1 |
100.00 |
| TERNARY |
156 |
1 |
1 |
100.00 |
| TERNARY |
155 |
2 |
2 |
100.00 |
| TERNARY |
156 |
2 |
2 |
100.00 |
| TERNARY |
155 |
1 |
1 |
100.00 |
| TERNARY |
156 |
1 |
1 |
100.00 |
| TERNARY |
155 |
2 |
2 |
100.00 |
| TERNARY |
156 |
2 |
2 |
100.00 |
| TERNARY |
155 |
2 |
2 |
100.00 |
| TERNARY |
156 |
2 |
2 |
100.00 |
| TERNARY |
155 |
2 |
2 |
100.00 |
| TERNARY |
156 |
2 |
2 |
100.00 |
| TERNARY |
155 |
1 |
1 |
100.00 |
| TERNARY |
156 |
1 |
1 |
100.00 |
| TERNARY |
155 |
1 |
1 |
100.00 |
| TERNARY |
156 |
1 |
1 |
100.00 |
| TERNARY |
155 |
1 |
1 |
100.00 |
| TERNARY |
156 |
1 |
1 |
100.00 |
| TERNARY |
155 |
2 |
2 |
100.00 |
| TERNARY |
156 |
2 |
2 |
100.00 |
| TERNARY |
155 |
2 |
2 |
100.00 |
| TERNARY |
156 |
2 |
2 |
100.00 |
| TERNARY |
155 |
1 |
1 |
100.00 |
| TERNARY |
156 |
1 |
1 |
100.00 |
| TERNARY |
155 |
1 |
1 |
100.00 |
| TERNARY |
156 |
1 |
1 |
100.00 |
| TERNARY |
155 |
1 |
1 |
100.00 |
| TERNARY |
156 |
1 |
1 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| TERNARY |
128 |
2 |
2 |
100.00 |
| IF |
191 |
2 |
2 |
100.00 |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T4,T5 |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T4,T5 |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR |
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==> (Excluded)
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Covered |
T1,T2,T3 |
|
| 0 |
Excluded |
|
vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR |
155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
-1-
==>
==> (Unreachable)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
-1-
==>
==> (Unreachable)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
128 assign prio_mask_d[offset] = (|req_i) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
191 if (!rst_ni) begin
-1-
192 prio_mask_q <= '0;
==>
193 end else begin
194 prio_mask_q <= prio_mask_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_scrmbl_mtx
Assertion Details
CheckHotOne_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
79962216 |
0 |
0 |
| T1 |
5511 |
5429 |
0 |
0 |
| T2 |
12159 |
11922 |
0 |
0 |
| T3 |
13200 |
12922 |
0 |
0 |
| T4 |
24822 |
24547 |
0 |
0 |
| T6 |
7902 |
7656 |
0 |
0 |
| T10 |
6437 |
6378 |
0 |
0 |
| T11 |
10342 |
10017 |
0 |
0 |
| T12 |
7144 |
7084 |
0 |
0 |
| T13 |
13944 |
13782 |
0 |
0 |
| T14 |
9797 |
9565 |
0 |
0 |
CheckNGreaterZero_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1123 |
1123 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
0 |
0 |
0 |
GntImpliesValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
0 |
0 |
0 |
GrantKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
79962216 |
0 |
0 |
| T1 |
5511 |
5429 |
0 |
0 |
| T2 |
12159 |
11922 |
0 |
0 |
| T3 |
13200 |
12922 |
0 |
0 |
| T4 |
24822 |
24547 |
0 |
0 |
| T6 |
7902 |
7656 |
0 |
0 |
| T10 |
6437 |
6378 |
0 |
0 |
| T11 |
10342 |
10017 |
0 |
0 |
| T12 |
7144 |
7084 |
0 |
0 |
| T13 |
13944 |
13782 |
0 |
0 |
| T14 |
9797 |
9565 |
0 |
0 |
IdxKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
79962216 |
0 |
0 |
| T1 |
5511 |
5429 |
0 |
0 |
| T2 |
12159 |
11922 |
0 |
0 |
| T3 |
13200 |
12922 |
0 |
0 |
| T4 |
24822 |
24547 |
0 |
0 |
| T6 |
7902 |
7656 |
0 |
0 |
| T10 |
6437 |
6378 |
0 |
0 |
| T11 |
10342 |
10017 |
0 |
0 |
| T12 |
7144 |
7084 |
0 |
0 |
| T13 |
13944 |
13782 |
0 |
0 |
| T14 |
9797 |
9565 |
0 |
0 |
IndexIsCorrect_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
0 |
0 |
0 |
LockArbDecision_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
46091276 |
0 |
0 |
| T1 |
5511 |
1833 |
0 |
0 |
| T2 |
12159 |
3175 |
0 |
0 |
| T3 |
13200 |
9914 |
0 |
0 |
| T4 |
24822 |
9593 |
0 |
0 |
| T6 |
7902 |
2596 |
0 |
0 |
| T10 |
6437 |
4063 |
0 |
0 |
| T11 |
10342 |
6882 |
0 |
0 |
| T12 |
7144 |
4769 |
0 |
0 |
| T13 |
13944 |
7819 |
0 |
0 |
| T14 |
9797 |
4786 |
0 |
0 |
ReadyAndValidImplyGrant_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
0 |
0 |
0 |
ReqAndReadyImplyGrant_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
0 |
0 |
0 |
ReqImpliesValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
33870940 |
0 |
0 |
| T1 |
5511 |
3596 |
0 |
0 |
| T2 |
12159 |
8747 |
0 |
0 |
| T3 |
13200 |
3008 |
0 |
0 |
| T4 |
24822 |
14954 |
0 |
0 |
| T6 |
7902 |
5060 |
0 |
0 |
| T10 |
6437 |
2315 |
0 |
0 |
| T11 |
10342 |
3135 |
0 |
0 |
| T12 |
7144 |
2315 |
0 |
0 |
| T13 |
13944 |
5963 |
0 |
0 |
| T14 |
9797 |
4779 |
0 |
0 |
ReqStaysHighUntilGranted0_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
0 |
0 |
0 |
RoundRobin_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
0 |
0 |
1107 |
ValidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
79962216 |
0 |
0 |
| T1 |
5511 |
5429 |
0 |
0 |
| T2 |
12159 |
11922 |
0 |
0 |
| T3 |
13200 |
12922 |
0 |
0 |
| T4 |
24822 |
24547 |
0 |
0 |
| T6 |
7902 |
7656 |
0 |
0 |
| T10 |
6437 |
6378 |
0 |
0 |
| T11 |
10342 |
10017 |
0 |
0 |
| T12 |
7144 |
7084 |
0 |
0 |
| T13 |
13944 |
13782 |
0 |
0 |
| T14 |
9797 |
9565 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
80791054 |
0 |
0 |
0 |