Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.20	94.51	100.00		85.00	95.35	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.54	96.38	100.00	100.00	85.00	94.64	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	94.16	95.24	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	94.16	95.24	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.13	100.00	100.00		95.65	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.98	100.00	100.00	100.00	95.65	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	94.16	95.24	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	86	94.51
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	66	61	92.42
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

137                       // Output partition error state.
138        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
139                     
140                       // This partition cannot do any write accesses, hence we tie this
141                       // constantly off.
142                       assign otp_wdata_o = '0;
143                       // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144                       // calculations and checks. To be on the safe side, the partition filters error responses at this
145                       // point and does not report any integrity errors if integrity is disabled.
146                       otp_err_e otp_err;
147                       if (Info.integrity) begin : gen_integrity
148                         assign otp_cmd_o = prim_otp_pkg::Read;
149                         assign otp_err = otp_err_e'(otp_err_i);
150                       end else begin : gen_no_integrity
151                         assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152                         always_comb begin
153        1/1                if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
           Tests:       T1 T2 T3 
154        1/1                  otp_err = NoError;
           Tests:       T3 T11 T151 
155                           end else begin
156        1/1                  otp_err = otp_err_e'(otp_err_i);
           Tests:       T1 T2 T3 
157                           end
158                         end
159                       end
160                     
161                       `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162                       always_comb begin : p_fsm
163                         // Default assignments
164        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
165                     
166                         // Response to init request
167        1/1              init_done_o = 1'b0;
           Tests:       T1 T2 T3 
168                     
169                         // OTP signals
170        1/1              otp_req_o   = 1'b0;
           Tests:       T1 T2 T3 
171        1/1              otp_addr_sel = DigestAddrSel;
           Tests:       T1 T2 T3 
172                     
173                         // TL-UL signals
174        1/1              tlul_gnt_o      = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              tlul_rvalid_o   = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              tlul_rerror_o   = '0;
           Tests:       T1 T2 T3 
177                     
178                         // Enable for buffered digest register
179        1/1              digest_reg_en = 1'b0;
           Tests:       T1 T2 T3 
180                     
181                         // Error Register
182        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
183        1/1              pending_tlul_error_d = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           ///////////////////////////////////////////////////////////////////
188                           // State right after reset. Wait here until we get a an
189                           // initialization request.
190                           ResetSt: begin
191        1/1                  if (init_req_i) begin
           Tests:       T1 T2 T3 
192                               // If the partition does not have a digest, no initialization is necessary.
193        1/1                    if (Info.sw_digest) begin
           Tests:       T1 T2 T3 
194        1/1                      state_d = InitSt;
           Tests:       T1 T2 T3 
195                               end else begin
196        unreachable              state_d = IdleSt;
197                               end
198                             end
                        MISSING_ELSE
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Initialization reads out the digest only in unbuffered
202                           // partitions. Wait here until the OTP request has been granted.
203                           // And then wait until the OTP word comes back.
204                           InitSt: begin
205        1/1                  otp_req_o = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  if (otp_gnt_i) begin
           Tests:       T1 T2 T3 
207        1/1                    state_d = InitWaitSt;
           Tests:       T1 T2 T3 
208                             end
                   ==>  MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // Wait for OTP response and write to digest buffer register. In
212                           // case an OTP transaction fails, latch the  OTP error code and
213                           // jump to a terminal error state.
214                           InitWaitSt: begin
215        1/1                  if (otp_rvalid_i) begin
           Tests:       T1 T2 T3 
216        1/1                    digest_reg_en = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T1 T2 T3 
218        1/1                      state_d = IdleSt;
           Tests:       T1 T2 T3 
219                                 // At this point the only error that we could have gotten are correctable ECC errors.
220        1/1                      if (otp_err != NoError) begin
           Tests:       T1 T2 T3 
221        excluded                   error_d = MacroEccCorrError;
Exclude Annotation: VC_COV_UNR
222                                 end
                        MISSING_ELSE
223                               end else begin
224        0/1     ==>              state_d = ErrorSt;
225        0/1     ==>              error_d = otp_err;
226                               end
227                             end
                        MISSING_ELSE
228                           end
229                           ///////////////////////////////////////////////////////////////////
230                           // Wait for TL-UL requests coming in.
231                           // Then latch address and go to readout state.
232                           IdleSt: begin
233        1/1                  init_done_o = 1'b1;
           Tests:       T1 T2 T3 
234        1/1                  if (tlul_req_i) begin
           Tests:       T1 T2 T3 
235        1/1                    error_d = NoError; // clear recoverable soft errors.
           Tests:       T3 T6 T4 
236        1/1                    state_d = ReadSt;
           Tests:       T3 T6 T4 
237        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T3 T6 T4 
238                             end
                        MISSING_ELSE
239                           end
240                           ///////////////////////////////////////////////////////////////////
241                           // If the address is out of bounds, or if the partition is
242                           // locked, signal back a bus error. Note that such an error does
243                           // not cause the partition to go into error state. Otherwise if
244                           // these checks pass, an OTP word is requested.
245                           ReadSt: begin
246        1/1                  init_done_o = 1'b1;
           Tests:       T3 T6 T4 
247                             // Double check the address range.
248        1/1                  if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
           Tests:       T3 T6 T4 
249        1/1                    otp_req_o = 1'b1;
           Tests:       T3 T4 T11 
250        1/1                    otp_addr_sel = DataAddrSel;
           Tests:       T3 T4 T11 
251        1/1                    if (otp_gnt_i) begin
           Tests:       T3 T4 T11 
252        1/1                      state_d = ReadWaitSt;
           Tests:       T3 T4 T11 
253                               end
                        MISSING_ELSE
254                             end else begin
255        1/1                    state_d = IdleSt;
           Tests:       T6 T4 T95 
256        1/1                    error_d = AccessError; // Signal this error, but do not go into terminal error state.
           Tests:       T6 T4 T95 
257        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T6 T4 T95 
258        1/1                    tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
           Tests:       T6 T4 T95 
259                             end
260                           end
261                           ///////////////////////////////////////////////////////////////////
262                           // Wait for OTP response and release the TL-UL response. In
263                           // case an OTP transaction fails, latch the OTP error code,
264                           // signal a TL-Ul bus error and jump to a terminal error state.
265                           ReadWaitSt: begin
266        1/1                  init_done_o = 1'b1;
           Tests:       T3 T4 T11 
267        1/1                  if (otp_rvalid_i) begin
           Tests:       T3 T4 T11 
268        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T3 T4 T11 
269        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T3 T4 T11 
270        1/1                      state_d = IdleSt;
           Tests:       T3 T4 T11 
271                                 // At this point the only error that we could have gotten are correctable ECC errors.
272        1/1                      if (otp_err != NoError) begin
           Tests:       T3 T4 T11 
273        excluded                   error_d = MacroEccCorrError;
Exclude Annotation: VC_COV_UNR
274                                 end
                        MISSING_ELSE
275                               end else begin
276        0/1     ==>              state_d = ErrorSt;
277        0/1     ==>              error_d = otp_err;
278                                 // This causes the TL-UL adapter to return a bus error.
279        0/1     ==>              tlul_rerror_o = 2'b11;
280                               end
281                             end
                        MISSING_ELSE
282                           end
283                           ///////////////////////////////////////////////////////////////////
284                           // Terminal Error State. This locks access to the partition.
285                           // Make sure the partition signals an error state if no error
286                           // code has been latched so far.
287                           ErrorSt: begin
288        1/1                  if (error_q == NoError) begin
           Tests:       T3 T6 T11 
289        1/1                    error_d = FsmStateError;
           Tests:       T26 T27 T28 
290                             end
                        MISSING_ELSE
291                     
292                             // Return bus errors if there are pending TL-UL requests.
293        1/1                  if (pending_tlul_error_q) begin
           Tests:       T3 T6 T11 
294        1/1                    tlul_rerror_o = 2'b11;
           Tests:       T6 T34 T7 
295        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T6 T34 T7 
296        1/1                  end else if (tlul_req_i) begin
           Tests:       T3 T6 T11 
297        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T6 T34 T7 
298        1/1                    pending_tlul_error_d = 1'b1;
           Tests:       T6 T34 T7 
299                             end
                        MISSING_ELSE
300                           end
301                           ///////////////////////////////////////////////////////////////////
302                           // We should never get here. If we do (e.g. via a malicious
303                           // glitch), error out immediately.
304                           default: begin
305                             state_d = ErrorSt;
306                             fsm_err_o = 1'b1;
307                           end
308                           ///////////////////////////////////////////////////////////////////
309                         endcase // state_q
310                     
311                         // Unconditionally jump into the terminal error state in case of
312                         // an ECC error or escalation, and lock access to the partition down.
313                         // SEC_CM: PART.FSM.LOCAL_ESC
314        1/1              if (ecc_err) begin
           Tests:       T1 T2 T3 
315        1/1                state_d = ErrorSt;
           Tests:       T187 
316        1/1                if (state_q != ErrorSt) begin
           Tests:       T187 
317        1/1                  error_d = CheckFailError;
           Tests:       T187 
318                           end
                        MISSING_ELSE
319                         end
                        MISSING_ELSE
320                         // SEC_CM: PART.FSM.GLOBAL_ESC
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                state_d = ErrorSt;
           Tests:       T3 T6 T11 
323        1/1                fsm_err_o = 1'b1;
           Tests:       T3 T6 T11 
324        1/1                if (state_q != ErrorSt) begin
           Tests:       T3 T6 T11 
325        1/1                  error_d = FsmStateError;
           Tests:       T3 T6 T11 
326                           end
                        MISSING_ELSE
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       ///////////////////////////////////
331                       // Signals to/from TL-UL Adapter //
332                       ///////////////////////////////////
333                     
334        1/1            assign tlul_addr_d  = tlul_addr_i;
           Tests:       T1 T2 T3 
335                       // Do not forward data in case of an error.
336        1/1            assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
           Tests:       T1 T2 T3 
337                     
338                       if (Info.offset == 0) begin : gen_zero_offset
339        1/1              assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
           Tests:       T1 T2 T3 
340                     
341                       end else begin : gen_nonzero_offset
342                         assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
343                                                     {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344                       end
345                     
346                       // Note that OTP works on halfword (16bit) addresses, hence need to
347                       // shift the addresses appropriately.
348                       logic [OtpByteAddrWidth-1:0] addr_calc;
349        1/1            assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
           Tests:       T1 T2 T3 
350        1/1            assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
           Tests:       T1 T2 T3 
351                     
352                       if (OtpAddrShift > 0) begin : gen_unused
353                         logic unused_bits;
354        1/1              assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
           Tests:       T1 T2 T3 
355                       end
356                     
357                       // Request 32bit except in case of the digest.
358        1/1            assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
           Tests:       T1 T2 T3 
359                                           OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360                                           OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361                     
362                       ////////////////
363                       // Digest Reg //
364                       ////////////////
365                     
366                       if (Info.sw_digest) begin : gen_ecc_reg
367                         // SEC_CM: PART.DATA_REG.INTEGRITY
368                         otp_ctrl_ecc_reg #(
369                           .Width ( ScrmblBlockWidth ),
370                           .Depth ( 1                )
371                         ) u_otp_ctrl_ecc_reg (
372                           .clk_i,
373                           .rst_ni,
374                           .wren_i    ( digest_reg_en ),
375                           .addr_i    ( '0            ),
376                           .wdata_i   ( otp_rdata_i   ),
377                           .rdata_o   (               ),
378                           .data_o    ( digest_o      ),
379                           .ecc_err_o ( ecc_err       )
380                         );
381                       end else begin : gen_no_ecc_reg
382                         logic unused_digest_reg_en;
383                         logic unused_rdata;
384                         assign unused_digest_reg_en = digest_reg_en;
385                         assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386                         assign digest_o = '0;
387                         assign ecc_err = 1'b0;
388                       end
389                     
390                       ////////////////////////
391                       // DAI Access Control //
392                       ////////////////////////
393                     
394                       mubi8_t init_locked;
395        1/1            assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
396                     
397                       // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398                       // Note that the locks are redundantly encoded values.
399                       part_access_t access_pre;
400                       prim_mubi8_sender #(
401                         .AsyncOn(0)
402                       ) u_prim_mubi8_sender_write_lock_pre (
403                         .clk_i,
404                         .rst_ni,
405                         .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406                         .mubi_o(access_pre.write_lock)
407                       );
408                       prim_mubi8_sender #(
409                         .AsyncOn(0)
410                       ) u_prim_mubi8_sender_read_lock_pre (
411                         .clk_i,
412                         .rst_ni,
413                         .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414                         .mubi_o(access_pre.read_lock)
415                       );
416                     
417                       // SEC_CM: PART.MEM.SW_UNWRITABLE
418                       if (Info.write_lock) begin : gen_digest_write_lock
419                         mubi8_t digest_locked;
420        1/1              assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
421                     
422                         // This prevents the synthesis tool from optimizing the multibit signal.
423                         prim_mubi8_sender #(
424                           .AsyncOn(0)
425                         ) u_prim_mubi8_sender_write_lock (
426                           .clk_i,
427                           .rst_ni,
428                           .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429                           .mubi_o(access_o.write_lock)
430                         );
431                     
432                         `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433                       end else begin : gen_no_digest_write_lock
434                         assign access_o.write_lock = access_pre.write_lock;
435                       end
436                     
437                       // SEC_CM: PART.MEM.SW_UNREADABLE
438                       if (Info.read_lock) begin : gen_digest_read_lock
439                         mubi8_t digest_locked;
440                         assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441                     
442                         // This prevents the synthesis tool from optimizing the multibit signal.
443                         prim_mubi8_sender #(
444                           .AsyncOn(0)
445                         ) u_prim_mubi8_sender_read_lock (
446                           .clk_i,
447                           .rst_ni,
448                           .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449                           .mubi_o(access_o.read_lock)
450                         );
451                     
452                         `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453                       end else begin : gen_no_digest_read_lock
454        1/1              assign access_o.read_lock = access_pre.read_lock;
           Tests:       T1 T2 T3 
455                       end
456                     
457                       ///////////////
458                       // Registers //
459                       ///////////////
460                     
461        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1                   `ifdef SIMULATION                                   
461.2                       prim_sparse_fsm_flop #(                           
461.3                         .StateEnumT(state_e),                            
461.4                         .Width($bits(state_e)),                          
461.5                         .ResetValue($bits(state_e)'(ResetSt)),          
461.6                         .EnableAlertTriggerSVA(1), 
461.7                         .CustomForceName("state_q")          
461.8                       ) u_state_regs (                                        
461.9                         .clk_i   ( clk_i   ),                           
461.10                        .rst_ni  ( rst_ni ),                           
461.11                        .state_i ( state_d     ),                           
461.12                        .state_o (         )                            
461.13                      );                                                
461.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
461.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
461.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
461.17                      end else begin                                    
461.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
461.19                      end                                               
461.20                    end  
461.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
461.22                      else begin                                                                           
461.23                        `ifdef UVM                                                                               
461.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
461.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);                                
461.26                  `else                                                                                    
461.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
461.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
461.29                  `endif                                                              
461.30                      end 
461.31                    `else                                               
461.32                      prim_sparse_fsm_flop #(                           
461.33                        .StateEnumT(state_e),                            
461.34                        .Width($bits(state_e)),                          
461.35                        .ResetValue($bits(state_e)'(ResetSt)),          
461.36                        .EnableAlertTriggerSVA(1)  
461.37                      ) u_state_regs (                                        
461.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
461.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
461.40                        .state_i ( state_d     ),                           
461.41                        .state_o ( state_q     )                            
461.42                      );                                                
461.43                    `endif462                     
463                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
465        1/1                error_q              <= NoError;
           Tests:       T1 T2 T3 
466        1/1                tlul_addr_q          <= '0;
           Tests:       T1 T2 T3 
467        1/1                pending_tlul_error_q <= 1'b0;
           Tests:       T1 T2 T3 
468                         end else begin
469        1/1                error_q              <= error_d;
           Tests:       T1 T2 T3 
470        1/1                pending_tlul_error_q <= pending_tlul_error_d;
           Tests:       T1 T2 T3 
471        1/1                if (tlul_gnt_o) begin
           Tests:       T1 T2 T3 
472        1/1                  tlul_addr_q <= tlul_addr_d;
           Tests:       T3 T6 T4 
473                           end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T3,T4,T11
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T11
1	Covered	T26,T27,T28

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T187
1	Covered	T187

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T11
1	Covered	T3,T6,T11

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T11

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T95
1	1	Covered	T3,T4,T11

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T11
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T3,T4,T11
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T95

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T95

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T6,T11
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T3,T6,T4
ReadWaitSt	252	Covered	T3,T4,T11
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T11,T14
IdleSt->ReadSt	236	Covered	T3,T6,T4
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T6,T34,T230
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T6,T4,T95
ReadSt->ReadWaitSt	252	Covered	T3,T4,T11
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T3,T4,T11
ResetSt->ErrorSt	315	Covered	T103,T104,T105
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T6,T4,T95
CheckFailError	317	Covered	T187
FsmStateError	289	Covered	T3,T6,T11
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T166,T231,T232
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T6,T4,T95
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T187
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T3,T6,T11
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T6,T4,T95
NoError->CheckFailError	317	Covered	T187
NoError->FsmStateError	289	Covered	T3,T6,T11
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		43	41	95.35
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	20	18	90.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

336          assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
                                                                          -1-  
                                                                          ==>  
                                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T11
0	Covered	T1,T2,T3

349          assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T11

358          assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T11

395          assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

420            assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T95
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              ///////////////////////////////////////////////////////////////////
188              // State right after reset. Wait here until we get a an
189              // initialization request.
190              ResetSt: begin
191                if (init_req_i) begin
                   -2-  
192                  // If the partition does not have a digest, no initialization is necessary.
193                  if (Info.sw_digest) begin
                     -3-  
194                    state_d = InitSt;
                       ==>
195                  end else begin
196                    state_d = IdleSt;
                       ==> (Unreachable)
197                  end
198                end
                   MISSING_ELSE
                   ==>
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Initialization reads out the digest only in unbuffered
202              // partitions. Wait here until the OTP request has been granted.
203              // And then wait until the OTP word comes back.
204              InitSt: begin
205                otp_req_o = 1'b1;
206                if (otp_gnt_i) begin
                   -4-  
207                  state_d = InitWaitSt;
                     ==>
208                end
                   MISSING_ELSE
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
209              end
210              ///////////////////////////////////////////////////////////////////
211              // Wait for OTP response and write to digest buffer register. In
212              // case an OTP transaction fails, latch the  OTP error code and
213              // jump to a terminal error state.
214              InitWaitSt: begin
215                if (otp_rvalid_i) begin
                   -5-  
216                  digest_reg_en = 1'b1;
217                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -6-  
218                    state_d = IdleSt;
219                    // At this point the only error that we could have gotten are correctable ECC errors.
220                    if (otp_err != NoError) begin
                       -7-  
221                      error_d = MacroEccCorrError;
                         ==> (Excluded)
Exclude Annotation: VC_COV_UNR
222                    end
                       MISSING_ELSE
                       ==>
223                  end else begin
224                    state_d = ErrorSt;
                       ==>
225                    error_d = otp_err;
226                  end
227                end
                   MISSING_ELSE
                   ==>
228              end
229              ///////////////////////////////////////////////////////////////////
230              // Wait for TL-UL requests coming in.
231              // Then latch address and go to readout state.
232              IdleSt: begin
233                init_done_o = 1'b1;
234                if (tlul_req_i) begin
                   -8-  
235                  error_d = NoError; // clear recoverable soft errors.
                     ==>
236                  state_d = ReadSt;
237                  tlul_gnt_o = 1'b1;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              ///////////////////////////////////////////////////////////////////
241              // If the address is out of bounds, or if the partition is
242              // locked, signal back a bus error. Note that such an error does
243              // not cause the partition to go into error state. Otherwise if
244              // these checks pass, an OTP word is requested.
245              ReadSt: begin
246                init_done_o = 1'b1;
247                // Double check the address range.
248                if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
                   -9-  
249                  otp_req_o = 1'b1;
250                  otp_addr_sel = DataAddrSel;
251                  if (otp_gnt_i) begin
                     -10-  
252                    state_d = ReadWaitSt;
                       ==>
253                  end
                     MISSING_ELSE
                     ==>
254                end else begin
255                  state_d = IdleSt;
                     ==>
256                  error_d = AccessError; // Signal this error, but do not go into terminal error state.
257                  tlul_rvalid_o = 1'b1;
258                  tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259                end
260              end
261              ///////////////////////////////////////////////////////////////////
262              // Wait for OTP response and release the TL-UL response. In
263              // case an OTP transaction fails, latch the OTP error code,
264              // signal a TL-Ul bus error and jump to a terminal error state.
265              ReadWaitSt: begin
266                init_done_o = 1'b1;
267                if (otp_rvalid_i) begin
                   -11-  
268                  tlul_rvalid_o = 1'b1;
269                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -12-  
270                    state_d = IdleSt;
271                    // At this point the only error that we could have gotten are correctable ECC errors.
272                    if (otp_err != NoError) begin
                       -13-  
273                      error_d = MacroEccCorrError;
                         ==> (Excluded)
Exclude Annotation: VC_COV_UNR
274                    end
                       MISSING_ELSE
                       ==>
275                  end else begin
276                    state_d = ErrorSt;
                       ==>
277                    error_d = otp_err;
278                    // This causes the TL-UL adapter to return a bus error.
279                    tlul_rerror_o = 2'b11;
280                  end
281                end
                   MISSING_ELSE
                   ==>
282              end
283              ///////////////////////////////////////////////////////////////////
284              // Terminal Error State. This locks access to the partition.
285              // Make sure the partition signals an error state if no error
286              // code has been latched so far.
287              ErrorSt: begin
288                if (error_q == NoError) begin
                   -14-  
289                  error_d = FsmStateError;
                     ==>
290                end
                   MISSING_ELSE
                   ==>
291        
292                // Return bus errors if there are pending TL-UL requests.
293                if (pending_tlul_error_q) begin
                   -15-  
294                  tlul_rerror_o = 2'b11;
                     ==>
295                  tlul_rvalid_o = 1'b1;
296                end else if (tlul_req_i) begin
                            -16-  
297                  tlul_gnt_o = 1'b1;
                     ==>
298                  pending_tlul_error_d = 1'b1;
299                end
                   MISSING_ELSE
                   ==>
300              end
301              ///////////////////////////////////////////////////////////////////
302              // We should never get here. If we do (e.g. via a malicious
303              // glitch), error out immediately.
304              default: begin
305                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T6,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T4,T11
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T4,T119,T201
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T4,T95
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T4,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T4,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T6,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T34,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T6,T34,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T6,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T28

314            if (ecc_err) begin
               -1-  
315              state_d = ErrorSt;
316              if (state_q != ErrorSt) begin
                 -2-  
317                error_d = CheckFailError;
                   ==>
318              end
                 MISSING_ELSE
                 ==>
319            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T187
1	0	Covered	T187
0	-	Covered	T1,T2,T3

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
               -1-  
322              state_d = ErrorSt;
323              fsm_err_o = 1'b1;
324              if (state_q != ErrorSt) begin
                 -2-  
325                error_d = FsmStateError;
                   ==>
326              end
                 MISSING_ELSE
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T6,T11
1	0	Covered	T3,T6,T11
0	-	Covered	T1,T2,T3

461          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

464            if (!rst_ni) begin
               -1-  
465              error_q              <= NoError;
                 ==>
466              tlul_addr_q          <= '0;
467              pending_tlul_error_q <= 1'b0;
468            end else begin
469              error_q              <= error_d;
470              pending_tlul_error_q <= pending_tlul_error_d;
471              if (tlul_gnt_o) begin
                 -2-  
472                tlul_addr_q <= tlul_addr_d;
                   ==>
473              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T6,T4
0	0	Covered	T1,T2,T3

153              if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
                 -1-  
154                otp_err = NoError;
                   ==>
155              end else begin
156                otp_err = otp_err_e'(otp_err_i);
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T151
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	80791054	79962216	0	0
DigestKnown_A	80791054	79962216	0	0
DigestOffsetMustBeRepresentable_A	1123	1123	0	0
EccErrorState_A	80791054	2416	0	0
ErrorKnown_A	80791054	79962216	0	0
FsmStateKnown_A	80791054	79962216	0	0
InitDoneKnown_A	80791054	79962216	0	0
InitReadLocksPartition_A	80791054	16887202	0	0
InitWriteLocksPartition_A	80791054	16887202	0	0
OffsetMustBeBlockAligned_A	1123	1123	0	0
OtpAddrKnown_A	80791054	79962216	0	0
OtpCmdKnown_A	80791054	79962216	0	0
OtpErrorState_A	80791054	0	0	0
OtpReqKnown_A	80791054	79962216	0	0
OtpSizeKnown_A	80791054	79962216	0	0
OtpWdataKnown_A	80791054	79962216	0	0
ReadLockPropagation_A	80791054	16426537	0	0
SizeMustBeBlockAligned_A	1123	1123	0	0
TlulGntKnown_A	80791054	79962216	0	0
TlulRdataKnown_A	80791054	79962216	0	0
TlulReadOnReadLock_A	80791054	5757	0	0
TlulRerrorKnown_A	80791054	79962216	0	0
TlulRvalidKnown_A	80791054	79962216	0	0
WriteLockPropagation_A	80791054	1809322	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	80791054	22110045	0	0
u_state_regs_A	80791054	79962216	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	2416	0	0
T187	8108	2416	0	0
T210	40742	0	0	0
T211	15998	0	0	0
T212	38167	0	0	0
T213	341586	0	0	0
T214	16672	0	0	0
T215	118881	0	0	0
T216	306590	0	0	0
T217	14120	0	0	0
T218	15807	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	16887202	0	0
T1	5511	318	0	0
T2	12159	120	0	0
T3	13200	4993	0	0
T4	24822	4331	0	0
T6	7902	1658	0	0
T10	6437	206	0	0
T11	10342	4306	0	0
T12	7144	279	0	0
T13	13944	3197	0	0
T14	9797	4061	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	16887202	0	0
T1	5511	318	0	0
T2	12159	120	0	0
T3	13200	4993	0	0
T4	24822	4331	0	0
T6	7902	1658	0	0
T10	6437	206	0	0
T11	10342	4306	0	0
T12	7144	279	0	0
T13	13944	3197	0	0
T14	9797	4061	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	16426537	0	0
T4	24822	1227	0	0
T5	23415	0	0	0
T6	7902	776	0	0
T11	10342	0	0	0
T12	7144	0	0	0
T13	13944	0	0	0
T14	9797	0	0	0
T20	0	13926	0	0
T21	0	3312	0	0
T34	22758	0	0	0
T36	0	12182	0	0
T89	0	5030	0	0
T95	25198	2990	0	0
T119	0	2072	0	0
T128	0	13097	0	0
T129	0	5190	0	0
T135	11155	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	5757	0	0
T4	24822	1	0	0
T5	23415	0	0	0
T6	7902	3	0	0
T7	0	4	0	0
T8	0	20	0	0
T9	0	8	0	0
T11	10342	0	0	0
T12	7144	0	0	0
T13	13944	0	0	0
T14	9797	0	0	0
T34	22758	1	0	0
T36	0	5	0	0
T95	25198	1	0	0
T128	0	1	0	0
T129	0	4	0	0
T135	11155	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	1809322	0	0
T21	54918	2442	0	0
T22	30128	0	0	0
T96	0	2709	0	0
T97	0	30415	0	0
T98	10292	0	0	0
T99	0	4601	0	0
T102	0	35619	0	0
T117	13269	0	0	0
T118	13703	0	0	0
T119	25492	793	0	0
T120	15620	0	0	0
T121	0	1457	0	0
T124	0	7205	0	0
T125	0	9294	0	0
T180	45656	0	0	0
T183	33102	0	0	0
T201	0	15191	0	0
T229	5426	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	22110045	0	0
T3	13200	3939	0	0
T4	24822	15733	0	0
T5	23415	0	0	0
T6	7902	0	0	0
T10	6437	0	0	0
T11	10342	0	0	0
T12	7144	0	0	0
T13	13944	0	0	0
T14	9797	0	0	0
T20	0	49646	0	0
T21	0	28276	0	0
T34	0	3579	0	0
T89	0	29739	0	0
T95	25198	18269	0	0
T114	0	2666	0	0
T119	0	18741	0	0
T129	0	25126	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

137                       // Output partition error state.
138        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
139                     
140                       // This partition cannot do any write accesses, hence we tie this
141                       // constantly off.
142                       assign otp_wdata_o = '0;
143                       // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144                       // calculations and checks. To be on the safe side, the partition filters error responses at this
145                       // point and does not report any integrity errors if integrity is disabled.
146                       otp_err_e otp_err;
147                       if (Info.integrity) begin : gen_integrity
148                         assign otp_cmd_o = prim_otp_pkg::Read;
149        1/1              assign otp_err = otp_err_e'(otp_err_i);
           Tests:       T1 T2 T3 
150                       end else begin : gen_no_integrity
151                         assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152                         always_comb begin
153                           if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
154                             otp_err = NoError;
155                           end else begin
156                             otp_err = otp_err_e'(otp_err_i);
157                           end
158                         end
159                       end
160                     
161                       `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162                       always_comb begin : p_fsm
163                         // Default assignments
164        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
165                     
166                         // Response to init request
167        1/1              init_done_o = 1'b0;
           Tests:       T1 T2 T3 
168                     
169                         // OTP signals
170        1/1              otp_req_o   = 1'b0;
           Tests:       T1 T2 T3 
171        1/1              otp_addr_sel = DigestAddrSel;
           Tests:       T1 T2 T3 
172                     
173                         // TL-UL signals
174        1/1              tlul_gnt_o      = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              tlul_rvalid_o   = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              tlul_rerror_o   = '0;
           Tests:       T1 T2 T3 
177                     
178                         // Enable for buffered digest register
179        1/1              digest_reg_en = 1'b0;
           Tests:       T1 T2 T3 
180                     
181                         // Error Register
182        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
183        1/1              pending_tlul_error_d = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           ///////////////////////////////////////////////////////////////////
188                           // State right after reset. Wait here until we get a an
189                           // initialization request.
190                           ResetSt: begin
191        1/1                  if (init_req_i) begin
           Tests:       T1 T2 T3 
192                               // If the partition does not have a digest, no initialization is necessary.
193        1/1                    if (Info.sw_digest) begin
           Tests:       T1 T2 T3 
194        1/1                      state_d = InitSt;
           Tests:       T1 T2 T3 
195                               end else begin
196        unreachable              state_d = IdleSt;
197                               end
198                             end
                        MISSING_ELSE
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Initialization reads out the digest only in unbuffered
202                           // partitions. Wait here until the OTP request has been granted.
203                           // And then wait until the OTP word comes back.
204                           InitSt: begin
205        1/1                  otp_req_o = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  if (otp_gnt_i) begin
           Tests:       T1 T2 T3 
207        1/1                    state_d = InitWaitSt;
           Tests:       T1 T2 T3 
208                             end
                        MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // Wait for OTP response and write to digest buffer register. In
212                           // case an OTP transaction fails, latch the  OTP error code and
213                           // jump to a terminal error state.
214                           InitWaitSt: begin
215        1/1                  if (otp_rvalid_i) begin
           Tests:       T1 T2 T3 
216        1/1                    digest_reg_en = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T1 T2 T3 
218        1/1                      state_d = IdleSt;
           Tests:       T1 T2 T3 
219                                 // At this point the only error that we could have gotten are correctable ECC errors.
220        1/1                      if (otp_err != NoError) begin
           Tests:       T1 T2 T3 
221        1/1                        error_d = MacroEccCorrError;
           Tests:       T151 T134 T46 
222                                 end
                        MISSING_ELSE
223                               end else begin
224        1/1                      state_d = ErrorSt;
           Tests:       T3 T188 T189 
225        1/1                      error_d = otp_err;
           Tests:       T3 T188 T189 
226                               end
227                             end
                        MISSING_ELSE
228                           end
229                           ///////////////////////////////////////////////////////////////////
230                           // Wait for TL-UL requests coming in.
231                           // Then latch address and go to readout state.
232                           IdleSt: begin
233        1/1                  init_done_o = 1'b1;
           Tests:       T1 T2 T3 
234        1/1                  if (tlul_req_i) begin
           Tests:       T1 T2 T3 
235        1/1                    error_d = NoError; // clear recoverable soft errors.
           Tests:       T3 T4 T11 
236        1/1                    state_d = ReadSt;
           Tests:       T3 T4 T11 
237        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T3 T4 T11 
238                             end
                        MISSING_ELSE
239                           end
240                           ///////////////////////////////////////////////////////////////////
241                           // If the address is out of bounds, or if the partition is
242                           // locked, signal back a bus error. Note that such an error does
243                           // not cause the partition to go into error state. Otherwise if
244                           // these checks pass, an OTP word is requested.
245                           ReadSt: begin
246        1/1                  init_done_o = 1'b1;
           Tests:       T3 T4 T11 
247                             // Double check the address range.
248        1/1                  if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
           Tests:       T3 T4 T11 
249        1/1                    otp_req_o = 1'b1;
           Tests:       T3 T11 T5 
250        1/1                    otp_addr_sel = DataAddrSel;
           Tests:       T3 T11 T5 
251        1/1                    if (otp_gnt_i) begin
           Tests:       T3 T11 T5 
252        1/1                      state_d = ReadWaitSt;
           Tests:       T3 T11 T5 
253                               end
                        MISSING_ELSE
254                             end else begin
255        1/1                    state_d = IdleSt;
           Tests:       T4 T95 T129 
256        1/1                    error_d = AccessError; // Signal this error, but do not go into terminal error state.
           Tests:       T4 T95 T129 
257        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T4 T95 T129 
258        1/1                    tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
           Tests:       T4 T95 T129 
259                             end
260                           end
261                           ///////////////////////////////////////////////////////////////////
262                           // Wait for OTP response and release the TL-UL response. In
263                           // case an OTP transaction fails, latch the OTP error code,
264                           // signal a TL-Ul bus error and jump to a terminal error state.
265                           ReadWaitSt: begin
266        1/1                  init_done_o = 1'b1;
           Tests:       T3 T11 T5 
267        1/1                  if (otp_rvalid_i) begin
           Tests:       T3 T11 T5 
268        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T3 T11 T5 
269        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T3 T11 T5 
270        1/1                      state_d = IdleSt;
           Tests:       T3 T11 T5 
271                                 // At this point the only error that we could have gotten are correctable ECC errors.
272        1/1                      if (otp_err != NoError) begin
           Tests:       T3 T11 T5 
273        1/1                        error_d = MacroEccCorrError;
           Tests:       T36 T89 T184 
274                                 end
                        MISSING_ELSE
275                               end else begin
276        1/1                      state_d = ErrorSt;
           Tests:       T181 T190 T191 
277        1/1                      error_d = otp_err;
           Tests:       T181 T190 T191 
278                                 // This causes the TL-UL adapter to return a bus error.
279        1/1                      tlul_rerror_o = 2'b11;
           Tests:       T181 T190 T191 
280                               end
281                             end
                        MISSING_ELSE
282                           end
283                           ///////////////////////////////////////////////////////////////////
284                           // Terminal Error State. This locks access to the partition.
285                           // Make sure the partition signals an error state if no error
286                           // code has been latched so far.
287                           ErrorSt: begin
288        1/1                  if (error_q == NoError) begin
           Tests:       T3 T6 T11 
289        1/1                    error_d = FsmStateError;
           Tests:       T26 T27 T28 
290                             end
                        MISSING_ELSE
291                     
292                             // Return bus errors if there are pending TL-UL requests.
293        1/1                  if (pending_tlul_error_q) begin
           Tests:       T3 T6 T11 
294        1/1                    tlul_rerror_o = 2'b11;
           Tests:       T6 T34 T7 
295        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T6 T34 T7 
296        1/1                  end else if (tlul_req_i) begin
           Tests:       T3 T6 T11 
297        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T6 T34 T7 
298        1/1                    pending_tlul_error_d = 1'b1;
           Tests:       T6 T34 T7 
299                             end
                        MISSING_ELSE
300                           end
301                           ///////////////////////////////////////////////////////////////////
302                           // We should never get here. If we do (e.g. via a malicious
303                           // glitch), error out immediately.
304                           default: begin
305                             state_d = ErrorSt;
306                             fsm_err_o = 1'b1;
307                           end
308                           ///////////////////////////////////////////////////////////////////
309                         endcase // state_q
310                     
311                         // Unconditionally jump into the terminal error state in case of
312                         // an ECC error or escalation, and lock access to the partition down.
313                         // SEC_CM: PART.FSM.LOCAL_ESC
314        1/1              if (ecc_err) begin
           Tests:       T1 T2 T3 
315        1/1                state_d = ErrorSt;
           Tests:       T187 T192 
316        1/1                if (state_q != ErrorSt) begin
           Tests:       T187 T192 
317        1/1                  error_d = CheckFailError;
           Tests:       T187 T192 
318                           end
                        MISSING_ELSE
319                         end
                        MISSING_ELSE
320                         // SEC_CM: PART.FSM.GLOBAL_ESC
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                state_d = ErrorSt;
           Tests:       T3 T6 T11 
323        1/1                fsm_err_o = 1'b1;
           Tests:       T3 T6 T11 
324        1/1                if (state_q != ErrorSt) begin
           Tests:       T3 T6 T11 
325        1/1                  error_d = FsmStateError;
           Tests:       T6 T11 T14 
326                           end
                        MISSING_ELSE
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       ///////////////////////////////////
331                       // Signals to/from TL-UL Adapter //
332                       ///////////////////////////////////
333                     
334        1/1            assign tlul_addr_d  = tlul_addr_i;
           Tests:       T1 T2 T3 
335                       // Do not forward data in case of an error.
336        1/1            assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
           Tests:       T1 T2 T3 
337                     
338                       if (Info.offset == 0) begin : gen_zero_offset
339                         assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
340                     
341                       end else begin : gen_nonzero_offset
342        1/1              assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
           Tests:       T1 T2 T3 
343                                                     {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344                       end
345                     
346                       // Note that OTP works on halfword (16bit) addresses, hence need to
347                       // shift the addresses appropriately.
348                       logic [OtpByteAddrWidth-1:0] addr_calc;
349        1/1            assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
           Tests:       T1 T2 T3 
350        1/1            assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
           Tests:       T1 T2 T3 
351                     
352                       if (OtpAddrShift > 0) begin : gen_unused
353                         logic unused_bits;
354        1/1              assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
           Tests:       T1 T2 T3 
355                       end
356                     
357                       // Request 32bit except in case of the digest.
358        1/1            assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
           Tests:       T1 T2 T3 
359                                           OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360                                           OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361                     
362                       ////////////////
363                       // Digest Reg //
364                       ////////////////
365                     
366                       if (Info.sw_digest) begin : gen_ecc_reg
367                         // SEC_CM: PART.DATA_REG.INTEGRITY
368                         otp_ctrl_ecc_reg #(
369                           .Width ( ScrmblBlockWidth ),
370                           .Depth ( 1                )
371                         ) u_otp_ctrl_ecc_reg (
372                           .clk_i,
373                           .rst_ni,
374                           .wren_i    ( digest_reg_en ),
375                           .addr_i    ( '0            ),
376                           .wdata_i   ( otp_rdata_i   ),
377                           .rdata_o   (               ),
378                           .data_o    ( digest_o      ),
379                           .ecc_err_o ( ecc_err       )
380                         );
381                       end else begin : gen_no_ecc_reg
382                         logic unused_digest_reg_en;
383                         logic unused_rdata;
384                         assign unused_digest_reg_en = digest_reg_en;
385                         assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386                         assign digest_o = '0;
387                         assign ecc_err = 1'b0;
388                       end
389                     
390                       ////////////////////////
391                       // DAI Access Control //
392                       ////////////////////////
393                     
394                       mubi8_t init_locked;
395        1/1            assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
396                     
397                       // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398                       // Note that the locks are redundantly encoded values.
399                       part_access_t access_pre;
400                       prim_mubi8_sender #(
401                         .AsyncOn(0)
402                       ) u_prim_mubi8_sender_write_lock_pre (
403                         .clk_i,
404                         .rst_ni,
405                         .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406                         .mubi_o(access_pre.write_lock)
407                       );
408                       prim_mubi8_sender #(
409                         .AsyncOn(0)
410                       ) u_prim_mubi8_sender_read_lock_pre (
411                         .clk_i,
412                         .rst_ni,
413                         .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414                         .mubi_o(access_pre.read_lock)
415                       );
416                     
417                       // SEC_CM: PART.MEM.SW_UNWRITABLE
418                       if (Info.write_lock) begin : gen_digest_write_lock
419                         mubi8_t digest_locked;
420        1/1              assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
421                     
422                         // This prevents the synthesis tool from optimizing the multibit signal.
423                         prim_mubi8_sender #(
424                           .AsyncOn(0)
425                         ) u_prim_mubi8_sender_write_lock (
426                           .clk_i,
427                           .rst_ni,
428                           .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429                           .mubi_o(access_o.write_lock)
430                         );
431                     
432                         `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433                       end else begin : gen_no_digest_write_lock
434                         assign access_o.write_lock = access_pre.write_lock;
435                       end
436                     
437                       // SEC_CM: PART.MEM.SW_UNREADABLE
438                       if (Info.read_lock) begin : gen_digest_read_lock
439                         mubi8_t digest_locked;
440                         assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441                     
442                         // This prevents the synthesis tool from optimizing the multibit signal.
443                         prim_mubi8_sender #(
444                           .AsyncOn(0)
445                         ) u_prim_mubi8_sender_read_lock (
446                           .clk_i,
447                           .rst_ni,
448                           .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449                           .mubi_o(access_o.read_lock)
450                         );
451                     
452                         `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453                       end else begin : gen_no_digest_read_lock
454        1/1              assign access_o.read_lock = access_pre.read_lock;
           Tests:       T1 T2 T3 
455                       end
456                     
457                       ///////////////
458                       // Registers //
459                       ///////////////
460                     
461        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1                   `ifdef SIMULATION                                   
461.2                       prim_sparse_fsm_flop #(                           
461.3                         .StateEnumT(state_e),                            
461.4                         .Width($bits(state_e)),                          
461.5                         .ResetValue($bits(state_e)'(ResetSt)),          
461.6                         .EnableAlertTriggerSVA(1), 
461.7                         .CustomForceName("state_q")          
461.8                       ) u_state_regs (                                        
461.9                         .clk_i   ( clk_i   ),                           
461.10                        .rst_ni  ( rst_ni ),                           
461.11                        .state_i ( state_d     ),                           
461.12                        .state_o (         )                            
461.13                      );                                                
461.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
461.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
461.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
461.17                      end else begin                                    
461.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
461.19                      end                                               
461.20                    end  
461.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
461.22                      else begin                                                                           
461.23                        `ifdef UVM                                                                               
461.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
461.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);                                
461.26                  `else                                                                                    
461.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
461.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
461.29                  `endif                                                              
461.30                      end 
461.31                    `else                                               
461.32                      prim_sparse_fsm_flop #(                           
461.33                        .StateEnumT(state_e),                            
461.34                        .Width($bits(state_e)),                          
461.35                        .ResetValue($bits(state_e)'(ResetSt)),          
461.36                        .EnableAlertTriggerSVA(1)  
461.37                      ) u_state_regs (                                        
461.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
461.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
461.40                        .state_i ( state_d     ),                           
461.41                        .state_o ( state_q     )                            
461.42                      );                                                
461.43                    `endif462                     
463                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
465        1/1                error_q              <= NoError;
           Tests:       T1 T2 T3 
466        1/1                tlul_addr_q          <= '0;
           Tests:       T1 T2 T3 
467        1/1                pending_tlul_error_q <= 1'b0;
           Tests:       T1 T2 T3 
468                         end else begin
469        1/1                error_q              <= error_d;
           Tests:       T1 T2 T3 
470        1/1                pending_tlul_error_q <= pending_tlul_error_d;
           Tests:       T1 T2 T3 
471        1/1                if (tlul_gnt_o) begin
           Tests:       T1 T2 T3 
472        1/1                  tlul_addr_q <= tlul_addr_d;
           Tests:       T3 T6 T4 
473                           end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T151,T134,T46

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T11,T5
1	Covered	T36,T89,T184

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T11
1	Covered	T26,T27,T28

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T187,T192
1	Covered	T187,T192

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T11
1	Covered	T6,T11,T14

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T95
1	1	Covered	T3,T11,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T6,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T3,T11,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T3,T11,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T95

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T95

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T6,T11
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T3,T4,T11
ReadWaitSt	252	Covered	T3,T11,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T11,T14,T151
IdleSt->ReadSt	236	Covered	T3,T4,T11
InitSt->ErrorSt	315	Covered	T6,T34,T230
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T3,T188,T189
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T95,T129
ReadSt->ReadWaitSt	252	Covered	T3,T11,T5
ReadWaitSt->ErrorSt	276	Covered	T181,T190,T191
ReadWaitSt->IdleSt	270	Covered	T3,T11,T5
ResetSt->ErrorSt	315	Covered	T103,T104,T105
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T95,T129
CheckFailError	317	Covered	T187,T192
FsmStateError	289	Covered	T6,T11,T14
MacroEccCorrError	221	Covered	T151,T134,T36
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T9,T166,T231
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T95,T129
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T187,T192
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T6,T11,T14
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T151,T134,T184
MacroEccCorrError->NoError	235	Covered	T36,T89,T87
NoError->AccessError	256	Covered	T4,T95,T129
NoError->CheckFailError	317	Covered	T187,T192
NoError->FsmStateError	289	Covered	T6,T11,T14
NoError->MacroEccCorrError	221	Covered	T151,T134,T36

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

336          assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
                                                                          -1-  
                                                                          ==>  
                                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T5
0	Covered	T1,T2,T3

349          assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T5

358          assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T5

395          assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

420            assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T95
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              ///////////////////////////////////////////////////////////////////
188              // State right after reset. Wait here until we get a an
189              // initialization request.
190              ResetSt: begin
191                if (init_req_i) begin
                   -2-  
192                  // If the partition does not have a digest, no initialization is necessary.
193                  if (Info.sw_digest) begin
                     -3-  
194                    state_d = InitSt;
                       ==>
195                  end else begin
196                    state_d = IdleSt;
                       ==> (Unreachable)
197                  end
198                end
                   MISSING_ELSE
                   ==>
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Initialization reads out the digest only in unbuffered
202              // partitions. Wait here until the OTP request has been granted.
203              // And then wait until the OTP word comes back.
204              InitSt: begin
205                otp_req_o = 1'b1;
206                if (otp_gnt_i) begin
                   -4-  
207                  state_d = InitWaitSt;
                     ==>
208                end
                   MISSING_ELSE
                   ==>
209              end
210              ///////////////////////////////////////////////////////////////////
211              // Wait for OTP response and write to digest buffer register. In
212              // case an OTP transaction fails, latch the  OTP error code and
213              // jump to a terminal error state.
214              InitWaitSt: begin
215                if (otp_rvalid_i) begin
                   -5-  
216                  digest_reg_en = 1'b1;
217                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -6-  
218                    state_d = IdleSt;
219                    // At this point the only error that we could have gotten are correctable ECC errors.
220                    if (otp_err != NoError) begin
                       -7-  
221                      error_d = MacroEccCorrError;
                         ==>
222                    end
                       MISSING_ELSE
                       ==>
223                  end else begin
224                    state_d = ErrorSt;
                       ==>
225                    error_d = otp_err;
226                  end
227                end
                   MISSING_ELSE
                   ==>
228              end
229              ///////////////////////////////////////////////////////////////////
230              // Wait for TL-UL requests coming in.
231              // Then latch address and go to readout state.
232              IdleSt: begin
233                init_done_o = 1'b1;
234                if (tlul_req_i) begin
                   -8-  
235                  error_d = NoError; // clear recoverable soft errors.
                     ==>
236                  state_d = ReadSt;
237                  tlul_gnt_o = 1'b1;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              ///////////////////////////////////////////////////////////////////
241              // If the address is out of bounds, or if the partition is
242              // locked, signal back a bus error. Note that such an error does
243              // not cause the partition to go into error state. Otherwise if
244              // these checks pass, an OTP word is requested.
245              ReadSt: begin
246                init_done_o = 1'b1;
247                // Double check the address range.
248                if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
                   -9-  
249                  otp_req_o = 1'b1;
250                  otp_addr_sel = DataAddrSel;
251                  if (otp_gnt_i) begin
                     -10-  
252                    state_d = ReadWaitSt;
                       ==>
253                  end
                     MISSING_ELSE
                     ==>
254                end else begin
255                  state_d = IdleSt;
                     ==>
256                  error_d = AccessError; // Signal this error, but do not go into terminal error state.
257                  tlul_rvalid_o = 1'b1;
258                  tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259                end
260              end
261              ///////////////////////////////////////////////////////////////////
262              // Wait for OTP response and release the TL-UL response. In
263              // case an OTP transaction fails, latch the OTP error code,
264              // signal a TL-Ul bus error and jump to a terminal error state.
265              ReadWaitSt: begin
266                init_done_o = 1'b1;
267                if (otp_rvalid_i) begin
                   -11-  
268                  tlul_rvalid_o = 1'b1;
269                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -12-  
270                    state_d = IdleSt;
271                    // At this point the only error that we could have gotten are correctable ECC errors.
272                    if (otp_err != NoError) begin
                       -13-  
273                      error_d = MacroEccCorrError;
                         ==>
274                    end
                       MISSING_ELSE
                       ==>
275                  end else begin
276                    state_d = ErrorSt;
                       ==>
277                    error_d = otp_err;
278                    // This causes the TL-UL adapter to return a bus error.
279                    tlul_rerror_o = 2'b11;
280                  end
281                end
                   MISSING_ELSE
                   ==>
282              end
283              ///////////////////////////////////////////////////////////////////
284              // Terminal Error State. This locks access to the partition.
285              // Make sure the partition signals an error state if no error
286              // code has been latched so far.
287              ErrorSt: begin
288                if (error_q == NoError) begin
                   -14-  
289                  error_d = FsmStateError;
                     ==>
290                end
                   MISSING_ELSE
                   ==>
291        
292                // Return bus errors if there are pending TL-UL requests.
293                if (pending_tlul_error_q) begin
                   -15-  
294                  tlul_rerror_o = 2'b11;
                     ==>
295                  tlul_rvalid_o = 1'b1;
296                end else if (tlul_req_i) begin
                            -16-  
297                  tlul_gnt_o = 1'b1;
                     ==>
298                  pending_tlul_error_d = 1'b1;
299                end
                   MISSING_ELSE
                   ==>
300              end
301              ///////////////////////////////////////////////////////////////////
302              // We should never get here. If we do (e.g. via a malicious
303              // glitch), error out immediately.
304              default: begin
305                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T151,T134,T46
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T188,T189
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T4,T11
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T11,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T130,T201,T233
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T95,T129
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T36,T89,T184
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T11,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T181,T190,T191
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T11,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T6,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T34,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T6,T34,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T6,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T28

314            if (ecc_err) begin
               -1-  
315              state_d = ErrorSt;
316              if (state_q != ErrorSt) begin
                 -2-  
317                error_d = CheckFailError;
                   ==>
318              end
                 MISSING_ELSE
                 ==>
319            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T187,T192
1	0	Covered	T187,T192
0	-	Covered	T1,T2,T3

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
               -1-  
322              state_d = ErrorSt;
323              fsm_err_o = 1'b1;
324              if (state_q != ErrorSt) begin
                 -2-  
325                error_d = FsmStateError;
                   ==>
326              end
                 MISSING_ELSE
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T6,T11,T14
1	0	Covered	T3,T6,T11
0	-	Covered	T1,T2,T3

461          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

464            if (!rst_ni) begin
               -1-  
465              error_q              <= NoError;
                 ==>
466              tlul_addr_q          <= '0;
467              pending_tlul_error_q <= 1'b0;
468            end else begin
469              error_q              <= error_d;
470              pending_tlul_error_q <= pending_tlul_error_d;
471              if (tlul_gnt_o) begin
                 -2-  
472                tlul_addr_q <= tlul_addr_d;
                   ==>
473              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T6,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	80791054	79962216	0	0
DigestKnown_A	80791054	79962216	0	0
DigestOffsetMustBeRepresentable_A	1123	1123	0	0
EccErrorState_A	80791054	5667	0	0
ErrorKnown_A	80791054	79962216	0	0
FsmStateKnown_A	80791054	79962216	0	0
InitDoneKnown_A	80791054	79962216	0	0
InitReadLocksPartition_A	80791054	17062043	0	0
InitWriteLocksPartition_A	80791054	17062043	0	0
OffsetMustBeBlockAligned_A	1123	1123	0	0
OtpAddrKnown_A	80791054	79962216	0	0
OtpCmdKnown_A	80791054	79962216	0	0
OtpErrorState_A	80791054	63	0	0
OtpReqKnown_A	80791054	79962216	0	0
OtpSizeKnown_A	80791054	79962216	0	0
OtpWdataKnown_A	80791054	79962216	0	0
ReadLockPropagation_A	80791054	16606195	0	0
SizeMustBeBlockAligned_A	1123	1123	0	0
TlulGntKnown_A	80791054	79962216	0	0
TlulRdataKnown_A	80791054	79962216	0	0
TlulReadOnReadLock_A	80791054	6048	0	0
TlulRerrorKnown_A	80791054	79962216	0	0
TlulRvalidKnown_A	80791054	79962216	0	0
WriteLockPropagation_A	80791054	1833009	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	80791054	22195744	0	0
u_state_regs_A	80791054	79962216	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	5667	0	0
T187	8108	2416	0	0
T192	0	3251	0	0
T210	40742	0	0	0
T211	15998	0	0	0
T212	38167	0	0	0
T213	341586	0	0	0
T214	16672	0	0	0
T215	118881	0	0	0
T216	306590	0	0	0
T217	14120	0	0	0
T218	15807	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	17062043	0	0
T1	5511	335	0	0
T2	12159	171	0	0
T3	13200	5017	0	0
T4	24822	4416	0	0
T6	7902	1692	0	0
T10	6437	223	0	0
T11	10342	4340	0	0
T12	7144	296	0	0
T13	13944	3248	0	0
T14	9797	4112	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	17062043	0	0
T1	5511	335	0	0
T2	12159	171	0	0
T3	13200	5017	0	0
T4	24822	4416	0	0
T6	7902	1692	0	0
T10	6437	223	0	0
T11	10342	4340	0	0
T12	7144	296	0	0
T13	13944	3248	0	0
T14	9797	4112	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	63	0	0
T3	13200	1	0	0
T4	24822	0	0	0
T5	23415	0	0	0
T6	7902	0	0	0
T10	6437	0	0	0
T11	10342	0	0	0
T12	7144	0	0	0
T13	13944	0	0	0
T14	9797	0	0	0
T95	25198	0	0	0
T181	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T222	0	1	0	0
T223	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	16606195	0	0
T4	24822	1261	0	0
T5	23415	0	0	0
T9	0	10833	0	0
T11	10342	0	0	0
T12	7144	0	0	0
T13	13944	0	0	0
T14	9797	0	0	0
T20	0	17461	0	0
T21	0	2206	0	0
T34	22758	0	0	0
T35	19639	0	0	0
T36	0	12709	0	0
T89	0	5119	0	0
T95	25198	4073	0	0
T119	0	1210	0	0
T128	0	15999	0	0
T129	0	2365	0	0
T135	11155	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	6048	0	0
T4	24822	2	0	0
T5	23415	0	0	0
T6	7902	1	0	0
T7	0	2	0	0
T8	0	11	0	0
T9	0	11	0	0
T11	10342	0	0	0
T12	7144	0	0	0
T13	13944	0	0	0
T14	9797	0	0	0
T20	0	4	0	0
T34	22758	2	0	0
T95	25198	1	0	0
T128	0	5	0	0
T129	0	3	0	0
T135	11155	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	1833009	0	0
T8	29526	0	0	0
T9	19629	0	0	0
T20	70897	14974	0	0
T36	65717	0	0	0
T93	46637	0	0	0
T96	0	4503	0	0
T102	0	21578	0	0
T119	0	3624	0	0
T121	0	10402	0	0
T122	0	2271	0	0
T124	0	2024	0	0
T125	0	11957	0	0
T126	20116	0	0	0
T127	6222	0	0	0
T128	38211	0	0	0
T129	37784	3599	0	0
T130	0	3115	0	0
T134	15276	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	22195744	0	0
T3	13200	3934	0	0
T4	24822	15665	0	0
T5	23415	0	0	0
T6	7902	0	0	0
T10	6437	0	0	0
T11	10342	0	0	0
T12	7144	0	0	0
T13	13944	0	0	0
T14	9797	0	0	0
T20	0	49561	0	0
T21	0	21347	0	0
T36	0	33267	0	0
T89	0	42891	0	0
T95	25198	18184	0	0
T119	0	18673	0	0
T128	0	18782	0	0
T129	0	25041	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

137                       // Output partition error state.
138        1/1            assign error_o = error_q;
           Tests:       T1 T2 T3 
139                     
140                       // This partition cannot do any write accesses, hence we tie this
141                       // constantly off.
142                       assign otp_wdata_o = '0;
143                       // Depending on the partition configuration, the wrapper is instructed to ignore integrity
144                       // calculations and checks. To be on the safe side, the partition filters error responses at this
145                       // point and does not report any integrity errors if integrity is disabled.
146                       otp_err_e otp_err;
147                       if (Info.integrity) begin : gen_integrity
148                         assign otp_cmd_o = prim_otp_pkg::Read;
149        1/1              assign otp_err = otp_err_e'(otp_err_i);
           Tests:       T1 T2 T3 
150                       end else begin : gen_no_integrity
151                         assign otp_cmd_o = prim_otp_pkg::ReadRaw;
152                         always_comb begin
153                           if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin
154                             otp_err = NoError;
155                           end else begin
156                             otp_err = otp_err_e'(otp_err_i);
157                           end
158                         end
159                       end
160                     
161                       `ASSERT_KNOWN(FsmStateKnown_A, state_q)
162                       always_comb begin : p_fsm
163                         // Default assignments
164        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
165                     
166                         // Response to init request
167        1/1              init_done_o = 1'b0;
           Tests:       T1 T2 T3 
168                     
169                         // OTP signals
170        1/1              otp_req_o   = 1'b0;
           Tests:       T1 T2 T3 
171        1/1              otp_addr_sel = DigestAddrSel;
           Tests:       T1 T2 T3 
172                     
173                         // TL-UL signals
174        1/1              tlul_gnt_o      = 1'b0;
           Tests:       T1 T2 T3 
175        1/1              tlul_rvalid_o   = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              tlul_rerror_o   = '0;
           Tests:       T1 T2 T3 
177                     
178                         // Enable for buffered digest register
179        1/1              digest_reg_en = 1'b0;
           Tests:       T1 T2 T3 
180                     
181                         // Error Register
182        1/1              error_d = error_q;
           Tests:       T1 T2 T3 
183        1/1              pending_tlul_error_d = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           ///////////////////////////////////////////////////////////////////
188                           // State right after reset. Wait here until we get a an
189                           // initialization request.
190                           ResetSt: begin
191        1/1                  if (init_req_i) begin
           Tests:       T1 T2 T3 
192                               // If the partition does not have a digest, no initialization is necessary.
193        1/1                    if (Info.sw_digest) begin
           Tests:       T1 T2 T3 
194        1/1                      state_d = InitSt;
           Tests:       T1 T2 T3 
195                               end else begin
196        unreachable              state_d = IdleSt;
197                               end
198                             end
                        MISSING_ELSE
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Initialization reads out the digest only in unbuffered
202                           // partitions. Wait here until the OTP request has been granted.
203                           // And then wait until the OTP word comes back.
204                           InitSt: begin
205        1/1                  otp_req_o = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  if (otp_gnt_i) begin
           Tests:       T1 T2 T3 
207        1/1                    state_d = InitWaitSt;
           Tests:       T1 T2 T3 
208                             end
                        MISSING_ELSE
209                           end
210                           ///////////////////////////////////////////////////////////////////
211                           // Wait for OTP response and write to digest buffer register. In
212                           // case an OTP transaction fails, latch the  OTP error code and
213                           // jump to a terminal error state.
214                           InitWaitSt: begin
215        1/1                  if (otp_rvalid_i) begin
           Tests:       T1 T2 T3 
216        1/1                    digest_reg_en = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T1 T2 T3 
218        1/1                      state_d = IdleSt;
           Tests:       T1 T2 T3 
219                                 // At this point the only error that we could have gotten are correctable ECC errors.
220        1/1                      if (otp_err != NoError) begin
           Tests:       T1 T2 T3 
221        1/1                        error_d = MacroEccCorrError;
           Tests:       T11 T98 T83 
222                                 end
                        MISSING_ELSE
223                               end else begin
224        1/1                      state_d = ErrorSt;
           Tests:       T151 T134 T114 
225        1/1                      error_d = otp_err;
           Tests:       T151 T134 T114 
226                               end
227                             end
                        MISSING_ELSE
228                           end
229                           ///////////////////////////////////////////////////////////////////
230                           // Wait for TL-UL requests coming in.
231                           // Then latch address and go to readout state.
232                           IdleSt: begin
233        1/1                  init_done_o = 1'b1;
           Tests:       T1 T2 T3 
234        1/1                  if (tlul_req_i) begin
           Tests:       T1 T2 T3 
235        1/1                    error_d = NoError; // clear recoverable soft errors.
           Tests:       T3 T4 T11 
236        1/1                    state_d = ReadSt;
           Tests:       T3 T4 T11 
237        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T3 T4 T11 
238                             end
                        MISSING_ELSE
239                           end
240                           ///////////////////////////////////////////////////////////////////
241                           // If the address is out of bounds, or if the partition is
242                           // locked, signal back a bus error. Note that such an error does
243                           // not cause the partition to go into error state. Otherwise if
244                           // these checks pass, an OTP word is requested.
245                           ReadSt: begin
246        1/1                  init_done_o = 1'b1;
           Tests:       T3 T4 T11 
247                             // Double check the address range.
248        1/1                  if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
           Tests:       T3 T4 T11 
249        1/1                    otp_req_o = 1'b1;
           Tests:       T3 T4 T11 
250        1/1                    otp_addr_sel = DataAddrSel;
           Tests:       T3 T4 T11 
251        1/1                    if (otp_gnt_i) begin
           Tests:       T3 T4 T11 
252        1/1                      state_d = ReadWaitSt;
           Tests:       T3 T4 T11 
253                               end
                        MISSING_ELSE
254                             end else begin
255        1/1                    state_d = IdleSt;
           Tests:       T129 T20 T128 
256        1/1                    error_d = AccessError; // Signal this error, but do not go into terminal error state.
           Tests:       T129 T20 T128 
257        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T129 T20 T128 
258        1/1                    tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
           Tests:       T129 T20 T128 
259                             end
260                           end
261                           ///////////////////////////////////////////////////////////////////
262                           // Wait for OTP response and release the TL-UL response. In
263                           // case an OTP transaction fails, latch the OTP error code,
264                           // signal a TL-Ul bus error and jump to a terminal error state.
265                           ReadWaitSt: begin
266        1/1                  init_done_o = 1'b1;
           Tests:       T3 T4 T11 
267        1/1                  if (otp_rvalid_i) begin
           Tests:       T3 T4 T11 
268        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T3 T4 T11 
269        1/1                    if (otp_err inside {NoError, MacroEccCorrError}) begin
           Tests:       T3 T4 T11 
270        1/1                      state_d = IdleSt;
           Tests:       T3 T4 T11 
271                                 // At this point the only error that we could have gotten are correctable ECC errors.
272        1/1                      if (otp_err != NoError) begin
           Tests:       T3 T4 T11 
273        1/1                        error_d = MacroEccCorrError;
           Tests:       T36 T89 T99 
274                                 end
                        MISSING_ELSE
275                               end else begin
276        1/1                      state_d = ErrorSt;
           Tests:       T180 T184 T181 
277        1/1                      error_d = otp_err;
           Tests:       T180 T184 T181 
278                                 // This causes the TL-UL adapter to return a bus error.
279        1/1                      tlul_rerror_o = 2'b11;
           Tests:       T180 T184 T181 
280                               end
281                             end
                        MISSING_ELSE
282                           end
283                           ///////////////////////////////////////////////////////////////////
284                           // Terminal Error State. This locks access to the partition.
285                           // Make sure the partition signals an error state if no error
286                           // code has been latched so far.
287                           ErrorSt: begin
288        1/1                  if (error_q == NoError) begin
           Tests:       T3 T6 T11 
289        1/1                    error_d = FsmStateError;
           Tests:       T26 T27 T28 
290                             end
                        MISSING_ELSE
291                     
292                             // Return bus errors if there are pending TL-UL requests.
293        1/1                  if (pending_tlul_error_q) begin
           Tests:       T3 T6 T11 
294        1/1                    tlul_rerror_o = 2'b11;
           Tests:       T6 T14 T34 
295        1/1                    tlul_rvalid_o = 1'b1;
           Tests:       T6 T14 T34 
296        1/1                  end else if (tlul_req_i) begin
           Tests:       T3 T6 T11 
297        1/1                    tlul_gnt_o = 1'b1;
           Tests:       T6 T14 T34 
298        1/1                    pending_tlul_error_d = 1'b1;
           Tests:       T6 T14 T34 
299                             end
                        MISSING_ELSE
300                           end
301                           ///////////////////////////////////////////////////////////////////
302                           // We should never get here. If we do (e.g. via a malicious
303                           // glitch), error out immediately.
304                           default: begin
305                             state_d = ErrorSt;
306                             fsm_err_o = 1'b1;
307                           end
308                           ///////////////////////////////////////////////////////////////////
309                         endcase // state_q
310                     
311                         // Unconditionally jump into the terminal error state in case of
312                         // an ECC error or escalation, and lock access to the partition down.
313                         // SEC_CM: PART.FSM.LOCAL_ESC
314        1/1              if (ecc_err) begin
           Tests:       T1 T2 T3 
315        1/1                state_d = ErrorSt;
           Tests:       T187 T193 
316        1/1                if (state_q != ErrorSt) begin
           Tests:       T187 T193 
317        1/1                  error_d = CheckFailError;
           Tests:       T187 T193 
318                           end
                        MISSING_ELSE
319                         end
                        MISSING_ELSE
320                         // SEC_CM: PART.FSM.GLOBAL_ESC
321        1/1              if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
           Tests:       T1 T2 T3 
322        1/1                state_d = ErrorSt;
           Tests:       T3 T6 T11 
323        1/1                fsm_err_o = 1'b1;
           Tests:       T3 T6 T11 
324        1/1                if (state_q != ErrorSt) begin
           Tests:       T3 T6 T11 
325        1/1                  error_d = FsmStateError;
           Tests:       T3 T6 T11 
326                           end
                        MISSING_ELSE
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       ///////////////////////////////////
331                       // Signals to/from TL-UL Adapter //
332                       ///////////////////////////////////
333                     
334        1/1            assign tlul_addr_d  = tlul_addr_i;
           Tests:       T1 T2 T3 
335                       // Do not forward data in case of an error.
336        1/1            assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
           Tests:       T1 T2 T3 
337                     
338                       if (Info.offset == 0) begin : gen_zero_offset
339                         assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd;
340                     
341                       end else begin : gen_nonzero_offset
342        1/1              assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset &&
           Tests:       T1 T2 T3 
343                                                     {1'b0, tlul_addr_q, 2'b00} < PartEnd;
344                       end
345                     
346                       // Note that OTP works on halfword (16bit) addresses, hence need to
347                       // shift the addresses appropriately.
348                       logic [OtpByteAddrWidth-1:0] addr_calc;
349        1/1            assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
           Tests:       T1 T2 T3 
350        1/1            assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift];
           Tests:       T1 T2 T3 
351                     
352                       if (OtpAddrShift > 0) begin : gen_unused
353                         logic unused_bits;
354        1/1              assign unused_bits = ^addr_calc[OtpAddrShift-1:0];
           Tests:       T1 T2 T3 
355                       end
356                     
357                       // Request 32bit except in case of the digest.
358        1/1            assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
           Tests:       T1 T2 T3 
359                                           OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) :
360                                           OtpSizeWidth'(unsigned'(32 / OtpWidth - 1));
361                     
362                       ////////////////
363                       // Digest Reg //
364                       ////////////////
365                     
366                       if (Info.sw_digest) begin : gen_ecc_reg
367                         // SEC_CM: PART.DATA_REG.INTEGRITY
368                         otp_ctrl_ecc_reg #(
369                           .Width ( ScrmblBlockWidth ),
370                           .Depth ( 1                )
371                         ) u_otp_ctrl_ecc_reg (
372                           .clk_i,
373                           .rst_ni,
374                           .wren_i    ( digest_reg_en ),
375                           .addr_i    ( '0            ),
376                           .wdata_i   ( otp_rdata_i   ),
377                           .rdata_o   (               ),
378                           .data_o    ( digest_o      ),
379                           .ecc_err_o ( ecc_err       )
380                         );
381                       end else begin : gen_no_ecc_reg
382                         logic unused_digest_reg_en;
383                         logic unused_rdata;
384                         assign unused_digest_reg_en = digest_reg_en;
385                         assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case.
386                         assign digest_o = '0;
387                         assign ecc_err = 1'b0;
388                       end
389                     
390                       ////////////////////////
391                       // DAI Access Control //
392                       ////////////////////////
393                     
394                       mubi8_t init_locked;
395        1/1            assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
396                     
397                       // Aggregate all possible DAI write locks. The partition is also locked when uninitialized.
398                       // Note that the locks are redundantly encoded values.
399                       part_access_t access_pre;
400                       prim_mubi8_sender #(
401                         .AsyncOn(0)
402                       ) u_prim_mubi8_sender_write_lock_pre (
403                         .clk_i,
404                         .rst_ni,
405                         .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)),
406                         .mubi_o(access_pre.write_lock)
407                       );
408                       prim_mubi8_sender #(
409                         .AsyncOn(0)
410                       ) u_prim_mubi8_sender_read_lock_pre (
411                         .clk_i,
412                         .rst_ni,
413                         .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)),
414                         .mubi_o(access_pre.read_lock)
415                       );
416                     
417                       // SEC_CM: PART.MEM.SW_UNWRITABLE
418                       if (Info.write_lock) begin : gen_digest_write_lock
419                         mubi8_t digest_locked;
420        1/1              assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
           Tests:       T1 T2 T3 
421                     
422                         // This prevents the synthesis tool from optimizing the multibit signal.
423                         prim_mubi8_sender #(
424                           .AsyncOn(0)
425                         ) u_prim_mubi8_sender_write_lock (
426                           .clk_i,
427                           .rst_ni,
428                           .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)),
429                           .mubi_o(access_o.write_lock)
430                         );
431                     
432                         `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock))
433                       end else begin : gen_no_digest_write_lock
434                         assign access_o.write_lock = access_pre.write_lock;
435                       end
436                     
437                       // SEC_CM: PART.MEM.SW_UNREADABLE
438                       if (Info.read_lock) begin : gen_digest_read_lock
439                         mubi8_t digest_locked;
440                         assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
441                     
442                         // This prevents the synthesis tool from optimizing the multibit signal.
443                         prim_mubi8_sender #(
444                           .AsyncOn(0)
445                         ) u_prim_mubi8_sender_read_lock (
446                           .clk_i,
447                           .rst_ni,
448                           .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)),
449                           .mubi_o(access_o.read_lock)
450                         );
451                     
452                         `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock))
453                       end else begin : gen_no_digest_read_lock
454        1/1              assign access_o.read_lock = access_pre.read_lock;
           Tests:       T1 T2 T3 
455                       end
456                     
457                       ///////////////
458                       // Registers //
459                       ///////////////
460                     
461        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt):
461.1                   `ifdef SIMULATION                                   
461.2                       prim_sparse_fsm_flop #(                           
461.3                         .StateEnumT(state_e),                            
461.4                         .Width($bits(state_e)),                          
461.5                         .ResetValue($bits(state_e)'(ResetSt)),          
461.6                         .EnableAlertTriggerSVA(1), 
461.7                         .CustomForceName("state_q")          
461.8                       ) u_state_regs (                                        
461.9                         .clk_i   ( clk_i   ),                           
461.10                        .rst_ni  ( rst_ni ),                           
461.11                        .state_i ( state_d     ),                           
461.12                        .state_o (         )                            
461.13                      );                                                
461.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
461.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
461.16     1/1                state_q <= ResetSt;                                
           Tests:       T1 T2 T3 
461.17                      end else begin                                    
461.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
461.19                      end                                               
461.20                    end  
461.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
461.22                      else begin                                                                           
461.23                        `ifdef UVM                                                                               
461.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
461.25                                              "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv", 461, "", 1);                                
461.26                  `else                                                                                    
461.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
461.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
461.29                  `endif                                                              
461.30                      end 
461.31                    `else                                               
461.32                      prim_sparse_fsm_flop #(                           
461.33                        .StateEnumT(state_e),                            
461.34                        .Width($bits(state_e)),                          
461.35                        .ResetValue($bits(state_e)'(ResetSt)),          
461.36                        .EnableAlertTriggerSVA(1)  
461.37                      ) u_state_regs (                                        
461.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
461.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
461.40                        .state_i ( state_d     ),                           
461.41                        .state_o ( state_q     )                            
461.42                      );                                                
461.43                    `endif462                     
463                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
464        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
465        1/1                error_q              <= NoError;
           Tests:       T1 T2 T3 
466        1/1                tlul_addr_q          <= '0;
           Tests:       T1 T2 T3 
467        1/1                pending_tlul_error_q <= 1'b0;
           Tests:       T1 T2 T3 
468                         end else begin
469        1/1                error_q              <= error_d;
           Tests:       T1 T2 T3 
470        1/1                pending_tlul_error_q <= pending_tlul_error_d;
           Tests:       T1 T2 T3 
471        1/1                if (tlul_gnt_o) begin
           Tests:       T1 T2 T3 
472        1/1                  tlul_addr_q <= tlul_addr_d;
           Tests:       T3 T6 T4 
473                           end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T98,T83

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T11
1	Covered	T36,T89,T99

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T11
1	Covered	T26,T27,T28

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T187,T193
1	Covered	T187,T193

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T11
1	Covered	T3,T6,T11

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T11

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T14,T34
1	1	Covered	T3,T4,T11

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T6,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T11
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T3,T4,T11
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T95,T151,T129

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T95,T151,T129

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T6,T11
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T3,T4,T11
ReadWaitSt	252	Covered	T3,T4,T11
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T11,T14,T7
IdleSt->ReadSt	236	Covered	T3,T4,T11
InitSt->ErrorSt	315	Covered	T6,T34,T234
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T3,T151,T134
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T129,T20,T128
ReadSt->ReadWaitSt	252	Covered	T3,T4,T11
ReadWaitSt->ErrorSt	276	Covered	T180,T184,T181
ReadWaitSt->IdleSt	270	Covered	T3,T4,T11
ResetSt->ErrorSt	315	Covered	T103,T104,T105
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	10	10	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T129,T20,T128
CheckFailError	317	Covered	T187,T193
FsmStateError	289	Covered	T3,T6,T11
MacroEccCorrError	221	Covered	T11,T36,T89
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T166,T231,T232
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T129,T20,T128
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T187,T193
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T6,T11
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Excluded		VC_COV_UNR
MacroEccCorrError->FsmStateError	325	Covered	T11,T98,T83
MacroEccCorrError->NoError	235	Covered	T36,T89,T99
NoError->AccessError	256	Covered	T129,T20,T128
NoError->CheckFailError	317	Covered	T187,T193
NoError->FsmStateError	289	Covered	T3,T6,T14
NoError->MacroEccCorrError	221	Covered	T11,T36,T89

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

336          assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0;
                                                                          -1-  
                                                                          ==>  
                                                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T11
0	Covered	T1,T2,T3

349          assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00};
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T11

358          assign otp_size_o = (otp_addr_sel == DigestAddrSel) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T11

395          assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

420            assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False;
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T95,T151,T129
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              ///////////////////////////////////////////////////////////////////
188              // State right after reset. Wait here until we get a an
189              // initialization request.
190              ResetSt: begin
191                if (init_req_i) begin
                   -2-  
192                  // If the partition does not have a digest, no initialization is necessary.
193                  if (Info.sw_digest) begin
                     -3-  
194                    state_d = InitSt;
                       ==>
195                  end else begin
196                    state_d = IdleSt;
                       ==> (Unreachable)
197                  end
198                end
                   MISSING_ELSE
                   ==>
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Initialization reads out the digest only in unbuffered
202              // partitions. Wait here until the OTP request has been granted.
203              // And then wait until the OTP word comes back.
204              InitSt: begin
205                otp_req_o = 1'b1;
206                if (otp_gnt_i) begin
                   -4-  
207                  state_d = InitWaitSt;
                     ==>
208                end
                   MISSING_ELSE
                   ==>
209              end
210              ///////////////////////////////////////////////////////////////////
211              // Wait for OTP response and write to digest buffer register. In
212              // case an OTP transaction fails, latch the  OTP error code and
213              // jump to a terminal error state.
214              InitWaitSt: begin
215                if (otp_rvalid_i) begin
                   -5-  
216                  digest_reg_en = 1'b1;
217                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -6-  
218                    state_d = IdleSt;
219                    // At this point the only error that we could have gotten are correctable ECC errors.
220                    if (otp_err != NoError) begin
                       -7-  
221                      error_d = MacroEccCorrError;
                         ==>
222                    end
                       MISSING_ELSE
                       ==>
223                  end else begin
224                    state_d = ErrorSt;
                       ==>
225                    error_d = otp_err;
226                  end
227                end
                   MISSING_ELSE
                   ==>
228              end
229              ///////////////////////////////////////////////////////////////////
230              // Wait for TL-UL requests coming in.
231              // Then latch address and go to readout state.
232              IdleSt: begin
233                init_done_o = 1'b1;
234                if (tlul_req_i) begin
                   -8-  
235                  error_d = NoError; // clear recoverable soft errors.
                     ==>
236                  state_d = ReadSt;
237                  tlul_gnt_o = 1'b1;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              ///////////////////////////////////////////////////////////////////
241              // If the address is out of bounds, or if the partition is
242              // locked, signal back a bus error. Note that such an error does
243              // not cause the partition to go into error state. Otherwise if
244              // these checks pass, an OTP word is requested.
245              ReadSt: begin
246                init_done_o = 1'b1;
247                // Double check the address range.
248                if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin
                   -9-  
249                  otp_req_o = 1'b1;
250                  otp_addr_sel = DataAddrSel;
251                  if (otp_gnt_i) begin
                     -10-  
252                    state_d = ReadWaitSt;
                       ==>
253                  end
                     MISSING_ELSE
                     ==>
254                end else begin
255                  state_d = IdleSt;
                     ==>
256                  error_d = AccessError; // Signal this error, but do not go into terminal error state.
257                  tlul_rvalid_o = 1'b1;
258                  tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error.
259                end
260              end
261              ///////////////////////////////////////////////////////////////////
262              // Wait for OTP response and release the TL-UL response. In
263              // case an OTP transaction fails, latch the OTP error code,
264              // signal a TL-Ul bus error and jump to a terminal error state.
265              ReadWaitSt: begin
266                init_done_o = 1'b1;
267                if (otp_rvalid_i) begin
                   -11-  
268                  tlul_rvalid_o = 1'b1;
269                  if (otp_err inside {NoError, MacroEccCorrError}) begin
                     -12-  
270                    state_d = IdleSt;
271                    // At this point the only error that we could have gotten are correctable ECC errors.
272                    if (otp_err != NoError) begin
                       -13-  
273                      error_d = MacroEccCorrError;
                         ==>
274                    end
                       MISSING_ELSE
                       ==>
275                  end else begin
276                    state_d = ErrorSt;
                       ==>
277                    error_d = otp_err;
278                    // This causes the TL-UL adapter to return a bus error.
279                    tlul_rerror_o = 2'b11;
280                  end
281                end
                   MISSING_ELSE
                   ==>
282              end
283              ///////////////////////////////////////////////////////////////////
284              // Terminal Error State. This locks access to the partition.
285              // Make sure the partition signals an error state if no error
286              // code has been latched so far.
287              ErrorSt: begin
288                if (error_q == NoError) begin
                   -14-  
289                  error_d = FsmStateError;
                     ==>
290                end
                   MISSING_ELSE
                   ==>
291        
292                // Return bus errors if there are pending TL-UL requests.
293                if (pending_tlul_error_q) begin
                   -15-  
294                  tlul_rerror_o = 2'b11;
                     ==>
295                  tlul_rvalid_o = 1'b1;
296                end else if (tlul_req_i) begin
                            -16-  
297                  tlul_gnt_o = 1'b1;
                     ==>
298                  pending_tlul_error_d = 1'b1;
299                end
                   MISSING_ELSE
                   ==>
300              end
301              ///////////////////////////////////////////////////////////////////
302              // We should never get here. If we do (e.g. via a malicious
303              // glitch), error out immediately.
304              default: begin
305                state_d = ErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T11,T98,T83
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T151,T134,T114
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T4,T11
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T4,T11
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T4,T93,T119
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T129,T20,T128
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T36,T89,T99
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T4,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T180,T184,T181
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T4,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T6,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T14,T34
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T6,T14,T34
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T6,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T28

314            if (ecc_err) begin
               -1-  
315              state_d = ErrorSt;
316              if (state_q != ErrorSt) begin
                 -2-  
317                error_d = CheckFailError;
                   ==>
318              end
                 MISSING_ELSE
                 ==>
319            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T187,T193
1	0	Covered	T187,T193
0	-	Covered	T1,T2,T3

321            if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin
               -1-  
322              state_d = ErrorSt;
323              fsm_err_o = 1'b1;
324              if (state_q != ErrorSt) begin
                 -2-  
325                error_d = FsmStateError;
                   ==>
326              end
                 MISSING_ELSE
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T6,T11
1	0	Covered	T3,T6,T11
0	-	Covered	T1,T2,T3

461          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

464            if (!rst_ni) begin
               -1-  
465              error_q              <= NoError;
                 ==>
466              tlul_addr_q          <= '0;
467              pending_tlul_error_q <= 1'b0;
468            end else begin
469              error_q              <= error_d;
470              pending_tlul_error_q <= pending_tlul_error_d;
471              if (tlul_gnt_o) begin
                 -2-  
472                tlul_addr_q <= tlul_addr_d;
                   ==>
473              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T6,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	80791054	79962216	0	0
DigestKnown_A	80791054	79962216	0	0
DigestOffsetMustBeRepresentable_A	1123	1123	0	0
EccErrorState_A	80791054	6211	0	0
ErrorKnown_A	80791054	79962216	0	0
FsmStateKnown_A	80791054	79962216	0	0
InitDoneKnown_A	80791054	79962216	0	0
InitReadLocksPartition_A	80791054	17235596	0	0
InitWriteLocksPartition_A	80791054	17235596	0	0
OffsetMustBeBlockAligned_A	1123	1123	0	0
OtpAddrKnown_A	80791054	79962216	0	0
OtpCmdKnown_A	80791054	79962216	0	0
OtpErrorState_A	80791054	59	0	0
OtpReqKnown_A	80791054	79962216	0	0
OtpSizeKnown_A	80791054	79962216	0	0
OtpWdataKnown_A	80791054	79962216	0	0
ReadLockPropagation_A	80791054	16358415	0	0
SizeMustBeBlockAligned_A	1123	1123	0	0
TlulGntKnown_A	80791054	79962216	0	0
TlulRdataKnown_A	80791054	79962216	0	0
TlulReadOnReadLock_A	80791054	6598	0	0
TlulRerrorKnown_A	80791054	79962216	0	0
TlulRvalidKnown_A	80791054	79962216	0	0
WriteLockPropagation_A	80791054	1048575	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	80791054	15024454	0	0
u_state_regs_A	80791054	79962216	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	6211	0	0
T187	8108	2416	0	0
T193	0	3795	0	0
T210	40742	0	0	0
T211	15998	0	0	0
T212	38167	0	0	0
T213	341586	0	0	0
T214	16672	0	0	0
T215	118881	0	0	0
T216	306590	0	0	0
T217	14120	0	0	0
T218	15807	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	17235596	0	0
T1	5511	352	0	0
T2	12159	222	0	0
T3	13200	5034	0	0
T4	24822	4501	0	0
T6	7902	1726	0	0
T10	6437	240	0	0
T11	10342	4374	0	0
T12	7144	313	0	0
T13	13944	3299	0	0
T14	9797	4163	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	17235596	0	0
T1	5511	352	0	0
T2	12159	222	0	0
T3	13200	5034	0	0
T4	24822	4501	0	0
T6	7902	1726	0	0
T10	6437	240	0	0
T11	10342	4374	0	0
T12	7144	313	0	0
T13	13944	3299	0	0
T14	9797	4163	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	59	0	0
T7	15632	0	0	0
T19	3897	0	0	0
T92	67704	0	0	0
T93	46637	0	0	0
T114	0	1	0	0
T129	37784	0	0	0
T133	20949	0	0	0
T134	15276	1	0	0
T136	24384	0	0	0
T137	12389	0	0	0
T151	13553	1	0	0
T180	0	1	0	0
T181	0	2	0	0
T184	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	0	1	0	0
T224	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	16358415	0	0
T7	15632	0	0	0
T19	3897	0	0	0
T20	0	18381	0	0
T21	0	786	0	0
T22	0	8002	0	0
T34	22758	0	0	0
T35	19639	0	0	0
T36	0	12393	0	0
T89	0	5196	0	0
T92	67704	0	0	0
T95	25198	1494	0	0
T119	0	1206	0	0
T128	0	15985	0	0
T129	0	3386	0	0
T135	11155	0	0	0
T136	24384	0	0	0
T137	12389	0	0	0
T151	13553	0	0	0
T166	0	7919	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123	1123	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	6598	0	0
T4	24822	0	0	0
T5	23415	0	0	0
T6	7902	2	0	0
T7	0	7	0	0
T8	0	20	0	0
T9	0	9	0	0
T11	10342	0	0	0
T12	7144	0	0	0
T13	13944	0	0	0
T14	9797	1	0	0
T20	0	1	0	0
T34	22758	1	0	0
T36	0	1	0	0
T95	25198	0	0	0
T128	0	2	0	0
T129	0	1	0	0
T135	11155	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	1048575	0	0
T7	15632	0	0	0
T18	0	1561	0	0
T19	3897	0	0	0
T34	22758	0	0	0
T35	19639	0	0	0
T92	67704	0	0	0
T95	25198	2364	0	0
T102	0	17414	0	0
T123	0	11851	0	0
T125	0	19552	0	0
T132	0	6392	0	0
T135	11155	0	0	0
T136	24384	0	0	0
T137	12389	0	0	0
T151	13553	0	0	0
T181	0	5810	0	0
T227	0	10840	0	0
T228	0	6177	0	0
T235	0	5473	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	15024454	0	0
T7	15632	0	0	0
T18	0	59740	0	0
T19	3897	0	0	0
T34	22758	0	0	0
T35	19639	0	0	0
T89	0	42755	0	0
T92	67704	0	0	0
T95	25198	18099	0	0
T102	0	113415	0	0
T114	0	2644	0	0
T119	0	18605	0	0
T121	0	90875	0	0
T129	0	24956	0	0
T134	0	3772	0	0
T135	11155	0	0	0
T136	24384	0	0	0
T137	12389	0	0	0
T151	13553	3443	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80791054	79962216	0	0
T1	5511	5429	0	0
T2	12159	11922	0	0
T3	13200	12922	0	0
T4	24822	24547	0	0
T6	7902	7656	0	0
T10	6437	6378	0	0
T11	10342	10017	0	0
T12	7144	7084	0	0
T13	13944	13782	0	0
T14	9797	9565	0	0