Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4282742	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2430485

1

T1

9

T2

230

T3

497

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5633444	1			T1	4		T2	427		T3	1012
values[0x0]	506566	1			T1	8		T2	141		T3	66
values[0x1]	573217	1			T1	7		T2	144		T3	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3155956	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3557271

1

T1

11

T2

342

T3

642

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32817	1			T2	3		T6	27		T8	37
valid_sources[0x01]	21750	1			T2	4		T6	4		T8	41
valid_sources[0x02]	20539	1			T2	2		T6	9		T8	44
valid_sources[0x03]	20357	1			T2	6		T5	34		T6	14
valid_sources[0x04]	21193	1			T6	8		T12	14		T8	37
valid_sources[0x05]	20601	1			T2	2		T6	17		T8	27
valid_sources[0x06]	22160	1			T2	2		T6	4		T8	51
valid_sources[0x07]	25068	1			T2	2		T6	7		T12	1
valid_sources[0x08]	19758	1			T2	1		T6	6		T8	57
valid_sources[0x09]	38099	1			T2	4		T7	5819		T6	3
valid_sources[0x0a]	45778	1			T2	1		T5	72		T6	13
valid_sources[0x0b]	22490	1			T6	16		T8	43		T85	1
valid_sources[0x0c]	22810	1			T2	1		T6	17		T8	27
valid_sources[0x0d]	24510	1			T2	5		T6	9		T8	26
valid_sources[0x0e]	22013	1			T2	2		T6	35		T8	51
valid_sources[0x0f]	21264	1			T2	2		T6	15		T8	38
valid_sources[0x10]	32322	1			T2	8		T6	6		T12	4
valid_sources[0x11]	20378	1			T2	2		T6	3		T8	48
valid_sources[0x12]	20629	1			T6	4		T8	31		T85	3
valid_sources[0x13]	21009	1			T2	4		T6	12		T8	25
valid_sources[0x14]	20417	1			T2	4		T6	9		T8	25
valid_sources[0x15]	22728	1			T6	5		T8	24		T85	2
valid_sources[0x16]	25102	1			T2	1		T6	4		T12	3
valid_sources[0x17]	19861	1			T2	8		T6	13		T8	25
valid_sources[0x18]	20532	1			T1	5		T2	5		T6	5
valid_sources[0x19]	20468	1			T2	3		T6	3		T8	36
valid_sources[0x1a]	86435	1			T2	3		T6	20		T8	27
valid_sources[0x1b]	21588	1			T2	2		T6	14		T8	41
valid_sources[0x1c]	21322	1			T2	1		T6	8		T8	31
valid_sources[0x1d]	20023	1			T2	1		T6	6		T8	42
valid_sources[0x1e]	41986	1			T2	1		T6	13		T12	2
valid_sources[0x1f]	22574	1			T6	15		T12	2		T8	36
valid_sources[0x20]	71228	1			T6	7		T12	3		T8	34
valid_sources[0x21]	22801	1			T2	3		T6	4		T12	5
valid_sources[0x22]	20083	1			T2	3		T6	12		T8	28
valid_sources[0x23]	24169	1			T2	1		T6	10		T8	42
valid_sources[0x24]	21757	1			T2	3		T6	16		T12	2
valid_sources[0x25]	20490	1			T6	8		T8	36		T85	2
valid_sources[0x26]	21480	1			T1	3		T2	1		T6	7
valid_sources[0x27]	26229	1			T2	1		T6	14		T12	1
valid_sources[0x28]	33094	1			T2	1		T5	13		T6	21
valid_sources[0x29]	23181	1			T2	2		T5	9		T6	13
valid_sources[0x2a]	22484	1			T2	1		T6	7		T8	26
valid_sources[0x2b]	25944	1			T2	2		T6	23		T8	41
valid_sources[0x2c]	23708	1			T2	1		T6	5		T8	49
valid_sources[0x2d]	78372	1			T2	4		T6	2		T8	32
valid_sources[0x2e]	39210	1			T2	2		T6	15		T8	53
valid_sources[0x2f]	23630	1			T6	9		T8	42		T85	3
valid_sources[0x30]	38184	1			T2	4		T6	11		T8	36
valid_sources[0x31]	27472	1			T2	1		T6	2		T8	45
valid_sources[0x32]	24280	1			T2	3		T6	7		T8	44
valid_sources[0x33]	21303	1			T1	1		T2	4		T6	4
valid_sources[0x34]	26151	1			T2	3		T5	24		T6	23
valid_sources[0x35]	19912	1			T2	4		T6	12		T8	23
valid_sources[0x36]	19854	1			T2	1		T6	16		T8	52
valid_sources[0x37]	96272	1			T2	4		T5	27		T6	9
valid_sources[0x38]	33335	1			T2	1		T6	2		T12	10
valid_sources[0x39]	35979	1			T2	1		T6	23		T8	26
valid_sources[0x3a]	22942	1			T2	2		T6	2		T8	37
valid_sources[0x3b]	22583	1			T2	1		T6	11		T8	59
valid_sources[0x3c]	20323	1			T2	5		T6	5		T12	5
valid_sources[0x3d]	38096	1			T2	3		T5	16		T6	5
valid_sources[0x3e]	46284	1			T2	2		T6	17		T8	54
valid_sources[0x3f]	24931	1			T2	2		T5	164		T6	17
valid_sources[0x40]	21215	1			T2	7		T5	24		T6	18
valid_sources[0x41]	20356	1			T2	6		T6	16		T8	29
valid_sources[0x42]	21137	1			T6	2		T8	40		T85	5
valid_sources[0x43]	37257	1			T2	3		T5	18		T6	20
valid_sources[0x44]	41919	1			T2	1		T6	2		T8	36
valid_sources[0x45]	48248	1			T2	1		T6	10		T8	31
valid_sources[0x46]	21342	1			T2	4		T6	22		T8	40
valid_sources[0x47]	24902	1			T2	6		T5	30		T6	1
valid_sources[0x48]	23230	1			T2	1		T6	3		T12	1
valid_sources[0x49]	29334	1			T6	6		T8	33		T85	1
valid_sources[0x4a]	24076	1			T2	8		T6	17		T8	37
valid_sources[0x4b]	23802	1			T2	5		T6	5		T8	46
valid_sources[0x4c]	24010	1			T2	1		T6	3		T8	32
valid_sources[0x4d]	25464	1			T2	5		T6	21		T12	4
valid_sources[0x4e]	20790	1			T2	4		T6	6		T8	30
valid_sources[0x4f]	21400	1			T2	6		T6	5		T8	48
valid_sources[0x50]	20318	1			T2	3		T6	11		T8	31
valid_sources[0x51]	27531	1			T2	3		T6	15		T12	4
valid_sources[0x52]	21817	1			T2	2		T6	11		T8	46
valid_sources[0x53]	84392	1			T2	3		T6	16		T8	45
valid_sources[0x54]	20649	1			T2	1		T6	12		T8	35
valid_sources[0x55]	22921	1			T2	2		T6	4		T12	2
valid_sources[0x56]	23977	1			T2	1		T5	2		T6	6
valid_sources[0x57]	26964	1			T2	1		T6	6		T12	2
valid_sources[0x58]	21451	1			T2	3		T6	10		T8	35
valid_sources[0x59]	23893	1			T1	1		T2	2		T8	23
valid_sources[0x5a]	21167	1			T2	1		T5	59		T6	16
valid_sources[0x5b]	20078	1			T6	5		T8	31		T85	2
valid_sources[0x5c]	34165	1			T2	2		T5	5		T6	2
valid_sources[0x5d]	25765	1			T2	4		T6	1		T8	59
valid_sources[0x5e]	21401	1			T2	1		T6	7		T8	31
valid_sources[0x5f]	20706	1			T2	5		T6	9		T8	39
valid_sources[0x60]	33836	1			T1	1		T2	1		T6	15
valid_sources[0x61]	36348	1			T2	5		T5	59		T6	3
valid_sources[0x62]	23149	1			T2	2		T6	11		T8	32
valid_sources[0x63]	20822	1			T2	1		T6	11		T8	42
valid_sources[0x64]	22199	1			T2	10		T6	15		T12	3
valid_sources[0x65]	35112	1			T2	1		T5	48		T6	10
valid_sources[0x66]	21705	1			T2	3		T5	41		T6	1
valid_sources[0x67]	19881	1			T2	8		T6	19		T8	34
valid_sources[0x68]	22379	1			T2	1		T6	6		T8	35
valid_sources[0x69]	21855	1			T5	17		T6	4		T12	1
valid_sources[0x6a]	29452	1			T2	1		T6	3		T12	7
valid_sources[0x6b]	20912	1			T6	5		T12	4		T8	44
valid_sources[0x6c]	25020	1			T2	4		T6	7		T8	33
valid_sources[0x6d]	20142	1			T2	1		T6	7		T8	47
valid_sources[0x6e]	20497	1			T2	6		T6	8		T12	7
valid_sources[0x6f]	21194	1			T6	7		T8	46		T85	6
valid_sources[0x70]	27630	1			T2	5		T6	5		T12	3
valid_sources[0x71]	23158	1			T2	2		T6	14		T8	27
valid_sources[0x72]	33455	1			T2	4		T5	14		T6	5
valid_sources[0x73]	26385	1			T6	14		T8	30		T85	4
valid_sources[0x74]	21655	1			T2	2		T6	11		T8	37
valid_sources[0x75]	20311	1			T2	1		T6	11		T8	49
valid_sources[0x76]	20257	1			T2	4		T6	10		T8	37
valid_sources[0x77]	31633	1			T2	5		T6	10		T12	1
valid_sources[0x78]	22084	1			T2	1		T6	14		T12	1
valid_sources[0x79]	20783	1			T2	2		T6	18		T12	3
valid_sources[0x7a]	29347	1			T2	3		T6	16		T8	33
valid_sources[0x7b]	23292	1			T2	1		T6	9		T8	26
valid_sources[0x7c]	24048	1			T2	1		T6	2		T12	1
valid_sources[0x7d]	23486	1			T2	1		T6	18		T8	42
valid_sources[0x7e]	19957	1			T2	1		T6	13		T8	38
valid_sources[0x7f]	20747	1			T2	1		T6	9		T8	30
valid_sources[0x80]	20242	1			T5	41		T6	15		T8	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1914403

1

T1

1

T2

127

T3

431

values[0x0]

all_enables

biggest_size

289017

1

T1

5

T2

56

T3

40

values[0x1]

all_enables

biggest_size

227065

1

T1

3

T2

47

T3

26

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26655	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

529947

1

T3

20

T4

80

T5

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	174805	1			T3	10		T4	40		T5	10
values[0x0]	185815	1			T3	4		T4	22		T5	8
values[0x1]	195982	1			T3	6		T4	18		T5	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14429	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

542173

1

T3

20

T4

80

T5

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2152	1			T6	6		T16	1		T18	1
valid_sources[0x01]	2167	1			T118	1		T106	2		T108	1
valid_sources[0x02]	1991	1			T16	1		T33	8		T107	1
valid_sources[0x03]	2019	1			T12	1		T90	1		T119	1
valid_sources[0x04]	2188	1			T31	11		T16	3		T111	1
valid_sources[0x05]	1845	1			T121	1		T18	1		T105	5
valid_sources[0x06]	1872	1			T90	1		T99	2		T33	3
valid_sources[0x07]	1881	1			T90	2		T31	1		T18	1
valid_sources[0x08]	1780	1			T16	4		T87	4		T33	2
valid_sources[0x09]	1977	1			T8	1		T89	4		T99	2
valid_sources[0x0a]	1716	1			T90	1		T92	1		T111	1
valid_sources[0x0b]	1993	1			T114	1		T13	42		T194	3
valid_sources[0x0c]	2632	1			T8	3		T31	1		T18	1
valid_sources[0x0d]	2331	1			T18	1		T106	2		T99	3
valid_sources[0x0e]	2114	1			T90	1		T119	1		T106	1
valid_sources[0x0f]	2020	1			T3	1		T106	4		T33	1
valid_sources[0x10]	2094	1			T18	1		T111	1		T106	1
valid_sources[0x11]	2647	1			T6	2		T90	1		T18	2
valid_sources[0x12]	2070	1			T219	2		T108	1		T286	1
valid_sources[0x13]	2229	1			T4	80		T6	3		T90	2
valid_sources[0x14]	2082	1			T90	3		T203	1		T14	17
valid_sources[0x15]	2014	1			T121	2		T92	1		T251	2
valid_sources[0x16]	2724	1			T90	1		T87	2		T120	1
valid_sources[0x17]	2753	1			T6	3		T90	1		T31	1
valid_sources[0x18]	2087	1			T6	7		T90	3		T13	2
valid_sources[0x19]	2412	1			T90	1		T105	8		T119	1
valid_sources[0x1a]	2193	1			T116	1		T105	3		T106	5
valid_sources[0x1b]	2483	1			T3	1		T87	5		T18	1
valid_sources[0x1c]	2319	1			T18	1		T92	1		T45	1
valid_sources[0x1d]	1925	1			T13	12		T167	8		T194	1
valid_sources[0x1e]	2204	1			T31	3		T87	3		T9	20
valid_sources[0x1f]	2660	1			T16	1		T14	19		T157	1
valid_sources[0x20]	2115	1			T87	1		T45	1		T33	4
valid_sources[0x21]	2058	1			T31	1		T18	4		T13	15
valid_sources[0x22]	3010	1			T16	1		T119	1		T99	3
valid_sources[0x23]	2064	1			T6	1		T16	1		T219	1
valid_sources[0x24]	2126	1			T45	2		T33	2		T108	2
valid_sources[0x25]	1907	1			T8	1		T45	2		T108	2
valid_sources[0x26]	2014	1			T12	2		T16	2		T45	1
valid_sources[0x27]	2215	1			T16	2		T116	5		T99	8
valid_sources[0x28]	1944	1			T16	2		T105	1		T111	1
valid_sources[0x29]	2206	1			T16	4		T87	1		T108	1
valid_sources[0x2a]	1814	1			T3	1		T16	1		T87	4
valid_sources[0x2b]	2392	1			T90	1		T16	1		T118	12
valid_sources[0x2c]	2841	1			T12	4		T111	1		T106	3
valid_sources[0x2d]	2044	1			T90	1		T31	1		T33	1
valid_sources[0x2e]	2153	1			T90	1		T16	1		T45	1
valid_sources[0x2f]	1971	1			T90	2		T16	1		T105	15
valid_sources[0x30]	2239	1			T33	1		T194	2		T14	16
valid_sources[0x31]	1855	1			T45	1		T219	1		T107	1
valid_sources[0x32]	2230	1			T16	1		T111	1		T45	1
valid_sources[0x33]	2044	1			T31	3		T106	3		T33	1
valid_sources[0x34]	2453	1			T106	1		T45	1		T251	2
valid_sources[0x35]	1869	1			T6	2		T31	2		T13	2
valid_sources[0x36]	1976	1			T90	1		T87	1		T121	1
valid_sources[0x37]	2152	1			T12	3		T90	1		T87	5
valid_sources[0x38]	1985	1			T119	1		T108	1		T13	2
valid_sources[0x39]	2064	1			T16	1		T111	1		T13	87
valid_sources[0x3a]	2209	1			T6	2		T45	1		T33	4
valid_sources[0x3b]	2433	1			T89	1		T16	4		T92	2
valid_sources[0x3c]	1983	1			T90	1		T89	3		T13	5
valid_sources[0x3d]	1989	1			T90	2		T31	1		T121	1
valid_sources[0x3e]	2299	1			T8	5		T31	2		T92	1
valid_sources[0x3f]	2176	1			T90	2		T31	3		T16	4
valid_sources[0x40]	2540	1			T90	1		T31	1		T120	1
valid_sources[0x41]	2512	1			T45	2		T108	2		T13	29
valid_sources[0x42]	2101	1			T6	5		T90	1		T99	7
valid_sources[0x43]	2317	1			T6	5		T31	3		T107	4
valid_sources[0x44]	2041	1			T31	2		T16	1		T106	4
valid_sources[0x45]	2394	1			T45	2		T286	1		T13	4
valid_sources[0x46]	2081	1			T87	2		T106	4		T251	1
valid_sources[0x47]	2274	1			T45	1		T33	1		T194	1
valid_sources[0x48]	2049	1			T6	4		T119	1		T45	1
valid_sources[0x49]	2321	1			T90	1		T121	1		T45	2
valid_sources[0x4a]	2836	1			T6	3		T119	1		T45	1
valid_sources[0x4b]	2222	1			T92	1		T45	3		T114	1
valid_sources[0x4c]	1857	1			T6	1		T87	1		T18	1
valid_sources[0x4d]	2073	1			T89	4		T87	1		T203	1
valid_sources[0x4e]	2427	1			T6	1		T16	3		T87	1
valid_sources[0x4f]	1947	1			T106	9		T108	1		T13	4
valid_sources[0x50]	2586	1			T31	1		T111	1		T33	1
valid_sources[0x51]	1997	1			T6	4		T90	1		T16	1
valid_sources[0x52]	2115	1			T6	3		T87	1		T111	1
valid_sources[0x53]	2190	1			T6	1		T90	1		T31	3
valid_sources[0x54]	2374	1			T106	4		T45	1		T107	1
valid_sources[0x55]	2429	1			T31	3		T45	2		T33	4
valid_sources[0x56]	2212	1			T90	2		T16	1		T92	1
valid_sources[0x57]	2046	1			T6	1		T18	1		T33	2
valid_sources[0x58]	2137	1			T90	3		T18	4		T105	8
valid_sources[0x59]	1840	1			T90	1		T89	1		T18	1
valid_sources[0x5a]	2020	1			T16	1		T87	1		T119	1
valid_sources[0x5b]	3425	1			T3	6		T92	1		T119	1
valid_sources[0x5c]	2055	1			T90	1		T16	1		T45	1
valid_sources[0x5d]	2192	1			T45	3		T251	1		T108	2
valid_sources[0x5e]	1964	1			T3	1		T31	3		T111	2
valid_sources[0x5f]	2111	1			T90	1		T111	1		T99	6
valid_sources[0x60]	2193	1			T87	1		T33	1		T13	4
valid_sources[0x61]	2378	1			T90	2		T31	4		T87	2
valid_sources[0x62]	2441	1			T8	1		T90	1		T31	5
valid_sources[0x63]	2237	1			T87	1		T121	1		T18	1
valid_sources[0x64]	1970	1			T18	2		T105	7		T99	1
valid_sources[0x65]	2026	1			T87	1		T119	1		T106	1
valid_sources[0x66]	2080	1			T90	1		T16	2		T105	8
valid_sources[0x67]	2113	1			T90	2		T106	3		T19	4
valid_sources[0x68]	2156	1			T6	1		T8	1		T33	3
valid_sources[0x69]	1981	1			T16	1		T18	1		T45	1
valid_sources[0x6a]	3052	1			T16	3		T251	1		T108	1
valid_sources[0x6b]	3040	1			T121	1		T106	2		T45	1
valid_sources[0x6c]	2183	1			T87	1		T13	2		T167	17
valid_sources[0x6d]	1842	1			T87	1		T92	1		T119	1
valid_sources[0x6e]	1911	1			T18	2		T105	7		T111	1
valid_sources[0x6f]	1998	1			T3	1		T6	1		T121	1
valid_sources[0x70]	1967	1			T99	1		T33	1		T108	1
valid_sources[0x71]	2014	1			T89	3		T87	2		T286	1
valid_sources[0x72]	1919	1			T90	1		T45	3		T219	1
valid_sources[0x73]	2043	1			T6	1		T90	1		T89	1
valid_sources[0x74]	2234	1			T111	1		T106	3		T108	1
valid_sources[0x75]	1951	1			T90	1		T31	3		T105	1
valid_sources[0x76]	2245	1			T90	2		T16	1		T99	1
valid_sources[0x77]	2068	1			T90	1		T92	1		T105	2
valid_sources[0x78]	3868	1			T31	6		T18	1		T45	2
valid_sources[0x79]	2167	1			T6	3		T12	1		T90	2
valid_sources[0x7a]	1905	1			T45	1		T203	2		T108	2
valid_sources[0x7b]	2181	1			T90	1		T31	1		T87	3
valid_sources[0x7c]	2118	1			T3	2		T18	1		T116	5
valid_sources[0x7d]	1869	1			T18	2		T45	2		T286	1
valid_sources[0x7e]	1881	1			T92	2		T45	2		T33	1
valid_sources[0x7f]	2129	1			T108	2		T13	138		T125	1
valid_sources[0x80]	2449	1			T90	1		T31	5		T105	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

161740

1

T3

10

T4

40

T5

10

values[0x0]

all_enables

biggest_size

184378

1

T3

4

T4

22

T5

8

values[0x1]

all_enables

biggest_size

183829

1

T3

6

T4

18

T5

2