Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5108388

1

T1

10

T2

482

T3

648

full_word

2480054

1

T1

9

T2

230

T3

497

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7588112	1			T1	19		T2	712		T3	1145
auto[TlIntgErrCmd]	95	1			T289	2		T290	2		T291	3
auto[TlIntgErrData]	123	1			T289	4		T290	6		T291	12
auto[TlIntgErrBoth]	112	1			T289	4		T290	2		T291	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5693942

1

T1

4

T2

427

T3

1012

auto[1]

1894500

1

T1

15

T2

285

T3

133

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3773395	1			T1	3		T2	300		T3	581
auto[TlIntgErrNone]	partial	auto[1]	1334686	1			T1	7		T2	182		T3	67
auto[TlIntgErrNone]	full_word	auto[0]	1920381	1			T1	1		T2	127		T3	431
auto[TlIntgErrNone]	full_word	auto[1]	559650	1			T1	8		T2	103		T3	66
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T289	1		T290	1		T291	1
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T289	1		T290	1		T291	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T379	1		T380	1		T381	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T290	3		T291	7		T382	3
auto[TlIntgErrData]	partial	auto[1]	53	1			T289	3		T290	2		T291	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T289	1		T290	1		T291	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T291	1		T383	1		T381	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T289	1		T290	2		T291	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T289	3		T291	2		T382	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T291	1		T384	1		T385	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T386	1		T384	1		T381	1