Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.98	94.16	95.24	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	89765363	380794	0	0
check_regwen_rd_A	89765363	1114	0	0
check_timeout_rd_A	89765363	803	0	0
check_trigger_regwen_rd_A	89765363	1072	0	0
consistency_check_period_rd_A	89765363	1119	0	0
creator_sw_cfg_read_lock_rd_A	89765363	663	0	0
direct_access_address_rd_A	89765363	394	0	0
direct_access_wdata_0_rd_A	89765363	51	0	0
direct_access_wdata_1_rd_A	89765363	71	0	0
integrity_check_period_rd_A	89765363	1181	0	0
intr_enable_rd_A	89765363	1965	0	0
owner_sw_cfg_read_lock_rd_A	89765363	616	0	0
rot_creator_auth_codesign_read_lock_rd_A	89765363	681	0	0
rot_creator_auth_state_read_lock_rd_A	89765363	513	0	0
vendor_test_read_lock_rd_A	89765363	705	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	380794	0	0
T13	138884	4616	0	0
T14	0	3927	0	0
T15	0	6767	0	0
T20	0	6454	0	0
T86	0	4695	0	0
T88	0	15672	0	0
T115	136070	0	0	0
T125	187327	0	0	0
T143	21835	0	0	0
T167	67708	0	0	0
T194	70872	0	0	0
T222	0	4911	0	0
T244	0	6780	0	0
T246	32004	0	0	0
T270	11609	0	0	0
T274	44738	0	0	0
T278	0	6028	0	0
T283	0	4460	0	0
T300	38630	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	1114	0	0
T21	0	13	0	0
T123	72692	0	0	0
T178	0	63	0	0
T222	247782	25	0	0
T243	762230	0	0	0
T338	0	12	0	0
T339	0	7	0	0
T340	0	18	0	0
T341	0	22	0	0
T342	0	24	0	0
T343	0	31	0	0
T344	0	32	0	0
T345	95731	0	0	0
T346	86085	0	0	0
T347	9351	0	0	0
T348	68460	0	0	0
T349	77224	0	0	0
T350	76788	0	0	0
T351	25775	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	803	0	0
T21	0	25	0	0
T123	72692	0	0	0
T178	0	73	0	0
T222	247782	22	0	0
T243	762230	0	0	0
T338	0	18	0	0
T339	0	12	0	0
T340	0	28	0	0
T341	0	32	0	0
T342	0	25	0	0
T343	0	54	0	0
T345	95731	0	0	0
T346	86085	0	0	0
T347	9351	0	0	0
T348	68460	0	0	0
T349	77224	0	0	0
T350	76788	0	0	0
T351	25775	0	0	0
T352	0	13	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	1072	0	0
T21	0	19	0	0
T123	72692	0	0	0
T178	0	34	0	0
T222	247782	26	0	0
T243	762230	0	0	0
T338	0	4	0	0
T339	0	27	0	0
T340	0	20	0	0
T341	0	11	0	0
T342	0	17	0	0
T343	0	41	0	0
T345	95731	0	0	0
T346	86085	0	0	0
T347	9351	0	0	0
T348	68460	0	0	0
T349	77224	0	0	0
T350	76788	0	0	0
T351	25775	0	0	0
T352	0	9	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	1119	0	0
T21	0	11	0	0
T123	72692	0	0	0
T178	0	46	0	0
T222	247782	20	0	0
T243	762230	0	0	0
T338	0	6	0	0
T339	0	24	0	0
T340	0	16	0	0
T341	0	12	0	0
T342	0	32	0	0
T343	0	36	0	0
T345	95731	0	0	0
T346	86085	0	0	0
T347	9351	0	0	0
T348	68460	0	0	0
T349	77224	0	0	0
T350	76788	0	0	0
T351	25775	0	0	0
T352	0	13	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	663	0	0
T21	0	28	0	0
T123	72692	0	0	0
T178	0	48	0	0
T222	247782	25	0	0
T243	762230	0	0	0
T338	0	10	0	0
T339	0	22	0	0
T340	0	19	0	0
T341	0	7	0	0
T342	0	10	0	0
T343	0	44	0	0
T345	95731	0	0	0
T346	86085	0	0	0
T347	9351	0	0	0
T348	68460	0	0	0
T349	77224	0	0	0
T350	76788	0	0	0
T351	25775	0	0	0
T352	0	32	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	394	0	0
T21	0	23	0	0
T123	72692	0	0	0
T178	0	55	0	0
T222	247782	12	0	0
T243	762230	0	0	0
T338	0	19	0	0
T339	0	16	0	0
T340	0	25	0	0
T341	0	23	0	0
T342	0	26	0	0
T343	0	61	0	0
T345	95731	0	0	0
T346	86085	0	0	0
T347	9351	0	0	0
T348	68460	0	0	0
T349	77224	0	0	0
T350	76788	0	0	0
T351	25775	0	0	0
T352	0	12	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	51	0	0
T178	502853	24	0	0
T179	28347	0	0	0
T180	175299	0	0	0
T181	78090	0	0	0
T182	5104	0	0	0
T342	0	5	0	0
T343	0	5	0	0
T344	0	6	0	0
T352	0	7	0	0
T353	0	4	0	0
T354	25791	0	0	0
T355	13281	0	0	0
T356	10787	0	0	0
T357	33376	0	0	0
T358	20294	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	71	0	0
T123	72692	0	0	0
T178	0	12	0	0
T222	247782	18	0	0
T243	762230	0	0	0
T339	0	7	0	0
T340	0	19	0	0
T342	0	2	0	0
T343	0	4	0	0
T344	0	3	0	0
T345	95731	0	0	0
T346	86085	0	0	0
T347	9351	0	0	0
T348	68460	0	0	0
T349	77224	0	0	0
T350	76788	0	0	0
T351	25775	0	0	0
T352	0	3	0	0
T359	0	2	0	0
T360	0	1	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	1181	0	0
T21	0	29	0	0
T123	72692	0	0	0
T178	0	30	0	0
T222	247782	27	0	0
T243	762230	0	0	0
T338	0	17	0	0
T339	0	18	0	0
T340	0	14	0	0
T341	0	25	0	0
T342	0	22	0	0
T343	0	43	0	0
T345	95731	0	0	0
T346	86085	0	0	0
T347	9351	0	0	0
T348	68460	0	0	0
T349	77224	0	0	0
T350	76788	0	0	0
T351	25775	0	0	0
T352	0	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	1965	0	0
T29	11752	0	0	0
T55	47580	0	0	0
T130	608529	18	0	0
T135	0	37	0	0
T159	81224	0	0	0
T178	0	82	0	0
T222	0	40	0	0
T275	0	10	0	0
T287	16104	0	0	0
T338	0	8	0	0
T361	0	21	0	0
T362	0	14	0	0
T363	0	11	0	0
T364	0	33	0	0
T365	22588	0	0	0
T366	4584	0	0	0
T367	125382	0	0	0
T368	88790	0	0	0
T369	119664	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	616	0	0
T21	0	17	0	0
T123	72692	0	0	0
T178	0	55	0	0
T222	247782	18	0	0
T243	762230	0	0	0
T338	0	27	0	0
T339	0	17	0	0
T340	0	19	0	0
T341	0	13	0	0
T342	0	19	0	0
T343	0	54	0	0
T345	95731	0	0	0
T346	86085	0	0	0
T347	9351	0	0	0
T348	68460	0	0	0
T349	77224	0	0	0
T350	76788	0	0	0
T351	25775	0	0	0
T352	0	1	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	681	0	0
T21	0	29	0	0
T123	72692	0	0	0
T178	0	30	0	0
T222	247782	35	0	0
T243	762230	0	0	0
T338	0	10	0	0
T339	0	19	0	0
T340	0	40	0	0
T341	0	14	0	0
T342	0	34	0	0
T343	0	42	0	0
T345	95731	0	0	0
T346	86085	0	0	0
T347	9351	0	0	0
T348	68460	0	0	0
T349	77224	0	0	0
T350	76788	0	0	0
T351	25775	0	0	0
T352	0	11	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	513	0	0
T21	0	18	0	0
T123	72692	0	0	0
T178	0	31	0	0
T222	247782	15	0	0
T243	762230	0	0	0
T338	0	2	0	0
T339	0	14	0	0
T340	0	24	0	0
T341	0	25	0	0
T342	0	17	0	0
T343	0	38	0	0
T345	95731	0	0	0
T346	86085	0	0	0
T347	9351	0	0	0
T348	68460	0	0	0
T349	77224	0	0	0
T350	76788	0	0	0
T351	25775	0	0	0
T352	0	9	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89765363	705	0	0
T21	0	21	0	0
T123	72692	0	0	0
T178	0	49	0	0
T222	247782	27	0	0
T243	762230	0	0	0
T338	0	13	0	0
T339	0	19	0	0
T340	0	18	0	0
T341	0	12	0	0
T342	0	27	0	0
T343	0	59	0	0
T345	95731	0	0	0
T346	86085	0	0	0
T347	9351	0	0	0
T348	68460	0	0	0
T349	77224	0	0	0
T350	76788	0	0	0
T351	25775	0	0	0
T352	0	19	0	0