Module Definition
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Module Instance : tb.dut.u_prim_lc_sender_otp_broadcast_valid

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.98 94.16 95.24 96.92 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sender_test_tokens_valid

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.98 94.16 95.24 96.92 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_no_flops.gen_bits[0].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[1].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[2].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sender_rma_token_valid

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.98 94.16 95.24 96.92 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_no_flops.gen_bits[0].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[1].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[2].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sender_secrets_valid

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.98 94.16 95.24 96.92 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_no_flops.gen_bits[0].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[1].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[2].u_prim_buf 100.00 100.00
gen_no_flops.gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_lc_sender ( parameter AsyncOn=1,ResetValueIsOn=0,ResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sender_otp_broadcast_valid

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 

Line Coverage for Module : prim_lc_sender ( parameter AsyncOn=0,ResetValueIsOn=0,ResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sender_test_tokens_valid

SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sender_rma_token_valid

SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sender_secrets_valid

Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN3211100.00
ALWAYS5833100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T1 T2 T3  59 1/1 unused_logic <= lc_ctrl_pkg::Off; Tests: T1 T2 T3  60 end else begin 61 1/1 unused_logic <= lc_en_i; Tests: T1 T2 T3  62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 

Branch Coverage for Module : prim_lc_sender
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 58 2 2 100.00


58 if (!rst_ni) begin -1- 59 unused_logic <= lc_ctrl_pkg::Off; ==> 60 end else begin 61 unused_logic <= lc_en_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sender_otp_broadcast_valid
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_prim_lc_sender_test_tokens_valid
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN3211100.00
ALWAYS5833100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T1 T2 T3  59 1/1 unused_logic <= lc_ctrl_pkg::Off; Tests: T1 T2 T3  60 end else begin 61 1/1 unused_logic <= lc_en_i; Tests: T1 T2 T3  62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_prim_lc_sender_test_tokens_valid
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 58 2 2 100.00


58 if (!rst_ni) begin -1- 59 unused_logic <= lc_ctrl_pkg::Off; ==> 60 end else begin 61 unused_logic <= lc_en_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sender_rma_token_valid
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN3211100.00
ALWAYS5833100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T1 T2 T3  59 1/1 unused_logic <= lc_ctrl_pkg::Off; Tests: T1 T2 T3  60 end else begin 61 1/1 unused_logic <= lc_en_i; Tests: T1 T2 T3  62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_prim_lc_sender_rma_token_valid
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 58 2 2 100.00


58 if (!rst_ni) begin -1- 59 unused_logic <= lc_ctrl_pkg::Off; ==> 60 end else begin 61 unused_logic <= lc_en_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sender_secrets_valid
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN3211100.00
ALWAYS5833100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 1/1 if (!rst_ni) begin Tests: T1 T2 T3  59 1/1 unused_logic <= lc_ctrl_pkg::Off; Tests: T1 T2 T3  60 end else begin 61 1/1 unused_logic <= lc_en_i; Tests: T1 T2 T3  62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_prim_lc_sender_secrets_valid
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 58 2 2 100.00


58 if (!rst_ni) begin -1- 59 unused_logic <= lc_ctrl_pkg::Off; ==> 60 end else begin 61 unused_logic <= lc_en_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

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