Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	69.12			69.12
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	71.32			71.32
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	72.06			72.06
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	73.53			73.53
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	74.26			74.26
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	75.00			75.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	75.74			75.74
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	76.47			76.47
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	77.94			77.94
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	82.35			82.35
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	86.76			86.76
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.12			69.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.12			69.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.32			71.32

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.32			71.32

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.06			72.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.53			73.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.26			74.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.26			74.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.74			75.74

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.74			75.74

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.47			76.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.47			76.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.94			77.94

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.94			77.94

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.35			82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.35			82.35

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.76			86.76

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.76			86.76

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T85,T90,T31	Yes	T85,T90,T31	INPUT
data_o[63:0]	Yes	Yes	T85,T90,T31	Yes	T85,T90,T31	OUTPUT
syndrome_o[2:0]	Yes	Yes	T100,T101,T160	Yes	T100,T101,T160	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T100,*T101,*T160	Yes	T100,T101,T160	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	188	69.12
Total Bits 0->1	136	94	69.12
Total Bits 1->0	136	94	69.12

Ports	2	0	0.00
Port Bits	272	188	69.12
Port Bits 0->1	136	94	69.12
Port Bits 1->0	136	94	69.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[5:0]	Yes	Yes	T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[6]	No	No		No		INPUT
data_i[9:7]	Yes	Yes	T5,T89,T31	Yes	T5,T89,T31	INPUT
data_i[10]	No	No		No		INPUT
data_i[12:11]	Yes	Yes	T5,T89,T31	Yes	T5,T89,T31	INPUT
data_i[13]	No	No		No		INPUT
data_i[19:14]	Yes	Yes	*T5,T89,T31	Yes	T5,T89,T31	INPUT
data_i[20]	No	No		No		INPUT
data_i[22:21]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[25:23]	No	No		No		INPUT
data_i[27:26]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[28]	No	No		No		INPUT
data_i[30:29]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[31]	No	No		No		INPUT
data_i[33:32]	Yes	Yes	T89,T16,T87	Yes	T89,T16,T87	INPUT
data_i[35:34]	No	No		No		INPUT
data_i[37:36]	Yes	Yes	T89,T16,T87	Yes	T89,T16,T87	INPUT
data_i[39:38]	No	No		No		INPUT
data_i[42:40]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[43]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[47]	No	No		No		INPUT
data_i[48]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[50:49]	No	No		No		INPUT
data_i[54:51]	Yes	Yes	T89,T16,T87	Yes	T89,T16,T87	INPUT
data_i[55]	No	No		No		INPUT
data_i[56]	Yes	Yes	*T89,*T16,*T87	Yes	T89,T16,T87	INPUT
data_i[57]	No	No		No		INPUT
data_i[61:58]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[63:62]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T6,T12,T89	Yes	T3,T6,T12	INPUT
data_o[5:0]	Yes	Yes	T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[9:7]	Yes	Yes	T5,T89,T31	Yes	T5,T89,T31	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[12:11]	Yes	Yes	T5,T89,T31	Yes	T5,T89,T31	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[19:14]	Yes	Yes	*T5,T89,T31	Yes	T5,T89,T31	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[22:21]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[25:23]	No	No		No		OUTPUT
data_o[27:26]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[30:29]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[33:32]	Yes	Yes	T89,T16,T87	Yes	T89,T16,T87	OUTPUT
data_o[35:34]	No	No		No		OUTPUT
data_o[37:36]	Yes	Yes	T89,T16,T87	Yes	T89,T16,T87	OUTPUT
data_o[39:38]	No	No		No		OUTPUT
data_o[42:40]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[48]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[50:49]	No	No		No		OUTPUT
data_o[54:51]	Yes	Yes	T89,T16,T87	Yes	T89,T16,T87	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[56]	Yes	Yes	*T89,*T16,*T87	Yes	T89,T16,T87	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[61:58]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[63:62]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	194	71.32
Total Bits 0->1	136	97	71.32
Total Bits 1->0	136	97	71.32

Ports	2	0	0.00
Port Bits	272	194	71.32
Port Bits 0->1	136	97	71.32
Port Bits 1->0	136	97	71.32

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T5,*T6,*T89	Yes	T3,T5,T6	INPUT
data_i[1]	No	No		No		INPUT
data_i[4:2]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	INPUT
data_i[6:5]	No	No		No		INPUT
data_i[8:7]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	INPUT
data_i[9]	No	No		No		INPUT
data_i[12:10]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	INPUT
data_i[14:13]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T5,*T6,*T89	Yes	T3,T5,T6	INPUT
data_i[16]	No	No		No		INPUT
data_i[17]	Yes	Yes	*T5,*T6,*T31	Yes	T3,T5,T6	INPUT
data_i[18]	No	No		No		INPUT
data_i[22:19]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[23]	No	No		No		INPUT
data_i[24]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[25]	No	No		No		INPUT
data_i[28:26]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[29]	No	No		No		INPUT
data_i[30]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[31]	No	No		No		INPUT
data_i[32]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[33]	No	No		No		INPUT
data_i[38:34]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[39]	No	No		No		INPUT
data_i[45:40]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[46]	No	No		No		INPUT
data_i[48:47]	Yes	Yes	T5,T6,T31	Yes	T3,T5,T6	INPUT
data_i[49]	No	No		No		INPUT
data_i[50]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[51]	No	No		No		INPUT
data_i[53:52]	Yes	Yes	T5,T6,T31	Yes	T3,T5,T6	INPUT
data_i[55:54]	No	No		No		INPUT
data_i[68:56]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[69]	No	No		No		INPUT
data_i[71:70]	Yes	Yes	T12,T89,T31	Yes	T12,T89,T31	INPUT
data_o[0]	Yes	Yes	*T5,*T6,*T89	Yes	T3,T5,T6	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[4:2]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	OUTPUT
data_o[6:5]	No	No		No		OUTPUT
data_o[8:7]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[12:10]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	OUTPUT
data_o[14:13]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T5,*T6,*T89	Yes	T3,T5,T6	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[17]	Yes	Yes	*T5,*T6,*T31	Yes	T3,T5,T6	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[22:19]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[24]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[28:26]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[30]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[32]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[38:34]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[45:40]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[48:47]	Yes	Yes	T5,T6,T31	Yes	T3,T5,T6	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[50]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[53:52]	Yes	Yes	T5,T6,T31	Yes	T3,T5,T6	OUTPUT
data_o[55:54]	No	No		No		OUTPUT
data_o[63:56]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	196	72.06
Total Bits 0->1	136	98	72.06
Total Bits 1->0	136	98	72.06

Ports	2	0	0.00
Port Bits	272	196	72.06
Port Bits 0->1	136	98	72.06
Port Bits 1->0	136	98	72.06

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[3:0]	No	No		No		INPUT
data_i[9:4]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[10]	No	No		No		INPUT
data_i[15:11]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[16]	No	No		No		INPUT
data_i[19:17]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[21:20]	No	No		No		INPUT
data_i[30:22]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[32:31]	No	No		No		INPUT
data_i[39:33]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[40]	No	No		No		INPUT
data_i[46:41]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[47]	No	No		No		INPUT
data_i[48]	Yes	Yes	*T5,*T6,*T89	Yes	T3,T5,T6	INPUT
data_i[50:49]	No	No		No		INPUT
data_i[52:51]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[54:53]	No	No		No		INPUT
data_i[55]	Yes	Yes	*T5,*T6,*T89	Yes	T3,T5,T6	INPUT
data_i[57:56]	No	No		No		INPUT
data_i[64:58]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[65]	No	No		No		INPUT
data_i[68:66]	Yes	Yes	T121,*T117,*T45	Yes	T110,T121,T117	INPUT
data_i[69]	No	No		No		INPUT
data_i[71:70]	Yes	Yes	T121,T117,T45	Yes	T110,T121,T117	INPUT
data_o[3:0]	No	No		No		OUTPUT
data_o[9:4]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[15:11]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[19:17]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[21:20]	No	No		No		OUTPUT
data_o[30:22]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[32:31]	No	No		No		OUTPUT
data_o[39:33]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[46:41]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[48]	Yes	Yes	*T5,*T6,*T89	Yes	T3,T5,T6	OUTPUT
data_o[50:49]	No	No		No		OUTPUT
data_o[52:51]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[54:53]	No	No		No		OUTPUT
data_o[55]	Yes	Yes	*T5,*T6,*T89	Yes	T3,T5,T6	OUTPUT
data_o[57:56]	No	No		No		OUTPUT
data_o[63:58]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	200	73.53
Total Bits 0->1	136	100	73.53
Total Bits 1->0	136	100	73.53

Ports	2	0	0.00
Port Bits	272	200	73.53
Port Bits 0->1	136	100	73.53
Port Bits 1->0	136	100	73.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[2:1]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	INPUT
data_i[3]	No	No		No		INPUT
data_i[4]	Yes	Yes	*T6,*T31,*T16	Yes	T3,T6,T31	INPUT
data_i[5]	No	No		No		INPUT
data_i[11:6]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[12]	No	No		No		INPUT
data_i[16:13]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[17]	No	No		No		INPUT
data_i[22:18]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[23]	No	No		No		INPUT
data_i[25:24]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	INPUT
data_i[26]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T6,*T31,*T16	Yes	T3,T6,T31	INPUT
data_i[28]	No	No		No		INPUT
data_i[30:29]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	INPUT
data_i[32:31]	No	No		No		INPUT
data_i[34:33]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	INPUT
data_i[36:35]	No	No		No		INPUT
data_i[38:37]	Yes	Yes	*T2,*T6,*T31	Yes	T2,T3,T6	INPUT
data_i[39]	No	No		No		INPUT
data_i[40]	Yes	Yes	*T6,*T31,*T16	Yes	T3,T6,T31	INPUT
data_i[41]	No	No		No		INPUT
data_i[45:42]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	INPUT
data_i[46]	No	No		No		INPUT
data_i[50:47]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[51]	No	No		No		INPUT
data_i[57:52]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[58]	No	No		No		INPUT
data_i[62:59]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T5,T12,T89	Yes	T5,T12,T89	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[2:1]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[4]	Yes	Yes	*T6,*T31,*T16	Yes	T3,T6,T31	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[11:6]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[16:13]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[22:18]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[25:24]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T6,*T31,*T16	Yes	T3,T6,T31	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[30:29]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	OUTPUT
data_o[32:31]	No	No		No		OUTPUT
data_o[34:33]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	OUTPUT
data_o[36:35]	No	No		No		OUTPUT
data_o[38:37]	Yes	Yes	*T2,*T6,*T31	Yes	T2,T3,T6	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[40]	Yes	Yes	*T6,*T31,*T16	Yes	T3,T6,T31	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[45:42]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[50:47]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[57:52]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[62:59]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	202	74.26
Total Bits 0->1	136	101	74.26
Total Bits 1->0	136	101	74.26

Ports	2	0	0.00
Port Bits	272	202	74.26
Port Bits 0->1	136	101	74.26
Port Bits 1->0	136	101	74.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[2:0]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	INPUT
data_i[3]	No	No		No		INPUT
data_i[9:4]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	INPUT
data_i[12:10]	No	No		No		INPUT
data_i[18:13]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	INPUT
data_i[19]	No	No		No		INPUT
data_i[24:20]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	INPUT
data_i[26:25]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[29]	No	No		No		INPUT
data_i[30]	Yes	Yes	*T5,*T6,*T89	Yes	T5,T6,T89	INPUT
data_i[31]	No	No		No		INPUT
data_i[33:32]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[34]	No	No		No		INPUT
data_i[38:35]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	INPUT
data_i[39]	No	No		No		INPUT
data_i[43:40]	Yes	Yes	*T129,*T5,*T6	Yes	T129,T3,T5	INPUT
data_i[44]	No	No		No		INPUT
data_i[49:45]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	INPUT
data_i[52:50]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[55]	No	No		No		INPUT
data_i[62:56]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[63]	No	No		No		INPUT
data_i[70:64]	Yes	Yes	*T6,*T118,*T45	Yes	T6,T118,T45	INPUT
data_i[71]	No	No		No		INPUT
data_o[2:0]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[9:4]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	OUTPUT
data_o[12:10]	No	No		No		OUTPUT
data_o[18:13]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[24:20]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	OUTPUT
data_o[26:25]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[30]	Yes	Yes	*T5,*T6,*T89	Yes	T5,T6,T89	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[33:32]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[38:35]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[43:40]	Yes	Yes	*T129,*T5,*T6	Yes	T129,T3,T5	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[49:45]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	OUTPUT
data_o[52:50]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[62:56]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	204	75.00
Total Bits 0->1	136	102	75.00
Total Bits 1->0	136	102	75.00

Ports	2	0	0.00
Port Bits	272	204	75.00
Port Bits 0->1	136	102	75.00
Port Bits 1->0	136	102	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[3:0]	Yes	Yes	*T5,*T6,*T31	Yes	T3,T5,T6	INPUT
data_i[4]	No	No		No		INPUT
data_i[5]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[6]	No	No		No		INPUT
data_i[13:7]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[14]	No	No		No		INPUT
data_i[17:15]	Yes	Yes	T5,T6,T31	Yes	T3,T5,T6	INPUT
data_i[19:18]	No	No		No		INPUT
data_i[21:20]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[22]	No	No		No		INPUT
data_i[24:23]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[25]	No	No		No		INPUT
data_i[33:26]	Yes	Yes	T5,T6,T31	Yes	T3,T5,T6	INPUT
data_i[34]	No	No		No		INPUT
data_i[37:35]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[38]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[40]	No	No		No		INPUT
data_i[45:41]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[47:46]	No	No		No		INPUT
data_i[48]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[49]	No	No		No		INPUT
data_i[53:50]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[55:54]	No	No		No		INPUT
data_i[59:56]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	INPUT
data_i[61:60]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	INPUT
data_o[3:0]	Yes	Yes	*T5,*T6,*T31	Yes	T3,T5,T6	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[5]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[13:7]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[17:15]	Yes	Yes	T5,T6,T31	Yes	T3,T5,T6	OUTPUT
data_o[19:18]	No	No		No		OUTPUT
data_o[21:20]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[24:23]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[33:26]	Yes	Yes	T5,T6,T31	Yes	T3,T5,T6	OUTPUT
data_o[34]	No	No		No		OUTPUT
data_o[37:35]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[45:41]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[47:46]	No	No		No		OUTPUT
data_o[48]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[53:50]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[55:54]	No	No		No		OUTPUT
data_o[59:56]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	OUTPUT
data_o[61:60]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	206	75.74
Total Bits 0->1	136	103	75.74
Total Bits 1->0	136	103	75.74

Ports	2	0	0.00
Port Bits	272	206	75.74
Port Bits 0->1	136	103	75.74
Port Bits 1->0	136	103	75.74

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[2:1]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[3]	No	No		No		INPUT
data_i[12:4]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[14:13]	No	No		No		INPUT
data_i[18:15]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[20:19]	No	No		No		INPUT
data_i[23:21]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[24]	No	No		No		INPUT
data_i[26:25]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[28:27]	No	No		No		INPUT
data_i[37:29]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[38]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[41:40]	No	No		No		INPUT
data_i[48:42]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[49]	No	No		No		INPUT
data_i[59:50]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[62:60]	No	No		No		INPUT
data_i[67:63]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[68]	No	No		No		INPUT
data_i[71:69]	Yes	Yes	T3,T5,T6	Yes	T5,T6,T12	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[2:1]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[12:4]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[14:13]	No	No		No		OUTPUT
data_o[18:15]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[20:19]	No	No		No		OUTPUT
data_o[23:21]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[26:25]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[28:27]	No	No		No		OUTPUT
data_o[37:29]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[41:40]	No	No		No		OUTPUT
data_o[48:42]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[59:50]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[62:60]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	208	76.47
Total Bits 0->1	136	104	76.47
Total Bits 1->0	136	104	76.47

Ports	2	0	0.00
Port Bits	272	208	76.47
Port Bits 0->1	136	104	76.47
Port Bits 1->0	136	104	76.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[4:1]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	INPUT
data_i[7:5]	No	No		No		INPUT
data_i[8]	Yes	Yes	*T5,*T6,*T89	Yes	T5,T6,T89	INPUT
data_i[9]	No	No		No		INPUT
data_i[16:10]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	INPUT
data_i[17]	No	No		No		INPUT
data_i[19:18]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[20]	No	No		No		INPUT
data_i[30:21]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[31]	No	No		No		INPUT
data_i[35:32]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[36]	No	No		No		INPUT
data_i[37]	Yes	Yes	*T5,*T6,*T89	Yes	T5,T6,T89	INPUT
data_i[38]	No	No		No		INPUT
data_i[43:39]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[44]	No	No		No		INPUT
data_i[50:45]	Yes	Yes	T5,*T6,T89	Yes	T5,T6,T89	INPUT
data_i[51]	No	No		No		INPUT
data_i[54:52]	Yes	Yes	T5,T89,T31	Yes	T5,T89,T31	INPUT
data_i[55]	No	No		No		INPUT
data_i[57:56]	Yes	Yes	T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[58]	No	No		No		INPUT
data_i[59]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[61:60]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[4:1]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	OUTPUT
data_o[7:5]	No	No		No		OUTPUT
data_o[8]	Yes	Yes	*T5,*T6,*T89	Yes	T5,T6,T89	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[16:10]	Yes	Yes	T5,T6,T89	Yes	T5,T6,T89	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[19:18]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[30:21]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[35:32]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[37]	Yes	Yes	*T5,*T6,*T89	Yes	T5,T6,T89	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[43:39]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[50:45]	Yes	Yes	T5,*T6,T89	Yes	T5,T6,T89	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[54:52]	Yes	Yes	T5,T89,T31	Yes	T5,T89,T31	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[57:56]	Yes	Yes	T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[59]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[61:60]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	212	77.94
Total Bits 0->1	136	106	77.94
Total Bits 1->0	136	106	77.94

Ports	2	0	0.00
Port Bits	272	212	77.94
Port Bits 0->1	136	106	77.94
Port Bits 1->0	136	106	77.94

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[2]	No	No		No		INPUT
data_i[11:3]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[12]	No	No		No		INPUT
data_i[14:13]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[15]	No	No		No		INPUT
data_i[19:16]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[21:20]	No	No		No		INPUT
data_i[23:22]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[25:24]	No	No		No		INPUT
data_i[26]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[27]	No	No		No		INPUT
data_i[31:28]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[32]	No	No		No		INPUT
data_i[38:33]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[39]	No	No		No		INPUT
data_i[45:40]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[46]	No	No		No		INPUT
data_i[47]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[48]	No	No		No		INPUT
data_i[52:49]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[53]	No	No		No		INPUT
data_i[54]	Yes	Yes	*T5,*T6,*T89	Yes	T3,T5,T6	INPUT
data_i[55]	No	No		No		INPUT
data_i[57:56]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	INPUT
data_i[58]	No	No		No		INPUT
data_i[71:59]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_o[1:0]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[11:3]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[14:13]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[19:16]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[21:20]	No	No		No		OUTPUT
data_o[23:22]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[25:24]	No	No		No		OUTPUT
data_o[26]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[31:28]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[38:33]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[45:40]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[47]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[52:49]	Yes	Yes	T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[54]	Yes	Yes	*T5,*T6,*T89	Yes	T3,T5,T6	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[57:56]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[63:59]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	224	82.35
Total Bits 0->1	136	112	82.35
Total Bits 1->0	136	112	82.35

Ports	2	0	0.00
Port Bits	272	224	82.35
Port Bits 0->1	136	112	82.35
Port Bits 1->0	136	112	82.35

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	No	No		No		INPUT
data_i[2:1]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	INPUT
data_i[4:3]	No	No		No		INPUT
data_i[8:5]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[10:9]	No	No		No		INPUT
data_i[19:11]	Yes	Yes	*T6,*T31,*T16	Yes	T3,T6,T31	INPUT
data_i[20]	No	No		No		INPUT
data_i[21]	Yes	Yes	*T6,*T31,*T16	Yes	T3,T6,T31	INPUT
data_i[22]	No	No		No		INPUT
data_i[29:23]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[30]	No	No		No		INPUT
data_i[39:31]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[41:40]	No	No		No		INPUT
data_i[45:42]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	INPUT
data_i[46]	No	No		No		INPUT
data_i[50:47]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_i[51]	No	No		No		INPUT
data_i[71:52]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[2:1]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	OUTPUT
data_o[4:3]	No	No		No		OUTPUT
data_o[8:5]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[10:9]	No	No		No		OUTPUT
data_o[19:11]	Yes	Yes	*T6,*T31,*T16	Yes	T3,T6,T31	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[21]	Yes	Yes	*T6,*T31,*T16	Yes	T3,T6,T31	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[29:23]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[39:31]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[41:40]	No	No		No		OUTPUT
data_o[45:42]	Yes	Yes	*T5,T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[50:47]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[63:52]	Yes	Yes	T6,T31,T16	Yes	T3,T6,T31	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	272	236	86.76
Total Bits 0->1	136	118	86.76
Total Bits 1->0	136	118	86.76

Ports	2	0	0.00
Port Bits	272	236	86.76
Port Bits 0->1	136	118	86.76
Port Bits 1->0	136	118	86.76

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[0]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[1]	No	No		No		INPUT
data_i[2]	Yes	Yes	*T5,*T6,*T89	Yes	T3,T5,T6	INPUT
data_i[3]	No	No		No		INPUT
data_i[7:4]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	INPUT
data_i[8]	No	No		No		INPUT
data_i[19:9]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	INPUT
data_i[20]	No	No		No		INPUT
data_i[22:21]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	INPUT
data_i[23]	No	No		No		INPUT
data_i[24]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[25]	No	No		No		INPUT
data_i[26]	Yes	Yes	*T284	Yes	T284	INPUT
data_i[27]	No	No		No		INPUT
data_i[34:28]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[35]	No	No		No		INPUT
data_i[62:36]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T5,T6,T12	Yes	T3,T5,T6	INPUT
data_o[0]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[2]	Yes	Yes	*T5,*T6,*T89	Yes	T3,T5,T6	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[7:4]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[19:9]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[22:21]	Yes	Yes	T5,T6,T89	Yes	T3,T5,T6	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[24]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[26]	Yes	Yes	*T284	Yes	T284	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[34:28]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[62:36]	Yes	Yes	*T5,*T6,*T12	Yes	T3,T5,T6	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T90,T31,T87	Yes	T90,T31,T87	INPUT
data_o[63:0]	Yes	Yes	T90,T31,T87	Yes	T90,T31,T87	OUTPUT
syndrome_o[2:0]	Yes	Yes	T100,T144,T145	Yes	T100,T144,T145	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T100,*T144,*T145	Yes	T100,T144,T145	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T85,T90,T106	Yes	T85,T90,T106	INPUT
data_o[63:0]	Yes	Yes	T85,T90,T106	Yes	T85,T90,T106	OUTPUT
syndrome_o[2:0]	Yes	Yes	T100,T101,T152	Yes	T100,T101,T152	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T100,*T101,*T152	Yes	T100,T101,T152	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T31,T87,T111	Yes	T31,T110,T87	INPUT
data_o[63:0]	Yes	Yes	T31,T87,T111	Yes	T31,T110,T87	OUTPUT
syndrome_o[2:0]	Yes	Yes	T160,T161,T152	Yes	T160,T161,T152	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T160,*T161,*T152	Yes	T160,T161,T152	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	280	280	100.00
Total Bits 0->1	140	140	100.00
Total Bits 1->0	140	140	100.00

Ports	4	4	100.00
Port Bits	280	280	100.00
Port Bits 0->1	140	140	100.00
Port Bits 1->0	140	140	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T16,T118,T164	Yes	T16,T118,T164	INPUT
data_o[63:0]	Yes	Yes	T16,T118,T164	Yes	T16,T118,T164	OUTPUT
syndrome_o[2:0]	Yes	Yes	T100,T144,T152	Yes	T100,T144,T152	OUTPUT
syndrome_o[7:3]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[0]	Yes	Yes	*T100,*T144,*T152	Yes	T100,T144,T152	OUTPUT
err_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T6,T105	Yes	T5,T6,T105	INPUT
data_o[63:0]	Yes	Yes	T5,T6,T105	Yes	T5,T6,T105	OUTPUT
syndrome_o[7:0]	Excluded	Excluded	T101,T145,T161	Excluded	T101,T145,T161	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded	T101,T145,T161	Excluded	T101,T145,T161	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T274,T125,T168	Yes	T274,T125,T168	INPUT
data_o[63:0]	Yes	Yes	T274,T125,T168	Yes	T274,T125,T168	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T18,T112,T54	Yes	T18,T164,T112	INPUT
data_o[63:0]	Yes	Yes	T18,T112,T54	Yes	T18,T164,T112	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T105,T111,T112	Yes	T105,T111,T203	INPUT
data_o[63:0]	Yes	Yes	T105,T111,T112	Yes	T105,T111,T203	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T116,T194	Yes	T2,T116,T251	INPUT
data_o[63:0]	Yes	Yes	T2,T116,T194	Yes	T2,T116,T251	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T111,T113,T285	Yes	T111,T113,T285	INPUT
data_o[63:0]	Yes	Yes	T111,T113,T285	Yes	T111,T113,T285	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T16,T111,T285	Yes	T16,T111,T286	INPUT
data_o[63:0]	Yes	Yes	T16,T111,T285	Yes	T16,T111,T286	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T118,T269,T249	Yes	T118,T269,T249	INPUT
data_o[63:0]	Yes	Yes	T118,T269,T249	Yes	T118,T269,T249	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T16,T287,T55	Yes	T16,T120,T287	INPUT
data_o[63:0]	Yes	Yes	T16,T287,T55	Yes	T16,T120,T287	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T6,T31,T87	Yes	T3,T6,T31	INPUT
data_o[63:0]	Yes	Yes	T6,T31,T87	Yes	T3,T6,T31	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T89,T18	Yes	T2,T89,T18	INPUT
data_o[63:0]	Yes	Yes	T2,T89,T18	Yes	T2,T89,T18	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T6,T89,T31	Yes	T6,T89,T31	INPUT
data_o[63:0]	Yes	Yes	T6,T89,T31	Yes	T6,T89,T31	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T89,T31,T121	Yes	T3,T89,T31	INPUT
data_o[63:0]	Yes	Yes	T89,T31,T121	Yes	T3,T89,T31	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T106,T19,T203	Yes	T3,T106,T19	INPUT
data_o[63:0]	Yes	Yes	T106,T19,T203	Yes	T3,T106,T19	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T6,T105	Yes	T3,T6,T105	INPUT
data_o[63:0]	Yes	Yes	T3,T6,T105	Yes	T3,T6,T105	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T89,T16	Yes	T5,T89,T16	INPUT
data_o[63:0]	Yes	Yes	T5,T89,T16	Yes	T5,T89,T16	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T6,T31,T16	Yes	T6,T31,T16	INPUT
data_o[63:0]	Yes	Yes	T6,T31,T16	Yes	T6,T31,T16	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T2,T58,T106	Yes	T2,T58,T106	INPUT
data_o[63:0]	Yes	Yes	T2,T58,T106	Yes	T2,T58,T106	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T3,T105,T111	Yes	T3,T105,T111	INPUT
data_o[63:0]	Yes	Yes	T3,T105,T111	Yes	T3,T105,T111	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T111,T19,T99	Yes	T111,T19,T99	INPUT
data_o[63:0]	Yes	Yes	T111,T19,T99	Yes	T111,T19,T99	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T112,T133,T115	Yes	T3,T4,T198	INPUT
data_o[63:0]	Yes	Yes	T112,T133,T115	Yes	T3,T4,T198	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T58,T99,T125	Yes	T58,T99,T125	INPUT
data_o[63:0]	Yes	Yes	T58,T99,T125	Yes	T58,T99,T125	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T116,T114,T194	Yes	T116,T19,T114	INPUT
data_o[63:0]	Yes	Yes	T116,T114,T194	Yes	T116,T19,T114	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T117,T111	Yes	T5,T117,T111	INPUT
data_o[63:0]	Yes	Yes	T5,T117,T111	Yes	T5,T117,T111	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T89,T148,T286	Yes	T89,T148,T286	INPUT
data_o[63:0]	Yes	Yes	T89,T148,T286	Yes	T89,T148,T286	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T19,T33,T112	Yes	T19,T33,T198	INPUT
data_o[63:0]	Yes	Yes	T19,T33,T112	Yes	T19,T33,T198	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T111,T33,T115	Yes	T111,T33,T115	INPUT
data_o[63:0]	Yes	Yes	T111,T33,T115	Yes	T111,T33,T115	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T5,T6,T31	Yes	T5,T6,T31	INPUT
data_o[63:0]	Yes	Yes	T5,T6,T31	Yes	T5,T6,T31	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T203,T194,T54	Yes	T203,T194,T54	INPUT
data_o[63:0]	Yes	Yes	T203,T194,T54	Yes	T203,T194,T54	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T203,T108,T112	Yes	T203,T108,T112	INPUT
data_o[63:0]	Yes	Yes	T203,T108,T112	Yes	T203,T108,T112	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T108,T254,T249	Yes	T108,T254,T249	INPUT
data_o[63:0]	Yes	Yes	T108,T254,T249	Yes	T108,T254,T249	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T58,T194,T136	Yes	T58,T18,T194	INPUT
data_o[63:0]	Yes	Yes	T58,T194,T136	Yes	T58,T18,T194	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T89,T105,T106	Yes	T89,T105,T106	INPUT
data_o[63:0]	Yes	Yes	T89,T105,T106	Yes	T89,T105,T106	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T89,T16,T121	Yes	T89,T16,T121	INPUT
data_o[63:0]	Yes	Yes	T89,T16,T121	Yes	T89,T16,T121	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T89,T164,T108	Yes	T89,T164,T108	INPUT
data_o[63:0]	Yes	Yes	T89,T164,T108	Yes	T89,T164,T108	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T164,T99,T112	Yes	T164,T99,T112	INPUT
data_o[63:0]	Yes	Yes	T164,T99,T112	Yes	T164,T99,T112	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T164,T108,T114	Yes	T164,T108,T114	INPUT
data_o[63:0]	Yes	Yes	T164,T108,T114	Yes	T164,T108,T114	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T16,T105,T164	Yes	T16,T105,T164	INPUT
data_o[63:0]	Yes	Yes	T16,T105,T164	Yes	T16,T105,T164	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[71:0]	Yes	Yes	T6,T89,T31	Yes	T3,T6,T89	INPUT
data_o[63:0]	Yes	Yes	T6,T89,T31	Yes	T3,T6,T89	OUTPUT
syndrome_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR