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Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 u_csr3_field4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 u_csr3_field5


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 u_csr3_field6


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 u_csr3_field7


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 u_csr3_field8


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_csr4_field0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_csr4_field1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_csr4_field2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_csr4_field3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_csr5_field0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_csr5_field1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 u_csr5_field2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 u_csr5_field3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 u_csr5_field4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 u_csr5_field5


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_csr5_field6


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5.wr_en_data_arb
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN43100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300


42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         0/1     ==>      assign wr_en   = de;
44         0/1     ==>      assign wr_data = d;
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN43100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300


42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         0/1     ==>      assign wr_en   = de;
44         0/1     ==>      assign wr_data = d;
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN43100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300


42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         0/1     ==>      assign wr_en   = de;
44         0/1     ==>      assign wr_data = d;
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN43100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300


42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         0/1     ==>      assign wr_en   = de;
44         0/1     ==>      assign wr_data = d;
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN43100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300


42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         0/1     ==>      assign wr_en   = de;
44         0/1     ==>      assign wr_data = d;
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T1 T2 T3 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT16,T18,T19 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T18,T19 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T18,T19
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T16,T18,T19
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T1 T2 T3 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT16,T18,T19 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T18,T19 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T18,T19
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T16,T18,T19
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T1 T2 T3 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT16,T18,T19 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T18,T19 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T18,T19
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T16,T18,T19
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T1 T2 T3 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT16,T18,T19 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T18,T19 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T18,T19
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T16,T18,T19
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T1 T2 T3 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTestsExclude Annotation
00CoveredT1,T2,T3
01Excluded VC_COV_UNR
10CoveredT16,T143,T115 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T143,T115 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T143,T115
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T16,T143,T115
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T1 T2 T3 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTestsExclude Annotation
00CoveredT1,T2,T3
01Excluded VC_COV_UNR
10CoveredT16,T143,T115 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T143,T115 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T143,T115
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T16,T143,T115
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN43100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300


42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         0/1     ==>      assign wr_en   = de;
44         0/1     ==>      assign wr_data = d;
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN43100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300


42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         0/1     ==>      assign wr_en   = de;
44         0/1     ==>      assign wr_data = d;
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN43100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300


42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         0/1     ==>      assign wr_en   = de;
44         0/1     ==>      assign wr_data = d;
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN43100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300


42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         0/1     ==>      assign wr_en   = de;
44         0/1     ==>      assign wr_data = d;
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T1 T2 T3 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTestsExclude Annotation
00CoveredT1,T2,T3
01Excluded VC_COV_UNR
10CoveredT16,T143,T115 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T143,T115 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T143,T115
Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T16,T143,T115
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%