Unified Coverage Report :: Module :: prim_subreg_ext

Module : prim_subreg_ext

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core.u_intr_test_otp_operation_done	100.00	100.00
tb.dut.u_reg_core.u_intr_test_otp_error	100.00	100.00
tb.dut.u_reg_core.u_alert_test_fatal_macro_error	100.00	100.00
tb.dut.u_reg_core.u_alert_test_fatal_check_error	100.00	100.00
tb.dut.u_reg_core.u_alert_test_fatal_bus_integ_error	100.00	100.00
tb.dut.u_reg_core.u_alert_test_fatal_prim_otp_alert	100.00	100.00
tb.dut.u_reg_core.u_alert_test_recov_prim_otp_alert	100.00	100.00
tb.dut.u_reg_core.u_status_vendor_test_error	100.00	100.00
tb.dut.u_reg_core.u_status_creator_sw_cfg_error	100.00	100.00
tb.dut.u_reg_core.u_status_owner_sw_cfg_error	100.00	100.00
tb.dut.u_reg_core.u_status_rot_creator_auth_codesign_error	100.00	100.00
tb.dut.u_reg_core.u_status_rot_creator_auth_state_error	100.00	100.00
tb.dut.u_reg_core.u_status_hw_cfg0_error	100.00	100.00
tb.dut.u_reg_core.u_status_hw_cfg1_error	100.00	100.00
tb.dut.u_reg_core.u_status_secret0_error	100.00	100.00
tb.dut.u_reg_core.u_status_secret1_error	100.00	100.00
tb.dut.u_reg_core.u_status_secret2_error	100.00	100.00
tb.dut.u_reg_core.u_status_life_cycle_error	100.00	100.00
tb.dut.u_reg_core.u_status_dai_error	100.00	100.00
tb.dut.u_reg_core.u_status_lci_error	100.00	100.00
tb.dut.u_reg_core.u_status_timeout_error	100.00	100.00
tb.dut.u_reg_core.u_status_lfsr_fsm_error	100.00	100.00
tb.dut.u_reg_core.u_status_scrambling_fsm_error	100.00	100.00
tb.dut.u_reg_core.u_status_key_deriv_fsm_error	100.00	100.00
tb.dut.u_reg_core.u_status_bus_integ_error	100.00	100.00
tb.dut.u_reg_core.u_status_dai_idle	100.00	100.00
tb.dut.u_reg_core.u_status_check_pending	100.00	100.00
tb.dut.u_reg_core.u_err_code_0	100.00	100.00
tb.dut.u_reg_core.u_err_code_1	100.00	100.00
tb.dut.u_reg_core.u_err_code_2	100.00	100.00
tb.dut.u_reg_core.u_err_code_3	100.00	100.00
tb.dut.u_reg_core.u_err_code_4	100.00	100.00
tb.dut.u_reg_core.u_err_code_5	100.00	100.00
tb.dut.u_reg_core.u_err_code_6	100.00	100.00
tb.dut.u_reg_core.u_err_code_7	100.00	100.00
tb.dut.u_reg_core.u_err_code_8	100.00	100.00
tb.dut.u_reg_core.u_err_code_9	100.00	100.00
tb.dut.u_reg_core.u_err_code_10	100.00	100.00
tb.dut.u_reg_core.u_err_code_11	100.00	100.00
tb.dut.u_reg_core.u_err_code_12	100.00	100.00
tb.dut.u_reg_core.u_direct_access_regwen	100.00	100.00
tb.dut.u_reg_core.u_direct_access_cmd_rd	100.00	100.00
tb.dut.u_reg_core.u_direct_access_cmd_wr	100.00	100.00
tb.dut.u_reg_core.u_direct_access_cmd_digest	100.00	100.00
tb.dut.u_reg_core.u_direct_access_rdata_0	100.00	100.00
tb.dut.u_reg_core.u_direct_access_rdata_1	100.00	100.00
tb.dut.u_reg_core.u_check_trigger_integrity	100.00	100.00
tb.dut.u_reg_core.u_check_trigger_consistency	100.00	100.00
tb.dut.u_reg_core.u_vendor_test_digest_0	100.00	100.00
tb.dut.u_reg_core.u_vendor_test_digest_1	100.00	100.00
tb.dut.u_reg_core.u_creator_sw_cfg_digest_0	100.00	100.00
tb.dut.u_reg_core.u_creator_sw_cfg_digest_1	100.00	100.00
tb.dut.u_reg_core.u_owner_sw_cfg_digest_0	100.00	100.00
tb.dut.u_reg_core.u_owner_sw_cfg_digest_1	100.00	100.00
tb.dut.u_reg_core.u_rot_creator_auth_codesign_digest_0	100.00	100.00
tb.dut.u_reg_core.u_rot_creator_auth_codesign_digest_1	100.00	100.00
tb.dut.u_reg_core.u_rot_creator_auth_state_digest_0	100.00	100.00
tb.dut.u_reg_core.u_rot_creator_auth_state_digest_1	100.00	100.00
tb.dut.u_reg_core.u_hw_cfg0_digest_0	100.00	100.00
tb.dut.u_reg_core.u_hw_cfg0_digest_1	100.00	100.00
tb.dut.u_reg_core.u_hw_cfg1_digest_0	100.00	100.00
tb.dut.u_reg_core.u_hw_cfg1_digest_1	100.00	100.00
tb.dut.u_reg_core.u_secret0_digest_0	100.00	100.00
tb.dut.u_reg_core.u_secret0_digest_1	100.00	100.00
tb.dut.u_reg_core.u_secret1_digest_0	100.00	100.00
tb.dut.u_reg_core.u_secret1_digest_1	100.00	100.00
tb.dut.u_reg_core.u_secret2_digest_0	100.00	100.00
tb.dut.u_reg_core.u_secret2_digest_1	100.00	100.00

---

Module Instance : tb.dut.u_reg_core.u_intr_test_otp_operation_done

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_intr_test_otp_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_alert_test_fatal_macro_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_alert_test_fatal_check_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_alert_test_fatal_bus_integ_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_alert_test_fatal_prim_otp_alert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_alert_test_recov_prim_otp_alert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_vendor_test_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_creator_sw_cfg_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_owner_sw_cfg_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_rot_creator_auth_codesign_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_rot_creator_auth_state_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_hw_cfg0_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_hw_cfg1_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_secret0_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_secret1_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_secret2_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_life_cycle_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_dai_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_lci_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_timeout_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_lfsr_fsm_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_scrambling_fsm_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_key_deriv_fsm_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_bus_integ_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_dai_idle

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_status_check_pending

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_err_code_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_err_code_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_err_code_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_err_code_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_err_code_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_err_code_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_err_code_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_err_code_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_err_code_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_err_code_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_err_code_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_err_code_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_err_code_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_direct_access_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_direct_access_cmd_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_direct_access_cmd_wr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_direct_access_cmd_digest

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_direct_access_rdata_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_direct_access_rdata_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_check_trigger_integrity

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_check_trigger_consistency

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_vendor_test_digest_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_vendor_test_digest_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_creator_sw_cfg_digest_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_creator_sw_cfg_digest_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_owner_sw_cfg_digest_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_owner_sw_cfg_digest_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_rot_creator_auth_codesign_digest_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_rot_creator_auth_codesign_digest_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_rot_creator_auth_state_digest_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_rot_creator_auth_state_digest_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_hw_cfg0_digest_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_hw_cfg0_digest_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_hw_cfg1_digest_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_hw_cfg1_digest_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_secret0_digest_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_secret0_digest_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_secret1_digest_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_secret1_digest_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_secret2_digest_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_secret2_digest_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.43			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_subreg_ext

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T11 T17 T202 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_intr_test_otp_operation_done

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T13 T14 T249 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_core.u_intr_test_otp_error

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T13 T14 T249 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_core.u_alert_test_fatal_macro_error

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T11 T17 T202 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_core.u_alert_test_fatal_check_error

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T11 T17 T202 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_core.u_alert_test_fatal_bus_integ_error

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T11 T17 T202 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_core.u_alert_test_fatal_prim_otp_alert

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T11 T17 T202 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_core.u_alert_test_recov_prim_otp_alert

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T11 T17 T202 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_core.u_status_vendor_test_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_creator_sw_cfg_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_owner_sw_cfg_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_rot_creator_auth_codesign_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_rot_creator_auth_state_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_hw_cfg0_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_hw_cfg1_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_secret0_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_secret1_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_secret2_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_life_cycle_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_dai_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_lci_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_timeout_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_lfsr_fsm_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_scrambling_fsm_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_key_deriv_fsm_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_bus_integ_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_dai_idle

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_status_check_pending

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_2

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_3

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_4

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_5

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_6

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_7

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_8

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_9

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_10

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_11

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_12

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_direct_access_regwen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T13 T14 T15 
30         1/1            assign qre = re;
           Tests:       T3 T4 T7 

Line Coverage for Instance : tb.dut.u_reg_core.u_direct_access_cmd_rd

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_core.u_direct_access_cmd_wr

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_core.u_direct_access_cmd_digest

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_core.u_direct_access_rdata_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_core.u_direct_access_rdata_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg_core.u_check_trigger_integrity

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T3 T4 T5 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_core.u_check_trigger_consistency

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T3 T4 T5 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_core.u_vendor_test_digest_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_vendor_test_digest_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_creator_sw_cfg_digest_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_creator_sw_cfg_digest_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_owner_sw_cfg_digest_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_owner_sw_cfg_digest_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_rot_creator_auth_codesign_digest_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_rot_creator_auth_codesign_digest_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_rot_creator_auth_state_digest_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_rot_creator_auth_state_digest_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_hw_cfg0_digest_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_hw_cfg0_digest_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_hw_cfg1_digest_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_hw_cfg1_digest_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_secret0_digest_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_secret0_digest_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_secret1_digest_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_secret1_digest_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_secret2_digest_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5 

Line Coverage for Instance : tb.dut.u_reg_core.u_secret2_digest_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T3 T4 T5