| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.18 | 93.73 | 96.75 | 95.89 | 92.77 | 97.54 | 96.37 | 93.21 |
| T380 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1510383079 | Sep 18 07:14:57 PM UTC 24 | Sep 18 07:15:17 PM UTC 24 | 4839791695 ps | ||
| T1258 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.4179989798 | Sep 18 07:15:01 PM UTC 24 | Sep 18 07:15:06 PM UTC 24 | 348909440 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3243630590 | Sep 18 07:14:52 PM UTC 24 | Sep 18 07:15:13 PM UTC 24 | 3213639736 ps | ||
| T1259 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3401273300 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:19 PM UTC 24 | 92683276 ps | ||
| T1260 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3948958485 | Sep 18 07:15:03 PM UTC 24 | Sep 18 07:15:06 PM UTC 24 | 632716053 ps | ||
| T1261 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.132671483 | Sep 18 07:15:03 PM UTC 24 | Sep 18 07:15:06 PM UTC 24 | 109853943 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.123802178 | Sep 18 07:15:01 PM UTC 24 | Sep 18 07:15:06 PM UTC 24 | 402288053 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.4129957652 | Sep 18 07:14:50 PM UTC 24 | Sep 18 07:15:06 PM UTC 24 | 4802029236 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1489607251 | Sep 18 07:15:03 PM UTC 24 | Sep 18 07:15:07 PM UTC 24 | 439113817 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3786438999 | Sep 18 07:15:01 PM UTC 24 | Sep 18 07:15:07 PM UTC 24 | 303274045 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.694021905 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:07 PM UTC 24 | 70058057 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.1472265133 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:07 PM UTC 24 | 116120511 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.1253519855 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:07 PM UTC 24 | 96678601 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.791951607 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:07 PM UTC 24 | 39667111 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.1520690867 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:07 PM UTC 24 | 73667119 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2323138797 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:07 PM UTC 24 | 97532842 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1590985025 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:07 PM UTC 24 | 151901553 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1687237427 | Sep 18 07:15:03 PM UTC 24 | Sep 18 07:15:07 PM UTC 24 | 103660609 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.2857445158 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 73557885 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1890470933 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 157634503 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1257017496 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 89664407 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1664211875 | Sep 18 07:15:03 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 340376571 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.2655214840 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 46764989 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.2969603260 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 551987124 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.40055780 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 145176089 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.3415846494 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 136281772 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.478649915 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 69240139 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.3142857845 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 579879317 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.1911283765 | Sep 18 07:15:05 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 569945155 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2613635523 | Sep 18 07:15:03 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 1671087090 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.932341835 | Sep 18 07:15:03 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 1906679502 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.836687558 | Sep 18 07:15:03 PM UTC 24 | Sep 18 07:15:08 PM UTC 24 | 983536052 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1050227737 | Sep 18 07:15:03 PM UTC 24 | Sep 18 07:15:09 PM UTC 24 | 130047521 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1080961709 | Sep 18 07:15:01 PM UTC 24 | Sep 18 07:15:09 PM UTC 24 | 2613732362 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.1298479123 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:09 PM UTC 24 | 84305841 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2120579569 | Sep 18 07:14:49 PM UTC 24 | Sep 18 07:15:12 PM UTC 24 | 2605373730 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3502539841 | Sep 18 07:14:53 PM UTC 24 | Sep 18 07:15:13 PM UTC 24 | 2631472022 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.4067847784 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:19 PM UTC 24 | 138048307 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.3991202311 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:19 PM UTC 24 | 72110023 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.4160145616 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:19 PM UTC 24 | 48848897 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.4182810096 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:19 PM UTC 24 | 41091948 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.3619720645 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:19 PM UTC 24 | 52615288 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.1436098780 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:19 PM UTC 24 | 49738662 ps | ||
| T1297 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.3532450851 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:19 PM UTC 24 | 41323330 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2085969127 | Sep 18 07:15:01 PM UTC 24 | Sep 18 07:15:19 PM UTC 24 | 4760951644 ps | ||
| T1298 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.2127979095 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:19 PM UTC 24 | 550330059 ps | ||
| T1299 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3213182026 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:19 PM UTC 24 | 40796172 ps | ||
| T1300 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.85156059 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:19 PM UTC 24 | 145947123 ps | ||
| T1301 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.3822845707 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:20 PM UTC 24 | 511893715 ps | ||
| T1302 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.188150039 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:20 PM UTC 24 | 541508746 ps | ||
| T1303 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.3128723213 | Sep 18 07:15:07 PM UTC 24 | Sep 18 07:15:20 PM UTC 24 | 567366058 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1772993930 | Sep 18 07:15:01 PM UTC 24 | Sep 18 07:15:21 PM UTC 24 | 2344927130 ps | ||
| T1304 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2010846365 | Sep 18 07:14:58 PM UTC 24 | Sep 18 07:15:21 PM UTC 24 | 5087739931 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.4290302981 | Sep 18 07:15:03 PM UTC 24 | Sep 18 07:15:22 PM UTC 24 | 9760093752 ps | ||
| T1305 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2128554947 | Sep 18 07:15:01 PM UTC 24 | Sep 18 07:15:23 PM UTC 24 | 1819453141 ps | ||
| T1306 | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.284513587 | Sep 18 07:15:03 PM UTC 24 | Sep 18 07:15:31 PM UTC 24 | 20231295660 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.3538559676 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 491785965 ps |
| CPU time | 17.62 seconds |
| Started | Sep 18 04:43:12 PM UTC 24 |
| Finished | Sep 18 04:43:31 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538559676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.3538559676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.3015920803 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1427875224 ps |
| CPU time | 19.11 seconds |
| Started | Sep 18 04:43:21 PM UTC 24 |
| Finished | Sep 18 04:43:41 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015920803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.3015920803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.1942314000 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 20493555486 ps |
| CPU time | 97.54 seconds |
| Started | Sep 18 04:45:09 PM UTC 24 |
| Finished | Sep 18 04:46:49 PM UTC 24 |
| Peak memory | 255992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942314000 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.1942314000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.4144260413 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10109111924 ps |
| CPU time | 25.3 seconds |
| Started | Sep 18 04:43:11 PM UTC 24 |
| Finished | Sep 18 04:43:38 PM UTC 24 |
| Peak memory | 254028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144260413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.4144260413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.566943221 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2834367563 ps |
| CPU time | 75.53 seconds |
| Started | Sep 18 04:43:37 PM UTC 24 |
| Finished | Sep 18 04:44:54 PM UTC 24 |
| Peak memory | 268400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=566943221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.566943221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.1489033038 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 25389739078 ps |
| CPU time | 72.75 seconds |
| Started | Sep 18 04:43:21 PM UTC 24 |
| Finished | Sep 18 04:44:36 PM UTC 24 |
| Peak memory | 258040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489033038 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.1489033038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.1815550722 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 32495511382 ps |
| CPU time | 72.29 seconds |
| Started | Sep 18 04:43:16 PM UTC 24 |
| Finished | Sep 18 04:44:31 PM UTC 24 |
| Peak memory | 254068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815550722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.1815550722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.3707272426 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 38910244673 ps |
| CPU time | 190.08 seconds |
| Started | Sep 18 04:43:38 PM UTC 24 |
| Finished | Sep 18 04:46:52 PM UTC 24 |
| Peak memory | 288364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707272426 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3707272426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.1564976279 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 10026158636 ps |
| CPU time | 135.1 seconds |
| Started | Sep 18 04:44:09 PM UTC 24 |
| Finished | Sep 18 04:46:26 PM UTC 24 |
| Peak memory | 262208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564976279 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.1564976279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.2406332171 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 154490817 ps |
| CPU time | 6.19 seconds |
| Started | Sep 18 04:46:59 PM UTC 24 |
| Finished | Sep 18 04:47:07 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406332171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.2406332171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.3144845758 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1095558315 ps |
| CPU time | 36.38 seconds |
| Started | Sep 18 04:43:34 PM UTC 24 |
| Finished | Sep 18 04:44:12 PM UTC 24 |
| Peak memory | 255932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144845758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.3144845758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.4121492482 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 25000617501 ps |
| CPU time | 201.17 seconds |
| Started | Sep 18 04:45:31 PM UTC 24 |
| Finished | Sep 18 04:48:56 PM UTC 24 |
| Peak memory | 274524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121492482 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.4121492482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.2947753789 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 247309018 ps |
| CPU time | 4.27 seconds |
| Started | Sep 18 04:43:10 PM UTC 24 |
| Finished | Sep 18 04:43:15 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947753789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.2947753789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1355906363 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 663962272 ps |
| CPU time | 8.65 seconds |
| Started | Sep 18 07:14:35 PM UTC 24 |
| Finished | Sep 18 07:14:45 PM UTC 24 |
| Peak memory | 255668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355906363 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.1355906363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.286686117 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 8620530963 ps |
| CPU time | 201.19 seconds |
| Started | Sep 18 04:50:25 PM UTC 24 |
| Finished | Sep 18 04:53:50 PM UTC 24 |
| Peak memory | 274580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=286686117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.286686117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.278647059 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 91018061405 ps |
| CPU time | 207 seconds |
| Started | Sep 18 04:44:36 PM UTC 24 |
| Finished | Sep 18 04:48:07 PM UTC 24 |
| Peak memory | 256076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278647059 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.278647059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.2421349784 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 360628464 ps |
| CPU time | 4.48 seconds |
| Started | Sep 18 04:55:53 PM UTC 24 |
| Finished | Sep 18 04:55:59 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421349784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.2421349784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.2825537154 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8917047562 ps |
| CPU time | 116.27 seconds |
| Started | Sep 18 04:45:26 PM UTC 24 |
| Finished | Sep 18 04:47:25 PM UTC 24 |
| Peak memory | 268536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2825537154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.otp_ctrl_stress_all_with_rand_reset.2825537154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.337966424 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4925179511 ps |
| CPU time | 49.86 seconds |
| Started | Sep 18 04:44:47 PM UTC 24 |
| Finished | Sep 18 04:45:38 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337966424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.337966424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.1859467530 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 12091760404 ps |
| CPU time | 40.34 seconds |
| Started | Sep 18 04:48:03 PM UTC 24 |
| Finished | Sep 18 04:48:45 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859467530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.1859467530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.83205373 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1034974375 ps |
| CPU time | 21.07 seconds |
| Started | Sep 18 04:50:12 PM UTC 24 |
| Finished | Sep 18 04:50:35 PM UTC 24 |
| Peak memory | 252004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83205373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.83205373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.1496672894 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5034440547 ps |
| CPU time | 26.41 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:55:17 PM UTC 24 |
| Peak memory | 258224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1496672894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 66.otp_ctrl_stress_all_with_rand_reset.1496672894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.4065260114 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1446371090 ps |
| CPU time | 26.02 seconds |
| Started | Sep 18 04:44:45 PM UTC 24 |
| Finished | Sep 18 04:45:12 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065260114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.4065260114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.360582637 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 120198124 ps |
| CPU time | 5.14 seconds |
| Started | Sep 18 04:56:04 PM UTC 24 |
| Finished | Sep 18 04:56:11 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360582637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.360582637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.2036787147 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 7930397000 ps |
| CPU time | 28.1 seconds |
| Started | Sep 18 04:47:44 PM UTC 24 |
| Finished | Sep 18 04:48:13 PM UTC 24 |
| Peak memory | 252184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036787147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.2036787147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.1109154304 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 256464827 ps |
| CPU time | 6.98 seconds |
| Started | Sep 18 04:49:54 PM UTC 24 |
| Finished | Sep 18 04:50:02 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109154304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1109154304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.573896605 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 100063780 ps |
| CPU time | 3.11 seconds |
| Started | Sep 18 07:14:35 PM UTC 24 |
| Finished | Sep 18 07:14:39 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573896605 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.573896605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.2310068679 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 14046176743 ps |
| CPU time | 119.5 seconds |
| Started | Sep 18 04:50:06 PM UTC 24 |
| Finished | Sep 18 04:52:08 PM UTC 24 |
| Peak memory | 268496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2310068679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.otp_ctrl_stress_all_with_rand_reset.2310068679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.4035334387 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 155424313 ps |
| CPU time | 6.19 seconds |
| Started | Sep 18 04:44:14 PM UTC 24 |
| Finished | Sep 18 04:44:21 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035334387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.4035334387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.810438820 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1282316422 ps |
| CPU time | 3.04 seconds |
| Started | Sep 18 04:56:58 PM UTC 24 |
| Finished | Sep 18 04:57:03 PM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810438820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.810438820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.1706295772 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 646724184 ps |
| CPU time | 5.06 seconds |
| Started | Sep 18 04:55:58 PM UTC 24 |
| Finished | Sep 18 04:56:04 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706295772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1706295772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.1807758960 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 53844061650 ps |
| CPU time | 260.05 seconds |
| Started | Sep 18 04:49:08 PM UTC 24 |
| Finished | Sep 18 04:53:32 PM UTC 24 |
| Peak memory | 270328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807758960 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.1807758960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.4143457125 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 184079016 ps |
| CPU time | 4.86 seconds |
| Started | Sep 18 04:43:43 PM UTC 24 |
| Finished | Sep 18 04:43:49 PM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143457125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.4143457125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.1672751571 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 4614730550 ps |
| CPU time | 105.4 seconds |
| Started | Sep 18 04:47:22 PM UTC 24 |
| Finished | Sep 18 04:49:10 PM UTC 24 |
| Peak memory | 268372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672751571 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.1672751571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.387211076 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 2499891975 ps |
| CPU time | 4.17 seconds |
| Started | Sep 18 04:56:25 PM UTC 24 |
| Finished | Sep 18 04:56:30 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387211076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.387211076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.2815522580 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2685394131 ps |
| CPU time | 5.04 seconds |
| Started | Sep 18 04:56:53 PM UTC 24 |
| Finished | Sep 18 04:56:59 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815522580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2815522580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.667015342 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 144504171 ps |
| CPU time | 5.06 seconds |
| Started | Sep 18 04:55:56 PM UTC 24 |
| Finished | Sep 18 04:56:02 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667015342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.667015342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.1867854148 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 4880355154 ps |
| CPU time | 97.54 seconds |
| Started | Sep 18 04:53:47 PM UTC 24 |
| Finished | Sep 18 04:55:26 PM UTC 24 |
| Peak memory | 268368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867854148 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.1867854148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.2260884388 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 5187588985 ps |
| CPU time | 50.54 seconds |
| Started | Sep 18 04:47:34 PM UTC 24 |
| Finished | Sep 18 04:48:27 PM UTC 24 |
| Peak memory | 253892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260884388 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.2260884388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.1334347103 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 153046214 ps |
| CPU time | 5.83 seconds |
| Started | Sep 18 04:43:27 PM UTC 24 |
| Finished | Sep 18 04:43:34 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334347103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.1334347103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.4747084 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 732461241 ps |
| CPU time | 17.25 seconds |
| Started | Sep 18 04:51:18 PM UTC 24 |
| Finished | Sep 18 04:51:36 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4747084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.4747084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.1777584805 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 109760534535 ps |
| CPU time | 255.01 seconds |
| Started | Sep 18 04:47:10 PM UTC 24 |
| Finished | Sep 18 04:51:29 PM UTC 24 |
| Peak memory | 268368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777584805 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.1777584805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.3928698308 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 154286321 ps |
| CPU time | 2.63 seconds |
| Started | Sep 18 04:43:25 PM UTC 24 |
| Finished | Sep 18 04:43:29 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928698308 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.3928698308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.1644382659 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 1338721732 ps |
| CPU time | 49.61 seconds |
| Started | Sep 18 04:55:03 PM UTC 24 |
| Finished | Sep 18 04:55:54 PM UTC 24 |
| Peak memory | 274480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1644382659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 75.otp_ctrl_stress_all_with_rand_reset.1644382659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.282881673 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 402435081 ps |
| CPU time | 10.3 seconds |
| Started | Sep 18 04:45:06 PM UTC 24 |
| Finished | Sep 18 04:45:18 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282881673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.282881673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.4175739212 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1343816971 ps |
| CPU time | 19.36 seconds |
| Started | Sep 18 04:48:12 PM UTC 24 |
| Finished | Sep 18 04:48:32 PM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175739212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.4175739212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.3272338131 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 10746106840 ps |
| CPU time | 77.57 seconds |
| Started | Sep 18 04:51:41 PM UTC 24 |
| Finished | Sep 18 04:53:01 PM UTC 24 |
| Peak memory | 258120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272338131 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.3272338131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.3379318660 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 285027834 ps |
| CPU time | 3.93 seconds |
| Started | Sep 18 04:57:09 PM UTC 24 |
| Finished | Sep 18 04:57:15 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379318660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.3379318660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1510383079 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 4839791695 ps |
| CPU time | 18.52 seconds |
| Started | Sep 18 07:14:57 PM UTC 24 |
| Finished | Sep 18 07:15:17 PM UTC 24 |
| Peak memory | 257924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510383079 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.1510383079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.1663431347 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 144505133 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 04:56:19 PM UTC 24 |
| Finished | Sep 18 04:56:23 PM UTC 24 |
| Peak memory | 251668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663431347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.1663431347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.4028583075 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2939164962 ps |
| CPU time | 29.52 seconds |
| Started | Sep 18 04:44:23 PM UTC 24 |
| Finished | Sep 18 04:44:53 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028583075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.4028583075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.972269761 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 149841673 ps |
| CPU time | 6.45 seconds |
| Started | Sep 18 04:48:28 PM UTC 24 |
| Finished | Sep 18 04:48:36 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972269761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.972269761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.414825300 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 11479224630 ps |
| CPU time | 38.16 seconds |
| Started | Sep 18 04:45:50 PM UTC 24 |
| Finished | Sep 18 04:46:30 PM UTC 24 |
| Peak memory | 256024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414825300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.414825300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.3846448559 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 193381577 ps |
| CPU time | 6.55 seconds |
| Started | Sep 18 04:51:49 PM UTC 24 |
| Finished | Sep 18 04:51:57 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846448559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.3846448559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.2484228152 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1200700199 ps |
| CPU time | 11.74 seconds |
| Started | Sep 18 04:44:33 PM UTC 24 |
| Finished | Sep 18 04:44:46 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484228152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.2484228152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1116537268 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 2416782855 ps |
| CPU time | 16.21 seconds |
| Started | Sep 18 07:14:40 PM UTC 24 |
| Finished | Sep 18 07:14:58 PM UTC 24 |
| Peak memory | 255920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116537268 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.1116537268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.3941647115 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1888373045 ps |
| CPU time | 21.16 seconds |
| Started | Sep 18 04:43:57 PM UTC 24 |
| Finished | Sep 18 04:44:20 PM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941647115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.3941647115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.220871792 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 391996408 ps |
| CPU time | 5.38 seconds |
| Started | Sep 18 04:55:38 PM UTC 24 |
| Finished | Sep 18 04:55:45 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220871792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.220871792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.33260507 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1536953511 ps |
| CPU time | 19.56 seconds |
| Started | Sep 18 04:46:59 PM UTC 24 |
| Finished | Sep 18 04:47:20 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33260507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.33260507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.4069942388 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2374020398 ps |
| CPU time | 5.32 seconds |
| Started | Sep 18 04:55:56 PM UTC 24 |
| Finished | Sep 18 04:56:03 PM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069942388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.4069942388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.2178402196 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 136883905 ps |
| CPU time | 3.99 seconds |
| Started | Sep 18 04:56:25 PM UTC 24 |
| Finished | Sep 18 04:56:30 PM UTC 24 |
| Peak memory | 252100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178402196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2178402196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.3123110783 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 386708399 ps |
| CPU time | 7.58 seconds |
| Started | Sep 18 04:49:36 PM UTC 24 |
| Finished | Sep 18 04:49:45 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123110783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.3123110783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.922622695 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 557571167 ps |
| CPU time | 5.76 seconds |
| Started | Sep 18 04:50:06 PM UTC 24 |
| Finished | Sep 18 04:50:13 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922622695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.922622695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.2129139400 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1343752702 ps |
| CPU time | 17.35 seconds |
| Started | Sep 18 04:52:44 PM UTC 24 |
| Finished | Sep 18 04:53:03 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129139400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.2129139400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.1358355782 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 244258423 ps |
| CPU time | 6.81 seconds |
| Started | Sep 18 04:54:40 PM UTC 24 |
| Finished | Sep 18 04:54:48 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358355782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1358355782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.2459104796 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1585918624 ps |
| CPU time | 12.79 seconds |
| Started | Sep 18 04:54:42 PM UTC 24 |
| Finished | Sep 18 04:54:56 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459104796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.2459104796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.3788684784 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 41274620941 ps |
| CPU time | 308.55 seconds |
| Started | Sep 18 04:48:57 PM UTC 24 |
| Finished | Sep 18 04:54:10 PM UTC 24 |
| Peak memory | 290964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788684784 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.3788684784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.2078034040 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 9609031419 ps |
| CPU time | 178.65 seconds |
| Started | Sep 18 04:48:26 PM UTC 24 |
| Finished | Sep 18 04:51:28 PM UTC 24 |
| Peak memory | 268404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078034040 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.2078034040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.510652883 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 145954803 ps |
| CPU time | 1.45 seconds |
| Started | Sep 18 07:14:38 PM UTC 24 |
| Finished | Sep 18 07:14:41 PM UTC 24 |
| Peak memory | 253328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510652883 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.510652883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.2539470019 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1125172327 ps |
| CPU time | 10.97 seconds |
| Started | Sep 18 04:47:45 PM UTC 24 |
| Finished | Sep 18 04:47:58 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539470019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2539470019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.4228397015 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 12837730199 ps |
| CPU time | 46.86 seconds |
| Started | Sep 18 04:43:46 PM UTC 24 |
| Finished | Sep 18 04:44:35 PM UTC 24 |
| Peak memory | 254092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228397015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.4228397015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.1765016292 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 7736433229 ps |
| CPU time | 149.62 seconds |
| Started | Sep 18 04:49:08 PM UTC 24 |
| Finished | Sep 18 04:51:40 PM UTC 24 |
| Peak memory | 268404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1765016292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.otp_ctrl_stress_all_with_rand_reset.1765016292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.1846574187 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 501477980 ps |
| CPU time | 3.86 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:20 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846574187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.1846574187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.993287640 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 15865035176 ps |
| CPU time | 200.01 seconds |
| Started | Sep 18 04:46:55 PM UTC 24 |
| Finished | Sep 18 04:50:18 PM UTC 24 |
| Peak memory | 274192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993287640 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.993287640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.2186070733 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 814819254 ps |
| CPU time | 27.57 seconds |
| Started | Sep 18 04:47:28 PM UTC 24 |
| Finished | Sep 18 04:47:57 PM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186070733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.2186070733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.2677161391 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1176540131 ps |
| CPU time | 26.41 seconds |
| Started | Sep 18 04:46:40 PM UTC 24 |
| Finished | Sep 18 04:47:08 PM UTC 24 |
| Peak memory | 258092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677161391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2677161391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.3068634336 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 4047742686 ps |
| CPU time | 67.69 seconds |
| Started | Sep 18 04:52:26 PM UTC 24 |
| Finished | Sep 18 04:53:35 PM UTC 24 |
| Peak memory | 272528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3068634336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.otp_ctrl_stress_all_with_rand_reset.3068634336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.2142286333 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2609890613 ps |
| CPU time | 92.52 seconds |
| Started | Sep 18 04:55:48 PM UTC 24 |
| Finished | Sep 18 04:57:23 PM UTC 24 |
| Peak memory | 268404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2142286333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 97.otp_ctrl_stress_all_with_rand_reset.2142286333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.1429254593 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 3051484699 ps |
| CPU time | 37.37 seconds |
| Started | Sep 18 04:47:54 PM UTC 24 |
| Finished | Sep 18 04:48:33 PM UTC 24 |
| Peak memory | 252040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429254593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.1429254593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.2826747471 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 493429779 ps |
| CPU time | 4.69 seconds |
| Started | Sep 18 04:56:07 PM UTC 24 |
| Finished | Sep 18 04:56:12 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826747471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.2826747471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.187873673 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 191074790 ps |
| CPU time | 6.43 seconds |
| Started | Sep 18 04:47:36 PM UTC 24 |
| Finished | Sep 18 04:47:43 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187873673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.187873673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.3854154747 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 594457184 ps |
| CPU time | 4.25 seconds |
| Started | Sep 18 04:56:25 PM UTC 24 |
| Finished | Sep 18 04:56:30 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854154747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.3854154747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2414121287 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2283529604 ps |
| CPU time | 17.22 seconds |
| Started | Sep 18 07:14:56 PM UTC 24 |
| Finished | Sep 18 07:15:14 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414121287 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.2414121287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.1535753603 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 3100536430 ps |
| CPU time | 102.43 seconds |
| Started | Sep 18 04:54:58 PM UTC 24 |
| Finished | Sep 18 04:56:42 PM UTC 24 |
| Peak memory | 268496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1535753603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 71.otp_ctrl_stress_all_with_rand_reset.1535753603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.1161653138 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 130981911 ps |
| CPU time | 4.44 seconds |
| Started | Sep 18 04:53:15 PM UTC 24 |
| Finished | Sep 18 04:53:20 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161653138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.1161653138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.1474243873 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 17248301346 ps |
| CPU time | 151.74 seconds |
| Started | Sep 18 04:50:18 PM UTC 24 |
| Finished | Sep 18 04:52:52 PM UTC 24 |
| Peak memory | 258072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474243873 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.1474243873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.3844973140 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 110646755 ps |
| CPU time | 2.48 seconds |
| Started | Sep 18 04:43:06 PM UTC 24 |
| Finished | Sep 18 04:43:09 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844973140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes t +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.3844973140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.3033213593 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 697005820 ps |
| CPU time | 27.99 seconds |
| Started | Sep 18 04:46:59 PM UTC 24 |
| Finished | Sep 18 04:47:29 PM UTC 24 |
| Peak memory | 251808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033213593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3033213593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.1865783520 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 242164520 ps |
| CPU time | 10.44 seconds |
| Started | Sep 18 04:45:18 PM UTC 24 |
| Finished | Sep 18 04:45:30 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865783520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.1865783520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1772993930 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2344927130 ps |
| CPU time | 19.06 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:21 PM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772993930 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.1772993930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.4290302981 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 9760093752 ps |
| CPU time | 17.69 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:22 PM UTC 24 |
| Peak memory | 255852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290302981 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.4290302981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.397340565 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 173018338369 ps |
| CPU time | 311.34 seconds |
| Started | Sep 18 04:43:22 PM UTC 24 |
| Finished | Sep 18 04:48:38 PM UTC 24 |
| Peak memory | 298676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397340565 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.397340565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.454002173 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 128307551 ps |
| CPU time | 4.26 seconds |
| Started | Sep 18 04:56:50 PM UTC 24 |
| Finished | Sep 18 04:56:56 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454002173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.454002173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.114190687 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 14442063530 ps |
| CPU time | 49.16 seconds |
| Started | Sep 18 04:43:32 PM UTC 24 |
| Finished | Sep 18 04:44:22 PM UTC 24 |
| Peak memory | 254048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114190687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.114190687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.3425883555 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 273632927 ps |
| CPU time | 4.72 seconds |
| Started | Sep 18 04:56:36 PM UTC 24 |
| Finished | Sep 18 04:56:41 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425883555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.3425883555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.1912146382 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 116875043 ps |
| CPU time | 4.21 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:09 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912146382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1912146382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.3629159337 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 2140633796 ps |
| CPU time | 3.97 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:20 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629159337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3629159337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2539077703 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 831746327 ps |
| CPU time | 7.67 seconds |
| Started | Sep 18 07:14:35 PM UTC 24 |
| Finished | Sep 18 07:14:44 PM UTC 24 |
| Peak memory | 251560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539077703 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.2539077703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2927034168 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 353248155 ps |
| CPU time | 2.13 seconds |
| Started | Sep 18 07:14:35 PM UTC 24 |
| Finished | Sep 18 07:14:38 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927034168 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.2927034168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.4275877890 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 75622559 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 07:14:35 PM UTC 24 |
| Finished | Sep 18 07:14:38 PM UTC 24 |
| Peak memory | 257184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4275877890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_cs r_mem_rw_with_rand_reset.4275877890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.3248586862 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 39640616 ps |
| CPU time | 1.39 seconds |
| Started | Sep 18 07:14:35 PM UTC 24 |
| Finished | Sep 18 07:14:37 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248586862 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.3248586862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.2107267748 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 41435562 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 07:14:35 PM UTC 24 |
| Finished | Sep 18 07:14:37 PM UTC 24 |
| Peak memory | 239992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107267748 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2107267748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.441326190 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 125903041 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 07:14:35 PM UTC 24 |
| Finished | Sep 18 07:14:37 PM UTC 24 |
| Peak memory | 241128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441326190 -assert nopostproc +U VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.441326190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3221533546 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 138445089 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 07:14:35 PM UTC 24 |
| Finished | Sep 18 07:14:37 PM UTC 24 |
| Peak memory | 239960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221533546 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.3221533546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.667676467 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 82824211 ps |
| CPU time | 2.53 seconds |
| Started | Sep 18 07:14:35 PM UTC 24 |
| Finished | Sep 18 07:14:39 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667676467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.667676467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.785640247 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 86453672 ps |
| CPU time | 4.55 seconds |
| Started | Sep 18 07:14:34 PM UTC 24 |
| Finished | Sep 18 07:14:39 PM UTC 24 |
| Peak memory | 257676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785640247 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.785640247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2808561491 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 163291163 ps |
| CPU time | 5.18 seconds |
| Started | Sep 18 07:14:39 PM UTC 24 |
| Finished | Sep 18 07:14:45 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808561491 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.2808561491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.318565672 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1282184703 ps |
| CPU time | 3.88 seconds |
| Started | Sep 18 07:14:39 PM UTC 24 |
| Finished | Sep 18 07:14:44 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318565672 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.318565672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2802550840 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 383908221 ps |
| CPU time | 2.01 seconds |
| Started | Sep 18 07:14:38 PM UTC 24 |
| Finished | Sep 18 07:14:41 PM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802550840 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.2802550840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2468864924 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 87502885 ps |
| CPU time | 1.85 seconds |
| Started | Sep 18 07:14:39 PM UTC 24 |
| Finished | Sep 18 07:14:42 PM UTC 24 |
| Peak memory | 255116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2468864924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_cs r_mem_rw_with_rand_reset.2468864924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.3255268140 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 73137949 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:14:36 PM UTC 24 |
| Finished | Sep 18 07:14:38 PM UTC 24 |
| Peak memory | 240740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255268140 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3255268140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.1804896449 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 110629488 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 07:14:38 PM UTC 24 |
| Finished | Sep 18 07:14:40 PM UTC 24 |
| Peak memory | 239864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804896449 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.1804896449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1029355284 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 124610367 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 07:14:38 PM UTC 24 |
| Finished | Sep 18 07:14:40 PM UTC 24 |
| Peak memory | 240916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029355284 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.1029355284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2759891521 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 172035271 ps |
| CPU time | 1.65 seconds |
| Started | Sep 18 07:14:39 PM UTC 24 |
| Finished | Sep 18 07:14:42 PM UTC 24 |
| Peak memory | 253292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759891521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.2759891521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1586582459 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 641523056 ps |
| CPU time | 5.24 seconds |
| Started | Sep 18 07:14:35 PM UTC 24 |
| Finished | Sep 18 07:14:42 PM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586582459 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.1586582459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.422999012 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 902333638 ps |
| CPU time | 9.95 seconds |
| Started | Sep 18 07:14:36 PM UTC 24 |
| Finished | Sep 18 07:14:47 PM UTC 24 |
| Peak memory | 255480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422999012 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.422999012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3433107344 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 1555293904 ps |
| CPU time | 3.83 seconds |
| Started | Sep 18 07:14:57 PM UTC 24 |
| Finished | Sep 18 07:15:02 PM UTC 24 |
| Peak memory | 257732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3433107344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_c sr_mem_rw_with_rand_reset.3433107344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3588727893 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 64468767 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 07:14:57 PM UTC 24 |
| Finished | Sep 18 07:14:59 PM UTC 24 |
| Peak memory | 253264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588727893 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3588727893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.1347033167 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 93841277 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 07:14:57 PM UTC 24 |
| Finished | Sep 18 07:14:59 PM UTC 24 |
| Peak memory | 240200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347033167 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.1347033167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.4165698562 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 123469786 ps |
| CPU time | 1.89 seconds |
| Started | Sep 18 07:14:57 PM UTC 24 |
| Finished | Sep 18 07:15:00 PM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165698562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.4165698562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.725152726 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 228031515 ps |
| CPU time | 2.78 seconds |
| Started | Sep 18 07:14:56 PM UTC 24 |
| Finished | Sep 18 07:15:00 PM UTC 24 |
| Peak memory | 257692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725152726 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.725152726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.2148974315 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 109790647 ps |
| CPU time | 2.44 seconds |
| Started | Sep 18 07:14:58 PM UTC 24 |
| Finished | Sep 18 07:15:02 PM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2148974315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_c sr_mem_rw_with_rand_reset.2148974315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2507577672 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 81026241 ps |
| CPU time | 1.43 seconds |
| Started | Sep 18 07:14:58 PM UTC 24 |
| Finished | Sep 18 07:15:00 PM UTC 24 |
| Peak memory | 253284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507577672 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.2507577672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.3332168239 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 88169702 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 07:14:57 PM UTC 24 |
| Finished | Sep 18 07:14:59 PM UTC 24 |
| Peak memory | 240056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332168239 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.3332168239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.4104270739 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 664234075 ps |
| CPU time | 1.84 seconds |
| Started | Sep 18 07:14:58 PM UTC 24 |
| Finished | Sep 18 07:15:01 PM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104270739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.4104270739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1734746423 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 209135306 ps |
| CPU time | 2.97 seconds |
| Started | Sep 18 07:14:57 PM UTC 24 |
| Finished | Sep 18 07:15:01 PM UTC 24 |
| Peak memory | 257696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734746423 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.1734746423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.3049519848 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 197879757 ps |
| CPU time | 3.09 seconds |
| Started | Sep 18 07:14:59 PM UTC 24 |
| Finished | Sep 18 07:15:04 PM UTC 24 |
| Peak memory | 257764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3049519848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_c sr_mem_rw_with_rand_reset.3049519848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.4015488735 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 573000507 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 07:14:59 PM UTC 24 |
| Finished | Sep 18 07:15:02 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015488735 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.4015488735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.3093553876 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 77097163 ps |
| CPU time | 1.43 seconds |
| Started | Sep 18 07:14:59 PM UTC 24 |
| Finished | Sep 18 07:15:02 PM UTC 24 |
| Peak memory | 240196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093553876 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.3093553876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3394948520 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 1901564939 ps |
| CPU time | 4.52 seconds |
| Started | Sep 18 07:14:59 PM UTC 24 |
| Finished | Sep 18 07:15:05 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394948520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.3394948520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.921365526 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 287962031 ps |
| CPU time | 4.79 seconds |
| Started | Sep 18 07:14:58 PM UTC 24 |
| Finished | Sep 18 07:15:04 PM UTC 24 |
| Peak memory | 257772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921365526 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.921365526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2010846365 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 5087739931 ps |
| CPU time | 21.68 seconds |
| Started | Sep 18 07:14:58 PM UTC 24 |
| Finished | Sep 18 07:15:21 PM UTC 24 |
| Peak memory | 255724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010846365 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.2010846365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.4084563790 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 99728859 ps |
| CPU time | 2.84 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:05 PM UTC 24 |
| Peak memory | 257764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4084563790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_c sr_mem_rw_with_rand_reset.4084563790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.4113467169 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 137351185 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:03 PM UTC 24 |
| Peak memory | 251104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113467169 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.4113467169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.2193709573 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 552125869 ps |
| CPU time | 1.68 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:04 PM UTC 24 |
| Peak memory | 241084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193709573 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.2193709573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3614251174 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 275300008 ps |
| CPU time | 2.35 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:04 PM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614251174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.3614251174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3786438999 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 303274045 ps |
| CPU time | 5.36 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:07 PM UTC 24 |
| Peak memory | 257672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786438999 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3786438999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3044695965 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 108990080 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:05 PM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3044695965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_c sr_mem_rw_with_rand_reset.3044695965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2687496399 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 61818074 ps |
| CPU time | 1.39 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:04 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687496399 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.2687496399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.2444180574 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 90892493 ps |
| CPU time | 1.5 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:04 PM UTC 24 |
| Peak memory | 240200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444180574 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2444180574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.82765303 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 686228012 ps |
| CPU time | 2.16 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:04 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82765303 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.82765303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1080961709 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 2613732362 ps |
| CPU time | 6.82 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:09 PM UTC 24 |
| Peak memory | 257936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080961709 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.1080961709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2128554947 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 1819453141 ps |
| CPU time | 21 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:23 PM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128554947 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.2128554947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2755929385 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 258459924 ps |
| CPU time | 1.98 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:04 PM UTC 24 |
| Peak memory | 255148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2755929385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_c sr_mem_rw_with_rand_reset.2755929385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2400729709 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 82626866 ps |
| CPU time | 1.5 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:04 PM UTC 24 |
| Peak memory | 253328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400729709 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.2400729709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.2535824178 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 39052225 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:04 PM UTC 24 |
| Peak memory | 240256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535824178 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.2535824178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.1575049002 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 166989407 ps |
| CPU time | 2.2 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:05 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575049002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.1575049002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.123802178 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 402288053 ps |
| CPU time | 4.09 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:06 PM UTC 24 |
| Peak memory | 257632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123802178 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.123802178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2085969127 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 4760951644 ps |
| CPU time | 16.83 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:19 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085969127 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.2085969127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1489607251 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 439113817 ps |
| CPU time | 3.16 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:07 PM UTC 24 |
| Peak memory | 257836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1489607251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_c sr_mem_rw_with_rand_reset.1489607251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1661690763 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 44736098 ps |
| CPU time | 1.69 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:04 PM UTC 24 |
| Peak memory | 253272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661690763 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.1661690763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.2463230000 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 41666649 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:04 PM UTC 24 |
| Peak memory | 240260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463230000 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.2463230000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3695016998 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 142993892 ps |
| CPU time | 2.29 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:06 PM UTC 24 |
| Peak memory | 253704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695016998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.3695016998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.4179989798 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 348909440 ps |
| CPU time | 3.75 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:06 PM UTC 24 |
| Peak memory | 257696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179989798 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.4179989798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2606367747 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 696629821 ps |
| CPU time | 9.81 seconds |
| Started | Sep 18 07:15:01 PM UTC 24 |
| Finished | Sep 18 07:15:12 PM UTC 24 |
| Peak memory | 255632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606367747 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.2606367747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2613635523 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 1671087090 ps |
| CPU time | 4.09 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 257736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2613635523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_c sr_mem_rw_with_rand_reset.2613635523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3948958485 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 632716053 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:06 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948958485 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3948958485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.1088709754 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 78251461 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:05 PM UTC 24 |
| Peak memory | 241080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088709754 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.1088709754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.132671483 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 109853943 ps |
| CPU time | 2.37 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:06 PM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132671483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.132671483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.836687558 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 983536052 ps |
| CPU time | 4.57 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 257708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836687558 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.836687558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1687237427 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 103660609 ps |
| CPU time | 3.24 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:07 PM UTC 24 |
| Peak memory | 257680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1687237427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_c sr_mem_rw_with_rand_reset.1687237427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3467595936 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 600795043 ps |
| CPU time | 1.86 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:06 PM UTC 24 |
| Peak memory | 253268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467595936 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.3467595936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.3556206277 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 68661404 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:05 PM UTC 24 |
| Peak memory | 239932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556206277 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.3556206277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.932341835 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 1906679502 ps |
| CPU time | 4.12 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932341835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.932341835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1664211875 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 340376571 ps |
| CPU time | 3.42 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 257892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664211875 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.1664211875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1474350424 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1231017193 ps |
| CPU time | 9.53 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:14 PM UTC 24 |
| Peak memory | 255704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474350424 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.1474350424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.478649915 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 69240139 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 257240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=478649915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_cs r_mem_rw_with_rand_reset.478649915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2323138797 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 97532842 ps |
| CPU time | 1.7 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:07 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323138797 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.2323138797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.34238326 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 567715491 ps |
| CPU time | 1.65 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:06 PM UTC 24 |
| Peak memory | 241088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34238326 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.34238326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1257017496 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 89664407 ps |
| CPU time | 1.77 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 253208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257017496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.1257017496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1050227737 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 130047521 ps |
| CPU time | 4.32 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:09 PM UTC 24 |
| Peak memory | 257580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050227737 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.1050227737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.284513587 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 20231295660 ps |
| CPU time | 26.26 seconds |
| Started | Sep 18 07:15:03 PM UTC 24 |
| Finished | Sep 18 07:15:31 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284513587 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.284513587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1532009739 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 79149834 ps |
| CPU time | 4.45 seconds |
| Started | Sep 18 07:14:43 PM UTC 24 |
| Finished | Sep 18 07:14:48 PM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532009739 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.1532009739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.455721515 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3751561528 ps |
| CPU time | 7.2 seconds |
| Started | Sep 18 07:14:42 PM UTC 24 |
| Finished | Sep 18 07:14:51 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455721515 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.455721515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.3771705354 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1555138839 ps |
| CPU time | 3.71 seconds |
| Started | Sep 18 07:14:41 PM UTC 24 |
| Finished | Sep 18 07:14:46 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771705354 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.3771705354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.953464313 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 115488187 ps |
| CPU time | 2.68 seconds |
| Started | Sep 18 07:14:44 PM UTC 24 |
| Finished | Sep 18 07:14:47 PM UTC 24 |
| Peak memory | 257664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=953464313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr _mem_rw_with_rand_reset.953464313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.212490582 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 40260593 ps |
| CPU time | 1.34 seconds |
| Started | Sep 18 07:14:42 PM UTC 24 |
| Finished | Sep 18 07:14:45 PM UTC 24 |
| Peak memory | 252484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212490582 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.212490582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.4195473800 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 146757016 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 07:14:41 PM UTC 24 |
| Finished | Sep 18 07:14:44 PM UTC 24 |
| Peak memory | 239204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195473800 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.4195473800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.4211376547 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 74105131 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:14:41 PM UTC 24 |
| Finished | Sep 18 07:14:44 PM UTC 24 |
| Peak memory | 239128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211376547 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.4211376547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3266593561 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 91437647 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 07:14:41 PM UTC 24 |
| Finished | Sep 18 07:14:44 PM UTC 24 |
| Peak memory | 239756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266593561 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.3266593561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3866526789 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 51271314 ps |
| CPU time | 1.81 seconds |
| Started | Sep 18 07:14:44 PM UTC 24 |
| Finished | Sep 18 07:14:46 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866526789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.3866526789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.4102312313 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 2122550673 ps |
| CPU time | 4.53 seconds |
| Started | Sep 18 07:14:40 PM UTC 24 |
| Finished | Sep 18 07:14:46 PM UTC 24 |
| Peak memory | 257764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102312313 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.4102312313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.1472265133 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 116120511 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:07 PM UTC 24 |
| Peak memory | 239900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472265133 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.1472265133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.694021905 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 70058057 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:07 PM UTC 24 |
| Peak memory | 240144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694021905 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.694021905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.1253519855 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 96678601 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:07 PM UTC 24 |
| Peak memory | 241144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253519855 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1253519855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.791951607 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 39667111 ps |
| CPU time | 1.39 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:07 PM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791951607 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.791951607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.1520690867 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 73667119 ps |
| CPU time | 1.43 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:07 PM UTC 24 |
| Peak memory | 239996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520690867 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.1520690867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.2969603260 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 551987124 ps |
| CPU time | 1.69 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 240256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969603260 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.2969603260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1590985025 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 151901553 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:07 PM UTC 24 |
| Peak memory | 241144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590985025 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1590985025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.40055780 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 145176089 ps |
| CPU time | 1.58 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 241088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40055780 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.40055780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.2655214840 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 46764989 ps |
| CPU time | 1.46 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 240048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655214840 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.2655214840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1890470933 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 157634503 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890470933 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1890470933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1448381721 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 113413858 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 07:14:45 PM UTC 24 |
| Finished | Sep 18 07:14:49 PM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448381721 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.1448381721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.54129051 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 311133446 ps |
| CPU time | 3.37 seconds |
| Started | Sep 18 07:14:45 PM UTC 24 |
| Finished | Sep 18 07:14:49 PM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54129051 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.54129051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2431584716 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 183216341 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 07:14:45 PM UTC 24 |
| Finished | Sep 18 07:14:48 PM UTC 24 |
| Peak memory | 253384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431584716 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.2431584716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2169353772 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 101245575 ps |
| CPU time | 1.85 seconds |
| Started | Sep 18 07:14:45 PM UTC 24 |
| Finished | Sep 18 07:14:48 PM UTC 24 |
| Peak memory | 255256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2169353772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_cs r_mem_rw_with_rand_reset.2169353772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.4006792975 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 148331602 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 07:14:45 PM UTC 24 |
| Finished | Sep 18 07:14:47 PM UTC 24 |
| Peak memory | 253408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006792975 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.4006792975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.559065078 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 144907046 ps |
| CPU time | 1.3 seconds |
| Started | Sep 18 07:14:45 PM UTC 24 |
| Finished | Sep 18 07:14:47 PM UTC 24 |
| Peak memory | 239940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559065078 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.559065078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1961234712 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 535260543 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 07:14:45 PM UTC 24 |
| Finished | Sep 18 07:14:47 PM UTC 24 |
| Peak memory | 240216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961234712 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.1961234712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.795924444 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 64057588 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 07:14:45 PM UTC 24 |
| Finished | Sep 18 07:14:47 PM UTC 24 |
| Peak memory | 240216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795924444 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.795924444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2820723584 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 219264632 ps |
| CPU time | 2.02 seconds |
| Started | Sep 18 07:14:45 PM UTC 24 |
| Finished | Sep 18 07:14:48 PM UTC 24 |
| Peak memory | 253720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820723584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.2820723584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1325664206 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 90194406 ps |
| CPU time | 5.09 seconds |
| Started | Sep 18 07:14:44 PM UTC 24 |
| Finished | Sep 18 07:14:50 PM UTC 24 |
| Peak memory | 257820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325664206 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1325664206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.388575728 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 1733387856 ps |
| CPU time | 18.96 seconds |
| Started | Sep 18 07:14:45 PM UTC 24 |
| Finished | Sep 18 07:15:05 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388575728 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.388575728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.2857445158 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 73557885 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 241084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857445158 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.2857445158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.3142857845 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 579879317 ps |
| CPU time | 1.57 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 241084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142857845 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.3142857845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.3415846494 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 136281772 ps |
| CPU time | 1.43 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 239996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415846494 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.3415846494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.1911283765 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 569945155 ps |
| CPU time | 1.46 seconds |
| Started | Sep 18 07:15:05 PM UTC 24 |
| Finished | Sep 18 07:15:08 PM UTC 24 |
| Peak memory | 240196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911283765 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1911283765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.4191298610 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 38155666 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:19 PM UTC 24 |
| Peak memory | 240108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191298610 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.4191298610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3401273300 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 92683276 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:19 PM UTC 24 |
| Peak memory | 240284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401273300 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3401273300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.4067847784 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 138048307 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:19 PM UTC 24 |
| Peak memory | 239936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067847784 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.4067847784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.3991202311 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 72110023 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:19 PM UTC 24 |
| Peak memory | 241140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991202311 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3991202311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.2127979095 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 550330059 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:19 PM UTC 24 |
| Peak memory | 239996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127979095 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2127979095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.4160145616 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 48848897 ps |
| CPU time | 1.32 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:19 PM UTC 24 |
| Peak memory | 240260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160145616 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.4160145616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1533185884 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 223599537 ps |
| CPU time | 3.27 seconds |
| Started | Sep 18 07:14:48 PM UTC 24 |
| Finished | Sep 18 07:14:53 PM UTC 24 |
| Peak memory | 253776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533185884 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.1533185884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1378775661 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 162552544 ps |
| CPU time | 3.2 seconds |
| Started | Sep 18 07:14:48 PM UTC 24 |
| Finished | Sep 18 07:14:53 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378775661 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.1378775661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1478258939 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 262659181 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 07:14:47 PM UTC 24 |
| Finished | Sep 18 07:14:50 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478258939 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.1478258939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3051116068 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 102897370 ps |
| CPU time | 2.98 seconds |
| Started | Sep 18 07:14:48 PM UTC 24 |
| Finished | Sep 18 07:14:52 PM UTC 24 |
| Peak memory | 257736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3051116068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_cs r_mem_rw_with_rand_reset.3051116068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3468724685 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 43388442 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 07:14:48 PM UTC 24 |
| Finished | Sep 18 07:14:51 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468724685 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3468724685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.3580961752 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 74755116 ps |
| CPU time | 1.21 seconds |
| Started | Sep 18 07:14:46 PM UTC 24 |
| Finished | Sep 18 07:14:48 PM UTC 24 |
| Peak memory | 241020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580961752 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.3580961752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.4156743815 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 144403278 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 07:14:47 PM UTC 24 |
| Finished | Sep 18 07:14:49 PM UTC 24 |
| Peak memory | 240160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156743815 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.4156743815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3561110017 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 100169451 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 07:14:47 PM UTC 24 |
| Finished | Sep 18 07:14:49 PM UTC 24 |
| Peak memory | 238216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561110017 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.3561110017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2400237111 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 242079162 ps |
| CPU time | 2.95 seconds |
| Started | Sep 18 07:14:48 PM UTC 24 |
| Finished | Sep 18 07:14:52 PM UTC 24 |
| Peak memory | 253572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400237111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.2400237111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2005166059 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 181989692 ps |
| CPU time | 5.19 seconds |
| Started | Sep 18 07:14:46 PM UTC 24 |
| Finished | Sep 18 07:14:52 PM UTC 24 |
| Peak memory | 257676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005166059 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.2005166059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1494979745 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1412289060 ps |
| CPU time | 15.95 seconds |
| Started | Sep 18 07:14:46 PM UTC 24 |
| Finished | Sep 18 07:15:03 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494979745 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.1494979745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.1298479123 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 84305841 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:09 PM UTC 24 |
| Peak memory | 240200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298479123 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.1298479123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.1436098780 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 49738662 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:19 PM UTC 24 |
| Peak memory | 240056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436098780 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.1436098780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.4182810096 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 41091948 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:19 PM UTC 24 |
| Peak memory | 240196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182810096 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.4182810096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.3619720645 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 52615288 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:19 PM UTC 24 |
| Peak memory | 241084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619720645 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3619720645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.188150039 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 541508746 ps |
| CPU time | 1.8 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:20 PM UTC 24 |
| Peak memory | 240252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188150039 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.188150039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.3532450851 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 41323330 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:19 PM UTC 24 |
| Peak memory | 240048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532450851 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.3532450851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.3128723213 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 567366058 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:20 PM UTC 24 |
| Peak memory | 240220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128723213 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.3128723213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.85156059 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 145947123 ps |
| CPU time | 1.46 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:19 PM UTC 24 |
| Peak memory | 241088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85156059 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.85156059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.3822845707 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 511893715 ps |
| CPU time | 1.5 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:20 PM UTC 24 |
| Peak memory | 240256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822845707 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.3822845707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3213182026 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 40796172 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 07:15:07 PM UTC 24 |
| Finished | Sep 18 07:15:19 PM UTC 24 |
| Peak memory | 241084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213182026 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3213182026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2537453676 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 75127942 ps |
| CPU time | 1.85 seconds |
| Started | Sep 18 07:14:50 PM UTC 24 |
| Finished | Sep 18 07:14:53 PM UTC 24 |
| Peak memory | 255200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2537453676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_cs r_mem_rw_with_rand_reset.2537453676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1824344516 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 140360745 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 07:14:49 PM UTC 24 |
| Finished | Sep 18 07:14:51 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824344516 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.1824344516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.3290275443 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 37546215 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 07:14:49 PM UTC 24 |
| Finished | Sep 18 07:14:51 PM UTC 24 |
| Peak memory | 241020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290275443 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3290275443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.379344577 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 89342548 ps |
| CPU time | 1.74 seconds |
| Started | Sep 18 07:14:49 PM UTC 24 |
| Finished | Sep 18 07:14:51 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379344577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.379344577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2153466406 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 351130366 ps |
| CPU time | 5.99 seconds |
| Started | Sep 18 07:14:48 PM UTC 24 |
| Finished | Sep 18 07:14:56 PM UTC 24 |
| Peak memory | 257696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153466406 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.2153466406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2120579569 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2605373730 ps |
| CPU time | 21.94 seconds |
| Started | Sep 18 07:14:49 PM UTC 24 |
| Finished | Sep 18 07:15:12 PM UTC 24 |
| Peak memory | 255724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120579569 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.2120579569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3463073057 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 145070483 ps |
| CPU time | 1.91 seconds |
| Started | Sep 18 07:14:51 PM UTC 24 |
| Finished | Sep 18 07:14:54 PM UTC 24 |
| Peak memory | 255212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3463073057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_cs r_mem_rw_with_rand_reset.3463073057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2645420129 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 59233911 ps |
| CPU time | 1.55 seconds |
| Started | Sep 18 07:14:50 PM UTC 24 |
| Finished | Sep 18 07:14:52 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645420129 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2645420129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.785080981 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 56217653 ps |
| CPU time | 1.21 seconds |
| Started | Sep 18 07:14:50 PM UTC 24 |
| Finished | Sep 18 07:14:52 PM UTC 24 |
| Peak memory | 241088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785080981 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.785080981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1101788950 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 111745175 ps |
| CPU time | 2.1 seconds |
| Started | Sep 18 07:14:50 PM UTC 24 |
| Finished | Sep 18 07:14:53 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101788950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.1101788950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3528525964 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 183094287 ps |
| CPU time | 5.72 seconds |
| Started | Sep 18 07:14:50 PM UTC 24 |
| Finished | Sep 18 07:14:57 PM UTC 24 |
| Peak memory | 257492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528525964 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.3528525964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.4129957652 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 4802029236 ps |
| CPU time | 15.66 seconds |
| Started | Sep 18 07:14:50 PM UTC 24 |
| Finished | Sep 18 07:15:06 PM UTC 24 |
| Peak memory | 255660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129957652 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.4129957652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1657684133 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 1684697808 ps |
| CPU time | 3.17 seconds |
| Started | Sep 18 07:14:52 PM UTC 24 |
| Finished | Sep 18 07:14:56 PM UTC 24 |
| Peak memory | 257768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1657684133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_cs r_mem_rw_with_rand_reset.1657684133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.380492576 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 171209602 ps |
| CPU time | 1.52 seconds |
| Started | Sep 18 07:14:52 PM UTC 24 |
| Finished | Sep 18 07:14:55 PM UTC 24 |
| Peak memory | 253324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380492576 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.380492576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.3619902258 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 148771217 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 07:14:52 PM UTC 24 |
| Finished | Sep 18 07:14:54 PM UTC 24 |
| Peak memory | 241020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619902258 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3619902258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2640558452 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 233902134 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 07:14:52 PM UTC 24 |
| Finished | Sep 18 07:14:55 PM UTC 24 |
| Peak memory | 253164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640558452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.2640558452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1301219048 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 817716616 ps |
| CPU time | 2.88 seconds |
| Started | Sep 18 07:14:51 PM UTC 24 |
| Finished | Sep 18 07:14:55 PM UTC 24 |
| Peak memory | 257700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301219048 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.1301219048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3243630590 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 3213639736 ps |
| CPU time | 19.49 seconds |
| Started | Sep 18 07:14:52 PM UTC 24 |
| Finished | Sep 18 07:15:13 PM UTC 24 |
| Peak memory | 255648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243630590 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.3243630590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.510177563 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 279361673 ps |
| CPU time | 2.14 seconds |
| Started | Sep 18 07:14:53 PM UTC 24 |
| Finished | Sep 18 07:14:57 PM UTC 24 |
| Peak memory | 257728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=510177563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr _mem_rw_with_rand_reset.510177563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2095094421 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 132425396 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 07:14:53 PM UTC 24 |
| Finished | Sep 18 07:14:56 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095094421 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.2095094421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.1116266932 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 557908551 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 07:14:53 PM UTC 24 |
| Finished | Sep 18 07:14:56 PM UTC 24 |
| Peak memory | 241028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116266932 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.1116266932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2311645317 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 490986059 ps |
| CPU time | 2.79 seconds |
| Started | Sep 18 07:14:53 PM UTC 24 |
| Finished | Sep 18 07:14:57 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311645317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.2311645317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.4071018289 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 190499220 ps |
| CPU time | 2.61 seconds |
| Started | Sep 18 07:14:53 PM UTC 24 |
| Finished | Sep 18 07:14:57 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071018289 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.4071018289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3502539841 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 2631472022 ps |
| CPU time | 18.48 seconds |
| Started | Sep 18 07:14:53 PM UTC 24 |
| Finished | Sep 18 07:15:13 PM UTC 24 |
| Peak memory | 255704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502539841 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.3502539841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3445778702 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 1715052958 ps |
| CPU time | 3.99 seconds |
| Started | Sep 18 07:14:56 PM UTC 24 |
| Finished | Sep 18 07:15:01 PM UTC 24 |
| Peak memory | 257928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3445778702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_cs r_mem_rw_with_rand_reset.3445778702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3208351622 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 542369999 ps |
| CPU time | 1.43 seconds |
| Started | Sep 18 07:14:55 PM UTC 24 |
| Finished | Sep 18 07:14:57 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208351622 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.3208351622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.198435372 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 75198875 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 07:14:54 PM UTC 24 |
| Finished | Sep 18 07:14:56 PM UTC 24 |
| Peak memory | 240264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198435372 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.198435372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3626011132 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 99881806 ps |
| CPU time | 1.74 seconds |
| Started | Sep 18 07:14:55 PM UTC 24 |
| Finished | Sep 18 07:14:57 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626011132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.3626011132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3518615874 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 114536417 ps |
| CPU time | 3.71 seconds |
| Started | Sep 18 07:14:53 PM UTC 24 |
| Finished | Sep 18 07:14:58 PM UTC 24 |
| Peak memory | 257776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518615874 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.3518615874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3022241457 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1283478585 ps |
| CPU time | 9.48 seconds |
| Started | Sep 18 07:14:53 PM UTC 24 |
| Finished | Sep 18 07:15:04 PM UTC 24 |
| Peak memory | 255528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022241457 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.3022241457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.273801510 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 321246337 ps |
| CPU time | 15.87 seconds |
| Started | Sep 18 04:43:16 PM UTC 24 |
| Finished | Sep 18 04:43:33 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273801510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.273801510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.3816182541 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2638161058 ps |
| CPU time | 11.2 seconds |
| Started | Sep 18 04:43:16 PM UTC 24 |
| Finished | Sep 18 04:43:29 PM UTC 24 |
| Peak memory | 252128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816182541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3816182541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.4252805176 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3072686748 ps |
| CPU time | 14 seconds |
| Started | Sep 18 04:43:10 PM UTC 24 |
| Finished | Sep 18 04:43:25 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252805176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.4252805176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.1434909799 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1238697190 ps |
| CPU time | 35.34 seconds |
| Started | Sep 18 04:43:19 PM UTC 24 |
| Finished | Sep 18 04:43:56 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434909799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.1434909799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.709246359 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 11404631572 ps |
| CPU time | 58.42 seconds |
| Started | Sep 18 04:43:19 PM UTC 24 |
| Finished | Sep 18 04:44:19 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709246359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.709246359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.1987598810 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4020747728 ps |
| CPU time | 7.5 seconds |
| Started | Sep 18 04:43:15 PM UTC 24 |
| Finished | Sep 18 04:43:24 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987598810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.1987598810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.980383080 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 709425024 ps |
| CPU time | 25.58 seconds |
| Started | Sep 18 04:43:10 PM UTC 24 |
| Finished | Sep 18 04:43:37 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980383080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.980383080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.3518605830 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2435692388 ps |
| CPU time | 15.43 seconds |
| Started | Sep 18 04:43:19 PM UTC 24 |
| Finished | Sep 18 04:43:36 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518605830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.3518605830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.2724501740 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 451102441 ps |
| CPU time | 7.81 seconds |
| Started | Sep 18 04:43:09 PM UTC 24 |
| Finished | Sep 18 04:43:18 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724501740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.2724501740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.1974930044 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1001126358 ps |
| CPU time | 4.76 seconds |
| Started | Sep 18 04:43:42 PM UTC 24 |
| Finished | Sep 18 04:43:48 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974930044 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.1974930044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.2019465028 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1624029892 ps |
| CPU time | 14.15 seconds |
| Started | Sep 18 04:43:27 PM UTC 24 |
| Finished | Sep 18 04:43:42 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019465028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.2019465028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.763616579 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 788418120 ps |
| CPU time | 27.99 seconds |
| Started | Sep 18 04:43:29 PM UTC 24 |
| Finished | Sep 18 04:43:59 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763616579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.763616579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.1752049769 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 27578188650 ps |
| CPU time | 241 seconds |
| Started | Sep 18 04:43:29 PM UTC 24 |
| Finished | Sep 18 04:47:34 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752049769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.1752049769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.1303576068 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 225302570 ps |
| CPU time | 5.87 seconds |
| Started | Sep 18 04:43:34 PM UTC 24 |
| Finished | Sep 18 04:43:41 PM UTC 24 |
| Peak memory | 251808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303576068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.1303576068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.1956251988 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 628880283 ps |
| CPU time | 6.33 seconds |
| Started | Sep 18 04:43:28 PM UTC 24 |
| Finished | Sep 18 04:43:36 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956251988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.1956251988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.150686909 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1631582184 ps |
| CPU time | 30.95 seconds |
| Started | Sep 18 04:43:27 PM UTC 24 |
| Finished | Sep 18 04:43:59 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150686909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.150686909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.1302089483 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 207209493 ps |
| CPU time | 9.54 seconds |
| Started | Sep 18 04:43:34 PM UTC 24 |
| Finished | Sep 18 04:43:45 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302089483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.1302089483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.3090596931 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 305480418 ps |
| CPU time | 5.85 seconds |
| Started | Sep 18 04:43:26 PM UTC 24 |
| Finished | Sep 18 04:43:33 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090596931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3090596931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.2747514373 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 18801102706 ps |
| CPU time | 55.37 seconds |
| Started | Sep 18 04:43:38 PM UTC 24 |
| Finished | Sep 18 04:44:35 PM UTC 24 |
| Peak memory | 254136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747514373 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.2747514373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.4079885028 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 247540662 ps |
| CPU time | 11.92 seconds |
| Started | Sep 18 04:43:37 PM UTC 24 |
| Finished | Sep 18 04:43:50 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079885028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.4079885028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.434295341 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 128016876 ps |
| CPU time | 3.29 seconds |
| Started | Sep 18 04:47:24 PM UTC 24 |
| Finished | Sep 18 04:47:28 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434295341 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.434295341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.3658465992 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2500865584 ps |
| CPU time | 30.23 seconds |
| Started | Sep 18 04:47:17 PM UTC 24 |
| Finished | Sep 18 04:47:49 PM UTC 24 |
| Peak memory | 252204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658465992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.3658465992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.2323570892 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3614917798 ps |
| CPU time | 26.42 seconds |
| Started | Sep 18 04:47:17 PM UTC 24 |
| Finished | Sep 18 04:47:45 PM UTC 24 |
| Peak memory | 254048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323570892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.2323570892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.2398457465 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 976870562 ps |
| CPU time | 24.05 seconds |
| Started | Sep 18 04:47:17 PM UTC 24 |
| Finished | Sep 18 04:47:43 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398457465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2398457465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.2899026669 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 503472906 ps |
| CPU time | 4.03 seconds |
| Started | Sep 18 04:47:12 PM UTC 24 |
| Finished | Sep 18 04:47:18 PM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899026669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.2899026669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.318130293 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 5005902466 ps |
| CPU time | 10.52 seconds |
| Started | Sep 18 04:47:19 PM UTC 24 |
| Finished | Sep 18 04:47:31 PM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318130293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.318130293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.1291141404 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 11198136991 ps |
| CPU time | 23.78 seconds |
| Started | Sep 18 04:47:19 PM UTC 24 |
| Finished | Sep 18 04:47:44 PM UTC 24 |
| Peak memory | 254132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291141404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.1291141404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.897728204 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 327290656 ps |
| CPU time | 8.86 seconds |
| Started | Sep 18 04:47:17 PM UTC 24 |
| Finished | Sep 18 04:47:27 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897728204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.897728204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.3584418751 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 6545860588 ps |
| CPU time | 15.25 seconds |
| Started | Sep 18 04:47:14 PM UTC 24 |
| Finished | Sep 18 04:47:30 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584418751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.3584418751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.1309836137 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 174602228 ps |
| CPU time | 4.88 seconds |
| Started | Sep 18 04:47:19 PM UTC 24 |
| Finished | Sep 18 04:47:25 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309836137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.1309836137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.1113540843 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 274211130 ps |
| CPU time | 6.22 seconds |
| Started | Sep 18 04:47:11 PM UTC 24 |
| Finished | Sep 18 04:47:18 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113540843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.1113540843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.2104709169 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 9911329981 ps |
| CPU time | 90.11 seconds |
| Started | Sep 18 04:47:22 PM UTC 24 |
| Finished | Sep 18 04:48:54 PM UTC 24 |
| Peak memory | 258120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2104709169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.otp_ctrl_stress_all_with_rand_reset.2104709169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.4055940250 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2574148226 ps |
| CPU time | 27.85 seconds |
| Started | Sep 18 04:47:22 PM UTC 24 |
| Finished | Sep 18 04:47:52 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055940250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.4055940250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.3435067041 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 3882533822 ps |
| CPU time | 15.72 seconds |
| Started | Sep 18 04:55:53 PM UTC 24 |
| Finished | Sep 18 04:56:10 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435067041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.3435067041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.3219296539 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 519388214 ps |
| CPU time | 5.22 seconds |
| Started | Sep 18 04:55:56 PM UTC 24 |
| Finished | Sep 18 04:56:02 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219296539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3219296539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.738562370 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 85251681 ps |
| CPU time | 4.38 seconds |
| Started | Sep 18 04:55:56 PM UTC 24 |
| Finished | Sep 18 04:56:02 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738562370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.738562370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.1056978328 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 110395961 ps |
| CPU time | 5.6 seconds |
| Started | Sep 18 04:55:56 PM UTC 24 |
| Finished | Sep 18 04:56:03 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056978328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.1056978328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.835513445 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 652358981 ps |
| CPU time | 5.9 seconds |
| Started | Sep 18 04:55:56 PM UTC 24 |
| Finished | Sep 18 04:56:03 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835513445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.835513445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.1614875013 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 159787426 ps |
| CPU time | 5.58 seconds |
| Started | Sep 18 04:55:56 PM UTC 24 |
| Finished | Sep 18 04:56:03 PM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614875013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.1614875013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.3674694152 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 140541574 ps |
| CPU time | 7.58 seconds |
| Started | Sep 18 04:55:56 PM UTC 24 |
| Finished | Sep 18 04:56:05 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674694152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.3674694152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.3005595139 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 1769823319 ps |
| CPU time | 8.75 seconds |
| Started | Sep 18 04:55:56 PM UTC 24 |
| Finished | Sep 18 04:56:07 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005595139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.3005595139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.1398536290 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 1210795376 ps |
| CPU time | 9.78 seconds |
| Started | Sep 18 04:55:56 PM UTC 24 |
| Finished | Sep 18 04:56:08 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398536290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.1398536290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.1087980422 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2810612310 ps |
| CPU time | 16.49 seconds |
| Started | Sep 18 04:55:59 PM UTC 24 |
| Finished | Sep 18 04:56:17 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087980422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.1087980422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.2518019225 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 572970975 ps |
| CPU time | 5.95 seconds |
| Started | Sep 18 04:56:00 PM UTC 24 |
| Finished | Sep 18 04:56:07 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518019225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.2518019225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.2292129621 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 274890997 ps |
| CPU time | 5 seconds |
| Started | Sep 18 04:56:02 PM UTC 24 |
| Finished | Sep 18 04:56:09 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292129621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.2292129621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.4208949484 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 519397806 ps |
| CPU time | 5.14 seconds |
| Started | Sep 18 04:56:02 PM UTC 24 |
| Finished | Sep 18 04:56:09 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208949484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.4208949484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.942973852 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 243046854 ps |
| CPU time | 8.72 seconds |
| Started | Sep 18 04:56:03 PM UTC 24 |
| Finished | Sep 18 04:56:13 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942973852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.942973852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.3822087892 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 1752553047 ps |
| CPU time | 7.42 seconds |
| Started | Sep 18 04:56:03 PM UTC 24 |
| Finished | Sep 18 04:56:11 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822087892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.3822087892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.3220472322 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 632677471 ps |
| CPU time | 19.06 seconds |
| Started | Sep 18 04:56:04 PM UTC 24 |
| Finished | Sep 18 04:56:24 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220472322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.3220472322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.1300923374 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 113909864 ps |
| CPU time | 2.53 seconds |
| Started | Sep 18 04:47:34 PM UTC 24 |
| Finished | Sep 18 04:47:38 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300923374 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.1300923374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.639766938 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 449085582 ps |
| CPU time | 7.49 seconds |
| Started | Sep 18 04:47:32 PM UTC 24 |
| Finished | Sep 18 04:47:40 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639766938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.639766938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.3194128318 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 923406764 ps |
| CPU time | 27.79 seconds |
| Started | Sep 18 04:47:32 PM UTC 24 |
| Finished | Sep 18 04:48:01 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194128318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.3194128318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.3373892867 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1493774270 ps |
| CPU time | 31.48 seconds |
| Started | Sep 18 04:47:28 PM UTC 24 |
| Finished | Sep 18 04:48:01 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373892867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.3373892867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.2511418301 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 429705148 ps |
| CPU time | 5.02 seconds |
| Started | Sep 18 04:47:28 PM UTC 24 |
| Finished | Sep 18 04:47:34 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511418301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.2511418301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.2666402431 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 4096947365 ps |
| CPU time | 51.84 seconds |
| Started | Sep 18 04:47:32 PM UTC 24 |
| Finished | Sep 18 04:48:25 PM UTC 24 |
| Peak memory | 268472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666402431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.2666402431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.2629937134 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1352545564 ps |
| CPU time | 29.49 seconds |
| Started | Sep 18 04:47:32 PM UTC 24 |
| Finished | Sep 18 04:48:03 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629937134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2629937134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.3688190921 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 177820801 ps |
| CPU time | 3.63 seconds |
| Started | Sep 18 04:47:28 PM UTC 24 |
| Finished | Sep 18 04:47:33 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688190921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.3688190921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.3222457777 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 272652021 ps |
| CPU time | 6.48 seconds |
| Started | Sep 18 04:47:32 PM UTC 24 |
| Finished | Sep 18 04:47:40 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222457777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.3222457777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.2303374349 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 146398746 ps |
| CPU time | 4.31 seconds |
| Started | Sep 18 04:47:28 PM UTC 24 |
| Finished | Sep 18 04:47:34 PM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303374349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.2303374349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.999294892 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2296511908 ps |
| CPU time | 67.67 seconds |
| Started | Sep 18 04:47:32 PM UTC 24 |
| Finished | Sep 18 04:48:41 PM UTC 24 |
| Peak memory | 268400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=999294892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.999294892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.1963773752 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1006763527 ps |
| CPU time | 15.44 seconds |
| Started | Sep 18 04:47:32 PM UTC 24 |
| Finished | Sep 18 04:47:49 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963773752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.1963773752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.3057089373 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 1598815200 ps |
| CPU time | 6.65 seconds |
| Started | Sep 18 04:56:04 PM UTC 24 |
| Finished | Sep 18 04:56:12 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057089373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.3057089373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.4104699086 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 343364447 ps |
| CPU time | 9.97 seconds |
| Started | Sep 18 04:56:04 PM UTC 24 |
| Finished | Sep 18 04:56:15 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104699086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.4104699086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.3344241148 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 119881708 ps |
| CPU time | 5.31 seconds |
| Started | Sep 18 04:56:04 PM UTC 24 |
| Finished | Sep 18 04:56:11 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344241148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3344241148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.1476490117 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 2317252687 ps |
| CPU time | 31.03 seconds |
| Started | Sep 18 04:56:04 PM UTC 24 |
| Finished | Sep 18 04:56:37 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476490117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.1476490117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.1060711417 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 2077694966 ps |
| CPU time | 8.59 seconds |
| Started | Sep 18 04:56:05 PM UTC 24 |
| Finished | Sep 18 04:56:15 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060711417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.1060711417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.1342443924 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 518008211 ps |
| CPU time | 10.63 seconds |
| Started | Sep 18 04:56:08 PM UTC 24 |
| Finished | Sep 18 04:56:20 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342443924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.1342443924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.882641719 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 138817769 ps |
| CPU time | 4.24 seconds |
| Started | Sep 18 04:56:08 PM UTC 24 |
| Finished | Sep 18 04:56:13 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882641719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.882641719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.1201447748 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 358891143 ps |
| CPU time | 4.59 seconds |
| Started | Sep 18 04:56:10 PM UTC 24 |
| Finished | Sep 18 04:56:15 PM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201447748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.1201447748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.4087976107 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 374714317 ps |
| CPU time | 5.27 seconds |
| Started | Sep 18 04:56:10 PM UTC 24 |
| Finished | Sep 18 04:56:16 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087976107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.4087976107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.3247577742 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 1318976378 ps |
| CPU time | 11.58 seconds |
| Started | Sep 18 04:56:10 PM UTC 24 |
| Finished | Sep 18 04:56:22 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247577742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3247577742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.3459035670 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 306492630 ps |
| CPU time | 5.37 seconds |
| Started | Sep 18 04:56:10 PM UTC 24 |
| Finished | Sep 18 04:56:16 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459035670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.3459035670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.2302453059 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 537473245 ps |
| CPU time | 5.98 seconds |
| Started | Sep 18 04:56:11 PM UTC 24 |
| Finished | Sep 18 04:56:19 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302453059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.2302453059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.2271334422 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1611002241 ps |
| CPU time | 6 seconds |
| Started | Sep 18 04:56:11 PM UTC 24 |
| Finished | Sep 18 04:56:19 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271334422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.2271334422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.2536042625 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 145538847 ps |
| CPU time | 6.77 seconds |
| Started | Sep 18 04:56:12 PM UTC 24 |
| Finished | Sep 18 04:56:19 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536042625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.2536042625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.1084039853 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 118912359 ps |
| CPU time | 4 seconds |
| Started | Sep 18 04:56:12 PM UTC 24 |
| Finished | Sep 18 04:56:17 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084039853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.1084039853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.2417529673 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 613832033 ps |
| CPU time | 7 seconds |
| Started | Sep 18 04:56:14 PM UTC 24 |
| Finished | Sep 18 04:56:22 PM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417529673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2417529673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.4208361424 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 234777858 ps |
| CPU time | 4.25 seconds |
| Started | Sep 18 04:56:14 PM UTC 24 |
| Finished | Sep 18 04:56:19 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208361424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.4208361424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.780978222 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 260762314 ps |
| CPU time | 6.79 seconds |
| Started | Sep 18 04:56:14 PM UTC 24 |
| Finished | Sep 18 04:56:22 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780978222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.780978222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.327440381 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 76596089 ps |
| CPU time | 3.16 seconds |
| Started | Sep 18 04:47:50 PM UTC 24 |
| Finished | Sep 18 04:47:54 PM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327440381 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.327440381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.2904979900 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1812056234 ps |
| CPU time | 30.54 seconds |
| Started | Sep 18 04:47:41 PM UTC 24 |
| Finished | Sep 18 04:48:13 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904979900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.2904979900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.788671741 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1356357035 ps |
| CPU time | 21.47 seconds |
| Started | Sep 18 04:47:40 PM UTC 24 |
| Finished | Sep 18 04:48:03 PM UTC 24 |
| Peak memory | 252084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788671741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.788671741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.2761154842 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1624517055 ps |
| CPU time | 31.97 seconds |
| Started | Sep 18 04:47:45 PM UTC 24 |
| Finished | Sep 18 04:48:19 PM UTC 24 |
| Peak memory | 255948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761154842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.2761154842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.2293887738 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3068324779 ps |
| CPU time | 30.07 seconds |
| Started | Sep 18 04:47:45 PM UTC 24 |
| Finished | Sep 18 04:48:17 PM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293887738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.2293887738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.3937169518 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 630850366 ps |
| CPU time | 8.14 seconds |
| Started | Sep 18 04:47:39 PM UTC 24 |
| Finished | Sep 18 04:47:48 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937169518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.3937169518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.228579296 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 145609600 ps |
| CPU time | 7.04 seconds |
| Started | Sep 18 04:47:36 PM UTC 24 |
| Finished | Sep 18 04:47:44 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228579296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.228579296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.2227382125 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 2003207719 ps |
| CPU time | 11.69 seconds |
| Started | Sep 18 04:47:34 PM UTC 24 |
| Finished | Sep 18 04:47:47 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227382125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2227382125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.1071753830 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 10766214118 ps |
| CPU time | 57.25 seconds |
| Started | Sep 18 04:47:50 PM UTC 24 |
| Finished | Sep 18 04:48:49 PM UTC 24 |
| Peak memory | 255992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071753830 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.1071753830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.473062009 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3764983766 ps |
| CPU time | 20.47 seconds |
| Started | Sep 18 04:47:47 PM UTC 24 |
| Finished | Sep 18 04:48:09 PM UTC 24 |
| Peak memory | 252004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473062009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.473062009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.237846151 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 442265984 ps |
| CPU time | 5.72 seconds |
| Started | Sep 18 04:56:14 PM UTC 24 |
| Finished | Sep 18 04:56:21 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237846151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.237846151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.3106275478 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 872325875 ps |
| CPU time | 8.18 seconds |
| Started | Sep 18 04:56:14 PM UTC 24 |
| Finished | Sep 18 04:56:23 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106275478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.3106275478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.2017295590 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 245944431 ps |
| CPU time | 4.84 seconds |
| Started | Sep 18 04:56:14 PM UTC 24 |
| Finished | Sep 18 04:56:20 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017295590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2017295590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.1598362884 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 578895909 ps |
| CPU time | 7.47 seconds |
| Started | Sep 18 04:56:14 PM UTC 24 |
| Finished | Sep 18 04:56:23 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598362884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.1598362884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.633787775 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 95786109 ps |
| CPU time | 4.27 seconds |
| Started | Sep 18 04:56:18 PM UTC 24 |
| Finished | Sep 18 04:56:24 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633787775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.633787775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.3993814097 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 385966888 ps |
| CPU time | 9.5 seconds |
| Started | Sep 18 04:56:18 PM UTC 24 |
| Finished | Sep 18 04:56:29 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993814097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.3993814097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.2237528717 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 127964226 ps |
| CPU time | 4.14 seconds |
| Started | Sep 18 04:56:18 PM UTC 24 |
| Finished | Sep 18 04:56:24 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237528717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.2237528717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.2286812565 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 134263590 ps |
| CPU time | 6.4 seconds |
| Started | Sep 18 04:56:18 PM UTC 24 |
| Finished | Sep 18 04:56:26 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286812565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.2286812565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.670783011 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 2510350134 ps |
| CPU time | 5.31 seconds |
| Started | Sep 18 04:56:19 PM UTC 24 |
| Finished | Sep 18 04:56:25 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670783011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.670783011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.2651916772 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 3352483740 ps |
| CPU time | 7.99 seconds |
| Started | Sep 18 04:56:19 PM UTC 24 |
| Finished | Sep 18 04:56:28 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651916772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.2651916772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.730143765 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 868110140 ps |
| CPU time | 10.35 seconds |
| Started | Sep 18 04:56:19 PM UTC 24 |
| Finished | Sep 18 04:56:30 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730143765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.730143765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.1340644152 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 166002460 ps |
| CPU time | 4.17 seconds |
| Started | Sep 18 04:56:19 PM UTC 24 |
| Finished | Sep 18 04:56:24 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340644152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.1340644152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.189638536 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 109737986 ps |
| CPU time | 3.17 seconds |
| Started | Sep 18 04:56:19 PM UTC 24 |
| Finished | Sep 18 04:56:23 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189638536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.189638536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.3581193508 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 135506282 ps |
| CPU time | 3.79 seconds |
| Started | Sep 18 04:56:19 PM UTC 24 |
| Finished | Sep 18 04:56:24 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581193508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.3581193508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.3850382045 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 1826811274 ps |
| CPU time | 16.65 seconds |
| Started | Sep 18 04:56:22 PM UTC 24 |
| Finished | Sep 18 04:56:40 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850382045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.3850382045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.3261941210 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 609160559 ps |
| CPU time | 4.76 seconds |
| Started | Sep 18 04:56:22 PM UTC 24 |
| Finished | Sep 18 04:56:28 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261941210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.3261941210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.4112214940 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 1310498409 ps |
| CPU time | 12.69 seconds |
| Started | Sep 18 04:56:22 PM UTC 24 |
| Finished | Sep 18 04:56:36 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112214940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.4112214940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.1424760753 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 172000571 ps |
| CPU time | 3.44 seconds |
| Started | Sep 18 04:56:22 PM UTC 24 |
| Finished | Sep 18 04:56:26 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424760753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.1424760753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.896467168 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 70687060 ps |
| CPU time | 3.5 seconds |
| Started | Sep 18 04:56:22 PM UTC 24 |
| Finished | Sep 18 04:56:26 PM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896467168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.896467168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.1318186103 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 91722094 ps |
| CPU time | 1.83 seconds |
| Started | Sep 18 04:48:06 PM UTC 24 |
| Finished | Sep 18 04:48:09 PM UTC 24 |
| Peak memory | 250764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318186103 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1318186103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.3007446094 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1055038710 ps |
| CPU time | 33.27 seconds |
| Started | Sep 18 04:48:00 PM UTC 24 |
| Finished | Sep 18 04:48:35 PM UTC 24 |
| Peak memory | 252120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007446094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.3007446094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.2437342957 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 21838491845 ps |
| CPU time | 62.68 seconds |
| Started | Sep 18 04:47:59 PM UTC 24 |
| Finished | Sep 18 04:49:03 PM UTC 24 |
| Peak memory | 262240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437342957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.2437342957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.1394978243 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3039719093 ps |
| CPU time | 36.46 seconds |
| Started | Sep 18 04:47:59 PM UTC 24 |
| Finished | Sep 18 04:48:37 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394978243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.1394978243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.2082963943 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 222786453 ps |
| CPU time | 5.07 seconds |
| Started | Sep 18 04:47:53 PM UTC 24 |
| Finished | Sep 18 04:47:59 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082963943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.2082963943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.2497919826 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 166031540 ps |
| CPU time | 6.83 seconds |
| Started | Sep 18 04:48:03 PM UTC 24 |
| Finished | Sep 18 04:48:11 PM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497919826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.2497919826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.783153512 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 235939050 ps |
| CPU time | 5.45 seconds |
| Started | Sep 18 04:47:55 PM UTC 24 |
| Finished | Sep 18 04:48:02 PM UTC 24 |
| Peak memory | 251648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783153512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.783153512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.707033462 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 4220836010 ps |
| CPU time | 19.98 seconds |
| Started | Sep 18 04:48:03 PM UTC 24 |
| Finished | Sep 18 04:48:24 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707033462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.707033462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.1701388925 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1306127451 ps |
| CPU time | 19.25 seconds |
| Started | Sep 18 04:47:51 PM UTC 24 |
| Finished | Sep 18 04:48:12 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701388925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1701388925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.230079440 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 19145631881 ps |
| CPU time | 87.5 seconds |
| Started | Sep 18 04:48:05 PM UTC 24 |
| Finished | Sep 18 04:49:35 PM UTC 24 |
| Peak memory | 255988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230079440 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.230079440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.3913258857 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 12348060304 ps |
| CPU time | 20.68 seconds |
| Started | Sep 18 04:48:03 PM UTC 24 |
| Finished | Sep 18 04:48:25 PM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913258857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.3913258857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.1521046140 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 507958569 ps |
| CPU time | 4.97 seconds |
| Started | Sep 18 04:56:22 PM UTC 24 |
| Finished | Sep 18 04:56:28 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521046140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.1521046140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.4105981199 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 4074671354 ps |
| CPU time | 11.92 seconds |
| Started | Sep 18 04:56:22 PM UTC 24 |
| Finished | Sep 18 04:56:35 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105981199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.4105981199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.1814223657 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 155711783 ps |
| CPU time | 4.12 seconds |
| Started | Sep 18 04:56:22 PM UTC 24 |
| Finished | Sep 18 04:56:27 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814223657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.1814223657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.4102297052 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 2491069784 ps |
| CPU time | 17.51 seconds |
| Started | Sep 18 04:56:22 PM UTC 24 |
| Finished | Sep 18 04:56:41 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102297052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.4102297052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.3350954429 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 279721985 ps |
| CPU time | 3.87 seconds |
| Started | Sep 18 04:56:22 PM UTC 24 |
| Finished | Sep 18 04:56:27 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350954429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.3350954429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.138930679 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 310436127 ps |
| CPU time | 9.77 seconds |
| Started | Sep 18 04:56:22 PM UTC 24 |
| Finished | Sep 18 04:56:33 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138930679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.138930679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.751545914 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 128068729 ps |
| CPU time | 5.07 seconds |
| Started | Sep 18 04:56:25 PM UTC 24 |
| Finished | Sep 18 04:56:31 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751545914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.751545914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.1041191952 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 91546930 ps |
| CPU time | 4.73 seconds |
| Started | Sep 18 04:56:25 PM UTC 24 |
| Finished | Sep 18 04:56:31 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041191952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.1041191952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.3527903346 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 785036573 ps |
| CPU time | 11.96 seconds |
| Started | Sep 18 04:56:25 PM UTC 24 |
| Finished | Sep 18 04:56:38 PM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527903346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.3527903346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.468968817 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 556411466 ps |
| CPU time | 4.32 seconds |
| Started | Sep 18 04:56:25 PM UTC 24 |
| Finished | Sep 18 04:56:30 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468968817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.468968817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.678867457 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 397744835 ps |
| CPU time | 4.05 seconds |
| Started | Sep 18 04:56:25 PM UTC 24 |
| Finished | Sep 18 04:56:30 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678867457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.678867457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.1629315460 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 170226380 ps |
| CPU time | 6.91 seconds |
| Started | Sep 18 04:56:25 PM UTC 24 |
| Finished | Sep 18 04:56:33 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629315460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1629315460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.262692759 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 520272995 ps |
| CPU time | 5.56 seconds |
| Started | Sep 18 04:56:25 PM UTC 24 |
| Finished | Sep 18 04:56:32 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262692759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.262692759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.575156713 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 1688231059 ps |
| CPU time | 10.5 seconds |
| Started | Sep 18 04:56:25 PM UTC 24 |
| Finished | Sep 18 04:56:37 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575156713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.575156713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.4292941868 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 621790542 ps |
| CPU time | 7.8 seconds |
| Started | Sep 18 04:56:25 PM UTC 24 |
| Finished | Sep 18 04:56:34 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292941868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.4292941868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.1291227589 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 133429536 ps |
| CPU time | 4.76 seconds |
| Started | Sep 18 04:56:27 PM UTC 24 |
| Finished | Sep 18 04:56:33 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291227589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.1291227589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.3694358531 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 279852272 ps |
| CPU time | 9.27 seconds |
| Started | Sep 18 04:56:27 PM UTC 24 |
| Finished | Sep 18 04:56:37 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694358531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.3694358531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.4103888994 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 156036123 ps |
| CPU time | 2.84 seconds |
| Started | Sep 18 04:48:26 PM UTC 24 |
| Finished | Sep 18 04:48:30 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103888994 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.4103888994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.1386331427 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 115579378 ps |
| CPU time | 5.82 seconds |
| Started | Sep 18 04:48:15 PM UTC 24 |
| Finished | Sep 18 04:48:22 PM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386331427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.1386331427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.777622906 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 343491757 ps |
| CPU time | 13.58 seconds |
| Started | Sep 18 04:48:15 PM UTC 24 |
| Finished | Sep 18 04:48:30 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777622906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.777622906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.3651847211 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1383764561 ps |
| CPU time | 22 seconds |
| Started | Sep 18 04:48:13 PM UTC 24 |
| Finished | Sep 18 04:48:36 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651847211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.3651847211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.820099224 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 121170451 ps |
| CPU time | 4.16 seconds |
| Started | Sep 18 04:48:10 PM UTC 24 |
| Finished | Sep 18 04:48:15 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820099224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.820099224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.1416360082 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 654425275 ps |
| CPU time | 11.8 seconds |
| Started | Sep 18 04:48:16 PM UTC 24 |
| Finished | Sep 18 04:48:29 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416360082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1416360082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.4227291843 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 488935166 ps |
| CPU time | 21.56 seconds |
| Started | Sep 18 04:48:18 PM UTC 24 |
| Finished | Sep 18 04:48:41 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227291843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.4227291843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.2128880761 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 396783767 ps |
| CPU time | 15.41 seconds |
| Started | Sep 18 04:48:11 PM UTC 24 |
| Finished | Sep 18 04:48:27 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128880761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.2128880761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.563777436 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 575760784 ps |
| CPU time | 6.41 seconds |
| Started | Sep 18 04:48:21 PM UTC 24 |
| Finished | Sep 18 04:48:28 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563777436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.563777436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.1668746760 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1632020995 ps |
| CPU time | 9.87 seconds |
| Started | Sep 18 04:48:09 PM UTC 24 |
| Finished | Sep 18 04:48:20 PM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668746760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1668746760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.3466234154 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 32979905744 ps |
| CPU time | 115.25 seconds |
| Started | Sep 18 04:48:23 PM UTC 24 |
| Finished | Sep 18 04:50:21 PM UTC 24 |
| Peak memory | 268528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3466234154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.otp_ctrl_stress_all_with_rand_reset.3466234154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.331446714 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 957344860 ps |
| CPU time | 32.27 seconds |
| Started | Sep 18 04:48:22 PM UTC 24 |
| Finished | Sep 18 04:48:55 PM UTC 24 |
| Peak memory | 252072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331446714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.331446714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.2256450575 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 1948676411 ps |
| CPU time | 6.19 seconds |
| Started | Sep 18 04:56:27 PM UTC 24 |
| Finished | Sep 18 04:56:34 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256450575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2256450575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.3789463975 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 190213965 ps |
| CPU time | 11.18 seconds |
| Started | Sep 18 04:56:27 PM UTC 24 |
| Finished | Sep 18 04:56:39 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789463975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.3789463975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.1263810886 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 171433700 ps |
| CPU time | 5.29 seconds |
| Started | Sep 18 04:56:27 PM UTC 24 |
| Finished | Sep 18 04:56:33 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263810886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.1263810886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.3934317886 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 6319795669 ps |
| CPU time | 15.93 seconds |
| Started | Sep 18 04:56:29 PM UTC 24 |
| Finished | Sep 18 04:56:46 PM UTC 24 |
| Peak memory | 251556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934317886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.3934317886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.3976831635 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 504526000 ps |
| CPU time | 4.91 seconds |
| Started | Sep 18 04:56:29 PM UTC 24 |
| Finished | Sep 18 04:56:35 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976831635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3976831635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.1961777516 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 351208788 ps |
| CPU time | 5.58 seconds |
| Started | Sep 18 04:56:29 PM UTC 24 |
| Finished | Sep 18 04:56:36 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961777516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.1961777516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.1395952660 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 104209134 ps |
| CPU time | 4.6 seconds |
| Started | Sep 18 04:56:29 PM UTC 24 |
| Finished | Sep 18 04:56:35 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395952660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.1395952660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.1041799456 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 772521865 ps |
| CPU time | 9.87 seconds |
| Started | Sep 18 04:56:29 PM UTC 24 |
| Finished | Sep 18 04:56:40 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041799456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.1041799456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.3028611544 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 120011851 ps |
| CPU time | 4.65 seconds |
| Started | Sep 18 04:56:29 PM UTC 24 |
| Finished | Sep 18 04:56:35 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028611544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.3028611544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.4278006876 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 258281000 ps |
| CPU time | 6.27 seconds |
| Started | Sep 18 04:56:29 PM UTC 24 |
| Finished | Sep 18 04:56:36 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278006876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.4278006876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.3511879610 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 380323408 ps |
| CPU time | 4.33 seconds |
| Started | Sep 18 04:56:31 PM UTC 24 |
| Finished | Sep 18 04:56:36 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511879610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.3511879610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.2934056198 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 437177269 ps |
| CPU time | 4.04 seconds |
| Started | Sep 18 04:56:31 PM UTC 24 |
| Finished | Sep 18 04:56:36 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934056198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.2934056198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.440899702 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 2716063285 ps |
| CPU time | 7.07 seconds |
| Started | Sep 18 04:56:31 PM UTC 24 |
| Finished | Sep 18 04:56:39 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440899702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.440899702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.2392829825 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 3956484388 ps |
| CPU time | 12.11 seconds |
| Started | Sep 18 04:56:31 PM UTC 24 |
| Finished | Sep 18 04:56:44 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392829825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.2392829825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.665562103 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 614983817 ps |
| CPU time | 6.06 seconds |
| Started | Sep 18 04:56:31 PM UTC 24 |
| Finished | Sep 18 04:56:38 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665562103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.665562103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.2645901698 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 3544242900 ps |
| CPU time | 6.73 seconds |
| Started | Sep 18 04:56:31 PM UTC 24 |
| Finished | Sep 18 04:56:39 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645901698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.2645901698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.4033415886 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 258394551 ps |
| CPU time | 3.6 seconds |
| Started | Sep 18 04:56:31 PM UTC 24 |
| Finished | Sep 18 04:56:36 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033415886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.4033415886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.1120104572 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 141067624 ps |
| CPU time | 4.53 seconds |
| Started | Sep 18 04:56:33 PM UTC 24 |
| Finished | Sep 18 04:56:39 PM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120104572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.1120104572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.1770042073 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 503935960 ps |
| CPU time | 4.52 seconds |
| Started | Sep 18 04:56:33 PM UTC 24 |
| Finished | Sep 18 04:56:39 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770042073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.1770042073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.1648077129 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 1212832167 ps |
| CPU time | 8.13 seconds |
| Started | Sep 18 04:56:33 PM UTC 24 |
| Finished | Sep 18 04:56:43 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648077129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1648077129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.3486654459 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 628002148 ps |
| CPU time | 3.57 seconds |
| Started | Sep 18 04:48:38 PM UTC 24 |
| Finished | Sep 18 04:48:43 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486654459 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.3486654459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.242840953 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 377382865 ps |
| CPU time | 11.33 seconds |
| Started | Sep 18 04:48:31 PM UTC 24 |
| Finished | Sep 18 04:48:44 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242840953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.242840953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.3134595648 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 775651131 ps |
| CPU time | 29.03 seconds |
| Started | Sep 18 04:48:31 PM UTC 24 |
| Finished | Sep 18 04:49:02 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134595648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.3134595648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.1693666492 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2047189410 ps |
| CPU time | 8.99 seconds |
| Started | Sep 18 04:48:29 PM UTC 24 |
| Finished | Sep 18 04:48:40 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693666492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.1693666492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.1987794479 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 248078044 ps |
| CPU time | 7.98 seconds |
| Started | Sep 18 04:48:31 PM UTC 24 |
| Finished | Sep 18 04:48:41 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987794479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1987794479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.2130743602 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 896781346 ps |
| CPU time | 22.5 seconds |
| Started | Sep 18 04:48:34 PM UTC 24 |
| Finished | Sep 18 04:48:59 PM UTC 24 |
| Peak memory | 252080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130743602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.2130743602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.741548727 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2311268567 ps |
| CPU time | 4.99 seconds |
| Started | Sep 18 04:48:28 PM UTC 24 |
| Finished | Sep 18 04:48:35 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741548727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.741548727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.2983977530 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 458282592 ps |
| CPU time | 8.07 seconds |
| Started | Sep 18 04:48:28 PM UTC 24 |
| Finished | Sep 18 04:48:38 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983977530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.2983977530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.456873497 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 257968777 ps |
| CPU time | 8.35 seconds |
| Started | Sep 18 04:48:34 PM UTC 24 |
| Finished | Sep 18 04:48:44 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456873497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.456873497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.3376126295 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 403354252 ps |
| CPU time | 7.53 seconds |
| Started | Sep 18 04:48:26 PM UTC 24 |
| Finished | Sep 18 04:48:34 PM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376126295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.3376126295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.823301405 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 31714124428 ps |
| CPU time | 69.53 seconds |
| Started | Sep 18 04:48:37 PM UTC 24 |
| Finished | Sep 18 04:49:48 PM UTC 24 |
| Peak memory | 257976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823301405 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.823301405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.2273468964 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 5593599921 ps |
| CPU time | 15.84 seconds |
| Started | Sep 18 04:48:37 PM UTC 24 |
| Finished | Sep 18 04:48:54 PM UTC 24 |
| Peak memory | 254076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273468964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.2273468964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.1853751096 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 152898140 ps |
| CPU time | 5.53 seconds |
| Started | Sep 18 04:56:33 PM UTC 24 |
| Finished | Sep 18 04:56:40 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853751096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.1853751096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.2872303900 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 57868324 ps |
| CPU time | 2.63 seconds |
| Started | Sep 18 04:56:33 PM UTC 24 |
| Finished | Sep 18 04:56:37 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872303900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.2872303900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.1729610853 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 276103078 ps |
| CPU time | 3.52 seconds |
| Started | Sep 18 04:56:35 PM UTC 24 |
| Finished | Sep 18 04:56:40 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729610853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.1729610853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.282530064 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 15924429952 ps |
| CPU time | 31.8 seconds |
| Started | Sep 18 04:56:35 PM UTC 24 |
| Finished | Sep 18 04:57:09 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282530064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.282530064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.3258588142 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 540500216 ps |
| CPU time | 4.88 seconds |
| Started | Sep 18 04:56:35 PM UTC 24 |
| Finished | Sep 18 04:56:41 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258588142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.3258588142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.2352648447 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 389958168 ps |
| CPU time | 8.91 seconds |
| Started | Sep 18 04:56:35 PM UTC 24 |
| Finished | Sep 18 04:56:45 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352648447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.2352648447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.2900168904 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 614719287 ps |
| CPU time | 8.24 seconds |
| Started | Sep 18 04:56:36 PM UTC 24 |
| Finished | Sep 18 04:56:45 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900168904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.2900168904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.4017800285 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 203648985 ps |
| CPU time | 3.65 seconds |
| Started | Sep 18 04:56:36 PM UTC 24 |
| Finished | Sep 18 04:56:40 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017800285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.4017800285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.2268828904 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 232215348 ps |
| CPU time | 4.64 seconds |
| Started | Sep 18 04:56:36 PM UTC 24 |
| Finished | Sep 18 04:56:41 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268828904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2268828904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.558841869 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 155744697 ps |
| CPU time | 3.52 seconds |
| Started | Sep 18 04:56:39 PM UTC 24 |
| Finished | Sep 18 04:56:43 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558841869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.558841869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.1040488855 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 1402400351 ps |
| CPU time | 11.17 seconds |
| Started | Sep 18 04:56:39 PM UTC 24 |
| Finished | Sep 18 04:56:51 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040488855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.1040488855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.2933388933 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 328533083 ps |
| CPU time | 3.12 seconds |
| Started | Sep 18 04:56:39 PM UTC 24 |
| Finished | Sep 18 04:56:43 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933388933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.2933388933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.4267842492 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 2821447674 ps |
| CPU time | 17.51 seconds |
| Started | Sep 18 04:56:39 PM UTC 24 |
| Finished | Sep 18 04:56:58 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267842492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.4267842492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.3295425503 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 98816962 ps |
| CPU time | 3.65 seconds |
| Started | Sep 18 04:56:39 PM UTC 24 |
| Finished | Sep 18 04:56:44 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295425503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.3295425503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.2370138989 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 3544817769 ps |
| CPU time | 7.11 seconds |
| Started | Sep 18 04:56:39 PM UTC 24 |
| Finished | Sep 18 04:56:47 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370138989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.2370138989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.3980689675 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 477111807 ps |
| CPU time | 3.43 seconds |
| Started | Sep 18 04:56:39 PM UTC 24 |
| Finished | Sep 18 04:56:44 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980689675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.3980689675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.3816347801 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 231568748 ps |
| CPU time | 3.65 seconds |
| Started | Sep 18 04:56:39 PM UTC 24 |
| Finished | Sep 18 04:56:44 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816347801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.3816347801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.1643049728 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 369356780 ps |
| CPU time | 3.43 seconds |
| Started | Sep 18 04:56:39 PM UTC 24 |
| Finished | Sep 18 04:56:44 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643049728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1643049728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.3428472082 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 2953362033 ps |
| CPU time | 8.5 seconds |
| Started | Sep 18 04:56:42 PM UTC 24 |
| Finished | Sep 18 04:56:52 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428472082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.3428472082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.1997127218 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 151149265 ps |
| CPU time | 2.79 seconds |
| Started | Sep 18 04:48:46 PM UTC 24 |
| Finished | Sep 18 04:48:50 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997127218 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.1997127218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.4066029618 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 726954054 ps |
| CPU time | 14.79 seconds |
| Started | Sep 18 04:48:43 PM UTC 24 |
| Finished | Sep 18 04:48:59 PM UTC 24 |
| Peak memory | 253948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066029618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.4066029618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.1921154605 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 2959693256 ps |
| CPU time | 19.99 seconds |
| Started | Sep 18 04:48:43 PM UTC 24 |
| Finished | Sep 18 04:49:04 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921154605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1921154605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.1710704004 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1691335843 ps |
| CPU time | 8.41 seconds |
| Started | Sep 18 04:48:41 PM UTC 24 |
| Finished | Sep 18 04:48:50 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710704004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.1710704004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.2610659756 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 243052344 ps |
| CPU time | 4.97 seconds |
| Started | Sep 18 04:48:38 PM UTC 24 |
| Finished | Sep 18 04:48:45 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610659756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2610659756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.2497407037 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 272763939 ps |
| CPU time | 7.14 seconds |
| Started | Sep 18 04:48:43 PM UTC 24 |
| Finished | Sep 18 04:48:51 PM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497407037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.2497407037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.3345203681 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1474949850 ps |
| CPU time | 48.4 seconds |
| Started | Sep 18 04:48:43 PM UTC 24 |
| Finished | Sep 18 04:49:33 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345203681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.3345203681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.547291771 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1426239428 ps |
| CPU time | 18.84 seconds |
| Started | Sep 18 04:48:40 PM UTC 24 |
| Finished | Sep 18 04:49:00 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547291771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.547291771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.1745534730 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 804476034 ps |
| CPU time | 21.22 seconds |
| Started | Sep 18 04:48:39 PM UTC 24 |
| Finished | Sep 18 04:49:01 PM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745534730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.1745534730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.4203770764 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 284361764 ps |
| CPU time | 8.42 seconds |
| Started | Sep 18 04:48:44 PM UTC 24 |
| Finished | Sep 18 04:48:54 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203770764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.4203770764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.3064281643 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 315095537 ps |
| CPU time | 7.32 seconds |
| Started | Sep 18 04:48:38 PM UTC 24 |
| Finished | Sep 18 04:48:47 PM UTC 24 |
| Peak memory | 252072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064281643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.3064281643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.181858971 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 22902891188 ps |
| CPU time | 104.23 seconds |
| Started | Sep 18 04:48:46 PM UTC 24 |
| Finished | Sep 18 04:50:33 PM UTC 24 |
| Peak memory | 270344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181858971 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.181858971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.1858470295 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2524478369 ps |
| CPU time | 90.58 seconds |
| Started | Sep 18 04:48:46 PM UTC 24 |
| Finished | Sep 18 04:50:19 PM UTC 24 |
| Peak memory | 258156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1858470295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.otp_ctrl_stress_all_with_rand_reset.1858470295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.2847723868 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 927639215 ps |
| CPU time | 21.06 seconds |
| Started | Sep 18 04:48:46 PM UTC 24 |
| Finished | Sep 18 04:49:09 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847723868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.2847723868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.2461437394 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1811316515 ps |
| CPU time | 4.83 seconds |
| Started | Sep 18 04:56:42 PM UTC 24 |
| Finished | Sep 18 04:56:48 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461437394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.2461437394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.1227926137 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 139597431 ps |
| CPU time | 3.69 seconds |
| Started | Sep 18 04:56:42 PM UTC 24 |
| Finished | Sep 18 04:56:47 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227926137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.1227926137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.3969227465 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 1539833446 ps |
| CPU time | 4.67 seconds |
| Started | Sep 18 04:56:42 PM UTC 24 |
| Finished | Sep 18 04:56:48 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969227465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3969227465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.414275927 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 2734820107 ps |
| CPU time | 21.55 seconds |
| Started | Sep 18 04:56:42 PM UTC 24 |
| Finished | Sep 18 04:57:05 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414275927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.414275927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.4199059108 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 3090226525 ps |
| CPU time | 5.41 seconds |
| Started | Sep 18 04:56:42 PM UTC 24 |
| Finished | Sep 18 04:56:49 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199059108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.4199059108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.4276612538 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 394640953 ps |
| CPU time | 4.26 seconds |
| Started | Sep 18 04:56:42 PM UTC 24 |
| Finished | Sep 18 04:56:48 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276612538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.4276612538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.1700938934 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 127391733 ps |
| CPU time | 3.43 seconds |
| Started | Sep 18 04:56:42 PM UTC 24 |
| Finished | Sep 18 04:56:47 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700938934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.1700938934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.4041729995 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 499996242 ps |
| CPU time | 12.55 seconds |
| Started | Sep 18 04:56:42 PM UTC 24 |
| Finished | Sep 18 04:56:56 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041729995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.4041729995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.4290882569 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 102575990 ps |
| CPU time | 4.33 seconds |
| Started | Sep 18 04:56:42 PM UTC 24 |
| Finished | Sep 18 04:56:48 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290882569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.4290882569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.1903561586 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 378670100 ps |
| CPU time | 10.47 seconds |
| Started | Sep 18 04:56:42 PM UTC 24 |
| Finished | Sep 18 04:56:54 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903561586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.1903561586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.2836109627 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 191530056 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 04:56:42 PM UTC 24 |
| Finished | Sep 18 04:56:47 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836109627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2836109627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.4068878566 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 377933606 ps |
| CPU time | 4.56 seconds |
| Started | Sep 18 04:56:42 PM UTC 24 |
| Finished | Sep 18 04:56:48 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068878566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.4068878566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.1236154311 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 162401442 ps |
| CPU time | 4.17 seconds |
| Started | Sep 18 04:56:43 PM UTC 24 |
| Finished | Sep 18 04:56:48 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236154311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.1236154311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.3141207593 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 173090890 ps |
| CPU time | 4.88 seconds |
| Started | Sep 18 04:56:43 PM UTC 24 |
| Finished | Sep 18 04:56:49 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141207593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.3141207593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.1861202280 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 379385627 ps |
| CPU time | 4.66 seconds |
| Started | Sep 18 04:56:43 PM UTC 24 |
| Finished | Sep 18 04:56:48 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861202280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.1861202280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.2199007115 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 495258211 ps |
| CPU time | 5.59 seconds |
| Started | Sep 18 04:56:43 PM UTC 24 |
| Finished | Sep 18 04:56:49 PM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199007115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.2199007115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.4060693328 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 1608825694 ps |
| CPU time | 5.36 seconds |
| Started | Sep 18 04:56:43 PM UTC 24 |
| Finished | Sep 18 04:56:49 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060693328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.4060693328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.3767919550 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 568683019 ps |
| CPU time | 13.46 seconds |
| Started | Sep 18 04:56:43 PM UTC 24 |
| Finished | Sep 18 04:56:57 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767919550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.3767919550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.1338009777 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 1942288706 ps |
| CPU time | 5.87 seconds |
| Started | Sep 18 04:56:43 PM UTC 24 |
| Finished | Sep 18 04:56:50 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338009777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.1338009777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.2628294825 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 367038503 ps |
| CPU time | 14.9 seconds |
| Started | Sep 18 04:56:43 PM UTC 24 |
| Finished | Sep 18 04:56:59 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628294825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.2628294825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.409376120 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 166262816 ps |
| CPU time | 2.11 seconds |
| Started | Sep 18 04:49:02 PM UTC 24 |
| Finished | Sep 18 04:49:05 PM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409376120 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.409376120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.1308689385 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 16336749606 ps |
| CPU time | 35.28 seconds |
| Started | Sep 18 04:48:53 PM UTC 24 |
| Finished | Sep 18 04:49:30 PM UTC 24 |
| Peak memory | 256108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308689385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1308689385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.796266774 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1460159776 ps |
| CPU time | 41.09 seconds |
| Started | Sep 18 04:48:53 PM UTC 24 |
| Finished | Sep 18 04:49:36 PM UTC 24 |
| Peak memory | 258240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796266774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.796266774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.1107884403 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1312127395 ps |
| CPU time | 27.78 seconds |
| Started | Sep 18 04:48:53 PM UTC 24 |
| Finished | Sep 18 04:49:22 PM UTC 24 |
| Peak memory | 252084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107884403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.1107884403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.3178990238 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 480721232 ps |
| CPU time | 4.51 seconds |
| Started | Sep 18 04:48:47 PM UTC 24 |
| Finished | Sep 18 04:48:53 PM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178990238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.3178990238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.2754453548 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 678380333 ps |
| CPU time | 6.56 seconds |
| Started | Sep 18 04:48:55 PM UTC 24 |
| Finished | Sep 18 04:49:02 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754453548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.2754453548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.3898866915 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1100368272 ps |
| CPU time | 28.56 seconds |
| Started | Sep 18 04:48:55 PM UTC 24 |
| Finished | Sep 18 04:49:25 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898866915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.3898866915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.991305789 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 94478048 ps |
| CPU time | 5.22 seconds |
| Started | Sep 18 04:48:53 PM UTC 24 |
| Finished | Sep 18 04:49:00 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991305789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.991305789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.3202431885 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 895556107 ps |
| CPU time | 14.93 seconds |
| Started | Sep 18 04:48:51 PM UTC 24 |
| Finished | Sep 18 04:49:07 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202431885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.3202431885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.2013057056 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 615179150 ps |
| CPU time | 6.6 seconds |
| Started | Sep 18 04:48:55 PM UTC 24 |
| Finished | Sep 18 04:49:03 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013057056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.2013057056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.2396248489 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 6802691288 ps |
| CPU time | 21.72 seconds |
| Started | Sep 18 04:48:46 PM UTC 24 |
| Finished | Sep 18 04:49:09 PM UTC 24 |
| Peak memory | 252004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396248489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.2396248489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.1846144845 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 17530003712 ps |
| CPU time | 161.24 seconds |
| Started | Sep 18 04:48:57 PM UTC 24 |
| Finished | Sep 18 04:51:41 PM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846144845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.1846144845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.2232028107 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 1794996429 ps |
| CPU time | 3.56 seconds |
| Started | Sep 18 04:56:45 PM UTC 24 |
| Finished | Sep 18 04:56:50 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232028107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.2232028107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.2541214568 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 228197835 ps |
| CPU time | 8.43 seconds |
| Started | Sep 18 04:56:45 PM UTC 24 |
| Finished | Sep 18 04:56:55 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541214568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.2541214568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.3183396277 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 138926612 ps |
| CPU time | 3.94 seconds |
| Started | Sep 18 04:56:45 PM UTC 24 |
| Finished | Sep 18 04:56:50 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183396277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.3183396277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.3105792862 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 240324900 ps |
| CPU time | 4.95 seconds |
| Started | Sep 18 04:56:45 PM UTC 24 |
| Finished | Sep 18 04:56:51 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105792862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.3105792862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.1814678466 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 181044027 ps |
| CPU time | 4.43 seconds |
| Started | Sep 18 04:56:45 PM UTC 24 |
| Finished | Sep 18 04:56:51 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814678466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1814678466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.4250511334 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 300581840 ps |
| CPU time | 4.35 seconds |
| Started | Sep 18 04:56:46 PM UTC 24 |
| Finished | Sep 18 04:56:51 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250511334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.4250511334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.2552631821 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 523832854 ps |
| CPU time | 3.62 seconds |
| Started | Sep 18 04:56:46 PM UTC 24 |
| Finished | Sep 18 04:56:50 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552631821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.2552631821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.752409654 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 5296544324 ps |
| CPU time | 23.67 seconds |
| Started | Sep 18 04:56:46 PM UTC 24 |
| Finished | Sep 18 04:57:11 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752409654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.752409654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.2209376812 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 209732741 ps |
| CPU time | 3.47 seconds |
| Started | Sep 18 04:56:46 PM UTC 24 |
| Finished | Sep 18 04:56:50 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209376812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.2209376812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.1477469600 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 5267468942 ps |
| CPU time | 10.45 seconds |
| Started | Sep 18 04:56:46 PM UTC 24 |
| Finished | Sep 18 04:56:57 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477469600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.1477469600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.122080966 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 113113502 ps |
| CPU time | 4.74 seconds |
| Started | Sep 18 04:56:50 PM UTC 24 |
| Finished | Sep 18 04:56:56 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122080966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.122080966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.316915029 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 513622076 ps |
| CPU time | 7.53 seconds |
| Started | Sep 18 04:56:50 PM UTC 24 |
| Finished | Sep 18 04:56:59 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316915029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.316915029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.2417435919 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 251092163 ps |
| CPU time | 4.18 seconds |
| Started | Sep 18 04:56:50 PM UTC 24 |
| Finished | Sep 18 04:56:56 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417435919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.2417435919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.1398307120 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 187897686 ps |
| CPU time | 7.92 seconds |
| Started | Sep 18 04:56:50 PM UTC 24 |
| Finished | Sep 18 04:57:00 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398307120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.1398307120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.885109433 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 3816782317 ps |
| CPU time | 26.5 seconds |
| Started | Sep 18 04:56:50 PM UTC 24 |
| Finished | Sep 18 04:57:18 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885109433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.885109433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.2010015329 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 122475618 ps |
| CPU time | 4.98 seconds |
| Started | Sep 18 04:56:50 PM UTC 24 |
| Finished | Sep 18 04:56:57 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010015329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.2010015329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.3223479011 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 852593476 ps |
| CPU time | 9.33 seconds |
| Started | Sep 18 04:56:50 PM UTC 24 |
| Finished | Sep 18 04:57:01 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223479011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.3223479011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.2429102618 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 226506105 ps |
| CPU time | 4.21 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:56:56 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429102618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.2429102618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.4040636231 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 809548758 ps |
| CPU time | 6.48 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:56:58 PM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040636231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.4040636231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.783578704 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 102697250 ps |
| CPU time | 2.84 seconds |
| Started | Sep 18 04:49:08 PM UTC 24 |
| Finished | Sep 18 04:49:12 PM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783578704 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.783578704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.1881744928 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11643304570 ps |
| CPU time | 21.95 seconds |
| Started | Sep 18 04:49:04 PM UTC 24 |
| Finished | Sep 18 04:49:27 PM UTC 24 |
| Peak memory | 254256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881744928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1881744928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.2289034348 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 18270166267 ps |
| CPU time | 36.09 seconds |
| Started | Sep 18 04:49:04 PM UTC 24 |
| Finished | Sep 18 04:49:41 PM UTC 24 |
| Peak memory | 258272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289034348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.2289034348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.1483742603 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1282066737 ps |
| CPU time | 19.05 seconds |
| Started | Sep 18 04:49:04 PM UTC 24 |
| Finished | Sep 18 04:49:24 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483742603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.1483742603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.1836322534 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 164093304 ps |
| CPU time | 3.56 seconds |
| Started | Sep 18 04:49:02 PM UTC 24 |
| Finished | Sep 18 04:49:07 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836322534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.1836322534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.2069285560 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 4292676603 ps |
| CPU time | 19.55 seconds |
| Started | Sep 18 04:49:04 PM UTC 24 |
| Finished | Sep 18 04:49:25 PM UTC 24 |
| Peak memory | 252244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069285560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.2069285560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.3813966568 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1561867697 ps |
| CPU time | 36.57 seconds |
| Started | Sep 18 04:49:06 PM UTC 24 |
| Finished | Sep 18 04:49:44 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813966568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.3813966568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.1156700643 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1181695029 ps |
| CPU time | 3.62 seconds |
| Started | Sep 18 04:49:04 PM UTC 24 |
| Finished | Sep 18 04:49:09 PM UTC 24 |
| Peak memory | 251668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156700643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.1156700643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.1399803285 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2099583683 ps |
| CPU time | 21.35 seconds |
| Started | Sep 18 04:49:02 PM UTC 24 |
| Finished | Sep 18 04:49:25 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399803285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.1399803285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.3093530186 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 181477035 ps |
| CPU time | 6.24 seconds |
| Started | Sep 18 04:49:07 PM UTC 24 |
| Finished | Sep 18 04:49:14 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093530186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.3093530186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.1729184794 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 318604764 ps |
| CPU time | 8.88 seconds |
| Started | Sep 18 04:49:02 PM UTC 24 |
| Finished | Sep 18 04:49:12 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729184794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.1729184794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.1582710528 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 6718000587 ps |
| CPU time | 41.51 seconds |
| Started | Sep 18 04:49:07 PM UTC 24 |
| Finished | Sep 18 04:49:50 PM UTC 24 |
| Peak memory | 253964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582710528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.1582710528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.3321262078 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 383527561 ps |
| CPU time | 3.92 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:56:56 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321262078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3321262078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.729644107 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 749998222 ps |
| CPU time | 9.57 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:57:02 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729644107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.729644107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.1351727979 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 283989577 ps |
| CPU time | 4.42 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:56:56 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351727979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.1351727979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.3601676460 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 1800731595 ps |
| CPU time | 6.76 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:56:59 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601676460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.3601676460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.3453389079 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 415022368 ps |
| CPU time | 4.98 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:56:57 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453389079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.3453389079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.1725633365 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 231698936 ps |
| CPU time | 5.42 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:56:58 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725633365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.1725633365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.2866021273 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 233269657 ps |
| CPU time | 3.96 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:56:56 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866021273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2866021273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.3298290714 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 429324519 ps |
| CPU time | 12.16 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:57:05 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298290714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.3298290714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.906300200 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 404295420 ps |
| CPU time | 5.72 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:56:58 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906300200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.906300200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.3697015002 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 155536666 ps |
| CPU time | 5.32 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:56:58 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697015002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.3697015002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.1754547933 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 270795264 ps |
| CPU time | 3.76 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:56:56 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754547933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1754547933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.2650915972 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 1852892711 ps |
| CPU time | 5.19 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:56:58 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650915972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.2650915972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.2401344713 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 143618416 ps |
| CPU time | 4.15 seconds |
| Started | Sep 18 04:56:51 PM UTC 24 |
| Finished | Sep 18 04:56:57 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401344713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.2401344713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.557040771 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 586368641 ps |
| CPU time | 9.09 seconds |
| Started | Sep 18 04:56:53 PM UTC 24 |
| Finished | Sep 18 04:57:03 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557040771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.557040771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.3461004412 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 1560872200 ps |
| CPU time | 4.81 seconds |
| Started | Sep 18 04:56:53 PM UTC 24 |
| Finished | Sep 18 04:56:58 PM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461004412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.3461004412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.1176980373 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 144372209 ps |
| CPU time | 5.29 seconds |
| Started | Sep 18 04:56:53 PM UTC 24 |
| Finished | Sep 18 04:56:59 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176980373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.1176980373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.174620712 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 322746738 ps |
| CPU time | 4.93 seconds |
| Started | Sep 18 04:56:53 PM UTC 24 |
| Finished | Sep 18 04:56:59 PM UTC 24 |
| Peak memory | 251736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174620712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.174620712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.1392700689 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 5976451320 ps |
| CPU time | 12.12 seconds |
| Started | Sep 18 04:56:53 PM UTC 24 |
| Finished | Sep 18 04:57:06 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392700689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.1392700689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.3982706683 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 122365669 ps |
| CPU time | 5.31 seconds |
| Started | Sep 18 04:56:53 PM UTC 24 |
| Finished | Sep 18 04:56:59 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982706683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.3982706683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.284141363 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 64526068 ps |
| CPU time | 2.46 seconds |
| Started | Sep 18 04:49:24 PM UTC 24 |
| Finished | Sep 18 04:49:28 PM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284141363 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.284141363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.3551239988 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5757221949 ps |
| CPU time | 14.48 seconds |
| Started | Sep 18 04:49:16 PM UTC 24 |
| Finished | Sep 18 04:49:31 PM UTC 24 |
| Peak memory | 252056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551239988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.3551239988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.3146893434 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 223302187 ps |
| CPU time | 14.7 seconds |
| Started | Sep 18 04:49:16 PM UTC 24 |
| Finished | Sep 18 04:49:31 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146893434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.3146893434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.1747153489 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 628708412 ps |
| CPU time | 10.92 seconds |
| Started | Sep 18 04:49:15 PM UTC 24 |
| Finished | Sep 18 04:49:27 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747153489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.1747153489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.3589459541 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 376564935 ps |
| CPU time | 5.29 seconds |
| Started | Sep 18 04:49:10 PM UTC 24 |
| Finished | Sep 18 04:49:16 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589459541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.3589459541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.1843763853 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 13666428441 ps |
| CPU time | 32.6 seconds |
| Started | Sep 18 04:49:17 PM UTC 24 |
| Finished | Sep 18 04:49:51 PM UTC 24 |
| Peak memory | 258192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843763853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.1843763853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.3603301975 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 10130335593 ps |
| CPU time | 49.04 seconds |
| Started | Sep 18 04:49:17 PM UTC 24 |
| Finished | Sep 18 04:50:08 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603301975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.3603301975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.3358579105 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 293390996 ps |
| CPU time | 8.06 seconds |
| Started | Sep 18 04:49:13 PM UTC 24 |
| Finished | Sep 18 04:49:22 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358579105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.3358579105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.3758162561 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 462133969 ps |
| CPU time | 15.96 seconds |
| Started | Sep 18 04:49:13 PM UTC 24 |
| Finished | Sep 18 04:49:30 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758162561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.3758162561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.811979389 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 252491705 ps |
| CPU time | 6.48 seconds |
| Started | Sep 18 04:49:19 PM UTC 24 |
| Finished | Sep 18 04:49:27 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811979389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.811979389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.3444615070 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 604460035 ps |
| CPU time | 7.8 seconds |
| Started | Sep 18 04:49:10 PM UTC 24 |
| Finished | Sep 18 04:49:18 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444615070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.3444615070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.2157020591 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 37951890173 ps |
| CPU time | 276.76 seconds |
| Started | Sep 18 04:49:24 PM UTC 24 |
| Finished | Sep 18 04:54:05 PM UTC 24 |
| Peak memory | 274516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157020591 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.2157020591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.2304827352 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 302838993 ps |
| CPU time | 8.56 seconds |
| Started | Sep 18 04:49:22 PM UTC 24 |
| Finished | Sep 18 04:49:32 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304827352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.2304827352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.390462813 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 274356648 ps |
| CPU time | 4.97 seconds |
| Started | Sep 18 04:56:53 PM UTC 24 |
| Finished | Sep 18 04:56:59 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390462813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.390462813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.944706699 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 305389347 ps |
| CPU time | 10.64 seconds |
| Started | Sep 18 04:56:55 PM UTC 24 |
| Finished | Sep 18 04:57:07 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944706699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.944706699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.3016575235 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 242954736 ps |
| CPU time | 3.18 seconds |
| Started | Sep 18 04:56:55 PM UTC 24 |
| Finished | Sep 18 04:56:59 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016575235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.3016575235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.2445786902 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 310803773 ps |
| CPU time | 3.54 seconds |
| Started | Sep 18 04:56:56 PM UTC 24 |
| Finished | Sep 18 04:57:01 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445786902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2445786902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.3203677074 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 166936824 ps |
| CPU time | 3.66 seconds |
| Started | Sep 18 04:56:56 PM UTC 24 |
| Finished | Sep 18 04:57:01 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203677074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.3203677074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.1475961332 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 7504844604 ps |
| CPU time | 21.1 seconds |
| Started | Sep 18 04:56:56 PM UTC 24 |
| Finished | Sep 18 04:57:19 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475961332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.1475961332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.349267584 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 314947041 ps |
| CPU time | 4.27 seconds |
| Started | Sep 18 04:56:57 PM UTC 24 |
| Finished | Sep 18 04:57:02 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349267584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.349267584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.3222508912 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 171764849 ps |
| CPU time | 3.34 seconds |
| Started | Sep 18 04:56:58 PM UTC 24 |
| Finished | Sep 18 04:57:03 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222508912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.3222508912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.2554396324 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 171451631 ps |
| CPU time | 3.46 seconds |
| Started | Sep 18 04:56:59 PM UTC 24 |
| Finished | Sep 18 04:57:03 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554396324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.2554396324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.3648223638 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 183139289 ps |
| CPU time | 4.54 seconds |
| Started | Sep 18 04:56:59 PM UTC 24 |
| Finished | Sep 18 04:57:04 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648223638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.3648223638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.4065636283 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 248676972 ps |
| CPU time | 4.21 seconds |
| Started | Sep 18 04:56:59 PM UTC 24 |
| Finished | Sep 18 04:57:04 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065636283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.4065636283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.636752777 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 108366192 ps |
| CPU time | 3.5 seconds |
| Started | Sep 18 04:56:59 PM UTC 24 |
| Finished | Sep 18 04:57:03 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636752777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.636752777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.1289416040 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 678192012 ps |
| CPU time | 8.04 seconds |
| Started | Sep 18 04:56:59 PM UTC 24 |
| Finished | Sep 18 04:57:08 PM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289416040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.1289416040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.47312938 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 458490577 ps |
| CPU time | 3.86 seconds |
| Started | Sep 18 04:56:59 PM UTC 24 |
| Finished | Sep 18 04:57:04 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47312938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.47312938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.4235019589 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 167718737 ps |
| CPU time | 3.31 seconds |
| Started | Sep 18 04:56:59 PM UTC 24 |
| Finished | Sep 18 04:57:03 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235019589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.4235019589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.3735789811 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 1949841792 ps |
| CPU time | 4.02 seconds |
| Started | Sep 18 04:56:59 PM UTC 24 |
| Finished | Sep 18 04:57:04 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735789811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.3735789811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.4202019188 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 154876199 ps |
| CPU time | 2.69 seconds |
| Started | Sep 18 04:56:59 PM UTC 24 |
| Finished | Sep 18 04:57:03 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202019188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.4202019188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.3280146685 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 198007003 ps |
| CPU time | 3.73 seconds |
| Started | Sep 18 04:56:59 PM UTC 24 |
| Finished | Sep 18 04:57:04 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280146685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.3280146685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.534931670 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 273154281 ps |
| CPU time | 3.2 seconds |
| Started | Sep 18 04:56:59 PM UTC 24 |
| Finished | Sep 18 04:57:03 PM UTC 24 |
| Peak memory | 252044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534931670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.534931670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.1132027807 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 325301901 ps |
| CPU time | 3.6 seconds |
| Started | Sep 18 04:44:10 PM UTC 24 |
| Finished | Sep 18 04:44:15 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132027807 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.1132027807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.3539451757 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4279201306 ps |
| CPU time | 37.7 seconds |
| Started | Sep 18 04:43:53 PM UTC 24 |
| Finished | Sep 18 04:44:32 PM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539451757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.3539451757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.3304150699 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1412123805 ps |
| CPU time | 15.31 seconds |
| Started | Sep 18 04:43:51 PM UTC 24 |
| Finished | Sep 18 04:44:08 PM UTC 24 |
| Peak memory | 252056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304150699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.3304150699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.54087275 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 910256238 ps |
| CPU time | 14 seconds |
| Started | Sep 18 04:43:57 PM UTC 24 |
| Finished | Sep 18 04:44:13 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54087275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.54087275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.2048701539 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 180569080 ps |
| CPU time | 6.89 seconds |
| Started | Sep 18 04:44:00 PM UTC 24 |
| Finished | Sep 18 04:44:08 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048701539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2048701539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.4089335808 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 245257904 ps |
| CPU time | 6.02 seconds |
| Started | Sep 18 04:43:50 PM UTC 24 |
| Finished | Sep 18 04:43:57 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089335808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.4089335808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.982340033 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1395130351 ps |
| CPU time | 18.33 seconds |
| Started | Sep 18 04:43:48 PM UTC 24 |
| Finished | Sep 18 04:44:08 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982340033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.982340033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.357999119 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1755657898 ps |
| CPU time | 6.12 seconds |
| Started | Sep 18 04:44:01 PM UTC 24 |
| Finished | Sep 18 04:44:09 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357999119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.357999119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.75969490 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9940577571 ps |
| CPU time | 199.48 seconds |
| Started | Sep 18 04:44:10 PM UTC 24 |
| Finished | Sep 18 04:47:33 PM UTC 24 |
| Peak memory | 288360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75969490 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.75969490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.2941012314 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 521795385 ps |
| CPU time | 9.07 seconds |
| Started | Sep 18 04:43:42 PM UTC 24 |
| Finished | Sep 18 04:43:52 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941012314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.2941012314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.2924059909 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2289871404 ps |
| CPU time | 70.98 seconds |
| Started | Sep 18 04:44:09 PM UTC 24 |
| Finished | Sep 18 04:45:22 PM UTC 24 |
| Peak memory | 258324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2924059909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.otp_ctrl_stress_all_with_rand_reset.2924059909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.3322646388 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 861820487 ps |
| CPU time | 13.26 seconds |
| Started | Sep 18 04:44:07 PM UTC 24 |
| Finished | Sep 18 04:44:22 PM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322646388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.3322646388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.1785530831 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 110401556 ps |
| CPU time | 2.99 seconds |
| Started | Sep 18 04:49:34 PM UTC 24 |
| Finished | Sep 18 04:49:38 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785530831 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.1785530831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.442374796 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 11382508972 ps |
| CPU time | 18.61 seconds |
| Started | Sep 18 04:49:29 PM UTC 24 |
| Finished | Sep 18 04:49:49 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442374796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.442374796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.4217378939 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 635328853 ps |
| CPU time | 14.63 seconds |
| Started | Sep 18 04:49:29 PM UTC 24 |
| Finished | Sep 18 04:49:45 PM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217378939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.4217378939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.1119719668 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 3793329786 ps |
| CPU time | 31.67 seconds |
| Started | Sep 18 04:49:29 PM UTC 24 |
| Finished | Sep 18 04:50:02 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119719668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.1119719668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.3616667823 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1901699197 ps |
| CPU time | 6.21 seconds |
| Started | Sep 18 04:49:27 PM UTC 24 |
| Finished | Sep 18 04:49:34 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616667823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.3616667823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.3025956470 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2487547260 ps |
| CPU time | 24.12 seconds |
| Started | Sep 18 04:49:29 PM UTC 24 |
| Finished | Sep 18 04:49:54 PM UTC 24 |
| Peak memory | 256288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025956470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.3025956470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.4264585359 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 627638301 ps |
| CPU time | 7.21 seconds |
| Started | Sep 18 04:49:30 PM UTC 24 |
| Finished | Sep 18 04:49:39 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264585359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.4264585359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.2231863543 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 94218245 ps |
| CPU time | 5.98 seconds |
| Started | Sep 18 04:49:27 PM UTC 24 |
| Finished | Sep 18 04:49:34 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231863543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.2231863543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.3499458437 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1767616758 ps |
| CPU time | 22.47 seconds |
| Started | Sep 18 04:49:27 PM UTC 24 |
| Finished | Sep 18 04:49:51 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499458437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.3499458437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.1700549401 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 960801114 ps |
| CPU time | 9.09 seconds |
| Started | Sep 18 04:49:32 PM UTC 24 |
| Finished | Sep 18 04:49:42 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700549401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.1700549401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.3912421679 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2449744245 ps |
| CPU time | 5.47 seconds |
| Started | Sep 18 04:49:27 PM UTC 24 |
| Finished | Sep 18 04:49:34 PM UTC 24 |
| Peak memory | 252132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912421679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.3912421679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.3037072536 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 23055537355 ps |
| CPU time | 58.12 seconds |
| Started | Sep 18 04:49:34 PM UTC 24 |
| Finished | Sep 18 04:50:34 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037072536 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.3037072536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.3601552007 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2187463294 ps |
| CPU time | 73.27 seconds |
| Started | Sep 18 04:49:34 PM UTC 24 |
| Finished | Sep 18 04:50:49 PM UTC 24 |
| Peak memory | 258192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3601552007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.otp_ctrl_stress_all_with_rand_reset.3601552007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.2807802027 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 3088670076 ps |
| CPU time | 15.85 seconds |
| Started | Sep 18 04:49:32 PM UTC 24 |
| Finished | Sep 18 04:49:49 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807802027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.2807802027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.1572200791 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 121498068 ps |
| CPU time | 3.1 seconds |
| Started | Sep 18 04:56:59 PM UTC 24 |
| Finished | Sep 18 04:57:03 PM UTC 24 |
| Peak memory | 251672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572200791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.1572200791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.4124896583 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 1545887426 ps |
| CPU time | 3.96 seconds |
| Started | Sep 18 04:56:59 PM UTC 24 |
| Finished | Sep 18 04:57:04 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124896583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.4124896583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.2339634604 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 225793116 ps |
| CPU time | 3.63 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:08 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339634604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.2339634604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.651300366 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 433636445 ps |
| CPU time | 3.73 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:08 PM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651300366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.651300366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.3280153462 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 195662469 ps |
| CPU time | 3.33 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:08 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280153462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.3280153462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.3345127646 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 2397171661 ps |
| CPU time | 4.35 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:09 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345127646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.3345127646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.4051701039 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 352586858 ps |
| CPU time | 3.61 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:08 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051701039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.4051701039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.630807734 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 165466246 ps |
| CPU time | 4.27 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:09 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630807734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.630807734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.195772576 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 1638053256 ps |
| CPU time | 4.15 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:09 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195772576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.195772576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.779512076 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 111394887 ps |
| CPU time | 2.74 seconds |
| Started | Sep 18 04:49:51 PM UTC 24 |
| Finished | Sep 18 04:49:55 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779512076 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.779512076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.4139067269 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2981030578 ps |
| CPU time | 29.16 seconds |
| Started | Sep 18 04:49:39 PM UTC 24 |
| Finished | Sep 18 04:50:10 PM UTC 24 |
| Peak memory | 256076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139067269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.4139067269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.4168242219 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 641995242 ps |
| CPU time | 13.55 seconds |
| Started | Sep 18 04:49:39 PM UTC 24 |
| Finished | Sep 18 04:49:54 PM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168242219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.4168242219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.4121941922 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1139217410 ps |
| CPU time | 25.43 seconds |
| Started | Sep 18 04:49:38 PM UTC 24 |
| Finished | Sep 18 04:50:05 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121941922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.4121941922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.137557670 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 142454714 ps |
| CPU time | 3.63 seconds |
| Started | Sep 18 04:49:36 PM UTC 24 |
| Finished | Sep 18 04:49:41 PM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137557670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.137557670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.2190806419 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 497450944 ps |
| CPU time | 19.46 seconds |
| Started | Sep 18 04:49:41 PM UTC 24 |
| Finished | Sep 18 04:50:02 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190806419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.2190806419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.2836433183 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 554047453 ps |
| CPU time | 18.36 seconds |
| Started | Sep 18 04:49:43 PM UTC 24 |
| Finished | Sep 18 04:50:03 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836433183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2836433183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.979850019 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 652838709 ps |
| CPU time | 11.91 seconds |
| Started | Sep 18 04:49:36 PM UTC 24 |
| Finished | Sep 18 04:49:49 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979850019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.979850019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.277460443 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 964080824 ps |
| CPU time | 9.06 seconds |
| Started | Sep 18 04:49:43 PM UTC 24 |
| Finished | Sep 18 04:49:53 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277460443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.277460443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.3369087675 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 6771830102 ps |
| CPU time | 15.34 seconds |
| Started | Sep 18 04:49:36 PM UTC 24 |
| Finished | Sep 18 04:49:53 PM UTC 24 |
| Peak memory | 252004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369087675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.3369087675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.1432024472 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 62623296174 ps |
| CPU time | 226.21 seconds |
| Started | Sep 18 04:49:47 PM UTC 24 |
| Finished | Sep 18 04:53:36 PM UTC 24 |
| Peak memory | 290964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432024472 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.1432024472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.152646944 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 813167011 ps |
| CPU time | 11.68 seconds |
| Started | Sep 18 04:49:47 PM UTC 24 |
| Finished | Sep 18 04:50:00 PM UTC 24 |
| Peak memory | 258136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152646944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.152646944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.1321673924 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 210382856 ps |
| CPU time | 3.82 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:09 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321673924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1321673924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.3247503055 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 218693236 ps |
| CPU time | 3.48 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:08 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247503055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.3247503055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.1075278968 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 1667457202 ps |
| CPU time | 3.68 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:09 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075278968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.1075278968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.376854833 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 102255238 ps |
| CPU time | 2.99 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:08 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376854833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.376854833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.3007567678 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 338731280 ps |
| CPU time | 2.84 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:08 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007567678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.3007567678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.124137144 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 582890674 ps |
| CPU time | 5.17 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:10 PM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124137144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.124137144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.4001426733 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 111092704 ps |
| CPU time | 3.49 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:09 PM UTC 24 |
| Peak memory | 251736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001426733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.4001426733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.787128261 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 423021545 ps |
| CPU time | 3.79 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:09 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787128261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.787128261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.3691641815 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 1667017371 ps |
| CPU time | 4.08 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:09 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691641815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3691641815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.2242202737 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 520130135 ps |
| CPU time | 3.45 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:08 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242202737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2242202737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.2182755452 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 857913236 ps |
| CPU time | 3.81 seconds |
| Started | Sep 18 04:49:59 PM UTC 24 |
| Finished | Sep 18 04:50:04 PM UTC 24 |
| Peak memory | 251648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182755452 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.2182755452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.2403110582 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3890199039 ps |
| CPU time | 30.22 seconds |
| Started | Sep 18 04:49:54 PM UTC 24 |
| Finished | Sep 18 04:50:26 PM UTC 24 |
| Peak memory | 252008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403110582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.2403110582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.1033440139 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 344112696 ps |
| CPU time | 16.48 seconds |
| Started | Sep 18 04:49:54 PM UTC 24 |
| Finished | Sep 18 04:50:12 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033440139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.1033440139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.611304413 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 2484521155 ps |
| CPU time | 25.39 seconds |
| Started | Sep 18 04:49:54 PM UTC 24 |
| Finished | Sep 18 04:50:21 PM UTC 24 |
| Peak memory | 252032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611304413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.611304413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.4172646603 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 464679607 ps |
| CPU time | 7.54 seconds |
| Started | Sep 18 04:49:55 PM UTC 24 |
| Finished | Sep 18 04:50:03 PM UTC 24 |
| Peak memory | 252084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172646603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.4172646603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.1895478522 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 592028100 ps |
| CPU time | 7.78 seconds |
| Started | Sep 18 04:49:55 PM UTC 24 |
| Finished | Sep 18 04:50:04 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895478522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.1895478522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.1482689439 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 104308283 ps |
| CPU time | 5.7 seconds |
| Started | Sep 18 04:49:54 PM UTC 24 |
| Finished | Sep 18 04:50:01 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482689439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.1482689439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.4268390913 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 200534974 ps |
| CPU time | 4 seconds |
| Started | Sep 18 04:49:54 PM UTC 24 |
| Finished | Sep 18 04:49:59 PM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268390913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.4268390913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.4121674699 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1980923303 ps |
| CPU time | 6.02 seconds |
| Started | Sep 18 04:49:56 PM UTC 24 |
| Finished | Sep 18 04:50:04 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121674699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.4121674699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.4036481997 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 244512650 ps |
| CPU time | 4.93 seconds |
| Started | Sep 18 04:49:52 PM UTC 24 |
| Finished | Sep 18 04:49:57 PM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036481997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.4036481997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.2428598028 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 30683832559 ps |
| CPU time | 83.49 seconds |
| Started | Sep 18 04:49:59 PM UTC 24 |
| Finished | Sep 18 04:51:24 PM UTC 24 |
| Peak memory | 258028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428598028 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.2428598028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.878619054 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2200892432 ps |
| CPU time | 19.55 seconds |
| Started | Sep 18 04:49:56 PM UTC 24 |
| Finished | Sep 18 04:50:18 PM UTC 24 |
| Peak memory | 252052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878619054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.878619054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.2636641541 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 160830343 ps |
| CPU time | 2.87 seconds |
| Started | Sep 18 04:57:03 PM UTC 24 |
| Finished | Sep 18 04:57:08 PM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636641541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2636641541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.3765803339 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 240989827 ps |
| CPU time | 3.78 seconds |
| Started | Sep 18 04:57:05 PM UTC 24 |
| Finished | Sep 18 04:57:10 PM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765803339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3765803339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.4206786579 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 114642799 ps |
| CPU time | 3.46 seconds |
| Started | Sep 18 04:57:05 PM UTC 24 |
| Finished | Sep 18 04:57:10 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206786579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.4206786579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.1948323414 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 116554501 ps |
| CPU time | 3.88 seconds |
| Started | Sep 18 04:57:05 PM UTC 24 |
| Finished | Sep 18 04:57:10 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948323414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.1948323414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.3217545989 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 182401381 ps |
| CPU time | 3.85 seconds |
| Started | Sep 18 04:57:05 PM UTC 24 |
| Finished | Sep 18 04:57:10 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217545989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.3217545989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.2638474553 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 2633101721 ps |
| CPU time | 7.38 seconds |
| Started | Sep 18 04:57:05 PM UTC 24 |
| Finished | Sep 18 04:57:14 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638474553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2638474553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.4209286654 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 2510491069 ps |
| CPU time | 5.65 seconds |
| Started | Sep 18 04:57:05 PM UTC 24 |
| Finished | Sep 18 04:57:12 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209286654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.4209286654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.1627887346 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 211541234 ps |
| CPU time | 3.58 seconds |
| Started | Sep 18 04:57:05 PM UTC 24 |
| Finished | Sep 18 04:57:10 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627887346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.1627887346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.2715588311 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 224028895 ps |
| CPU time | 4.95 seconds |
| Started | Sep 18 04:57:05 PM UTC 24 |
| Finished | Sep 18 04:57:11 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715588311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.2715588311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.3404736248 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 364293572 ps |
| CPU time | 4.16 seconds |
| Started | Sep 18 04:57:05 PM UTC 24 |
| Finished | Sep 18 04:57:11 PM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404736248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.3404736248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.690048558 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 65593713 ps |
| CPU time | 2.77 seconds |
| Started | Sep 18 04:50:08 PM UTC 24 |
| Finished | Sep 18 04:50:12 PM UTC 24 |
| Peak memory | 251464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690048558 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.690048558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.4268007947 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 3896607886 ps |
| CPU time | 20.43 seconds |
| Started | Sep 18 04:50:06 PM UTC 24 |
| Finished | Sep 18 04:50:28 PM UTC 24 |
| Peak memory | 252108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268007947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.4268007947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.3274158149 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 4221129076 ps |
| CPU time | 32.21 seconds |
| Started | Sep 18 04:50:06 PM UTC 24 |
| Finished | Sep 18 04:50:39 PM UTC 24 |
| Peak memory | 258108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274158149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3274158149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.3482455255 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 666142987 ps |
| CPU time | 10.15 seconds |
| Started | Sep 18 04:50:06 PM UTC 24 |
| Finished | Sep 18 04:50:17 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482455255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.3482455255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.64676028 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 160558614 ps |
| CPU time | 5.17 seconds |
| Started | Sep 18 04:50:00 PM UTC 24 |
| Finished | Sep 18 04:50:07 PM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64676028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.64676028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.3331894859 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 6818077914 ps |
| CPU time | 71.95 seconds |
| Started | Sep 18 04:50:06 PM UTC 24 |
| Finished | Sep 18 04:51:20 PM UTC 24 |
| Peak memory | 256168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331894859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3331894859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.2985570809 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1240080488 ps |
| CPU time | 11.73 seconds |
| Started | Sep 18 04:50:06 PM UTC 24 |
| Finished | Sep 18 04:50:19 PM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985570809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.2985570809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.979552015 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1567166628 ps |
| CPU time | 15.87 seconds |
| Started | Sep 18 04:50:00 PM UTC 24 |
| Finished | Sep 18 04:50:18 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979552015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.979552015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.1218878380 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2093630398 ps |
| CPU time | 9.32 seconds |
| Started | Sep 18 04:50:06 PM UTC 24 |
| Finished | Sep 18 04:50:17 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218878380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.1218878380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.3473249898 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 484000914 ps |
| CPU time | 6.09 seconds |
| Started | Sep 18 04:49:59 PM UTC 24 |
| Finished | Sep 18 04:50:06 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473249898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.3473249898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.941499028 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 167664127628 ps |
| CPU time | 268.49 seconds |
| Started | Sep 18 04:50:08 PM UTC 24 |
| Finished | Sep 18 04:54:41 PM UTC 24 |
| Peak memory | 274584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941499028 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.941499028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.791384272 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 3112250678 ps |
| CPU time | 51.47 seconds |
| Started | Sep 18 04:50:06 PM UTC 24 |
| Finished | Sep 18 04:51:00 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791384272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.791384272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.618112044 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 333433416 ps |
| CPU time | 3.4 seconds |
| Started | Sep 18 04:57:05 PM UTC 24 |
| Finished | Sep 18 04:57:10 PM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618112044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.618112044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.2449667238 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 206321963 ps |
| CPU time | 3.61 seconds |
| Started | Sep 18 04:57:05 PM UTC 24 |
| Finished | Sep 18 04:57:10 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449667238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.2449667238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.2475405499 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 2408912680 ps |
| CPU time | 4.68 seconds |
| Started | Sep 18 04:57:05 PM UTC 24 |
| Finished | Sep 18 04:57:11 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475405499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.2475405499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.1943379707 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 460361183 ps |
| CPU time | 3.7 seconds |
| Started | Sep 18 04:57:06 PM UTC 24 |
| Finished | Sep 18 04:57:10 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943379707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.1943379707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.2489874584 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 286157499 ps |
| CPU time | 3.98 seconds |
| Started | Sep 18 04:57:06 PM UTC 24 |
| Finished | Sep 18 04:57:11 PM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489874584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.2489874584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.3793881782 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 385559898 ps |
| CPU time | 4.24 seconds |
| Started | Sep 18 04:57:06 PM UTC 24 |
| Finished | Sep 18 04:57:11 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793881782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.3793881782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.4010747698 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 140779172 ps |
| CPU time | 3.68 seconds |
| Started | Sep 18 04:57:06 PM UTC 24 |
| Finished | Sep 18 04:57:10 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010747698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.4010747698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.93923073 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 133828756 ps |
| CPU time | 4.04 seconds |
| Started | Sep 18 04:57:09 PM UTC 24 |
| Finished | Sep 18 04:57:14 PM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93923073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.93923073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1158867064 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 201144052 ps |
| CPU time | 4.04 seconds |
| Started | Sep 18 04:57:09 PM UTC 24 |
| Finished | Sep 18 04:57:14 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158867064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.1158867064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.2300448925 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 664417437 ps |
| CPU time | 4.23 seconds |
| Started | Sep 18 04:57:09 PM UTC 24 |
| Finished | Sep 18 04:57:15 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300448925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.2300448925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.1084807025 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 205526630 ps |
| CPU time | 4.98 seconds |
| Started | Sep 18 04:50:18 PM UTC 24 |
| Finished | Sep 18 04:50:24 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084807025 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.1084807025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.3226186546 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 732815324 ps |
| CPU time | 12.79 seconds |
| Started | Sep 18 04:50:11 PM UTC 24 |
| Finished | Sep 18 04:50:26 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226186546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.3226186546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.639346147 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 24078848099 ps |
| CPU time | 71.53 seconds |
| Started | Sep 18 04:50:10 PM UTC 24 |
| Finished | Sep 18 04:51:23 PM UTC 24 |
| Peak memory | 254004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639346147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.639346147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.4144518634 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 289183631 ps |
| CPU time | 6.27 seconds |
| Started | Sep 18 04:50:08 PM UTC 24 |
| Finished | Sep 18 04:50:15 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144518634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.4144518634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.3720647741 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 1221298437 ps |
| CPU time | 15.05 seconds |
| Started | Sep 18 04:50:14 PM UTC 24 |
| Finished | Sep 18 04:50:31 PM UTC 24 |
| Peak memory | 252076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720647741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.3720647741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.1242897368 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 439057734 ps |
| CPU time | 4.89 seconds |
| Started | Sep 18 04:50:14 PM UTC 24 |
| Finished | Sep 18 04:50:20 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242897368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.1242897368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.1026787072 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 148327530 ps |
| CPU time | 7 seconds |
| Started | Sep 18 04:50:10 PM UTC 24 |
| Finished | Sep 18 04:50:18 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026787072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1026787072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.2989574270 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 164006351 ps |
| CPU time | 8.45 seconds |
| Started | Sep 18 04:50:08 PM UTC 24 |
| Finished | Sep 18 04:50:18 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989574270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.2989574270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.2890450530 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 189337788 ps |
| CPU time | 6.42 seconds |
| Started | Sep 18 04:50:16 PM UTC 24 |
| Finished | Sep 18 04:50:24 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890450530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.2890450530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.1928098478 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 913990599 ps |
| CPU time | 8.16 seconds |
| Started | Sep 18 04:50:08 PM UTC 24 |
| Finished | Sep 18 04:50:17 PM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928098478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.1928098478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.2553749544 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 4547261230 ps |
| CPU time | 13.81 seconds |
| Started | Sep 18 04:50:17 PM UTC 24 |
| Finished | Sep 18 04:50:32 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553749544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.2553749544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.3103658374 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 629885809 ps |
| CPU time | 4.41 seconds |
| Started | Sep 18 04:57:09 PM UTC 24 |
| Finished | Sep 18 04:57:15 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103658374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.3103658374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.1649703559 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 118130078 ps |
| CPU time | 3.17 seconds |
| Started | Sep 18 04:57:09 PM UTC 24 |
| Finished | Sep 18 04:57:14 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649703559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.1649703559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.3191985989 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 207431943 ps |
| CPU time | 3.6 seconds |
| Started | Sep 18 04:57:09 PM UTC 24 |
| Finished | Sep 18 04:57:14 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191985989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.3191985989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.224179433 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 230999596 ps |
| CPU time | 2.73 seconds |
| Started | Sep 18 04:57:09 PM UTC 24 |
| Finished | Sep 18 04:57:13 PM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224179433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.224179433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.3500113010 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 161367962 ps |
| CPU time | 3.95 seconds |
| Started | Sep 18 04:57:09 PM UTC 24 |
| Finished | Sep 18 04:57:15 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500113010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.3500113010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.3968353661 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 224725539 ps |
| CPU time | 3.18 seconds |
| Started | Sep 18 04:57:09 PM UTC 24 |
| Finished | Sep 18 04:57:14 PM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968353661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.3968353661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3619874171 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 502826229 ps |
| CPU time | 3.6 seconds |
| Started | Sep 18 04:57:09 PM UTC 24 |
| Finished | Sep 18 04:57:14 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619874171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.3619874171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.3515225287 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 270957255 ps |
| CPU time | 3.34 seconds |
| Started | Sep 18 04:57:09 PM UTC 24 |
| Finished | Sep 18 04:57:14 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515225287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.3515225287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.4165068096 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 1649960837 ps |
| CPU time | 4.08 seconds |
| Started | Sep 18 04:57:09 PM UTC 24 |
| Finished | Sep 18 04:57:15 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165068096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.4165068096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.2417462387 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 105155657 ps |
| CPU time | 2.85 seconds |
| Started | Sep 18 04:50:27 PM UTC 24 |
| Finished | Sep 18 04:50:31 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417462387 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.2417462387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.4111053803 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1864195586 ps |
| CPU time | 20.79 seconds |
| Started | Sep 18 04:50:23 PM UTC 24 |
| Finished | Sep 18 04:50:45 PM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111053803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.4111053803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.3284502856 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 4978326312 ps |
| CPU time | 25.87 seconds |
| Started | Sep 18 04:50:23 PM UTC 24 |
| Finished | Sep 18 04:50:50 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284502856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.3284502856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.3576589362 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 285733636 ps |
| CPU time | 8.04 seconds |
| Started | Sep 18 04:50:23 PM UTC 24 |
| Finished | Sep 18 04:50:32 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576589362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.3576589362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.1098743511 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 145229947 ps |
| CPU time | 3.35 seconds |
| Started | Sep 18 04:50:23 PM UTC 24 |
| Finished | Sep 18 04:50:28 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098743511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1098743511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.3700055569 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2250794293 ps |
| CPU time | 44.78 seconds |
| Started | Sep 18 04:50:23 PM UTC 24 |
| Finished | Sep 18 04:51:10 PM UTC 24 |
| Peak memory | 254060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700055569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.3700055569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.2312845470 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 5435159831 ps |
| CPU time | 67.41 seconds |
| Started | Sep 18 04:50:25 PM UTC 24 |
| Finished | Sep 18 04:51:34 PM UTC 24 |
| Peak memory | 252144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312845470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.2312845470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.3833584295 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 881453640 ps |
| CPU time | 12.51 seconds |
| Started | Sep 18 04:50:23 PM UTC 24 |
| Finished | Sep 18 04:50:37 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833584295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.3833584295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.2159753858 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 514063699 ps |
| CPU time | 16.13 seconds |
| Started | Sep 18 04:50:23 PM UTC 24 |
| Finished | Sep 18 04:50:40 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159753858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2159753858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.3143365615 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 251468790 ps |
| CPU time | 4.77 seconds |
| Started | Sep 18 04:50:25 PM UTC 24 |
| Finished | Sep 18 04:50:31 PM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143365615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.3143365615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.15020728 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 359857165 ps |
| CPU time | 7.39 seconds |
| Started | Sep 18 04:50:23 PM UTC 24 |
| Finished | Sep 18 04:50:32 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15020728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.15020728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.1710983362 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2112892693 ps |
| CPU time | 41.31 seconds |
| Started | Sep 18 04:50:25 PM UTC 24 |
| Finished | Sep 18 04:51:08 PM UTC 24 |
| Peak memory | 253896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710983362 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.1710983362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.981885869 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1059403742 ps |
| CPU time | 18.94 seconds |
| Started | Sep 18 04:50:25 PM UTC 24 |
| Finished | Sep 18 04:50:45 PM UTC 24 |
| Peak memory | 252068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981885869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.981885869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.4255300493 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 2090204674 ps |
| CPU time | 4.79 seconds |
| Started | Sep 18 04:57:11 PM UTC 24 |
| Finished | Sep 18 04:57:17 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255300493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.4255300493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.4129922806 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 1547892227 ps |
| CPU time | 3.78 seconds |
| Started | Sep 18 04:57:11 PM UTC 24 |
| Finished | Sep 18 04:57:16 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129922806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.4129922806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.4038576514 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 2436662904 ps |
| CPU time | 6.21 seconds |
| Started | Sep 18 04:57:11 PM UTC 24 |
| Finished | Sep 18 04:57:19 PM UTC 24 |
| Peak memory | 250800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038576514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.4038576514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.2110668482 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 309859773 ps |
| CPU time | 3.7 seconds |
| Started | Sep 18 04:57:11 PM UTC 24 |
| Finished | Sep 18 04:57:16 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110668482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.2110668482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.597163845 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 181044201 ps |
| CPU time | 3.36 seconds |
| Started | Sep 18 04:57:11 PM UTC 24 |
| Finished | Sep 18 04:57:16 PM UTC 24 |
| Peak memory | 250824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597163845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.597163845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.1947409568 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 120282462 ps |
| CPU time | 3.43 seconds |
| Started | Sep 18 04:57:11 PM UTC 24 |
| Finished | Sep 18 04:57:16 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947409568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.1947409568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.1168432402 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 458744729 ps |
| CPU time | 3.71 seconds |
| Started | Sep 18 04:57:11 PM UTC 24 |
| Finished | Sep 18 04:57:16 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168432402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.1168432402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.3447246130 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 553783088 ps |
| CPU time | 4.55 seconds |
| Started | Sep 18 04:57:11 PM UTC 24 |
| Finished | Sep 18 04:57:18 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447246130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.3447246130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.2723107608 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 143114002 ps |
| CPU time | 4.28 seconds |
| Started | Sep 18 04:57:11 PM UTC 24 |
| Finished | Sep 18 04:57:17 PM UTC 24 |
| Peak memory | 251136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723107608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.2723107608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.2147281940 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 313659859 ps |
| CPU time | 3.77 seconds |
| Started | Sep 18 04:57:11 PM UTC 24 |
| Finished | Sep 18 04:57:17 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147281940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2147281940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.618292875 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 100595499 ps |
| CPU time | 2.56 seconds |
| Started | Sep 18 04:50:37 PM UTC 24 |
| Finished | Sep 18 04:50:40 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618292875 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.618292875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.1427104273 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 3723184848 ps |
| CPU time | 23.24 seconds |
| Started | Sep 18 04:50:35 PM UTC 24 |
| Finished | Sep 18 04:50:59 PM UTC 24 |
| Peak memory | 254064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427104273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.1427104273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.1490720980 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 3005193290 ps |
| CPU time | 46.97 seconds |
| Started | Sep 18 04:50:32 PM UTC 24 |
| Finished | Sep 18 04:51:20 PM UTC 24 |
| Peak memory | 264348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490720980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.1490720980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.2176838436 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 6974056214 ps |
| CPU time | 17.17 seconds |
| Started | Sep 18 04:50:32 PM UTC 24 |
| Finished | Sep 18 04:50:50 PM UTC 24 |
| Peak memory | 252052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176838436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.2176838436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.963346706 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 172601187 ps |
| CPU time | 3.66 seconds |
| Started | Sep 18 04:50:29 PM UTC 24 |
| Finished | Sep 18 04:50:33 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963346706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.963346706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.2002747191 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1746891675 ps |
| CPU time | 23.35 seconds |
| Started | Sep 18 04:50:35 PM UTC 24 |
| Finished | Sep 18 04:51:00 PM UTC 24 |
| Peak memory | 254044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002747191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.2002747191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.3187040273 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 572651495 ps |
| CPU time | 16.93 seconds |
| Started | Sep 18 04:50:35 PM UTC 24 |
| Finished | Sep 18 04:50:53 PM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187040273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.3187040273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.1675705190 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 815225107 ps |
| CPU time | 15.47 seconds |
| Started | Sep 18 04:50:32 PM UTC 24 |
| Finished | Sep 18 04:50:49 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675705190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.1675705190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.3403196070 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1145052183 ps |
| CPU time | 17.83 seconds |
| Started | Sep 18 04:50:29 PM UTC 24 |
| Finished | Sep 18 04:50:48 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403196070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3403196070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.1671643138 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3514430197 ps |
| CPU time | 18.73 seconds |
| Started | Sep 18 04:50:35 PM UTC 24 |
| Finished | Sep 18 04:50:55 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671643138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.1671643138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.2604905969 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 397360214 ps |
| CPU time | 6.15 seconds |
| Started | Sep 18 04:50:29 PM UTC 24 |
| Finished | Sep 18 04:50:36 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604905969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2604905969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.1494679283 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 15514134119 ps |
| CPU time | 222.21 seconds |
| Started | Sep 18 04:50:37 PM UTC 24 |
| Finished | Sep 18 04:54:22 PM UTC 24 |
| Peak memory | 276540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494679283 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.1494679283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.2614946726 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1392660438 ps |
| CPU time | 15.92 seconds |
| Started | Sep 18 04:50:37 PM UTC 24 |
| Finished | Sep 18 04:50:54 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614946726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.2614946726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.4161441055 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 2390933353 ps |
| CPU time | 6.94 seconds |
| Started | Sep 18 04:57:11 PM UTC 24 |
| Finished | Sep 18 04:57:20 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161441055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.4161441055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.1517629360 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 388557903 ps |
| CPU time | 4.25 seconds |
| Started | Sep 18 04:57:11 PM UTC 24 |
| Finished | Sep 18 04:57:17 PM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517629360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.1517629360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.3423865004 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 1811844679 ps |
| CPU time | 5.86 seconds |
| Started | Sep 18 04:57:11 PM UTC 24 |
| Finished | Sep 18 04:57:19 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423865004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.3423865004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.3862283672 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 506072454 ps |
| CPU time | 3.42 seconds |
| Started | Sep 18 04:57:12 PM UTC 24 |
| Finished | Sep 18 04:57:16 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862283672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3862283672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.4245847170 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 1663164176 ps |
| CPU time | 5.92 seconds |
| Started | Sep 18 04:57:12 PM UTC 24 |
| Finished | Sep 18 04:57:19 PM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245847170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.4245847170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.3379825596 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 264348260 ps |
| CPU time | 3.43 seconds |
| Started | Sep 18 04:57:12 PM UTC 24 |
| Finished | Sep 18 04:57:16 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379825596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.3379825596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.2252837954 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 273070106 ps |
| CPU time | 3.92 seconds |
| Started | Sep 18 04:57:12 PM UTC 24 |
| Finished | Sep 18 04:57:17 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252837954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.2252837954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.3148458175 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 131830447 ps |
| CPU time | 3.34 seconds |
| Started | Sep 18 04:57:12 PM UTC 24 |
| Finished | Sep 18 04:57:17 PM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148458175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.3148458175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.2482265213 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 152541287 ps |
| CPU time | 4.16 seconds |
| Started | Sep 18 04:57:12 PM UTC 24 |
| Finished | Sep 18 04:57:17 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482265213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.2482265213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.258974940 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 273545357 ps |
| CPU time | 4.44 seconds |
| Started | Sep 18 04:57:12 PM UTC 24 |
| Finished | Sep 18 04:57:18 PM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258974940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.258974940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.1597465412 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 197365916 ps |
| CPU time | 2.73 seconds |
| Started | Sep 18 04:50:54 PM UTC 24 |
| Finished | Sep 18 04:50:57 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597465412 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1597465412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.2847620046 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8486021566 ps |
| CPU time | 34.23 seconds |
| Started | Sep 18 04:50:50 PM UTC 24 |
| Finished | Sep 18 04:51:25 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847620046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.2847620046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.1311499863 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 1458881179 ps |
| CPU time | 33.18 seconds |
| Started | Sep 18 04:50:48 PM UTC 24 |
| Finished | Sep 18 04:51:22 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311499863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1311499863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.372349260 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 266781168 ps |
| CPU time | 9.6 seconds |
| Started | Sep 18 04:50:46 PM UTC 24 |
| Finished | Sep 18 04:50:57 PM UTC 24 |
| Peak memory | 252096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372349260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.372349260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.654796284 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 232108932 ps |
| CPU time | 5.31 seconds |
| Started | Sep 18 04:50:42 PM UTC 24 |
| Finished | Sep 18 04:50:48 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654796284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.654796284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.2424806704 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1060758006 ps |
| CPU time | 21.41 seconds |
| Started | Sep 18 04:50:50 PM UTC 24 |
| Finished | Sep 18 04:51:12 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424806704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2424806704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.2944398403 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1540127253 ps |
| CPU time | 42.99 seconds |
| Started | Sep 18 04:50:50 PM UTC 24 |
| Finished | Sep 18 04:51:34 PM UTC 24 |
| Peak memory | 258016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944398403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.2944398403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.687324786 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 2349805993 ps |
| CPU time | 9.31 seconds |
| Started | Sep 18 04:50:42 PM UTC 24 |
| Finished | Sep 18 04:50:52 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687324786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.687324786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.1634467213 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 416337399 ps |
| CPU time | 18.02 seconds |
| Started | Sep 18 04:50:42 PM UTC 24 |
| Finished | Sep 18 04:51:01 PM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634467213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.1634467213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.1259174531 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 262895653 ps |
| CPU time | 10.5 seconds |
| Started | Sep 18 04:50:50 PM UTC 24 |
| Finished | Sep 18 04:51:01 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259174531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.1259174531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.2881769694 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 152361895 ps |
| CPU time | 8.79 seconds |
| Started | Sep 18 04:50:38 PM UTC 24 |
| Finished | Sep 18 04:50:48 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881769694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2881769694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.1180719024 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 7668124321 ps |
| CPU time | 72.6 seconds |
| Started | Sep 18 04:50:52 PM UTC 24 |
| Finished | Sep 18 04:52:07 PM UTC 24 |
| Peak memory | 258128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180719024 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.1180719024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.236104994 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 7541716991 ps |
| CPU time | 94.96 seconds |
| Started | Sep 18 04:50:52 PM UTC 24 |
| Finished | Sep 18 04:52:29 PM UTC 24 |
| Peak memory | 258324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=236104994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.236104994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.2257699514 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 190686298 ps |
| CPU time | 4.75 seconds |
| Started | Sep 18 04:50:52 PM UTC 24 |
| Finished | Sep 18 04:50:58 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257699514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.2257699514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.252415139 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 145574961 ps |
| CPU time | 3.39 seconds |
| Started | Sep 18 04:57:12 PM UTC 24 |
| Finished | Sep 18 04:57:17 PM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252415139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.252415139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.3204957164 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 264584189 ps |
| CPU time | 3.52 seconds |
| Started | Sep 18 04:57:12 PM UTC 24 |
| Finished | Sep 18 04:57:17 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204957164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3204957164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.4208033724 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 146406154 ps |
| CPU time | 3.06 seconds |
| Started | Sep 18 04:57:12 PM UTC 24 |
| Finished | Sep 18 04:57:17 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208033724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.4208033724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.3759031450 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 159703301 ps |
| CPU time | 3.79 seconds |
| Started | Sep 18 04:57:12 PM UTC 24 |
| Finished | Sep 18 04:57:17 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759031450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.3759031450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.4121254347 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 410021905 ps |
| CPU time | 3.39 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:20 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121254347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.4121254347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.1437827681 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 457734402 ps |
| CPU time | 2.96 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:19 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437827681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.1437827681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.3350834755 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 113323395 ps |
| CPU time | 3.68 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:20 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350834755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.3350834755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.4186570768 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 117225601 ps |
| CPU time | 3.54 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:20 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186570768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.4186570768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.49848386 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 115427167 ps |
| CPU time | 2.84 seconds |
| Started | Sep 18 04:51:10 PM UTC 24 |
| Finished | Sep 18 04:51:14 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49848386 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.49848386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.1675055521 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 4361690048 ps |
| CPU time | 31.81 seconds |
| Started | Sep 18 04:51:02 PM UTC 24 |
| Finished | Sep 18 04:51:36 PM UTC 24 |
| Peak memory | 254028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675055521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.1675055521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.1340024803 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 14109810959 ps |
| CPU time | 38.85 seconds |
| Started | Sep 18 04:50:59 PM UTC 24 |
| Finished | Sep 18 04:51:39 PM UTC 24 |
| Peak memory | 253968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340024803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.1340024803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.2669378257 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1705575481 ps |
| CPU time | 39.36 seconds |
| Started | Sep 18 04:50:58 PM UTC 24 |
| Finished | Sep 18 04:51:39 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669378257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.2669378257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.4134956346 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 160047356 ps |
| CPU time | 6.34 seconds |
| Started | Sep 18 04:50:55 PM UTC 24 |
| Finished | Sep 18 04:51:03 PM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134956346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.4134956346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.677300079 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 6127678689 ps |
| CPU time | 13.38 seconds |
| Started | Sep 18 04:51:02 PM UTC 24 |
| Finished | Sep 18 04:51:17 PM UTC 24 |
| Peak memory | 258132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677300079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.677300079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.2631357071 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 506296113 ps |
| CPU time | 12.25 seconds |
| Started | Sep 18 04:51:03 PM UTC 24 |
| Finished | Sep 18 04:51:16 PM UTC 24 |
| Peak memory | 252016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631357071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.2631357071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.2741786009 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 433601432 ps |
| CPU time | 16.63 seconds |
| Started | Sep 18 04:50:58 PM UTC 24 |
| Finished | Sep 18 04:51:16 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741786009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.2741786009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.2509491281 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 490498566 ps |
| CPU time | 10.52 seconds |
| Started | Sep 18 04:50:57 PM UTC 24 |
| Finished | Sep 18 04:51:08 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509491281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.2509491281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.993051937 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1137567452 ps |
| CPU time | 11.67 seconds |
| Started | Sep 18 04:51:03 PM UTC 24 |
| Finished | Sep 18 04:51:15 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993051937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.993051937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.2298484451 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 751898543 ps |
| CPU time | 10.76 seconds |
| Started | Sep 18 04:50:55 PM UTC 24 |
| Finished | Sep 18 04:51:07 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298484451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.2298484451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.3317948246 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 82100745962 ps |
| CPU time | 140.77 seconds |
| Started | Sep 18 04:51:08 PM UTC 24 |
| Finished | Sep 18 04:53:31 PM UTC 24 |
| Peak memory | 270340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317948246 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.3317948246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.686593973 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3362645690 ps |
| CPU time | 35.8 seconds |
| Started | Sep 18 04:51:03 PM UTC 24 |
| Finished | Sep 18 04:51:40 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686593973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.686593973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.1711226328 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 156406627 ps |
| CPU time | 3.43 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:20 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711226328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.1711226328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.1024281798 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 360883973 ps |
| CPU time | 3.21 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:20 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024281798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.1024281798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.2157775627 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 2243818199 ps |
| CPU time | 5.74 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:22 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157775627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2157775627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.2955001701 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 134011995 ps |
| CPU time | 3.17 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:20 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955001701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.2955001701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.2915385451 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 278579140 ps |
| CPU time | 2.73 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:19 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915385451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.2915385451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.1496657511 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 498694376 ps |
| CPU time | 3.56 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:20 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496657511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.1496657511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.3845579857 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 463142548 ps |
| CPU time | 3.47 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:20 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845579857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.3845579857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.2500682669 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 474459174 ps |
| CPU time | 3.96 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:21 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500682669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.2500682669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.2825388822 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 195366482 ps |
| CPU time | 3.55 seconds |
| Started | Sep 18 04:57:15 PM UTC 24 |
| Finished | Sep 18 04:57:20 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825388822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.2825388822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.539767241 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 432963860 ps |
| CPU time | 3.72 seconds |
| Started | Sep 18 04:57:17 PM UTC 24 |
| Finished | Sep 18 04:57:22 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539767241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.539767241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.1269961200 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 222999937 ps |
| CPU time | 3.34 seconds |
| Started | Sep 18 04:51:24 PM UTC 24 |
| Finished | Sep 18 04:51:29 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269961200 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.1269961200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.1811431900 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 5590014786 ps |
| CPU time | 14.91 seconds |
| Started | Sep 18 04:51:18 PM UTC 24 |
| Finished | Sep 18 04:51:34 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811431900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.1811431900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.3226650504 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 727218779 ps |
| CPU time | 19.65 seconds |
| Started | Sep 18 04:51:15 PM UTC 24 |
| Finished | Sep 18 04:51:35 PM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226650504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3226650504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.137457498 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 141402286 ps |
| CPU time | 5.92 seconds |
| Started | Sep 18 04:51:10 PM UTC 24 |
| Finished | Sep 18 04:51:17 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137457498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.137457498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.2478240397 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1964574830 ps |
| CPU time | 21.06 seconds |
| Started | Sep 18 04:51:18 PM UTC 24 |
| Finished | Sep 18 04:51:40 PM UTC 24 |
| Peak memory | 252016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478240397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.2478240397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.705414680 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 22005601277 ps |
| CPU time | 58.75 seconds |
| Started | Sep 18 04:51:18 PM UTC 24 |
| Finished | Sep 18 04:52:18 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705414680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.705414680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.1736654015 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2142206519 ps |
| CPU time | 9.46 seconds |
| Started | Sep 18 04:51:13 PM UTC 24 |
| Finished | Sep 18 04:51:24 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736654015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.1736654015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.1968208473 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 13015207958 ps |
| CPU time | 29.12 seconds |
| Started | Sep 18 04:51:11 PM UTC 24 |
| Finished | Sep 18 04:51:42 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968208473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1968208473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.3154266128 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 322931159 ps |
| CPU time | 8.18 seconds |
| Started | Sep 18 04:51:18 PM UTC 24 |
| Finished | Sep 18 04:51:27 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154266128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.3154266128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.1481192569 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 305714587 ps |
| CPU time | 5.52 seconds |
| Started | Sep 18 04:51:10 PM UTC 24 |
| Finished | Sep 18 04:51:16 PM UTC 24 |
| Peak memory | 252008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481192569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1481192569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.4039600474 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 27287771928 ps |
| CPU time | 223.18 seconds |
| Started | Sep 18 04:51:22 PM UTC 24 |
| Finished | Sep 18 04:55:09 PM UTC 24 |
| Peak memory | 268436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039600474 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.4039600474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.883192945 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 5430947293 ps |
| CPU time | 39.95 seconds |
| Started | Sep 18 04:51:22 PM UTC 24 |
| Finished | Sep 18 04:52:04 PM UTC 24 |
| Peak memory | 258256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=883192945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.883192945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.3894933826 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 780717311 ps |
| CPU time | 15.82 seconds |
| Started | Sep 18 04:51:19 PM UTC 24 |
| Finished | Sep 18 04:51:36 PM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894933826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.3894933826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.243798888 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 225491992 ps |
| CPU time | 3.44 seconds |
| Started | Sep 18 04:57:17 PM UTC 24 |
| Finished | Sep 18 04:57:21 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243798888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.243798888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.394732478 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 170455513 ps |
| CPU time | 3.09 seconds |
| Started | Sep 18 04:57:17 PM UTC 24 |
| Finished | Sep 18 04:57:21 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394732478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.394732478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.2611457611 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 121863661 ps |
| CPU time | 4.15 seconds |
| Started | Sep 18 04:57:17 PM UTC 24 |
| Finished | Sep 18 04:57:22 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611457611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.2611457611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.2030174380 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 169594941 ps |
| CPU time | 3.93 seconds |
| Started | Sep 18 04:57:17 PM UTC 24 |
| Finished | Sep 18 04:57:22 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030174380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.2030174380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.2794328936 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 100960206 ps |
| CPU time | 3.75 seconds |
| Started | Sep 18 04:57:17 PM UTC 24 |
| Finished | Sep 18 04:57:22 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794328936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.2794328936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.2544803693 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 116828667 ps |
| CPU time | 3.79 seconds |
| Started | Sep 18 04:57:17 PM UTC 24 |
| Finished | Sep 18 04:57:22 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544803693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.2544803693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.2133830717 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 131653230 ps |
| CPU time | 3.37 seconds |
| Started | Sep 18 04:57:17 PM UTC 24 |
| Finished | Sep 18 04:57:21 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133830717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.2133830717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.1262033799 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 307235568 ps |
| CPU time | 3.53 seconds |
| Started | Sep 18 04:57:17 PM UTC 24 |
| Finished | Sep 18 04:57:22 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262033799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.1262033799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.1859591406 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 293626779 ps |
| CPU time | 4.18 seconds |
| Started | Sep 18 04:57:20 PM UTC 24 |
| Finished | Sep 18 04:57:25 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859591406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.1859591406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.2683016505 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 324367947 ps |
| CPU time | 3.72 seconds |
| Started | Sep 18 04:57:20 PM UTC 24 |
| Finished | Sep 18 04:57:25 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683016505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.2683016505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.1058545390 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 152571858 ps |
| CPU time | 3.18 seconds |
| Started | Sep 18 04:44:37 PM UTC 24 |
| Finished | Sep 18 04:44:41 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058545390 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1058545390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.304698265 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 186779030 ps |
| CPU time | 5.89 seconds |
| Started | Sep 18 04:44:16 PM UTC 24 |
| Finished | Sep 18 04:44:23 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304698265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.304698265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.1359490894 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 258020449 ps |
| CPU time | 9.88 seconds |
| Started | Sep 18 04:44:25 PM UTC 24 |
| Finished | Sep 18 04:44:35 PM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359490894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1359490894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.4258470806 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 416235085 ps |
| CPU time | 10.04 seconds |
| Started | Sep 18 04:44:23 PM UTC 24 |
| Finished | Sep 18 04:44:34 PM UTC 24 |
| Peak memory | 252068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258470806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.4258470806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.2777964078 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2708394880 ps |
| CPU time | 29.53 seconds |
| Started | Sep 18 04:44:25 PM UTC 24 |
| Finished | Sep 18 04:44:55 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777964078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.2777964078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.1032116099 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 7029675927 ps |
| CPU time | 14.09 seconds |
| Started | Sep 18 04:44:29 PM UTC 24 |
| Finished | Sep 18 04:44:44 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032116099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1032116099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.2421523683 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 358396896 ps |
| CPU time | 12.19 seconds |
| Started | Sep 18 04:44:21 PM UTC 24 |
| Finished | Sep 18 04:44:35 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421523683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.2421523683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.781709267 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1217579639 ps |
| CPU time | 22.43 seconds |
| Started | Sep 18 04:44:21 PM UTC 24 |
| Finished | Sep 18 04:44:45 PM UTC 24 |
| Peak memory | 252028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781709267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.781709267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.53654504 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11486138580 ps |
| CPU time | 192.86 seconds |
| Started | Sep 18 04:44:36 PM UTC 24 |
| Finished | Sep 18 04:47:52 PM UTC 24 |
| Peak memory | 290552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53654504 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.53654504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.2371935433 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1663089347 ps |
| CPU time | 12.83 seconds |
| Started | Sep 18 04:44:14 PM UTC 24 |
| Finished | Sep 18 04:44:28 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371935433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2371935433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.4017600352 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3318776221 ps |
| CPU time | 40.79 seconds |
| Started | Sep 18 04:44:33 PM UTC 24 |
| Finished | Sep 18 04:45:15 PM UTC 24 |
| Peak memory | 253880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017600352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.4017600352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.1192536556 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 51070695 ps |
| CPU time | 2.61 seconds |
| Started | Sep 18 04:51:41 PM UTC 24 |
| Finished | Sep 18 04:51:45 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192536556 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.1192536556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.1353376962 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1209917329 ps |
| CPU time | 18.57 seconds |
| Started | Sep 18 04:51:32 PM UTC 24 |
| Finished | Sep 18 04:51:52 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353376962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1353376962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.3407762876 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1781334121 ps |
| CPU time | 23.09 seconds |
| Started | Sep 18 04:51:32 PM UTC 24 |
| Finished | Sep 18 04:51:57 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407762876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.3407762876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.2663795709 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1049237896 ps |
| CPU time | 22.57 seconds |
| Started | Sep 18 04:51:32 PM UTC 24 |
| Finished | Sep 18 04:51:56 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663795709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2663795709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.1592553652 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 567373014 ps |
| CPU time | 5.15 seconds |
| Started | Sep 18 04:51:32 PM UTC 24 |
| Finished | Sep 18 04:51:38 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592553652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1592553652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.148107219 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 758565364 ps |
| CPU time | 10.75 seconds |
| Started | Sep 18 04:51:37 PM UTC 24 |
| Finished | Sep 18 04:51:49 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148107219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.148107219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.3662531973 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1488012928 ps |
| CPU time | 32.15 seconds |
| Started | Sep 18 04:51:37 PM UTC 24 |
| Finished | Sep 18 04:52:11 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662531973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.3662531973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.2864091153 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 518729496 ps |
| CPU time | 6.52 seconds |
| Started | Sep 18 04:51:32 PM UTC 24 |
| Finished | Sep 18 04:51:40 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864091153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.2864091153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.3840443460 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1517705305 ps |
| CPU time | 16.31 seconds |
| Started | Sep 18 04:51:32 PM UTC 24 |
| Finished | Sep 18 04:51:50 PM UTC 24 |
| Peak memory | 251528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840443460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3840443460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.2978702754 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 260536280 ps |
| CPU time | 8.35 seconds |
| Started | Sep 18 04:51:37 PM UTC 24 |
| Finished | Sep 18 04:51:47 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978702754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.2978702754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.2797602584 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 283495404 ps |
| CPU time | 7.46 seconds |
| Started | Sep 18 04:51:32 PM UTC 24 |
| Finished | Sep 18 04:51:41 PM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797602584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.2797602584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.3014809703 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 1094554786 ps |
| CPU time | 28.76 seconds |
| Started | Sep 18 04:51:41 PM UTC 24 |
| Finished | Sep 18 04:52:12 PM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014809703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.3014809703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.3183847530 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 69158803 ps |
| CPU time | 2.85 seconds |
| Started | Sep 18 04:51:47 PM UTC 24 |
| Finished | Sep 18 04:51:51 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183847530 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.3183847530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.3292406170 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 982940120 ps |
| CPU time | 11.88 seconds |
| Started | Sep 18 04:51:42 PM UTC 24 |
| Finished | Sep 18 04:51:55 PM UTC 24 |
| Peak memory | 258032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292406170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3292406170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.2952438441 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 504857199 ps |
| CPU time | 12.28 seconds |
| Started | Sep 18 04:51:42 PM UTC 24 |
| Finished | Sep 18 04:51:55 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952438441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.2952438441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.59670872 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1844829510 ps |
| CPU time | 22.69 seconds |
| Started | Sep 18 04:51:42 PM UTC 24 |
| Finished | Sep 18 04:52:06 PM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59670872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.59670872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.933216723 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 135543503 ps |
| CPU time | 4.16 seconds |
| Started | Sep 18 04:51:41 PM UTC 24 |
| Finished | Sep 18 04:51:47 PM UTC 24 |
| Peak memory | 251328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933216723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.933216723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.3062750465 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3247039423 ps |
| CPU time | 30.51 seconds |
| Started | Sep 18 04:51:42 PM UTC 24 |
| Finished | Sep 18 04:52:14 PM UTC 24 |
| Peak memory | 256148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062750465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.3062750465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.2575357582 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 234511021 ps |
| CPU time | 4.73 seconds |
| Started | Sep 18 04:51:42 PM UTC 24 |
| Finished | Sep 18 04:51:48 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575357582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.2575357582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.1361126906 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 1124760627 ps |
| CPU time | 19.26 seconds |
| Started | Sep 18 04:51:42 PM UTC 24 |
| Finished | Sep 18 04:52:02 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361126906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1361126906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.234031417 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 634255871 ps |
| CPU time | 6.32 seconds |
| Started | Sep 18 04:51:41 PM UTC 24 |
| Finished | Sep 18 04:51:49 PM UTC 24 |
| Peak memory | 251584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234031417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.234031417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.2873216955 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 241238177 ps |
| CPU time | 6.22 seconds |
| Started | Sep 18 04:51:42 PM UTC 24 |
| Finished | Sep 18 04:51:50 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873216955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2873216955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.3017543581 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 443150676 ps |
| CPU time | 6.44 seconds |
| Started | Sep 18 04:51:41 PM UTC 24 |
| Finished | Sep 18 04:51:49 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017543581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3017543581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.2290359060 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2172844765 ps |
| CPU time | 52.94 seconds |
| Started | Sep 18 04:51:44 PM UTC 24 |
| Finished | Sep 18 04:52:38 PM UTC 24 |
| Peak memory | 253936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290359060 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.2290359060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.3304890639 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 2053493284 ps |
| CPU time | 46.13 seconds |
| Started | Sep 18 04:51:44 PM UTC 24 |
| Finished | Sep 18 04:52:32 PM UTC 24 |
| Peak memory | 268384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3304890639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.otp_ctrl_stress_all_with_rand_reset.3304890639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.1494948021 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 8410218324 ps |
| CPU time | 20.02 seconds |
| Started | Sep 18 04:51:44 PM UTC 24 |
| Finished | Sep 18 04:52:05 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494948021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.1494948021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.3590702134 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 61485440 ps |
| CPU time | 2.88 seconds |
| Started | Sep 18 04:51:55 PM UTC 24 |
| Finished | Sep 18 04:51:59 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590702134 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.3590702134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.1160703543 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 612790072 ps |
| CPU time | 7.41 seconds |
| Started | Sep 18 04:51:52 PM UTC 24 |
| Finished | Sep 18 04:52:01 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160703543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.1160703543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.3229641400 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1453864491 ps |
| CPU time | 48.78 seconds |
| Started | Sep 18 04:51:52 PM UTC 24 |
| Finished | Sep 18 04:52:43 PM UTC 24 |
| Peak memory | 260184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229641400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.3229641400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.865494815 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 563488895 ps |
| CPU time | 12.08 seconds |
| Started | Sep 18 04:51:52 PM UTC 24 |
| Finished | Sep 18 04:52:05 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865494815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.865494815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.177808848 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2042964708 ps |
| CPU time | 5.07 seconds |
| Started | Sep 18 04:51:48 PM UTC 24 |
| Finished | Sep 18 04:51:54 PM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177808848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.177808848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.3303946452 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 2154164106 ps |
| CPU time | 35.89 seconds |
| Started | Sep 18 04:51:52 PM UTC 24 |
| Finished | Sep 18 04:52:30 PM UTC 24 |
| Peak memory | 256184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303946452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.3303946452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.1879007898 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2561735932 ps |
| CPU time | 23.15 seconds |
| Started | Sep 18 04:51:52 PM UTC 24 |
| Finished | Sep 18 04:52:17 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879007898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.1879007898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.3286261895 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 301805774 ps |
| CPU time | 4.48 seconds |
| Started | Sep 18 04:51:48 PM UTC 24 |
| Finished | Sep 18 04:51:54 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286261895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.3286261895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.450873667 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 222154949 ps |
| CPU time | 11.13 seconds |
| Started | Sep 18 04:51:52 PM UTC 24 |
| Finished | Sep 18 04:52:05 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450873667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.450873667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.3288500097 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 806443039 ps |
| CPU time | 5.89 seconds |
| Started | Sep 18 04:51:47 PM UTC 24 |
| Finished | Sep 18 04:51:54 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288500097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.3288500097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.1859608212 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 17256298324 ps |
| CPU time | 221.06 seconds |
| Started | Sep 18 04:51:55 PM UTC 24 |
| Finished | Sep 18 04:55:40 PM UTC 24 |
| Peak memory | 268368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859608212 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.1859608212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.3174016572 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 15487651679 ps |
| CPU time | 216.61 seconds |
| Started | Sep 18 04:51:54 PM UTC 24 |
| Finished | Sep 18 04:55:34 PM UTC 24 |
| Peak memory | 274676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3174016572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.otp_ctrl_stress_all_with_rand_reset.3174016572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.4193350072 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 3109055540 ps |
| CPU time | 22.52 seconds |
| Started | Sep 18 04:51:52 PM UTC 24 |
| Finished | Sep 18 04:52:16 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193350072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.4193350072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.1256382009 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 306906114 ps |
| CPU time | 5.79 seconds |
| Started | Sep 18 04:52:05 PM UTC 24 |
| Finished | Sep 18 04:52:12 PM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256382009 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.1256382009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.3234192340 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 6048018992 ps |
| CPU time | 22.47 seconds |
| Started | Sep 18 04:52:00 PM UTC 24 |
| Finished | Sep 18 04:52:24 PM UTC 24 |
| Peak memory | 254064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234192340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.3234192340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.2753957346 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 432618187 ps |
| CPU time | 13.35 seconds |
| Started | Sep 18 04:51:59 PM UTC 24 |
| Finished | Sep 18 04:52:14 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753957346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.2753957346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.3554081157 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 3752803324 ps |
| CPU time | 37.45 seconds |
| Started | Sep 18 04:51:59 PM UTC 24 |
| Finished | Sep 18 04:52:38 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554081157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3554081157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.3281687785 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 193638800 ps |
| CPU time | 4.78 seconds |
| Started | Sep 18 04:51:57 PM UTC 24 |
| Finished | Sep 18 04:52:03 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281687785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.3281687785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.4133272672 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1160713171 ps |
| CPU time | 33.54 seconds |
| Started | Sep 18 04:52:01 PM UTC 24 |
| Finished | Sep 18 04:52:36 PM UTC 24 |
| Peak memory | 256020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133272672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.4133272672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.576399803 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 3566609498 ps |
| CPU time | 28.37 seconds |
| Started | Sep 18 04:52:02 PM UTC 24 |
| Finished | Sep 18 04:52:32 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576399803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.576399803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.423653772 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 680613439 ps |
| CPU time | 9.27 seconds |
| Started | Sep 18 04:51:59 PM UTC 24 |
| Finished | Sep 18 04:52:09 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423653772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.423653772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.218125885 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 728837384 ps |
| CPU time | 30.11 seconds |
| Started | Sep 18 04:51:57 PM UTC 24 |
| Finished | Sep 18 04:52:28 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218125885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.218125885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.2601433853 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 561344321 ps |
| CPU time | 5.05 seconds |
| Started | Sep 18 04:52:05 PM UTC 24 |
| Finished | Sep 18 04:52:11 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601433853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.2601433853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.993668678 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 573838342 ps |
| CPU time | 5.75 seconds |
| Started | Sep 18 04:51:55 PM UTC 24 |
| Finished | Sep 18 04:52:02 PM UTC 24 |
| Peak memory | 252004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993668678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.993668678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.343058063 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 22097281704 ps |
| CPU time | 164.96 seconds |
| Started | Sep 18 04:52:05 PM UTC 24 |
| Finished | Sep 18 04:54:53 PM UTC 24 |
| Peak memory | 268436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343058063 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.343058063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.2302192844 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 31764897622 ps |
| CPU time | 78.75 seconds |
| Started | Sep 18 04:52:05 PM UTC 24 |
| Finished | Sep 18 04:53:25 PM UTC 24 |
| Peak memory | 268496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2302192844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.otp_ctrl_stress_all_with_rand_reset.2302192844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.3253906914 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1172385154 ps |
| CPU time | 19.71 seconds |
| Started | Sep 18 04:52:05 PM UTC 24 |
| Finished | Sep 18 04:52:26 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253906914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.3253906914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.3971530822 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 235008563 ps |
| CPU time | 3.49 seconds |
| Started | Sep 18 04:52:17 PM UTC 24 |
| Finished | Sep 18 04:52:21 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971530822 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.3971530822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.1397738595 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 1501096256 ps |
| CPU time | 15.9 seconds |
| Started | Sep 18 04:52:13 PM UTC 24 |
| Finished | Sep 18 04:52:30 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397738595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1397738595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.1159957931 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 308540356 ps |
| CPU time | 18.04 seconds |
| Started | Sep 18 04:52:10 PM UTC 24 |
| Finished | Sep 18 04:52:30 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159957931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.1159957931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.2145104992 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 19731168888 ps |
| CPU time | 28.7 seconds |
| Started | Sep 18 04:52:10 PM UTC 24 |
| Finished | Sep 18 04:52:40 PM UTC 24 |
| Peak memory | 254096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145104992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.2145104992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.3378214768 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 519551161 ps |
| CPU time | 6.88 seconds |
| Started | Sep 18 04:52:07 PM UTC 24 |
| Finished | Sep 18 04:52:15 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378214768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.3378214768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.2609297067 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 462862653 ps |
| CPU time | 8.39 seconds |
| Started | Sep 18 04:52:13 PM UTC 24 |
| Finished | Sep 18 04:52:23 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609297067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.2609297067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.707600570 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 6598834998 ps |
| CPU time | 16.27 seconds |
| Started | Sep 18 04:52:13 PM UTC 24 |
| Finished | Sep 18 04:52:31 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707600570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.707600570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.4017194213 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 332343773 ps |
| CPU time | 9.01 seconds |
| Started | Sep 18 04:52:10 PM UTC 24 |
| Finished | Sep 18 04:52:20 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017194213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.4017194213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.4095446138 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 309510274 ps |
| CPU time | 6.49 seconds |
| Started | Sep 18 04:52:07 PM UTC 24 |
| Finished | Sep 18 04:52:14 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095446138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.4095446138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.3579601388 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 324912485 ps |
| CPU time | 8.86 seconds |
| Started | Sep 18 04:52:13 PM UTC 24 |
| Finished | Sep 18 04:52:23 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579601388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.3579601388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.917492030 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 5513145367 ps |
| CPU time | 12.4 seconds |
| Started | Sep 18 04:52:07 PM UTC 24 |
| Finished | Sep 18 04:52:20 PM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917492030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.917492030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.1506524656 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 10696282090 ps |
| CPU time | 68.23 seconds |
| Started | Sep 18 04:52:16 PM UTC 24 |
| Finished | Sep 18 04:53:27 PM UTC 24 |
| Peak memory | 255988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506524656 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.1506524656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.421738439 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2843708185 ps |
| CPU time | 32.17 seconds |
| Started | Sep 18 04:52:13 PM UTC 24 |
| Finished | Sep 18 04:52:47 PM UTC 24 |
| Peak memory | 252052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421738439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.421738439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.2210842628 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 227567490 ps |
| CPU time | 2.88 seconds |
| Started | Sep 18 04:52:27 PM UTC 24 |
| Finished | Sep 18 04:52:31 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210842628 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2210842628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.1037857514 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1644906328 ps |
| CPU time | 36.42 seconds |
| Started | Sep 18 04:52:22 PM UTC 24 |
| Finished | Sep 18 04:53:00 PM UTC 24 |
| Peak memory | 253964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037857514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.1037857514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.2367123246 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 652427191 ps |
| CPU time | 19.39 seconds |
| Started | Sep 18 04:52:22 PM UTC 24 |
| Finished | Sep 18 04:52:42 PM UTC 24 |
| Peak memory | 252216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367123246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.2367123246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.4173266202 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 308022580 ps |
| CPU time | 11.1 seconds |
| Started | Sep 18 04:52:20 PM UTC 24 |
| Finished | Sep 18 04:52:33 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173266202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.4173266202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.225147408 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 182150074 ps |
| CPU time | 4.55 seconds |
| Started | Sep 18 04:52:18 PM UTC 24 |
| Finished | Sep 18 04:52:24 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225147408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.225147408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.3058465753 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 849286050 ps |
| CPU time | 9.82 seconds |
| Started | Sep 18 04:52:22 PM UTC 24 |
| Finished | Sep 18 04:52:33 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058465753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3058465753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.2992612618 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 669035535 ps |
| CPU time | 11.11 seconds |
| Started | Sep 18 04:52:23 PM UTC 24 |
| Finished | Sep 18 04:52:35 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992612618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.2992612618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.2237568968 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 179638982 ps |
| CPU time | 6.3 seconds |
| Started | Sep 18 04:52:18 PM UTC 24 |
| Finished | Sep 18 04:52:26 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237568968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.2237568968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.3457184782 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 756376395 ps |
| CPU time | 17.67 seconds |
| Started | Sep 18 04:52:18 PM UTC 24 |
| Finished | Sep 18 04:52:38 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457184782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.3457184782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.3164845562 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 328447556 ps |
| CPU time | 12.05 seconds |
| Started | Sep 18 04:52:23 PM UTC 24 |
| Finished | Sep 18 04:52:36 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164845562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.3164845562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.428112693 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 701006469 ps |
| CPU time | 8.15 seconds |
| Started | Sep 18 04:52:17 PM UTC 24 |
| Finished | Sep 18 04:52:26 PM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428112693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.428112693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.863797443 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 3260743744 ps |
| CPU time | 11.11 seconds |
| Started | Sep 18 04:52:26 PM UTC 24 |
| Finished | Sep 18 04:52:38 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863797443 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.863797443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.3126874348 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 758851016 ps |
| CPU time | 15.86 seconds |
| Started | Sep 18 04:52:24 PM UTC 24 |
| Finished | Sep 18 04:52:41 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126874348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.3126874348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.1865792138 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 66829560 ps |
| CPU time | 3 seconds |
| Started | Sep 18 04:52:36 PM UTC 24 |
| Finished | Sep 18 04:52:40 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865792138 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.1865792138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.2667320373 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 701683857 ps |
| CPU time | 13.77 seconds |
| Started | Sep 18 04:52:34 PM UTC 24 |
| Finished | Sep 18 04:52:48 PM UTC 24 |
| Peak memory | 252076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667320373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.2667320373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.3664335008 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1891848251 ps |
| CPU time | 30.88 seconds |
| Started | Sep 18 04:52:33 PM UTC 24 |
| Finished | Sep 18 04:53:06 PM UTC 24 |
| Peak memory | 255836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664335008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.3664335008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.1593327405 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1692198796 ps |
| CPU time | 22.64 seconds |
| Started | Sep 18 04:52:31 PM UTC 24 |
| Finished | Sep 18 04:52:55 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593327405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.1593327405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.3262974577 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 174696982 ps |
| CPU time | 5.25 seconds |
| Started | Sep 18 04:52:27 PM UTC 24 |
| Finished | Sep 18 04:52:34 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262974577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3262974577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.2550373452 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 590095093 ps |
| CPU time | 17.05 seconds |
| Started | Sep 18 04:52:34 PM UTC 24 |
| Finished | Sep 18 04:52:52 PM UTC 24 |
| Peak memory | 252152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550373452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.2550373452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.3695786690 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 4901563086 ps |
| CPU time | 37.45 seconds |
| Started | Sep 18 04:52:34 PM UTC 24 |
| Finished | Sep 18 04:53:13 PM UTC 24 |
| Peak memory | 252008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695786690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.3695786690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.992607242 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1209910110 ps |
| CPU time | 20.99 seconds |
| Started | Sep 18 04:52:31 PM UTC 24 |
| Finished | Sep 18 04:52:53 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992607242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.992607242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.3392810350 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 809438026 ps |
| CPU time | 12.42 seconds |
| Started | Sep 18 04:52:31 PM UTC 24 |
| Finished | Sep 18 04:52:44 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392810350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.3392810350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.1232094108 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 407610861 ps |
| CPU time | 8.38 seconds |
| Started | Sep 18 04:52:34 PM UTC 24 |
| Finished | Sep 18 04:52:43 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232094108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.1232094108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.930053669 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 5105125610 ps |
| CPU time | 9.78 seconds |
| Started | Sep 18 04:52:27 PM UTC 24 |
| Finished | Sep 18 04:52:38 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930053669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.930053669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.4057683994 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 76554139852 ps |
| CPU time | 94.63 seconds |
| Started | Sep 18 04:52:34 PM UTC 24 |
| Finished | Sep 18 04:54:11 PM UTC 24 |
| Peak memory | 258036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057683994 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.4057683994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.528886278 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 20906608253 ps |
| CPU time | 47.01 seconds |
| Started | Sep 18 04:52:34 PM UTC 24 |
| Finished | Sep 18 04:53:22 PM UTC 24 |
| Peak memory | 254108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528886278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.528886278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.3295803670 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 264391042 ps |
| CPU time | 1.91 seconds |
| Started | Sep 18 04:52:45 PM UTC 24 |
| Finished | Sep 18 04:52:48 PM UTC 24 |
| Peak memory | 250576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295803670 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.3295803670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.1506188485 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 760821934 ps |
| CPU time | 17.91 seconds |
| Started | Sep 18 04:52:44 PM UTC 24 |
| Finished | Sep 18 04:53:03 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506188485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.1506188485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.682341496 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 471001187 ps |
| CPU time | 16.7 seconds |
| Started | Sep 18 04:52:44 PM UTC 24 |
| Finished | Sep 18 04:53:02 PM UTC 24 |
| Peak memory | 252160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682341496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.682341496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.2052817159 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 171439576 ps |
| CPU time | 5.6 seconds |
| Started | Sep 18 04:52:38 PM UTC 24 |
| Finished | Sep 18 04:52:45 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052817159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2052817159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.462417517 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1024390897 ps |
| CPU time | 7.79 seconds |
| Started | Sep 18 04:52:44 PM UTC 24 |
| Finished | Sep 18 04:52:53 PM UTC 24 |
| Peak memory | 253968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462417517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.462417517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.1764987955 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 5900117144 ps |
| CPU time | 12.47 seconds |
| Started | Sep 18 04:52:44 PM UTC 24 |
| Finished | Sep 18 04:52:58 PM UTC 24 |
| Peak memory | 258084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764987955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.1764987955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.2168000245 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1492512620 ps |
| CPU time | 4.11 seconds |
| Started | Sep 18 04:52:38 PM UTC 24 |
| Finished | Sep 18 04:52:43 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168000245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.2168000245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.1627375448 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1255906872 ps |
| CPU time | 14.18 seconds |
| Started | Sep 18 04:52:38 PM UTC 24 |
| Finished | Sep 18 04:52:53 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627375448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.1627375448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.960544764 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 3999489475 ps |
| CPU time | 12.78 seconds |
| Started | Sep 18 04:52:44 PM UTC 24 |
| Finished | Sep 18 04:52:58 PM UTC 24 |
| Peak memory | 252044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960544764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.960544764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.1098835410 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 382181049 ps |
| CPU time | 5 seconds |
| Started | Sep 18 04:52:36 PM UTC 24 |
| Finished | Sep 18 04:52:42 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098835410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.1098835410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.4094043662 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 10014453156 ps |
| CPU time | 88.73 seconds |
| Started | Sep 18 04:52:45 PM UTC 24 |
| Finished | Sep 18 04:54:15 PM UTC 24 |
| Peak memory | 258036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094043662 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.4094043662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.1457739200 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2539076408 ps |
| CPU time | 49.05 seconds |
| Started | Sep 18 04:52:45 PM UTC 24 |
| Finished | Sep 18 04:53:35 PM UTC 24 |
| Peak memory | 258096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1457739200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.otp_ctrl_stress_all_with_rand_reset.1457739200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.711509842 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 9728877270 ps |
| CPU time | 24.25 seconds |
| Started | Sep 18 04:52:45 PM UTC 24 |
| Finished | Sep 18 04:53:10 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711509842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.711509842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.3143560239 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 102967658 ps |
| CPU time | 2.35 seconds |
| Started | Sep 18 04:52:56 PM UTC 24 |
| Finished | Sep 18 04:52:59 PM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143560239 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.3143560239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.3960470715 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 584469253 ps |
| CPU time | 23.35 seconds |
| Started | Sep 18 04:52:48 PM UTC 24 |
| Finished | Sep 18 04:53:14 PM UTC 24 |
| Peak memory | 254072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960470715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3960470715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.3391461357 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 784233901 ps |
| CPU time | 23.04 seconds |
| Started | Sep 18 04:52:48 PM UTC 24 |
| Finished | Sep 18 04:53:13 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391461357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.3391461357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.3593058168 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 375899036 ps |
| CPU time | 10.17 seconds |
| Started | Sep 18 04:52:48 PM UTC 24 |
| Finished | Sep 18 04:53:00 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593058168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.3593058168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.893533202 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 133622249 ps |
| CPU time | 4.34 seconds |
| Started | Sep 18 04:52:48 PM UTC 24 |
| Finished | Sep 18 04:52:54 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893533202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.893533202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.3712242823 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 750382423 ps |
| CPU time | 17.07 seconds |
| Started | Sep 18 04:52:48 PM UTC 24 |
| Finished | Sep 18 04:53:07 PM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712242823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3712242823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.3875536101 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 2578229114 ps |
| CPU time | 34.83 seconds |
| Started | Sep 18 04:52:48 PM UTC 24 |
| Finished | Sep 18 04:53:25 PM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875536101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.3875536101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.898441876 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 638512338 ps |
| CPU time | 8 seconds |
| Started | Sep 18 04:52:48 PM UTC 24 |
| Finished | Sep 18 04:52:58 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898441876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.898441876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.613445635 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2438558325 ps |
| CPU time | 23.35 seconds |
| Started | Sep 18 04:52:48 PM UTC 24 |
| Finished | Sep 18 04:53:14 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613445635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.613445635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.3697835310 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 106746501 ps |
| CPU time | 5.88 seconds |
| Started | Sep 18 04:52:48 PM UTC 24 |
| Finished | Sep 18 04:52:56 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697835310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3697835310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.974739519 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 5267149838 ps |
| CPU time | 15 seconds |
| Started | Sep 18 04:52:48 PM UTC 24 |
| Finished | Sep 18 04:53:05 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974739519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.974739519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.3929656502 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 18252841441 ps |
| CPU time | 71.86 seconds |
| Started | Sep 18 04:52:50 PM UTC 24 |
| Finished | Sep 18 04:54:04 PM UTC 24 |
| Peak memory | 256084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929656502 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.3929656502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.1162316556 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2596744921 ps |
| CPU time | 57.31 seconds |
| Started | Sep 18 04:52:50 PM UTC 24 |
| Finished | Sep 18 04:53:49 PM UTC 24 |
| Peak memory | 258160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1162316556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.otp_ctrl_stress_all_with_rand_reset.1162316556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.448592556 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 580493334 ps |
| CPU time | 23.18 seconds |
| Started | Sep 18 04:52:50 PM UTC 24 |
| Finished | Sep 18 04:53:14 PM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448592556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.448592556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.3282451353 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 58646340 ps |
| CPU time | 1.94 seconds |
| Started | Sep 18 04:53:01 PM UTC 24 |
| Finished | Sep 18 04:53:04 PM UTC 24 |
| Peak memory | 250764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282451353 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.3282451353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.2076025479 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 7742476038 ps |
| CPU time | 32.35 seconds |
| Started | Sep 18 04:52:57 PM UTC 24 |
| Finished | Sep 18 04:53:31 PM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076025479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.2076025479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.3887518589 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 974471555 ps |
| CPU time | 27.05 seconds |
| Started | Sep 18 04:52:56 PM UTC 24 |
| Finished | Sep 18 04:53:24 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887518589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.3887518589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.1541737003 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 1258639755 ps |
| CPU time | 20.21 seconds |
| Started | Sep 18 04:52:56 PM UTC 24 |
| Finished | Sep 18 04:53:17 PM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541737003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.1541737003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.2547926398 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 418382957 ps |
| CPU time | 4.68 seconds |
| Started | Sep 18 04:52:56 PM UTC 24 |
| Finished | Sep 18 04:53:01 PM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547926398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.2547926398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.762758335 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 1089267900 ps |
| CPU time | 13.01 seconds |
| Started | Sep 18 04:53:00 PM UTC 24 |
| Finished | Sep 18 04:53:14 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762758335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.762758335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.2618441099 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 541042942 ps |
| CPU time | 18.46 seconds |
| Started | Sep 18 04:53:00 PM UTC 24 |
| Finished | Sep 18 04:53:19 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618441099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.2618441099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.1271617298 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2817565264 ps |
| CPU time | 26.52 seconds |
| Started | Sep 18 04:52:56 PM UTC 24 |
| Finished | Sep 18 04:53:23 PM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271617298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.1271617298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.3843887887 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 301955650 ps |
| CPU time | 5.94 seconds |
| Started | Sep 18 04:52:56 PM UTC 24 |
| Finished | Sep 18 04:53:03 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843887887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.3843887887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.258208501 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2596153664 ps |
| CPU time | 9.27 seconds |
| Started | Sep 18 04:53:00 PM UTC 24 |
| Finished | Sep 18 04:53:10 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258208501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.258208501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.2974155380 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 162518394 ps |
| CPU time | 3.82 seconds |
| Started | Sep 18 04:52:56 PM UTC 24 |
| Finished | Sep 18 04:53:00 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974155380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.2974155380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.647138865 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 19780933598 ps |
| CPU time | 53.34 seconds |
| Started | Sep 18 04:53:01 PM UTC 24 |
| Finished | Sep 18 04:53:56 PM UTC 24 |
| Peak memory | 253884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647138865 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.647138865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.3361175089 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 1945323918 ps |
| CPU time | 55.2 seconds |
| Started | Sep 18 04:53:01 PM UTC 24 |
| Finished | Sep 18 04:53:58 PM UTC 24 |
| Peak memory | 258244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3361175089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.otp_ctrl_stress_all_with_rand_reset.3361175089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.1105771006 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 745672879 ps |
| CPU time | 30.09 seconds |
| Started | Sep 18 04:53:00 PM UTC 24 |
| Finished | Sep 18 04:53:31 PM UTC 24 |
| Peak memory | 252088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105771006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.1105771006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.1824362869 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 93444575 ps |
| CPU time | 2.72 seconds |
| Started | Sep 18 04:45:14 PM UTC 24 |
| Finished | Sep 18 04:45:18 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824362869 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.1824362869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.3497713778 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2284478568 ps |
| CPU time | 32.08 seconds |
| Started | Sep 18 04:44:42 PM UTC 24 |
| Finished | Sep 18 04:45:15 PM UTC 24 |
| Peak memory | 251972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497713778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.3497713778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.4191446171 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 5378825113 ps |
| CPU time | 41.46 seconds |
| Started | Sep 18 04:44:54 PM UTC 24 |
| Finished | Sep 18 04:45:37 PM UTC 24 |
| Peak memory | 256240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191446171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.4191446171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.3099537857 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 640123782 ps |
| CPU time | 21.6 seconds |
| Started | Sep 18 04:44:52 PM UTC 24 |
| Finished | Sep 18 04:45:15 PM UTC 24 |
| Peak memory | 252068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099537857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.3099537857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.1665573031 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2154737303 ps |
| CPU time | 10.38 seconds |
| Started | Sep 18 04:44:40 PM UTC 24 |
| Finished | Sep 18 04:44:51 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665573031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.1665573031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.1558001651 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 938976050 ps |
| CPU time | 26.58 seconds |
| Started | Sep 18 04:44:56 PM UTC 24 |
| Finished | Sep 18 04:45:24 PM UTC 24 |
| Peak memory | 254000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558001651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.1558001651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.3431539767 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1935227350 ps |
| CPU time | 7.13 seconds |
| Started | Sep 18 04:44:56 PM UTC 24 |
| Finished | Sep 18 04:45:05 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431539767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3431539767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.4218545580 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 913032150 ps |
| CPU time | 15.36 seconds |
| Started | Sep 18 04:44:47 PM UTC 24 |
| Finished | Sep 18 04:45:03 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218545580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.4218545580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.4136057290 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 11928915459 ps |
| CPU time | 247.72 seconds |
| Started | Sep 18 04:45:10 PM UTC 24 |
| Finished | Sep 18 04:49:21 PM UTC 24 |
| Peak memory | 298748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136057290 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.4136057290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.839717621 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 7433473940 ps |
| CPU time | 37.85 seconds |
| Started | Sep 18 04:44:40 PM UTC 24 |
| Finished | Sep 18 04:45:19 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839717621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.839717621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.137770891 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 227488842 ps |
| CPU time | 4.75 seconds |
| Started | Sep 18 04:45:06 PM UTC 24 |
| Finished | Sep 18 04:45:12 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137770891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.137770891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.3129264562 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 904504983 ps |
| CPU time | 4.22 seconds |
| Started | Sep 18 04:53:12 PM UTC 24 |
| Finished | Sep 18 04:53:17 PM UTC 24 |
| Peak memory | 251140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129264562 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.3129264562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.651549986 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 10745786463 ps |
| CPU time | 92.32 seconds |
| Started | Sep 18 04:53:06 PM UTC 24 |
| Finished | Sep 18 04:54:40 PM UTC 24 |
| Peak memory | 256080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651549986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.651549986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.3173040710 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 938341352 ps |
| CPU time | 18.54 seconds |
| Started | Sep 18 04:53:05 PM UTC 24 |
| Finished | Sep 18 04:53:24 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173040710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.3173040710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.2954549384 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 317568614 ps |
| CPU time | 6.14 seconds |
| Started | Sep 18 04:53:05 PM UTC 24 |
| Finished | Sep 18 04:53:12 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954549384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.2954549384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.4121613929 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 272566308 ps |
| CPU time | 5.15 seconds |
| Started | Sep 18 04:53:04 PM UTC 24 |
| Finished | Sep 18 04:53:11 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121613929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.4121613929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.1161089783 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 31984792279 ps |
| CPU time | 62.75 seconds |
| Started | Sep 18 04:53:06 PM UTC 24 |
| Finished | Sep 18 04:54:11 PM UTC 24 |
| Peak memory | 268444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161089783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.1161089783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.3087848373 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 5949776352 ps |
| CPU time | 35.48 seconds |
| Started | Sep 18 04:53:08 PM UTC 24 |
| Finished | Sep 18 04:53:45 PM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087848373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.3087848373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.1445485811 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 310584541 ps |
| CPU time | 4.39 seconds |
| Started | Sep 18 04:53:04 PM UTC 24 |
| Finished | Sep 18 04:53:10 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445485811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.1445485811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.1403984073 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 707643613 ps |
| CPU time | 17.74 seconds |
| Started | Sep 18 04:53:04 PM UTC 24 |
| Finished | Sep 18 04:53:24 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403984073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.1403984073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.3753750430 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 178052455 ps |
| CPU time | 7.02 seconds |
| Started | Sep 18 04:53:08 PM UTC 24 |
| Finished | Sep 18 04:53:16 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753750430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3753750430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.2862630647 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 584329324 ps |
| CPU time | 8.86 seconds |
| Started | Sep 18 04:53:04 PM UTC 24 |
| Finished | Sep 18 04:53:15 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862630647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.2862630647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.1850177652 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 21888285404 ps |
| CPU time | 210.92 seconds |
| Started | Sep 18 04:53:12 PM UTC 24 |
| Finished | Sep 18 04:56:46 PM UTC 24 |
| Peak memory | 290896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850177652 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.1850177652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.4264048342 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 2252908473 ps |
| CPU time | 75.48 seconds |
| Started | Sep 18 04:53:12 PM UTC 24 |
| Finished | Sep 18 04:54:29 PM UTC 24 |
| Peak memory | 268536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4264048342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.otp_ctrl_stress_all_with_rand_reset.4264048342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.3197581335 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 4060260162 ps |
| CPU time | 18.24 seconds |
| Started | Sep 18 04:53:09 PM UTC 24 |
| Finished | Sep 18 04:53:29 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197581335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.3197581335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.3660246209 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 71853123 ps |
| CPU time | 3.06 seconds |
| Started | Sep 18 04:53:22 PM UTC 24 |
| Finished | Sep 18 04:53:26 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660246209 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.3660246209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.8522352 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 2061579457 ps |
| CPU time | 21.73 seconds |
| Started | Sep 18 04:53:19 PM UTC 24 |
| Finished | Sep 18 04:53:41 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8522352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.8522352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.2987286244 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 2012310263 ps |
| CPU time | 31.64 seconds |
| Started | Sep 18 04:53:18 PM UTC 24 |
| Finished | Sep 18 04:53:51 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987286244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.2987286244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.95725586 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 14859760577 ps |
| CPU time | 26.2 seconds |
| Started | Sep 18 04:53:18 PM UTC 24 |
| Finished | Sep 18 04:53:46 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95725586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.95725586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.745392986 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 396321746 ps |
| CPU time | 11.53 seconds |
| Started | Sep 18 04:53:19 PM UTC 24 |
| Finished | Sep 18 04:53:31 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745392986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.745392986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.921319537 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 8454111108 ps |
| CPU time | 27.48 seconds |
| Started | Sep 18 04:53:19 PM UTC 24 |
| Finished | Sep 18 04:53:47 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921319537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.921319537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.210816436 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 812760201 ps |
| CPU time | 12 seconds |
| Started | Sep 18 04:53:18 PM UTC 24 |
| Finished | Sep 18 04:53:32 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210816436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.210816436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.2655510736 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 631417535 ps |
| CPU time | 19.45 seconds |
| Started | Sep 18 04:53:15 PM UTC 24 |
| Finished | Sep 18 04:53:35 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655510736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.2655510736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.4096211433 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 1949095308 ps |
| CPU time | 8.83 seconds |
| Started | Sep 18 04:53:19 PM UTC 24 |
| Finished | Sep 18 04:53:29 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096211433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.4096211433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.2932705688 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 315858941 ps |
| CPU time | 8.11 seconds |
| Started | Sep 18 04:53:12 PM UTC 24 |
| Finished | Sep 18 04:53:21 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932705688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.2932705688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.1687999691 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 35022442193 ps |
| CPU time | 146.84 seconds |
| Started | Sep 18 04:53:19 PM UTC 24 |
| Finished | Sep 18 04:55:48 PM UTC 24 |
| Peak memory | 270324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687999691 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.1687999691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.3825394622 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 4273851068 ps |
| CPU time | 13.33 seconds |
| Started | Sep 18 04:53:19 PM UTC 24 |
| Finished | Sep 18 04:53:33 PM UTC 24 |
| Peak memory | 252112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825394622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.3825394622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.366516182 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 789206343 ps |
| CPU time | 3.25 seconds |
| Started | Sep 18 04:53:29 PM UTC 24 |
| Finished | Sep 18 04:53:34 PM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366516182 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.366516182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.3976613066 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 977468370 ps |
| CPU time | 22.23 seconds |
| Started | Sep 18 04:53:26 PM UTC 24 |
| Finished | Sep 18 04:53:49 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976613066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.3976613066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.1283717566 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 1615182759 ps |
| CPU time | 23.13 seconds |
| Started | Sep 18 04:53:26 PM UTC 24 |
| Finished | Sep 18 04:53:50 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283717566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.1283717566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.3976139112 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 539564330 ps |
| CPU time | 19.73 seconds |
| Started | Sep 18 04:53:26 PM UTC 24 |
| Finished | Sep 18 04:53:46 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976139112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3976139112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.749232634 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2685450702 ps |
| CPU time | 10.5 seconds |
| Started | Sep 18 04:53:25 PM UTC 24 |
| Finished | Sep 18 04:53:37 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749232634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.749232634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.3701833812 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 1458624681 ps |
| CPU time | 13.8 seconds |
| Started | Sep 18 04:53:29 PM UTC 24 |
| Finished | Sep 18 04:53:44 PM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701833812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.3701833812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.2281867886 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 173143430 ps |
| CPU time | 9.08 seconds |
| Started | Sep 18 04:53:29 PM UTC 24 |
| Finished | Sep 18 04:53:39 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281867886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.2281867886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.185530911 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 229963664 ps |
| CPU time | 5.48 seconds |
| Started | Sep 18 04:53:25 PM UTC 24 |
| Finished | Sep 18 04:53:32 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185530911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.185530911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.810423230 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 1741569051 ps |
| CPU time | 13.73 seconds |
| Started | Sep 18 04:53:25 PM UTC 24 |
| Finished | Sep 18 04:53:40 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810423230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.810423230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.1238357216 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1259695026 ps |
| CPU time | 10.53 seconds |
| Started | Sep 18 04:53:29 PM UTC 24 |
| Finished | Sep 18 04:53:41 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238357216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.1238357216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.1104978193 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 260763448 ps |
| CPU time | 13.94 seconds |
| Started | Sep 18 04:53:22 PM UTC 24 |
| Finished | Sep 18 04:53:37 PM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104978193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.1104978193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.3271773958 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 11355741535 ps |
| CPU time | 56.45 seconds |
| Started | Sep 18 04:53:29 PM UTC 24 |
| Finished | Sep 18 04:54:27 PM UTC 24 |
| Peak memory | 266308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271773958 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.3271773958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.490571588 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 9209310030 ps |
| CPU time | 116.19 seconds |
| Started | Sep 18 04:53:29 PM UTC 24 |
| Finished | Sep 18 04:55:28 PM UTC 24 |
| Peak memory | 258176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=490571588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.490571588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.4206668723 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 731342036 ps |
| CPU time | 13.18 seconds |
| Started | Sep 18 04:53:29 PM UTC 24 |
| Finished | Sep 18 04:53:44 PM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206668723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.4206668723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.2180894575 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 68709828 ps |
| CPU time | 2.68 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:53:47 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180894575 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.2180894575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.2972538072 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 5114709111 ps |
| CPU time | 74.23 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:54:59 PM UTC 24 |
| Peak memory | 256208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972538072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.2972538072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.1265349681 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 829757752 ps |
| CPU time | 15.57 seconds |
| Started | Sep 18 04:53:33 PM UTC 24 |
| Finished | Sep 18 04:53:50 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265349681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.1265349681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.1375337043 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 1215667536 ps |
| CPU time | 22.24 seconds |
| Started | Sep 18 04:53:33 PM UTC 24 |
| Finished | Sep 18 04:53:57 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375337043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.1375337043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.2163225660 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 342980282 ps |
| CPU time | 3.69 seconds |
| Started | Sep 18 04:53:33 PM UTC 24 |
| Finished | Sep 18 04:53:38 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163225660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.2163225660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.1617082489 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1239181741 ps |
| CPU time | 19.88 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:54:04 PM UTC 24 |
| Peak memory | 252008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617082489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.1617082489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.2289089542 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 434189207 ps |
| CPU time | 6.75 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:53:50 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289089542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.2289089542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.4154073767 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 4660276889 ps |
| CPU time | 8.59 seconds |
| Started | Sep 18 04:53:33 PM UTC 24 |
| Finished | Sep 18 04:53:43 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154073767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.4154073767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.3720398528 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1466976139 ps |
| CPU time | 13.1 seconds |
| Started | Sep 18 04:53:33 PM UTC 24 |
| Finished | Sep 18 04:53:48 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720398528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.3720398528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.455199296 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 397582970 ps |
| CPU time | 6.31 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:53:50 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455199296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.455199296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.53622254 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 396482563 ps |
| CPU time | 6.83 seconds |
| Started | Sep 18 04:53:29 PM UTC 24 |
| Finished | Sep 18 04:53:37 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53622254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.53622254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.667462826 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 680475156 ps |
| CPU time | 13.04 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:53:57 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667462826 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.667462826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.2744614876 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 7924386073 ps |
| CPU time | 80.33 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:55:05 PM UTC 24 |
| Peak memory | 258188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2744614876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 43.otp_ctrl_stress_all_with_rand_reset.2744614876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.2990484058 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 1438380779 ps |
| CPU time | 19.07 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:54:03 PM UTC 24 |
| Peak memory | 252032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990484058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.2990484058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.1107876597 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 123254662 ps |
| CPU time | 2.59 seconds |
| Started | Sep 18 04:53:47 PM UTC 24 |
| Finished | Sep 18 04:53:50 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107876597 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.1107876597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.2038052897 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 2244769409 ps |
| CPU time | 30.92 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:54:15 PM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038052897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.2038052897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.3398331535 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3050335575 ps |
| CPU time | 14.05 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:53:58 PM UTC 24 |
| Peak memory | 252056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398331535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.3398331535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.750826393 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 957479916 ps |
| CPU time | 23.35 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:54:08 PM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750826393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.750826393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.1854637531 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 644053307 ps |
| CPU time | 6.81 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:53:51 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854637531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.1854637531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.392544406 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 8700199104 ps |
| CPU time | 21.53 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:54:06 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392544406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.392544406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.2229035075 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 540638807 ps |
| CPU time | 14.48 seconds |
| Started | Sep 18 04:53:45 PM UTC 24 |
| Finished | Sep 18 04:54:00 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229035075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.2229035075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.2069504746 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 310896718 ps |
| CPU time | 4.55 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:53:49 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069504746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.2069504746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.253672636 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 151466796 ps |
| CPU time | 4.12 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:53:48 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253672636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.253672636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.2229639712 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 222720107 ps |
| CPU time | 8 seconds |
| Started | Sep 18 04:53:45 PM UTC 24 |
| Finished | Sep 18 04:53:54 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229639712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.2229639712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.2498464539 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 239630283 ps |
| CPU time | 6.11 seconds |
| Started | Sep 18 04:53:43 PM UTC 24 |
| Finished | Sep 18 04:53:50 PM UTC 24 |
| Peak memory | 252008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498464539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.2498464539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.761283564 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 9325256018 ps |
| CPU time | 132.72 seconds |
| Started | Sep 18 04:53:45 PM UTC 24 |
| Finished | Sep 18 04:56:00 PM UTC 24 |
| Peak memory | 274564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=761283564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.761283564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.1029902513 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1882692548 ps |
| CPU time | 33.78 seconds |
| Started | Sep 18 04:53:45 PM UTC 24 |
| Finished | Sep 18 04:54:20 PM UTC 24 |
| Peak memory | 253976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029902513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.1029902513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.714660249 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 104605140 ps |
| CPU time | 2.07 seconds |
| Started | Sep 18 04:53:56 PM UTC 24 |
| Finished | Sep 18 04:53:59 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714660249 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.714660249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.3963056746 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 1522933367 ps |
| CPU time | 33.91 seconds |
| Started | Sep 18 04:53:49 PM UTC 24 |
| Finished | Sep 18 04:54:25 PM UTC 24 |
| Peak memory | 254232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963056746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.3963056746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.310547970 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 660001168 ps |
| CPU time | 17.83 seconds |
| Started | Sep 18 04:53:49 PM UTC 24 |
| Finished | Sep 18 04:54:08 PM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310547970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.310547970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.113384619 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1335492574 ps |
| CPU time | 27.21 seconds |
| Started | Sep 18 04:53:49 PM UTC 24 |
| Finished | Sep 18 04:54:18 PM UTC 24 |
| Peak memory | 251972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113384619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.113384619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.4063585807 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 480034408 ps |
| CPU time | 3.73 seconds |
| Started | Sep 18 04:53:49 PM UTC 24 |
| Finished | Sep 18 04:53:54 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063585807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.4063585807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.1868279227 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 13564755208 ps |
| CPU time | 28.78 seconds |
| Started | Sep 18 04:53:56 PM UTC 24 |
| Finished | Sep 18 04:54:26 PM UTC 24 |
| Peak memory | 258156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868279227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.1868279227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.3785086864 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 6368657212 ps |
| CPU time | 15.07 seconds |
| Started | Sep 18 04:53:56 PM UTC 24 |
| Finished | Sep 18 04:54:12 PM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785086864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.3785086864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.833872786 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 170214226 ps |
| CPU time | 7.74 seconds |
| Started | Sep 18 04:53:49 PM UTC 24 |
| Finished | Sep 18 04:53:58 PM UTC 24 |
| Peak memory | 252032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833872786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.833872786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.1209917478 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 897839356 ps |
| CPU time | 9.83 seconds |
| Started | Sep 18 04:53:49 PM UTC 24 |
| Finished | Sep 18 04:54:00 PM UTC 24 |
| Peak memory | 251672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209917478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.1209917478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.1196503539 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 210521430 ps |
| CPU time | 6.1 seconds |
| Started | Sep 18 04:53:56 PM UTC 24 |
| Finished | Sep 18 04:54:03 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196503539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.1196503539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.3874115327 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 780997333 ps |
| CPU time | 8.36 seconds |
| Started | Sep 18 04:53:47 PM UTC 24 |
| Finished | Sep 18 04:53:56 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874115327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3874115327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.1262197456 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1783794870 ps |
| CPU time | 37.58 seconds |
| Started | Sep 18 04:53:56 PM UTC 24 |
| Finished | Sep 18 04:54:35 PM UTC 24 |
| Peak memory | 270336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262197456 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.1262197456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.4199819583 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 5829978338 ps |
| CPU time | 93.84 seconds |
| Started | Sep 18 04:53:56 PM UTC 24 |
| Finished | Sep 18 04:55:32 PM UTC 24 |
| Peak memory | 258048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4199819583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.otp_ctrl_stress_all_with_rand_reset.4199819583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.1895565876 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 11687643648 ps |
| CPU time | 57.12 seconds |
| Started | Sep 18 04:53:56 PM UTC 24 |
| Finished | Sep 18 04:54:55 PM UTC 24 |
| Peak memory | 253964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895565876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.1895565876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.894102753 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 93171915 ps |
| CPU time | 2.65 seconds |
| Started | Sep 18 04:54:00 PM UTC 24 |
| Finished | Sep 18 04:54:04 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894102753 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.894102753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.3621044316 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 7938448063 ps |
| CPU time | 39.82 seconds |
| Started | Sep 18 04:53:58 PM UTC 24 |
| Finished | Sep 18 04:54:39 PM UTC 24 |
| Peak memory | 256100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621044316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.3621044316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.1695913329 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 5835973398 ps |
| CPU time | 13.06 seconds |
| Started | Sep 18 04:53:56 PM UTC 24 |
| Finished | Sep 18 04:54:11 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695913329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.1695913329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.3764210240 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 2313233046 ps |
| CPU time | 33.65 seconds |
| Started | Sep 18 04:53:56 PM UTC 24 |
| Finished | Sep 18 04:54:31 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764210240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.3764210240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.2474472876 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 262421679 ps |
| CPU time | 4.2 seconds |
| Started | Sep 18 04:53:56 PM UTC 24 |
| Finished | Sep 18 04:54:01 PM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474472876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2474472876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.3914778655 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1078983900 ps |
| CPU time | 18.33 seconds |
| Started | Sep 18 04:53:58 PM UTC 24 |
| Finished | Sep 18 04:54:18 PM UTC 24 |
| Peak memory | 254064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914778655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.3914778655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.1108907977 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 1348602355 ps |
| CPU time | 25.48 seconds |
| Started | Sep 18 04:53:58 PM UTC 24 |
| Finished | Sep 18 04:54:25 PM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108907977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1108907977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.1777746662 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 102879390 ps |
| CPU time | 4.24 seconds |
| Started | Sep 18 04:53:56 PM UTC 24 |
| Finished | Sep 18 04:54:02 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777746662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1777746662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.3896931409 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 606526852 ps |
| CPU time | 12.05 seconds |
| Started | Sep 18 04:53:56 PM UTC 24 |
| Finished | Sep 18 04:54:09 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896931409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3896931409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.2688956681 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 1059762161 ps |
| CPU time | 10.56 seconds |
| Started | Sep 18 04:53:58 PM UTC 24 |
| Finished | Sep 18 04:54:10 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688956681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2688956681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.3851569078 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1418851825 ps |
| CPU time | 10.5 seconds |
| Started | Sep 18 04:53:56 PM UTC 24 |
| Finished | Sep 18 04:54:08 PM UTC 24 |
| Peak memory | 252068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851569078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3851569078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.2754237072 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 11072799986 ps |
| CPU time | 82.6 seconds |
| Started | Sep 18 04:54:00 PM UTC 24 |
| Finished | Sep 18 04:55:25 PM UTC 24 |
| Peak memory | 268432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754237072 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.2754237072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.1003199590 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 5307086801 ps |
| CPU time | 72.31 seconds |
| Started | Sep 18 04:54:00 PM UTC 24 |
| Finished | Sep 18 04:55:14 PM UTC 24 |
| Peak memory | 258188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1003199590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.otp_ctrl_stress_all_with_rand_reset.1003199590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.2577447256 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 226349449 ps |
| CPU time | 9.9 seconds |
| Started | Sep 18 04:54:00 PM UTC 24 |
| Finished | Sep 18 04:54:11 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577447256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.2577447256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.3440104403 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 98568950 ps |
| CPU time | 3.57 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:54:19 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440104403 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.3440104403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.2680607205 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 209828180 ps |
| CPU time | 5.97 seconds |
| Started | Sep 18 04:54:04 PM UTC 24 |
| Finished | Sep 18 04:54:11 PM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680607205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.2680607205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.2171110778 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4649827239 ps |
| CPU time | 19.55 seconds |
| Started | Sep 18 04:54:04 PM UTC 24 |
| Finished | Sep 18 04:54:25 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171110778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.2171110778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.1856585472 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 3523512760 ps |
| CPU time | 43.56 seconds |
| Started | Sep 18 04:54:03 PM UTC 24 |
| Finished | Sep 18 04:54:48 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856585472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.1856585472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.2929294370 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 506427723 ps |
| CPU time | 5.25 seconds |
| Started | Sep 18 04:54:01 PM UTC 24 |
| Finished | Sep 18 04:54:08 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929294370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.2929294370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.1489112622 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 1612255285 ps |
| CPU time | 16.02 seconds |
| Started | Sep 18 04:54:04 PM UTC 24 |
| Finished | Sep 18 04:54:22 PM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489112622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.1489112622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.2567965406 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 145302910 ps |
| CPU time | 7.12 seconds |
| Started | Sep 18 04:54:06 PM UTC 24 |
| Finished | Sep 18 04:54:14 PM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567965406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2567965406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.1515177200 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 694251377 ps |
| CPU time | 7.66 seconds |
| Started | Sep 18 04:54:03 PM UTC 24 |
| Finished | Sep 18 04:54:12 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515177200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.1515177200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.328157281 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 906949966 ps |
| CPU time | 24.27 seconds |
| Started | Sep 18 04:54:02 PM UTC 24 |
| Finished | Sep 18 04:54:27 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328157281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.328157281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.2630013940 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 449367933 ps |
| CPU time | 10.02 seconds |
| Started | Sep 18 04:54:06 PM UTC 24 |
| Finished | Sep 18 04:54:17 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630013940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.2630013940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.2973766954 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 945514875 ps |
| CPU time | 6.49 seconds |
| Started | Sep 18 04:54:01 PM UTC 24 |
| Finished | Sep 18 04:54:09 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973766954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.2973766954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.2105543279 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 12372703601 ps |
| CPU time | 115.91 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:56:13 PM UTC 24 |
| Peak memory | 268288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105543279 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.2105543279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.1011138136 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 441297336 ps |
| CPU time | 15.74 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:54:31 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011138136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.1011138136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.1666037336 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 121700938 ps |
| CPU time | 2.75 seconds |
| Started | Sep 18 04:54:20 PM UTC 24 |
| Finished | Sep 18 04:54:24 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666037336 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.1666037336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.801499844 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1536718312 ps |
| CPU time | 25.47 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:54:42 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801499844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.801499844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.1105695158 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1425947085 ps |
| CPU time | 32.74 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:54:49 PM UTC 24 |
| Peak memory | 256024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105695158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.1105695158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.493400298 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 24818478933 ps |
| CPU time | 62.69 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:55:19 PM UTC 24 |
| Peak memory | 254132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493400298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.493400298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.2415710613 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 206127883 ps |
| CPU time | 4.91 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:54:21 PM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415710613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2415710613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.1457292318 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1121342693 ps |
| CPU time | 14.76 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:54:31 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457292318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.1457292318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.1158379310 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2339395482 ps |
| CPU time | 17.99 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:54:34 PM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158379310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.1158379310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.2465666701 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 587186434 ps |
| CPU time | 3.79 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:54:19 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465666701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2465666701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.4226429203 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 236298056 ps |
| CPU time | 7.34 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:54:23 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226429203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.4226429203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.2012600858 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 143188844 ps |
| CPU time | 4.54 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:54:21 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012600858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.2012600858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.1882303997 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 9013086315 ps |
| CPU time | 16.09 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:54:32 PM UTC 24 |
| Peak memory | 252128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882303997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.1882303997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.2282177263 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 20083493064 ps |
| CPU time | 203.73 seconds |
| Started | Sep 18 04:54:20 PM UTC 24 |
| Finished | Sep 18 04:57:48 PM UTC 24 |
| Peak memory | 278608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282177263 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.2282177263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3938209436 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1742767862 ps |
| CPU time | 63.57 seconds |
| Started | Sep 18 04:54:15 PM UTC 24 |
| Finished | Sep 18 04:55:20 PM UTC 24 |
| Peak memory | 258320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3938209436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.otp_ctrl_stress_all_with_rand_reset.3938209436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.1628463985 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 12708241806 ps |
| CPU time | 31.98 seconds |
| Started | Sep 18 04:54:14 PM UTC 24 |
| Finished | Sep 18 04:54:48 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628463985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1628463985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.253375162 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 117696331 ps |
| CPU time | 2.39 seconds |
| Started | Sep 18 04:54:28 PM UTC 24 |
| Finished | Sep 18 04:54:32 PM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253375162 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.253375162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.676891255 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 9841399434 ps |
| CPU time | 21.14 seconds |
| Started | Sep 18 04:54:20 PM UTC 24 |
| Finished | Sep 18 04:54:43 PM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676891255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.676891255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.1052053700 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 304423472 ps |
| CPU time | 10.89 seconds |
| Started | Sep 18 04:54:20 PM UTC 24 |
| Finished | Sep 18 04:54:33 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052053700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.1052053700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.1145966491 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 11610195700 ps |
| CPU time | 28.13 seconds |
| Started | Sep 18 04:54:20 PM UTC 24 |
| Finished | Sep 18 04:54:50 PM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145966491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.1145966491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.2184150852 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 351899499 ps |
| CPU time | 6.22 seconds |
| Started | Sep 18 04:54:20 PM UTC 24 |
| Finished | Sep 18 04:54:28 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184150852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.2184150852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.1564497592 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 625616461 ps |
| CPU time | 17.47 seconds |
| Started | Sep 18 04:54:23 PM UTC 24 |
| Finished | Sep 18 04:54:41 PM UTC 24 |
| Peak memory | 254076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564497592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.1564497592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.3587085931 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3693334095 ps |
| CPU time | 12.08 seconds |
| Started | Sep 18 04:54:23 PM UTC 24 |
| Finished | Sep 18 04:54:36 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587085931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.3587085931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.1733434329 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 84598879 ps |
| CPU time | 3.06 seconds |
| Started | Sep 18 04:54:20 PM UTC 24 |
| Finished | Sep 18 04:54:25 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733434329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.1733434329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.4064525766 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 11986244850 ps |
| CPU time | 23.56 seconds |
| Started | Sep 18 04:54:20 PM UTC 24 |
| Finished | Sep 18 04:54:45 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064525766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.4064525766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.1591442078 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 307229132 ps |
| CPU time | 5.23 seconds |
| Started | Sep 18 04:54:23 PM UTC 24 |
| Finished | Sep 18 04:54:29 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591442078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.1591442078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.3261272581 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 478260772 ps |
| CPU time | 5.87 seconds |
| Started | Sep 18 04:54:20 PM UTC 24 |
| Finished | Sep 18 04:54:27 PM UTC 24 |
| Peak memory | 251736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261272581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.3261272581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.26138965 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 10666299627 ps |
| CPU time | 77.73 seconds |
| Started | Sep 18 04:54:28 PM UTC 24 |
| Finished | Sep 18 04:55:48 PM UTC 24 |
| Peak memory | 255940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26138965 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.26138965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.1801769052 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 228226665 ps |
| CPU time | 5.13 seconds |
| Started | Sep 18 04:54:23 PM UTC 24 |
| Finished | Sep 18 04:54:29 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801769052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.1801769052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.1520668479 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 640600379 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 04:45:33 PM UTC 24 |
| Finished | Sep 18 04:45:37 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520668479 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.1520668479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.2687171949 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 457812719 ps |
| CPU time | 14.54 seconds |
| Started | Sep 18 04:45:16 PM UTC 24 |
| Finished | Sep 18 04:45:32 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687171949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.2687171949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.860866332 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 605243958 ps |
| CPU time | 13.48 seconds |
| Started | Sep 18 04:45:21 PM UTC 24 |
| Finished | Sep 18 04:45:36 PM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860866332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.860866332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.1934735025 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 10232612184 ps |
| CPU time | 47.37 seconds |
| Started | Sep 18 04:45:19 PM UTC 24 |
| Finished | Sep 18 04:46:09 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934735025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1934735025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.2497397360 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 647874227 ps |
| CPU time | 19.62 seconds |
| Started | Sep 18 04:45:18 PM UTC 24 |
| Finished | Sep 18 04:45:39 PM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497397360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.2497397360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.3049460928 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 160324871 ps |
| CPU time | 5.65 seconds |
| Started | Sep 18 04:45:14 PM UTC 24 |
| Finished | Sep 18 04:45:22 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049460928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.3049460928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.2538084477 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 2818697281 ps |
| CPU time | 20.33 seconds |
| Started | Sep 18 04:45:25 PM UTC 24 |
| Finished | Sep 18 04:45:46 PM UTC 24 |
| Peak memory | 256028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538084477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.2538084477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.327090692 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1496946248 ps |
| CPU time | 22.76 seconds |
| Started | Sep 18 04:45:25 PM UTC 24 |
| Finished | Sep 18 04:45:49 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327090692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.327090692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.1820030499 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4047158048 ps |
| CPU time | 44.19 seconds |
| Started | Sep 18 04:45:18 PM UTC 24 |
| Finished | Sep 18 04:46:04 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820030499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.1820030499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.4087918964 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 480465255 ps |
| CPU time | 7.48 seconds |
| Started | Sep 18 04:45:25 PM UTC 24 |
| Finished | Sep 18 04:45:33 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087918964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.4087918964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.1907454665 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2582399983 ps |
| CPU time | 8.03 seconds |
| Started | Sep 18 04:45:14 PM UTC 24 |
| Finished | Sep 18 04:45:24 PM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907454665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.1907454665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.3796015352 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 428376706 ps |
| CPU time | 13.35 seconds |
| Started | Sep 18 04:45:25 PM UTC 24 |
| Finished | Sep 18 04:45:39 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796015352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.3796015352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.4132349290 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 253110502 ps |
| CPU time | 4.59 seconds |
| Started | Sep 18 04:54:28 PM UTC 24 |
| Finished | Sep 18 04:54:34 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132349290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.4132349290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.3412386178 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 347325041 ps |
| CPU time | 5.37 seconds |
| Started | Sep 18 04:54:28 PM UTC 24 |
| Finished | Sep 18 04:54:35 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412386178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.3412386178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.14791504 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 21214320585 ps |
| CPU time | 150.09 seconds |
| Started | Sep 18 04:54:28 PM UTC 24 |
| Finished | Sep 18 04:57:01 PM UTC 24 |
| Peak memory | 268344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=14791504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.14791504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.3379731670 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 249840784 ps |
| CPU time | 4.56 seconds |
| Started | Sep 18 04:54:28 PM UTC 24 |
| Finished | Sep 18 04:54:34 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379731670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.3379731670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.3856688023 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 350493161 ps |
| CPU time | 5.73 seconds |
| Started | Sep 18 04:54:28 PM UTC 24 |
| Finished | Sep 18 04:54:35 PM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856688023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3856688023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.128190162 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 514546049 ps |
| CPU time | 4.62 seconds |
| Started | Sep 18 04:54:29 PM UTC 24 |
| Finished | Sep 18 04:54:34 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128190162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.128190162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.922969878 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 408367483 ps |
| CPU time | 4.96 seconds |
| Started | Sep 18 04:54:29 PM UTC 24 |
| Finished | Sep 18 04:54:35 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922969878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.922969878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.2151257427 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 2059201388 ps |
| CPU time | 23.36 seconds |
| Started | Sep 18 04:54:31 PM UTC 24 |
| Finished | Sep 18 04:54:56 PM UTC 24 |
| Peak memory | 258120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2151257427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 52.otp_ctrl_stress_all_with_rand_reset.2151257427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.1411963313 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 155625293 ps |
| CPU time | 4.41 seconds |
| Started | Sep 18 04:54:31 PM UTC 24 |
| Finished | Sep 18 04:54:37 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411963313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.1411963313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.999978394 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 213852660 ps |
| CPU time | 6.84 seconds |
| Started | Sep 18 04:54:31 PM UTC 24 |
| Finished | Sep 18 04:54:39 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999978394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.999978394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.4051573431 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 283312242 ps |
| CPU time | 6.13 seconds |
| Started | Sep 18 04:54:34 PM UTC 24 |
| Finished | Sep 18 04:54:42 PM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051573431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.4051573431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.3616395971 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 267191624 ps |
| CPU time | 4.72 seconds |
| Started | Sep 18 04:54:34 PM UTC 24 |
| Finished | Sep 18 04:54:40 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616395971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3616395971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.4114197147 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 5580049942 ps |
| CPU time | 41.19 seconds |
| Started | Sep 18 04:54:34 PM UTC 24 |
| Finished | Sep 18 04:55:17 PM UTC 24 |
| Peak memory | 258284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4114197147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 54.otp_ctrl_stress_all_with_rand_reset.4114197147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.3002544452 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 2633254673 ps |
| CPU time | 7.69 seconds |
| Started | Sep 18 04:54:34 PM UTC 24 |
| Finished | Sep 18 04:54:43 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002544452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.3002544452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.2922393326 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 100597319 ps |
| CPU time | 2.83 seconds |
| Started | Sep 18 04:54:34 PM UTC 24 |
| Finished | Sep 18 04:54:39 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922393326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.2922393326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.1241311656 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 143436578 ps |
| CPU time | 3.17 seconds |
| Started | Sep 18 04:54:34 PM UTC 24 |
| Finished | Sep 18 04:54:39 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241311656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.1241311656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.1768298055 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 977093977 ps |
| CPU time | 9.33 seconds |
| Started | Sep 18 04:54:36 PM UTC 24 |
| Finished | Sep 18 04:54:46 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768298055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1768298055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.939516369 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2121064685 ps |
| CPU time | 53.92 seconds |
| Started | Sep 18 04:54:36 PM UTC 24 |
| Finished | Sep 18 04:55:32 PM UTC 24 |
| Peak memory | 258260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=939516369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.939516369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.2553666495 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 108171736 ps |
| CPU time | 4.65 seconds |
| Started | Sep 18 04:54:36 PM UTC 24 |
| Finished | Sep 18 04:54:42 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553666495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.2553666495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.3725154499 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 892368656 ps |
| CPU time | 6.37 seconds |
| Started | Sep 18 04:54:36 PM UTC 24 |
| Finished | Sep 18 04:54:44 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725154499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.3725154499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.4022986869 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 205543734 ps |
| CPU time | 4.06 seconds |
| Started | Sep 18 04:54:36 PM UTC 24 |
| Finished | Sep 18 04:54:41 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022986869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.4022986869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.1231723700 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 1506586995 ps |
| CPU time | 18.22 seconds |
| Started | Sep 18 04:54:38 PM UTC 24 |
| Finished | Sep 18 04:54:58 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231723700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.1231723700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.2286640134 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 29328454861 ps |
| CPU time | 72.34 seconds |
| Started | Sep 18 04:54:38 PM UTC 24 |
| Finished | Sep 18 04:55:53 PM UTC 24 |
| Peak memory | 268564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2286640134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 58.otp_ctrl_stress_all_with_rand_reset.2286640134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.3217546788 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 137214093 ps |
| CPU time | 4.87 seconds |
| Started | Sep 18 04:54:38 PM UTC 24 |
| Finished | Sep 18 04:54:44 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217546788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.3217546788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.308183749 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1484553024 ps |
| CPU time | 8.43 seconds |
| Started | Sep 18 04:54:38 PM UTC 24 |
| Finished | Sep 18 04:54:48 PM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308183749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.308183749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.2561490350 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 20260073772 ps |
| CPU time | 118.95 seconds |
| Started | Sep 18 04:54:38 PM UTC 24 |
| Finished | Sep 18 04:56:40 PM UTC 24 |
| Peak memory | 268356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2561490350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 59.otp_ctrl_stress_all_with_rand_reset.2561490350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.2551972377 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 865142795 ps |
| CPU time | 4.1 seconds |
| Started | Sep 18 04:45:59 PM UTC 24 |
| Finished | Sep 18 04:46:04 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551972377 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.2551972377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.318249139 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 701717170 ps |
| CPU time | 18.3 seconds |
| Started | Sep 18 04:45:39 PM UTC 24 |
| Finished | Sep 18 04:45:58 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318249139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.318249139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.2786572931 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 9667644762 ps |
| CPU time | 31.62 seconds |
| Started | Sep 18 04:45:44 PM UTC 24 |
| Finished | Sep 18 04:46:18 PM UTC 24 |
| Peak memory | 256052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786572931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.2786572931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.3020739951 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2945768643 ps |
| CPU time | 40.14 seconds |
| Started | Sep 18 04:45:40 PM UTC 24 |
| Finished | Sep 18 04:46:22 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020739951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.3020739951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.2875720346 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 4035138736 ps |
| CPU time | 30.4 seconds |
| Started | Sep 18 04:45:40 PM UTC 24 |
| Finished | Sep 18 04:46:12 PM UTC 24 |
| Peak memory | 254100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875720346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.2875720346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.1118750612 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 204289801 ps |
| CPU time | 5.23 seconds |
| Started | Sep 18 04:45:37 PM UTC 24 |
| Finished | Sep 18 04:45:44 PM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118750612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1118750612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.717678249 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 631726738 ps |
| CPU time | 29.38 seconds |
| Started | Sep 18 04:45:50 PM UTC 24 |
| Finished | Sep 18 04:46:21 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717678249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.717678249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.4011534575 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1226171839 ps |
| CPU time | 23.66 seconds |
| Started | Sep 18 04:45:40 PM UTC 24 |
| Finished | Sep 18 04:46:05 PM UTC 24 |
| Peak memory | 251076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011534575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.4011534575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.2368677967 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1388862074 ps |
| CPU time | 17.77 seconds |
| Started | Sep 18 04:45:39 PM UTC 24 |
| Finished | Sep 18 04:45:58 PM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368677967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.2368677967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.2484426357 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 462864912 ps |
| CPU time | 3.29 seconds |
| Started | Sep 18 04:45:50 PM UTC 24 |
| Finished | Sep 18 04:45:55 PM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484426357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.2484426357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.1317557791 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 778907674 ps |
| CPU time | 10.49 seconds |
| Started | Sep 18 04:45:35 PM UTC 24 |
| Finished | Sep 18 04:45:47 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317557791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.1317557791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.4161733470 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 4623281235 ps |
| CPU time | 73.27 seconds |
| Started | Sep 18 04:45:59 PM UTC 24 |
| Finished | Sep 18 04:47:14 PM UTC 24 |
| Peak memory | 262148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161733470 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.4161733470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.3338303875 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 887390046 ps |
| CPU time | 19.3 seconds |
| Started | Sep 18 04:45:50 PM UTC 24 |
| Finished | Sep 18 04:46:11 PM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338303875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.3338303875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.594492113 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 133708560 ps |
| CPU time | 5.54 seconds |
| Started | Sep 18 04:54:40 PM UTC 24 |
| Finished | Sep 18 04:54:46 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594492113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.594492113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.816344695 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 32035242850 ps |
| CPU time | 97.32 seconds |
| Started | Sep 18 04:54:42 PM UTC 24 |
| Finished | Sep 18 04:56:21 PM UTC 24 |
| Peak memory | 268424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=816344695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.816344695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.22670410 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 367333024 ps |
| CPU time | 4.57 seconds |
| Started | Sep 18 04:54:42 PM UTC 24 |
| Finished | Sep 18 04:54:48 PM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22670410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.22670410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.473084484 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 3574854594 ps |
| CPU time | 106.48 seconds |
| Started | Sep 18 04:54:42 PM UTC 24 |
| Finished | Sep 18 04:56:31 PM UTC 24 |
| Peak memory | 268404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=473084484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.473084484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.1268250176 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 110044053 ps |
| CPU time | 4.93 seconds |
| Started | Sep 18 04:54:42 PM UTC 24 |
| Finished | Sep 18 04:54:48 PM UTC 24 |
| Peak memory | 251736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268250176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1268250176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.560057555 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 529687824 ps |
| CPU time | 6.88 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:54:57 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560057555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.560057555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.3615762516 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 5944257690 ps |
| CPU time | 58.29 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:55:49 PM UTC 24 |
| Peak memory | 258192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3615762516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 62.otp_ctrl_stress_all_with_rand_reset.3615762516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.1932008381 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 254597316 ps |
| CPU time | 4.06 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:54:54 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932008381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.1932008381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.3950088671 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 839260248 ps |
| CPU time | 8.26 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:54:58 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950088671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.3950088671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.3273187440 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 18435868583 ps |
| CPU time | 78.03 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:56:09 PM UTC 24 |
| Peak memory | 268412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3273187440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 63.otp_ctrl_stress_all_with_rand_reset.3273187440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.1663622890 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 545776440 ps |
| CPU time | 6.7 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:54:57 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663622890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.1663622890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.2072738156 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1001564634 ps |
| CPU time | 11.96 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:55:02 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072738156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.2072738156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.596204687 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 7798661959 ps |
| CPU time | 60.77 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:55:51 PM UTC 24 |
| Peak memory | 258192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=596204687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.596204687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.3545009104 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 1796114750 ps |
| CPU time | 6.15 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:54:56 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545009104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3545009104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.2311766919 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 256882766 ps |
| CPU time | 3.72 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:54:54 PM UTC 24 |
| Peak memory | 251736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311766919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.2311766919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.1769967021 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 14997797356 ps |
| CPU time | 140.27 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:57:12 PM UTC 24 |
| Peak memory | 268400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1769967021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 65.otp_ctrl_stress_all_with_rand_reset.1769967021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.3118990633 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 142823800 ps |
| CPU time | 4.55 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:54:55 PM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118990633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.3118990633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.308237123 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 1457451073 ps |
| CPU time | 6.04 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:54:56 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308237123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.308237123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.227295349 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 217151480 ps |
| CPU time | 4.8 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:54:55 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227295349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.227295349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.3980575761 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 2118314118 ps |
| CPU time | 9.91 seconds |
| Started | Sep 18 04:54:49 PM UTC 24 |
| Finished | Sep 18 04:55:00 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980575761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.3980575761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.359029676 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 143643513 ps |
| CPU time | 3.9 seconds |
| Started | Sep 18 04:54:52 PM UTC 24 |
| Finished | Sep 18 04:54:57 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359029676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.359029676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.1449493573 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1153696339 ps |
| CPU time | 17.13 seconds |
| Started | Sep 18 04:54:52 PM UTC 24 |
| Finished | Sep 18 04:55:10 PM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449493573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.1449493573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.539246517 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 16500698632 ps |
| CPU time | 56.88 seconds |
| Started | Sep 18 04:54:52 PM UTC 24 |
| Finished | Sep 18 04:55:50 PM UTC 24 |
| Peak memory | 258224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=539246517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.539246517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.916187551 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 180392684 ps |
| CPU time | 4.62 seconds |
| Started | Sep 18 04:54:52 PM UTC 24 |
| Finished | Sep 18 04:54:58 PM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916187551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.916187551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.1226573752 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 333030655 ps |
| CPU time | 7.46 seconds |
| Started | Sep 18 04:54:57 PM UTC 24 |
| Finished | Sep 18 04:55:06 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226573752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.1226573752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.3055795531 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 9551531715 ps |
| CPU time | 137.76 seconds |
| Started | Sep 18 04:54:57 PM UTC 24 |
| Finished | Sep 18 04:57:18 PM UTC 24 |
| Peak memory | 272592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3055795531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 69.otp_ctrl_stress_all_with_rand_reset.3055795531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.3635070681 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 222469465 ps |
| CPU time | 5.11 seconds |
| Started | Sep 18 04:46:29 PM UTC 24 |
| Finished | Sep 18 04:46:35 PM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635070681 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.3635070681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.277257640 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 334766150 ps |
| CPU time | 9 seconds |
| Started | Sep 18 04:46:06 PM UTC 24 |
| Finished | Sep 18 04:46:16 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277257640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.277257640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.4214409461 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 17786389373 ps |
| CPU time | 28.23 seconds |
| Started | Sep 18 04:46:18 PM UTC 24 |
| Finished | Sep 18 04:46:47 PM UTC 24 |
| Peak memory | 254060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214409461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.4214409461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.2777964866 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2901599735 ps |
| CPU time | 44.67 seconds |
| Started | Sep 18 04:46:13 PM UTC 24 |
| Finished | Sep 18 04:47:00 PM UTC 24 |
| Peak memory | 258076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777964866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2777964866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.2329287492 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1791932614 ps |
| CPU time | 18.43 seconds |
| Started | Sep 18 04:46:13 PM UTC 24 |
| Finished | Sep 18 04:46:33 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329287492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.2329287492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.2351502475 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 176052365 ps |
| CPU time | 5.63 seconds |
| Started | Sep 18 04:46:06 PM UTC 24 |
| Finished | Sep 18 04:46:13 PM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351502475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.2351502475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.265466473 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 6239408579 ps |
| CPU time | 67.39 seconds |
| Started | Sep 18 04:46:18 PM UTC 24 |
| Finished | Sep 18 04:47:27 PM UTC 24 |
| Peak memory | 270496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265466473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.265466473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.191374663 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 12968346458 ps |
| CPU time | 37.56 seconds |
| Started | Sep 18 04:46:19 PM UTC 24 |
| Finished | Sep 18 04:46:58 PM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191374663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.191374663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.129435058 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 250986015 ps |
| CPU time | 7.55 seconds |
| Started | Sep 18 04:46:12 PM UTC 24 |
| Finished | Sep 18 04:46:20 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129435058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.129435058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.1216533680 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 385108066 ps |
| CPU time | 12.29 seconds |
| Started | Sep 18 04:46:10 PM UTC 24 |
| Finished | Sep 18 04:46:24 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216533680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.1216533680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.962656259 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 799836422 ps |
| CPU time | 10.64 seconds |
| Started | Sep 18 04:46:21 PM UTC 24 |
| Finished | Sep 18 04:46:33 PM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962656259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.962656259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.1964392635 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 981106287 ps |
| CPU time | 9.13 seconds |
| Started | Sep 18 04:46:06 PM UTC 24 |
| Finished | Sep 18 04:46:16 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964392635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1964392635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.620498630 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 69603860641 ps |
| CPU time | 200.14 seconds |
| Started | Sep 18 04:46:25 PM UTC 24 |
| Finished | Sep 18 04:49:49 PM UTC 24 |
| Peak memory | 258044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620498630 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.620498630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.3057235164 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 4428118944 ps |
| CPU time | 164.79 seconds |
| Started | Sep 18 04:46:25 PM UTC 24 |
| Finished | Sep 18 04:49:13 PM UTC 24 |
| Peak memory | 268404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3057235164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.otp_ctrl_stress_all_with_rand_reset.3057235164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.2263490450 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1000211349 ps |
| CPU time | 12.54 seconds |
| Started | Sep 18 04:46:23 PM UTC 24 |
| Finished | Sep 18 04:46:37 PM UTC 24 |
| Peak memory | 252132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263490450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2263490450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.3666316375 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1815739905 ps |
| CPU time | 5.84 seconds |
| Started | Sep 18 04:54:57 PM UTC 24 |
| Finished | Sep 18 04:55:04 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666316375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.3666316375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.1108377111 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 515572495 ps |
| CPU time | 5.41 seconds |
| Started | Sep 18 04:54:57 PM UTC 24 |
| Finished | Sep 18 04:55:04 PM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108377111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.1108377111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.637271034 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 115409514 ps |
| CPU time | 5.86 seconds |
| Started | Sep 18 04:54:58 PM UTC 24 |
| Finished | Sep 18 04:55:05 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637271034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.637271034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.1974715411 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 188673630 ps |
| CPU time | 8.08 seconds |
| Started | Sep 18 04:54:58 PM UTC 24 |
| Finished | Sep 18 04:55:07 PM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974715411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.1974715411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.4119004319 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 1479498540 ps |
| CPU time | 6.98 seconds |
| Started | Sep 18 04:54:58 PM UTC 24 |
| Finished | Sep 18 04:55:06 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119004319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.4119004319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.218308192 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 350562084 ps |
| CPU time | 17.16 seconds |
| Started | Sep 18 04:54:58 PM UTC 24 |
| Finished | Sep 18 04:55:16 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218308192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.218308192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.2477692397 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2094552558 ps |
| CPU time | 30.55 seconds |
| Started | Sep 18 04:54:58 PM UTC 24 |
| Finished | Sep 18 04:55:30 PM UTC 24 |
| Peak memory | 258128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2477692397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 72.otp_ctrl_stress_all_with_rand_reset.2477692397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.2654524230 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 185058775 ps |
| CPU time | 6.51 seconds |
| Started | Sep 18 04:54:58 PM UTC 24 |
| Finished | Sep 18 04:55:05 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654524230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.2654524230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.2466514714 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 178432967 ps |
| CPU time | 7.76 seconds |
| Started | Sep 18 04:54:58 PM UTC 24 |
| Finished | Sep 18 04:55:07 PM UTC 24 |
| Peak memory | 251648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466514714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.2466514714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.4087295989 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 2394402412 ps |
| CPU time | 79.86 seconds |
| Started | Sep 18 04:54:58 PM UTC 24 |
| Finished | Sep 18 04:56:20 PM UTC 24 |
| Peak memory | 258096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4087295989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 73.otp_ctrl_stress_all_with_rand_reset.4087295989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.1467106693 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 298041783 ps |
| CPU time | 4.23 seconds |
| Started | Sep 18 04:55:00 PM UTC 24 |
| Finished | Sep 18 04:55:05 PM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467106693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.1467106693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.636356678 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 897906080 ps |
| CPU time | 17.9 seconds |
| Started | Sep 18 04:55:00 PM UTC 24 |
| Finished | Sep 18 04:55:19 PM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636356678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.636356678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.2454775198 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 282586724 ps |
| CPU time | 5.35 seconds |
| Started | Sep 18 04:55:00 PM UTC 24 |
| Finished | Sep 18 04:55:06 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454775198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.2454775198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.492043330 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3440265911 ps |
| CPU time | 26.05 seconds |
| Started | Sep 18 04:55:01 PM UTC 24 |
| Finished | Sep 18 04:55:29 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492043330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.492043330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.3855190430 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 178555515 ps |
| CPU time | 3.94 seconds |
| Started | Sep 18 04:55:05 PM UTC 24 |
| Finished | Sep 18 04:55:10 PM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855190430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.3855190430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.2982253050 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 6644557491 ps |
| CPU time | 14.63 seconds |
| Started | Sep 18 04:55:07 PM UTC 24 |
| Finished | Sep 18 04:55:23 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982253050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.2982253050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.905963484 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 483964990 ps |
| CPU time | 7.06 seconds |
| Started | Sep 18 04:55:07 PM UTC 24 |
| Finished | Sep 18 04:55:16 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905963484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.905963484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.119714069 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 337230394 ps |
| CPU time | 8.67 seconds |
| Started | Sep 18 04:55:07 PM UTC 24 |
| Finished | Sep 18 04:55:17 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119714069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.119714069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.1055891784 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 615898449 ps |
| CPU time | 6.38 seconds |
| Started | Sep 18 04:55:08 PM UTC 24 |
| Finished | Sep 18 04:55:15 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055891784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.1055891784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.1407982216 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 401147604 ps |
| CPU time | 4.67 seconds |
| Started | Sep 18 04:55:08 PM UTC 24 |
| Finished | Sep 18 04:55:13 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407982216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1407982216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.2219761016 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 131791667 ps |
| CPU time | 5.56 seconds |
| Started | Sep 18 04:55:08 PM UTC 24 |
| Finished | Sep 18 04:55:14 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219761016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2219761016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.2100368157 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 131615792 ps |
| CPU time | 5.6 seconds |
| Started | Sep 18 04:55:08 PM UTC 24 |
| Finished | Sep 18 04:55:15 PM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100368157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.2100368157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2474292885 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 7469354544 ps |
| CPU time | 69.17 seconds |
| Started | Sep 18 04:55:08 PM UTC 24 |
| Finished | Sep 18 04:56:19 PM UTC 24 |
| Peak memory | 258092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2474292885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 79.otp_ctrl_stress_all_with_rand_reset.2474292885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.3180954898 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 177432498 ps |
| CPU time | 3.43 seconds |
| Started | Sep 18 04:46:55 PM UTC 24 |
| Finished | Sep 18 04:47:00 PM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180954898 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.3180954898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.3067315436 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1594256172 ps |
| CPU time | 16.05 seconds |
| Started | Sep 18 04:46:34 PM UTC 24 |
| Finished | Sep 18 04:46:52 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067315436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.3067315436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.3902673364 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 264647876 ps |
| CPU time | 14.76 seconds |
| Started | Sep 18 04:46:40 PM UTC 24 |
| Finished | Sep 18 04:46:56 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902673364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.3902673364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.1456496142 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 503821099 ps |
| CPU time | 16.84 seconds |
| Started | Sep 18 04:46:38 PM UTC 24 |
| Finished | Sep 18 04:46:56 PM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456496142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.1456496142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.4219372685 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 339333288 ps |
| CPU time | 6.6 seconds |
| Started | Sep 18 04:46:32 PM UTC 24 |
| Finished | Sep 18 04:46:40 PM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219372685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.4219372685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.87708524 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 22617940800 ps |
| CPU time | 24.57 seconds |
| Started | Sep 18 04:46:45 PM UTC 24 |
| Finished | Sep 18 04:47:11 PM UTC 24 |
| Peak memory | 258212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87708524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.87708524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.39249370 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 806242657 ps |
| CPU time | 27.58 seconds |
| Started | Sep 18 04:46:51 PM UTC 24 |
| Finished | Sep 18 04:47:20 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39249370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.39249370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.2350712497 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 14587543694 ps |
| CPU time | 39.82 seconds |
| Started | Sep 18 04:46:37 PM UTC 24 |
| Finished | Sep 18 04:47:18 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350712497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2350712497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.1485022554 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 389570058 ps |
| CPU time | 8.52 seconds |
| Started | Sep 18 04:46:34 PM UTC 24 |
| Finished | Sep 18 04:46:44 PM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485022554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.1485022554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.2114712061 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 526783398 ps |
| CPU time | 13.85 seconds |
| Started | Sep 18 04:46:51 PM UTC 24 |
| Finished | Sep 18 04:47:07 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114712061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.2114712061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.3398866076 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 278611462 ps |
| CPU time | 5.74 seconds |
| Started | Sep 18 04:46:32 PM UTC 24 |
| Finished | Sep 18 04:46:39 PM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398866076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.3398866076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.3281455880 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1834082575 ps |
| CPU time | 27.17 seconds |
| Started | Sep 18 04:46:52 PM UTC 24 |
| Finished | Sep 18 04:47:20 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281455880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.3281455880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.4284157434 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 127464516 ps |
| CPU time | 6.77 seconds |
| Started | Sep 18 04:55:08 PM UTC 24 |
| Finished | Sep 18 04:55:16 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284157434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.4284157434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.3255482135 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 109883284 ps |
| CPU time | 3.09 seconds |
| Started | Sep 18 04:55:18 PM UTC 24 |
| Finished | Sep 18 04:55:22 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255482135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.3255482135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.3444990353 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 49397474082 ps |
| CPU time | 136.51 seconds |
| Started | Sep 18 04:55:18 PM UTC 24 |
| Finished | Sep 18 04:57:37 PM UTC 24 |
| Peak memory | 274544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3444990353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 80.otp_ctrl_stress_all_with_rand_reset.3444990353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.4206559100 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 102947523 ps |
| CPU time | 5.09 seconds |
| Started | Sep 18 04:55:18 PM UTC 24 |
| Finished | Sep 18 04:55:24 PM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206559100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.4206559100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.1518405145 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 412295593 ps |
| CPU time | 9.66 seconds |
| Started | Sep 18 04:55:18 PM UTC 24 |
| Finished | Sep 18 04:55:29 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518405145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.1518405145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.2842005417 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 5993005687 ps |
| CPU time | 77.05 seconds |
| Started | Sep 18 04:55:18 PM UTC 24 |
| Finished | Sep 18 04:56:37 PM UTC 24 |
| Peak memory | 258188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2842005417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 81.otp_ctrl_stress_all_with_rand_reset.2842005417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.2224341358 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 505381471 ps |
| CPU time | 5.44 seconds |
| Started | Sep 18 04:55:18 PM UTC 24 |
| Finished | Sep 18 04:55:24 PM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224341358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.2224341358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.1140663496 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 1131285111 ps |
| CPU time | 21.87 seconds |
| Started | Sep 18 04:55:18 PM UTC 24 |
| Finished | Sep 18 04:55:41 PM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140663496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.1140663496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.522895456 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 4162775050 ps |
| CPU time | 86.81 seconds |
| Started | Sep 18 04:55:18 PM UTC 24 |
| Finished | Sep 18 04:56:47 PM UTC 24 |
| Peak memory | 258100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=522895456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.522895456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.2249237431 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 418276601 ps |
| CPU time | 5.57 seconds |
| Started | Sep 18 04:55:18 PM UTC 24 |
| Finished | Sep 18 04:55:25 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249237431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.2249237431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.154192047 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 175963425 ps |
| CPU time | 7.14 seconds |
| Started | Sep 18 04:55:18 PM UTC 24 |
| Finished | Sep 18 04:55:26 PM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154192047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.154192047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.3187893119 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 9012238233 ps |
| CPU time | 34.36 seconds |
| Started | Sep 18 04:55:18 PM UTC 24 |
| Finished | Sep 18 04:55:54 PM UTC 24 |
| Peak memory | 258320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3187893119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 83.otp_ctrl_stress_all_with_rand_reset.3187893119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.2596852382 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 308823142 ps |
| CPU time | 4.41 seconds |
| Started | Sep 18 04:55:20 PM UTC 24 |
| Finished | Sep 18 04:55:26 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596852382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2596852382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.1379816419 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 2546573838 ps |
| CPU time | 27.93 seconds |
| Started | Sep 18 04:55:20 PM UTC 24 |
| Finished | Sep 18 04:55:49 PM UTC 24 |
| Peak memory | 252044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379816419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1379816419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.2357851944 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 29451741587 ps |
| CPU time | 90.13 seconds |
| Started | Sep 18 04:55:20 PM UTC 24 |
| Finished | Sep 18 04:56:52 PM UTC 24 |
| Peak memory | 270668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2357851944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 84.otp_ctrl_stress_all_with_rand_reset.2357851944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.2565225449 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 1272202397 ps |
| CPU time | 3.63 seconds |
| Started | Sep 18 04:55:20 PM UTC 24 |
| Finished | Sep 18 04:55:25 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565225449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2565225449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.794639482 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 1603397732 ps |
| CPU time | 9.86 seconds |
| Started | Sep 18 04:55:22 PM UTC 24 |
| Finished | Sep 18 04:55:33 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794639482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.794639482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.3534620200 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 2024650083 ps |
| CPU time | 51.94 seconds |
| Started | Sep 18 04:55:22 PM UTC 24 |
| Finished | Sep 18 04:56:16 PM UTC 24 |
| Peak memory | 258200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3534620200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 85.otp_ctrl_stress_all_with_rand_reset.3534620200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.3508739734 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 220709320 ps |
| CPU time | 4.19 seconds |
| Started | Sep 18 04:55:23 PM UTC 24 |
| Finished | Sep 18 04:55:28 PM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508739734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.3508739734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.4042366170 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 14290148238 ps |
| CPU time | 50.03 seconds |
| Started | Sep 18 04:55:24 PM UTC 24 |
| Finished | Sep 18 04:56:16 PM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042366170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.4042366170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.1906495623 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 96656321296 ps |
| CPU time | 141.07 seconds |
| Started | Sep 18 04:55:27 PM UTC 24 |
| Finished | Sep 18 04:57:51 PM UTC 24 |
| Peak memory | 268416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1906495623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 86.otp_ctrl_stress_all_with_rand_reset.1906495623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/86.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.3012611623 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 1622784986 ps |
| CPU time | 5.04 seconds |
| Started | Sep 18 04:55:27 PM UTC 24 |
| Finished | Sep 18 04:55:34 PM UTC 24 |
| Peak memory | 251432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012611623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.3012611623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.3547720317 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 349596217 ps |
| CPU time | 6.87 seconds |
| Started | Sep 18 04:55:27 PM UTC 24 |
| Finished | Sep 18 04:55:36 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547720317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.3547720317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.4280786175 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 248349076 ps |
| CPU time | 5.09 seconds |
| Started | Sep 18 04:55:28 PM UTC 24 |
| Finished | Sep 18 04:55:34 PM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280786175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.4280786175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.1765530862 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 511025143 ps |
| CPU time | 6.71 seconds |
| Started | Sep 18 04:55:28 PM UTC 24 |
| Finished | Sep 18 04:55:36 PM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765530862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.1765530862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.2474215377 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 19139127124 ps |
| CPU time | 94.76 seconds |
| Started | Sep 18 04:55:28 PM UTC 24 |
| Finished | Sep 18 04:57:05 PM UTC 24 |
| Peak memory | 258128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2474215377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 88.otp_ctrl_stress_all_with_rand_reset.2474215377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/88.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.1609609576 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 258819753 ps |
| CPU time | 4.54 seconds |
| Started | Sep 18 04:55:31 PM UTC 24 |
| Finished | Sep 18 04:55:37 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609609576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.1609609576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.3524198568 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 191767331 ps |
| CPU time | 3.84 seconds |
| Started | Sep 18 04:55:32 PM UTC 24 |
| Finished | Sep 18 04:55:36 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524198568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.3524198568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.2065458012 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 35737227016 ps |
| CPU time | 84.66 seconds |
| Started | Sep 18 04:55:32 PM UTC 24 |
| Finished | Sep 18 04:56:58 PM UTC 24 |
| Peak memory | 274776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2065458012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 89.otp_ctrl_stress_all_with_rand_reset.2065458012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.1634238454 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 78366700 ps |
| CPU time | 2.49 seconds |
| Started | Sep 18 04:47:10 PM UTC 24 |
| Finished | Sep 18 04:47:14 PM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634238454 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.1634238454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.2995807169 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 274441537 ps |
| CPU time | 5.54 seconds |
| Started | Sep 18 04:47:01 PM UTC 24 |
| Finished | Sep 18 04:47:08 PM UTC 24 |
| Peak memory | 252080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995807169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2995807169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.3053833256 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1438059009 ps |
| CPU time | 57.91 seconds |
| Started | Sep 18 04:47:01 PM UTC 24 |
| Finished | Sep 18 04:48:01 PM UTC 24 |
| Peak memory | 264268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053833256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.3053833256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.724624397 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1259795412 ps |
| CPU time | 22.83 seconds |
| Started | Sep 18 04:47:01 PM UTC 24 |
| Finished | Sep 18 04:47:25 PM UTC 24 |
| Peak memory | 252128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724624397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.724624397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.3678192011 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 274443298 ps |
| CPU time | 9.57 seconds |
| Started | Sep 18 04:47:05 PM UTC 24 |
| Finished | Sep 18 04:47:16 PM UTC 24 |
| Peak memory | 252032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678192011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.3678192011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.2035658810 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 811112789 ps |
| CPU time | 22.37 seconds |
| Started | Sep 18 04:47:05 PM UTC 24 |
| Finished | Sep 18 04:47:29 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035658810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2035658810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.3449167723 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 590231269 ps |
| CPU time | 9.14 seconds |
| Started | Sep 18 04:46:59 PM UTC 24 |
| Finished | Sep 18 04:47:10 PM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449167723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.3449167723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.3905933561 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 4566834148 ps |
| CPU time | 16.13 seconds |
| Started | Sep 18 04:47:08 PM UTC 24 |
| Finished | Sep 18 04:47:25 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905933561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3905933561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.824786830 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 196226621 ps |
| CPU time | 3.81 seconds |
| Started | Sep 18 04:46:59 PM UTC 24 |
| Finished | Sep 18 04:47:04 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824786830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.824786830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.2453140057 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2729491457 ps |
| CPU time | 89.2 seconds |
| Started | Sep 18 04:47:10 PM UTC 24 |
| Finished | Sep 18 04:48:41 PM UTC 24 |
| Peak memory | 258256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2453140057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.otp_ctrl_stress_all_with_rand_reset.2453140057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.3412770844 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2026668935 ps |
| CPU time | 13.91 seconds |
| Started | Sep 18 04:47:08 PM UTC 24 |
| Finished | Sep 18 04:47:23 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412770844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.3412770844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.1991979583 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 140033501 ps |
| CPU time | 5.75 seconds |
| Started | Sep 18 04:55:32 PM UTC 24 |
| Finished | Sep 18 04:55:38 PM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991979583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.1991979583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.2395042979 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 413810373 ps |
| CPU time | 7.42 seconds |
| Started | Sep 18 04:55:32 PM UTC 24 |
| Finished | Sep 18 04:55:40 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395042979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.2395042979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.756536240 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 1975000520 ps |
| CPU time | 6.11 seconds |
| Started | Sep 18 04:55:34 PM UTC 24 |
| Finished | Sep 18 04:55:41 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756536240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.756536240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.1630076382 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 644291524 ps |
| CPU time | 5.58 seconds |
| Started | Sep 18 04:55:34 PM UTC 24 |
| Finished | Sep 18 04:55:40 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630076382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1630076382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.874715569 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 10652130591 ps |
| CPU time | 168.44 seconds |
| Started | Sep 18 04:55:38 PM UTC 24 |
| Finished | Sep 18 04:58:29 PM UTC 24 |
| Peak memory | 268628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=874715569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.874715569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.838428637 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 154139566 ps |
| CPU time | 4.91 seconds |
| Started | Sep 18 04:55:38 PM UTC 24 |
| Finished | Sep 18 04:55:44 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838428637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.838428637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.249010993 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 867036077 ps |
| CPU time | 7.77 seconds |
| Started | Sep 18 04:55:38 PM UTC 24 |
| Finished | Sep 18 04:55:47 PM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249010993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.249010993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.2598221220 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 136507357 ps |
| CPU time | 5.16 seconds |
| Started | Sep 18 04:55:38 PM UTC 24 |
| Finished | Sep 18 04:55:44 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598221220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.2598221220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.4067751873 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 135377194 ps |
| CPU time | 5.13 seconds |
| Started | Sep 18 04:55:38 PM UTC 24 |
| Finished | Sep 18 04:55:44 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067751873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.4067751873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.3567353714 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 2604390925 ps |
| CPU time | 64.71 seconds |
| Started | Sep 18 04:55:38 PM UTC 24 |
| Finished | Sep 18 04:56:45 PM UTC 24 |
| Peak memory | 258192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3567353714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 93.otp_ctrl_stress_all_with_rand_reset.3567353714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/93.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.3627577441 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 461876238 ps |
| CPU time | 12.12 seconds |
| Started | Sep 18 04:55:39 PM UTC 24 |
| Finished | Sep 18 04:55:53 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627577441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.3627577441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.1896873614 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 607589321 ps |
| CPU time | 5.22 seconds |
| Started | Sep 18 04:55:47 PM UTC 24 |
| Finished | Sep 18 04:55:53 PM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896873614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.1896873614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.2494469697 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 426125493 ps |
| CPU time | 6.45 seconds |
| Started | Sep 18 04:55:47 PM UTC 24 |
| Finished | Sep 18 04:55:54 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494469697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2494469697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.3460204378 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2369968831 ps |
| CPU time | 7.06 seconds |
| Started | Sep 18 04:55:47 PM UTC 24 |
| Finished | Sep 18 04:55:55 PM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460204378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.3460204378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.1037580059 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 596952369 ps |
| CPU time | 7.53 seconds |
| Started | Sep 18 04:55:47 PM UTC 24 |
| Finished | Sep 18 04:55:56 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037580059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.1037580059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.2532092578 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 497762930 ps |
| CPU time | 22.19 seconds |
| Started | Sep 18 04:55:47 PM UTC 24 |
| Finished | Sep 18 04:56:11 PM UTC 24 |
| Peak memory | 258188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2532092578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 96.otp_ctrl_stress_all_with_rand_reset.2532092578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.54728393 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 192585472 ps |
| CPU time | 5.8 seconds |
| Started | Sep 18 04:55:47 PM UTC 24 |
| Finished | Sep 18 04:55:54 PM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54728393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.54728393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.2527464303 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 211185114 ps |
| CPU time | 6.97 seconds |
| Started | Sep 18 04:55:47 PM UTC 24 |
| Finished | Sep 18 04:55:55 PM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527464303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.2527464303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.3952594727 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 382344490 ps |
| CPU time | 6.01 seconds |
| Started | Sep 18 04:55:53 PM UTC 24 |
| Finished | Sep 18 04:56:00 PM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952594727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.3952594727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.1667525148 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 664753010 ps |
| CPU time | 17.86 seconds |
| Started | Sep 18 04:55:53 PM UTC 24 |
| Finished | Sep 18 04:56:12 PM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667525148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.1667525148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.2373669905 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 4515831606 ps |
| CPU time | 139.31 seconds |
| Started | Sep 18 04:55:53 PM UTC 24 |
| Finished | Sep 18 04:58:15 PM UTC 24 |
| Peak memory | 284796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2373669905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 98.otp_ctrl_stress_all_with_rand_reset.2373669905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.4159322240 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 1667327226 ps |
| CPU time | 7.19 seconds |
| Started | Sep 18 04:55:53 PM UTC 24 |
| Finished | Sep 18 04:56:02 PM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159322240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.4159322240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.725558685 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 320650223 ps |
| CPU time | 2.99 seconds |
| Started | Sep 18 04:55:53 PM UTC 24 |
| Finished | Sep 18 04:55:57 PM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725558685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.725558685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest |
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